Software and hardware combined memory access mode analysis method and device

Abstract

The invention provides a software and hardware combined memory access mode analysis method and device, and the method comprises the steps: obtaining a hardware platform used for executing an application program, querying an event type list of a performance counter in the hardware platform, and obtaining an event type set supported by the performance hardware counter; calling a system interface of a hardware platform to obtain an event code according to the event type set; configuring a hardware acquisition mechanism by using a system interface according to a preset event acquisition threshold value and acquisition frequency; distributing a storage space for storing event data in the hardware platform; the hardware platform runs a hardware acquisition mechanism, acquires event data generated when an application program accesses a memory according to an event acquisition threshold and an acquisition frequency, and writes the event data into a storage space; when the number of the events in the storage space reaches a set value, the memory analysis tool processes the event data in the storage space, calculates the step length between access addresses, and determines the memory access mode of the application program through the step length and the address access frequency.

Description

Technical Field

[0001] The present invention relates to the technical field of computer architecture, and in particular to a memory access pattern analysis method and device combining software and hardware. Background Art

[0002] The memory access pattern refers to the way and order in which the server accesses memory during the execution of the application, and describes how the application reads and writes data in the memory. The core of identifying the memory access pattern is to find the address of each memory access when the application is running. By analyzing the memory access pattern, the memory access characteristics of the application can be obtained, and the access pattern can be optimized for different memory access characteristics. For example, for applications with better locality, more memory can be allocated, and the memory access address can be predicted based on the application's memory access characteristics, and pre-fetching data can reduce the number of page fault exceptions and improve application performance.

[0003] Common memory access modes are: 1. Sequential access, applications access memory addresses one by one in the order of memory addresses. This memory access mode has good locality and can effectively utilize cache. 2. Random access, applications access memory addresses in an irregular order. This memory access mode has poor locality, low cache hit rate, and it is difficult to predict the next memory address to be accessed. 3. Jump access, applications access memory addresses with a fixed step size. This memory access mode is more common when processing matrices or multidimensional arrays. 4. Tree access, applications access memory addresses in a tree structure. This memory access mode is more common when processing binary trees or other tree data structures.

[0004] Memory access semantic black barrier refers to the inability of memory analysis tools to accurately understand or predict the memory access pattern of the program, which makes it difficult for many memory access optimization and management strategies to play their effectiveness, such as Figure 1 As shown in the figure, the experiment found that a regular Map-Reduce based Word Count operation, after passing through the big data framework, runtime, and OS layer, exhibits phase-changing memory access characteristics, accompanied by sequential + random mixed characteristics, resulting in an average performance drop of 1.4 times when big data applications (such as Spark and Cassandra) are executed in pooled memory compared to those executed on ordinary servers (with sufficient local memory).

[0005] Currently, applications developed based on managed languages ​​(such as Java, Python, etc.) are generally executed based on the runtime (Runtime) and provide users with easy-to-use data abstractions (such as Object, etc.). In addition to computing tasks, this type of application still contains many service tasks, such as garbage collection tasks (Garbage Collection, GC), Just-In-Time Compilation (Just-In-Time Compilation, JIT), etc. On the one hand, when these tasks are executed concurrently, they will compete for local memory, network bandwidth and other resources, which will cause interference problems; on the other hand, these semantically unrelated tasks have very different computing and memory access modes. When their memory access behaviors are mixed together, they present disordered and random memory access semantics, which makes it difficult for the underlying system-level optimization to respond correctly, such as Figure 2 : The memory access pattern of the computing task thread is mixed with the memory access pattern of the GC thread, resulting in the overall memory access pattern of the application reflected on the hardware being random and difficult to predict.

[0006] Therefore, in order to break the memory access semantic black barrier, it is very important to identify the application memory access mode and perceive the application memory access semantics. In order to help developers understand the application memory access mode, many memory analysis tools are proposed in the prior art.

[0007] The first method is to obtain the memory access pattern by simulating the execution of the application, but this method has limitations, which makes it not suitable for most applications. In addition, the memory access patterns obtained by the simulated application and the actual execution application on different machines or execution environments may not be exactly the same.

[0008] The second way is to insert code into the binary file during application execution to obtain memory access patterns. The most typical tool is Intel pin, based on which it can obtain each specified read or write operation. However, such tools will bring dozens or even hundreds of times of overhead to the application, which makes it unsuitable for large applications. The inserted code may change the application behavior or introduce new vulnerabilities, causing application instability. The inserted code is bound to a specific platform and compiler and may not be applicable to all environments, limiting portability on different systems.

[0009] The third method is to make full use of the memory sampling mechanism provided by the hardware. Compared with the first two software-based memory sampling mechanisms, the hardware sampling mechanism (PEBS) can periodically sample the information of executed instructions to obtain the address of memory access; and this sampling method greatly reduces the overhead and improves efficiency. For example, sampling the memory access data of an instruction through the hardware sampling mechanism (PEBS) will only bring 200-300 nanoseconds of overhead.

[0010] The first simulation of application operation and the second binary insertion technology mentioned above will have a huge impact on application performance and cannot accurately obtain the memory access pattern of the application. Using simulation of application operation and binary insertion technology may change application behavior and affect memory access patterns, resulting in inaccurate memory access pattern analysis results.

[0011] Researchers have also proposed many memory analysis tools based on hardware sampling mechanisms. First, although the current memory analysis tools based on hardware sampling mechanisms can perceive the application memory access mode, they lack an efficient application memory access semantic tracking mechanism and will turn off the hardware sampling mechanism when performing memory analysis. Some memory access information of the application cannot be collected, affecting the memory analysis results. Efficient tracking of a large number of memory access behaviors requires a lot of computing resources, resulting in high overhead and serious impact on application performance.

[0012] Secondly, existing memory analysis tools can only obtain coarse-grained application memory access features, and there is not enough memory access information to accurately outline the application's memory access pattern. The above main shortcomings make it impossible to effectively transmit the upper-level application memory access pattern to the underlying hardware architecture, and it is impossible to effectively break the semantic black barrier (Semantics Gap), and it is difficult to extract regular memory access features from it. In systems that need to identify application memory access patterns and perform data pre-fetching or data recycling, it leads to a series of problems such as reduced application throughput, longer tail latency, and performance fluctuations.

[0013] As can be seen above, designing and implementing a memory access semantics system that can efficiently and accurately perceive the application program has a series of challenging scientific problems: First, how to efficiently output memory access information at the hardware layer and whether the corresponding overhead meets the system requirements (whether it interferes with application behavior). Second, how to efficiently and accurately analyze memory access patterns at the software layer to ensure connectivity from the underlying hardware to the software layer. Summary of the invention

[0014] The goal of the present invention is to design a memory analysis tool that combines software and hardware, which can efficiently and accurately perceive the memory access semantics of an application and efficiently transmit it to the hardware, thereby breaking the semantic gap formed between the system software stack and the hardware, and ensuring ease of programmability, transparency, and generality of the application.

[0015] In order to achieve the above technical effects, the present invention proposes the following key technical points:

[0016] Key point 1: Hardware sampling mechanism. Developed based on the hardware sampling mechanism technology PEBS, it periodically samples memory information, which greatly reduces the overhead and improves the accuracy of sampling events compared to traditional performance counters;

[0017] Key point 2, software sampling mechanism based on hyperthreading technology. Compared with the analysis thread and application thread both belonging to one main process, the present invention is that the analysis thread and application thread are two processes. Developing memory analysis tools based on hyperthreading technology can analyze the collected events in a short time with little impact on the application, improve the processor physical processor efficiency, and improve the physical processor execution unit utilization;

[0018] Key point 3: Software sampling mechanism based on fine-grained memory analysis. Combined with real-time processing of event data, based on the event data collected by the hardware, there is enough address access information to identify the memory access pattern.

[0019] Specifically, in view of the shortcomings of existing technologies, such as Figure 6 As shown, the present invention proposes a memory access pattern analysis method combining software and hardware, which includes:

[0020] The initial step is to obtain a hardware platform for executing the application program, query the event type list of the performance counter in the hardware platform, and obtain the event type set supported by the performance hardware counter; according to the event type set, call the system interface of the hardware platform to obtain the event code;

[0021] The setting step is to configure the hardware collection mechanism using the system interface according to the preset event collection threshold and collection frequency; and to allocate storage space for storing event data in the hardware platform;

[0022] In a collection step, the hardware platform runs the hardware collection mechanism to collect event data generated when the application accesses the memory according to the event collection threshold and the collection frequency, and writes the event data into the storage space;

[0023] Analysis step, when the number of events in the storage space reaches a set value, the memory analysis tool processes the event data in the storage space, calculates the step length between access addresses, and determines the memory access pattern of the application program through the step length and address access frequency.

[0024] The memory access pattern analysis method combining software and hardware, wherein the hardware platform has two logical threads, namely a memory analysis thread and an application thread, the memory analysis tool runs on the memory analysis thread, the application runs on the application thread, and the memory analysis thread and the application thread run on two logical processors respectively.

[0025] The memory access pattern analysis method combining software and hardware, wherein the event data includes: register value, timestamp, thread number, and accessed memory address.

[0026] The memory access pattern analysis method combining software and hardware, wherein the memory analysis tool runs on the logical processor where the application thread is located, and shares the same physical processor resources with the application.

[0027] like Figure 7 As shown, the present invention also proposes a memory access pattern analysis device combining software and hardware, which includes:

[0028] The initial module obtains the hardware platform used to execute the application program, queries the event type list of the performance counter in the hardware platform, and obtains the event type set supported by the performance hardware counter; based on the event type set, calls the system interface of the hardware platform to obtain the event code;

[0029] The setting module configures the hardware collection mechanism using the system interface according to the preset event collection threshold and collection frequency; allocates storage space for storing event data in the hardware platform;

[0030] The acquisition module, the hardware platform runs the hardware acquisition mechanism, collects the event data generated when the application accesses the memory according to the event acquisition threshold and the acquisition frequency, and writes the event data into the storage space;

[0031] Analysis module, when the number of events in the storage space reaches the set value, the memory analysis tool processes the event data in the storage space, calculates the step length between access addresses, and determines the memory access pattern of the application through the step length and address access frequency.

[0032] The memory access pattern analysis device combined with software and hardware, wherein the hardware platform has two logical threads, namely a memory analysis thread and an application thread, the memory analysis tool runs on the memory analysis thread, the application runs on the application thread, and the memory analysis thread and the application thread run on two logical processors respectively;

[0033] The memory analysis tool runs on the logical processor where the application thread is located, and shares the same physical processor resources with the application.

[0034] The memory access pattern analysis device combining software and hardware, wherein the event data includes: register value, timestamp, thread number, and accessed memory address.

[0035] The present invention also proposes an electronic device, which includes the memory access pattern analysis device described above. The electronic device may be connected to an information display device, and the information display device is used to display the memory access pattern according to display parameters and attributes set by the user or through an artificial intelligence model.

[0036] The present invention also proposes a computer-readable storage medium on which a computer program is stored. When the computer program is executed by a processor, the steps of the memory access pattern analysis method are implemented.

[0037] The present invention also proposes a computer program product, comprising a computer program, wherein the computer program implements the steps of the memory access pattern analysis method when executed by a processor.

[0038] It can be seen from the above scheme that the advantages of the present invention are:

[0039] The memory analysis tool based on hardware sampling mechanism and hyperthreading technology has low overhead, and the impact on application performance is basically negligible. It does not modify the application code, ensuring the ease of programmability of the application. The hardware acquisition mechanism outputs fine-grained memory access information to ensure application transparency. Hyperthreading analyzes real-time memory access information, reduces the observer effect brought by memory analysis tools to applications, and more accurately and finely identifies memory access patterns, ensuring the generality of applications. BRIEF DESCRIPTION OF THE DRAWINGS

[0040] Figure 1 Big data application performance comparison chart;

[0041] Figure 2 Application memory access pattern diagram;

[0042] Figure 3 Hardware acquisition mechanism diagram;

[0043] Figure 4 Hyperthreading diagram;

[0044] Figure 5 System design block diagram;

[0045] Figure 6 is a flow chart of the method of the present invention;

[0046] Figure 7 It is a module diagram of the device of the present invention;

[0047] Figure 8 This is a schematic diagram of the structure of a first electronic device of the present invention;

[0048] Fig. 9This is a schematic diagram of the application environment structure of the first electronic device of the present invention;

[0049] Fig.10 It is a schematic diagram of the structure of a second electronic device of the present invention.

[0050] Reference numerals:

[0051] A-First electronic device;

[0052] B-memory access pattern analysis device;

[0053] C-data acquisition equipment;

[0054] D-information display device;

[0055] 1000 - second electronic device;

[0056] Ⅰ-computational unit;

[0057] II-ROM;

[0058] III-RAM;

[0059] IV-bus;

[0060] V-interface;

[0061] VI - input unit;

[0062] VII-output unit;

[0063] VIII- Storage medium;

[0064] Ⅸ-Communication unit. DETAILED DESCRIPTION

[0065] It should be noted that, in this application, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprises" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device.

[0066] Without more constraints, an element defined by the phrase "comprising a..." does not exclude the existence of other identical elements in the process, method, article or apparatus comprising the element.

[0067] The processor described in the present invention is the control center of the electronic device, which can be a processor or a general term for multiple processing elements. For example, it can be one or more central processing units (CPUs), or application specific integrated circuits (ASICs), or one or more integrated circuits configured to implement the embodiments of the present invention, such as one or more microprocessors (digital signal processors, DSPs), or one or more field programmable gate arrays (FPGAs).

[0068] Optionally, the processor can perform various functions of the electronic device by running or executing a software program stored in the memory, and calling data stored in the memory.

[0069] In a specific implementation, as an embodiment, the processor may include one or more CPUs. Each of these processors may be a single-core processor (single-CPU) or a multi-core processor (multi-CPU). The processor here may refer to one or more devices, circuits, and / or processing cores for processing data (such as computer program instructions). Electronic devices may include: servers, desktop computers, laptops, smart phones, tablet computers, embedded computers, etc., wherein the embedded computers include vehicles and robots, etc.

[0070] The memory is used to store the software program for executing the solution of the present invention, and the execution is controlled by the processor. The specific implementation method can refer to the above method embodiment and will not be repeated here.

[0071] It should be noted that the structure of the electronic device shown in the drawings of the present invention does not constitute a limitation thereto, and the actual knowledge structure recognition device may include more or fewer components than shown in the drawings, or a combination of certain components, or a different arrangement of components.

[0072] The above embodiments can be implemented in whole or in part by software, hardware (such as circuits), firmware or any other combination. When implemented by software, the above embodiments can be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer instructions or computer programs. When the computer instructions or computer programs are loaded or executed on a computer, the process or function described in the embodiment of the present invention is generated in whole or in part. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer instructions can be stored in a computer-readable storage medium, or transmitted from one computer-readable storage medium to another computer-readable storage medium. For example, the computer instructions can be transmitted from one website, computer, server or data center to another website, computer, server or data center by wired (such as infrared, wireless, microwave, etc.). The computer-readable storage medium can be any available medium that can be accessed by a computer or a data storage device such as a server or data center that contains one or more available media sets. The available medium can be a magnetic medium (for example, a floppy disk, a hard disk, a tape), an optical medium (for example, a DVD), or a semiconductor medium. The semiconductor medium can be a solid-state hard disk.

[0073] It should also be understood that the term "and / or" in this article is only a description of the association relationship of associated objects, indicating that there can be three relationships. For example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone. A and B can be singular or plural. In addition, the character " / " in this article generally indicates that the associated objects before and after are in an "or" relationship, but it may also indicate an "and / or" relationship. Please refer to the context for specific understanding.

[0074] In the present invention, "at least one" means one or more, and "more than one" means two or more. "At least one of the following" or similar expressions refers to any combination of these items, including any combination of single or plural items. For example, at least one of a, b, or c can be represented by: a, b, c, ab, ac, bc, or abc, where a, b, c can be single or multiple.

[0075] It should also be understood that in various embodiments of the present invention, the size of the serial numbers of the above-mentioned processes does not mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present invention.

[0076] In the several embodiments provided by the present invention, it should be understood that the disclosed devices, apparatuses and methods can be implemented in other ways. For example, the device embodiments described above are only schematic, for example, the division of the units is only a logical function division, and there may be other division methods in actual implementation, such as multiple units or components can be combined or integrated into another device, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, indirect coupling or communication connection of devices or units, which can be electrical, mechanical or other forms.

[0077] The units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0078] In addition, each functional unit in each embodiment of the present invention may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit.

[0079] If the functions are implemented in the form of software functional units and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present invention can be essentially or partly embodied in the form of a software product that contributes to the prior art. The computer software product is stored in a storage medium and includes several instructions for enabling a computer device (which can be a personal computer, a server, or a network device, etc.) to perform all or part of the steps of the methods described in various embodiments of the present invention. The aforementioned storage medium includes: various media that can store program codes, such as a USB flash drive, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a magnetic disk or an optical disk.

[0080] In order to make the above features and effects of the present invention more clearly and understandably described, embodiments are given below and described in detail with reference to the accompanying drawings. This specification discloses one or more embodiments that include the features of the present invention. The disclosed embodiments are only for illustration. The scope of protection of the present invention is not limited to the disclosed embodiments, and the present invention is defined by the attached claims.

[0081] When the inventor was researching memory analysis tools, he found that the first memory analysis tool in the prior art that simulated application running and binary insertion technology only considered obtaining memory access patterns, but did not consider the impact on application performance and the possible application behavior that caused inaccurate memory access pattern analysis results. The main reason is that the development of memory analysis tools is complex. In the trade-off between performance and accuracy, the basic problem of obtaining memory access patterns is first solved, and then the impact of memory analysis tools on application performance is considered. For example, binary code is inserted into a multi-threaded application to track memory access information. The inserted binary code will change the thread scheduling order, which may cause application running errors or certain concurrency errors that cannot be reproduced in the debugging environment.

[0082] The second type of existing memory analysis tools based on hardware sampling mechanism, although considering the efficient perception of application memory access mode with little impact on application performance, will inevitably cause application performance problems and interfere with application behavior to a certain extent. The core function of the tool is to obtain memory access information and analyze memory access mode. The memory analysis tool and application run directly on the logical processor, that is, the analysis thread and application thread are separated and run on two logical CPUs. For example, numamm, the analysis thread and application thread run in the same main thread, and the analysis thread will inevitably interfere with the application thread. The advantage of this is that the system design is simple, and the disadvantage is that when the operating system schedules the memory analysis tool and the application, there may be competition for computing resources and memory access resources between the memory analysis tool and the application, resulting in a greater impact of the memory analysis tool on the application performance. For example, when processing the overflow signal sent by the underlying hardware, the existing memory analysis tool based on the hardware sampling mechanism will temporarily shut down the underlying hardware sampling mechanism, interrupt the hardware sampling process, and the application's memory access information cannot be completely collected, affecting the memory analysis results.

[0083] After studying hardware sampling mechanisms and hyper-threading technology, the inventors found that the defects of existing memory analysis tools, such as a significant impact on application performance and inaccurate memory access pattern analysis results, can be solved by hardware sampling mechanisms and hyper-threading technology. A memory analysis tool design combining software and hardware is proposed, which can efficiently and accurately perceive the application memory access semantics, has little impact on application performance and does not interfere with application behavior.

[0084] The memory analysis tool that combines software and hardware uses the powerful performance analysis capabilities provided by the hardware sampling mechanism PEBS to help determine the exact location of the event, including the instruction address and program counter value, such as the event context. The context information captured by the hardware acquisition mechanism (PEBS) includes register values ​​and memory addresses, which can be used to gain in-depth understanding of the program state when the event occurred. It can also create detailed program execution traces, avoiding the serious overhead problems caused by simulated program operation and binary instrumentation. The processor (CPU) sets the hardware acquisition mechanism event, and the hardware acquisition mechanism triggers an interrupt to execute PEBS assist and write the event data to the memory space (PEBS buffer). The memory access information provided by the hardware acquisition mechanism includes timestamps, thread numbers, and memory addresses accessed. Compared with existing memory analysis tools, it can provide more sufficient, timely, and lower-overhead memory access information.

[0085] Therefore, we further utilize the hyperthreading technology based on the hardware sampling mechanism. Intel CPU allows each core to expose two logical cores and execute two hyperthreads. The memory analysis tool proposed by the inventor separates the memory analysis part during design, and the memory analysis thread and the application thread do not interfere with each other during operation. Therefore, the application thread can be accurately identified, and the application thread is placed on the logical processor. Our memory analysis tool based on the hardware sampling mechanism is placed on the corresponding hyperthreaded logical processor. The application thread and the memory analysis tool share the same physical processor. The advantage is that the observer effect and overhead brought to the application can be further reduced. The hyperthreading analyzes the memory access mode in real time and accurately based on the memory access information provided by the hardware acquisition mode, ensuring that the memory access characteristics are not lost during the process of passing from the underlying hardware to the software layer.

[0086] The present invention uses a technical solution based on a hardware sampling mechanism, and provides support for both read and write events under different microarchitectures (e.g., PEBS supports Skylake, Nehalem, Ice Lake, and Alder Lake architectures), which meets our needs for capturing memory access read and write. The memory analysis tool runs on the hyperthreaded logical processor corresponding to the application, sharing the same physical processor resources. The memory analysis tool formulates the events to be collected, and the hardware automatically saves the data of the collected events to the memory. When the number of collected events reaches the set threshold, an overflow signal is sent to the memory analysis tool, and then the memory analysis tool processes the event.

[0087] The first step is to initialize the performance hardware counter and obtain the event types supported by the current performance hardware counter. Check whether the system implements the hardware sampling mechanism, ensure that the relevant drivers and libraries have been correctly installed, call the system interface to initialize the performance counter, and query the list of event types supported by the performance counter, and record the available event types and their descriptions.

[0088] The second step is to obtain the event code of the corresponding event of the current operating system. According to the event type obtained in the first step, call the system interface to obtain the event code, verify that the code is consistent with the support list of the hardware counter to ensure there is no conflict.

[0089] The third step is to set the event threshold, collection frequency, collection events, and configure the hardware collection mechanism. Determine the collection threshold of the event and set it to a reasonable threshold to avoid too much or too little data collection. Configure the collection frequency to ensure that enough event data can be collected during the application operation. Use the system interface to configure the hardware collection mechanism and determine whether the setting is successful through the return value.

[0090] The fourth step is to allocate a memory space for storing data. According to the actual system resources, allocate a large enough memory space to store the collected event data, and ensure that the allocated memory is aligned to improve the reading and writing efficiency.

[0091] Step 5: Enable the hardware acquisition mechanism. Start the hardware acquisition mechanism and make sure it is active and ready to acquire data. Make sure there are no errors or warnings based on the return status.

[0092] Step 6: The hardware collection mechanism will not collect events when no application is running. When an application is detected to be running, it will collect events according to the set collection frequency, and the hardware collection mechanism will automatically write the event data into the allocated memory space. Ensure that the hardware collection mechanism can correctly identify the running status of the application, start or stop collection as needed, and verify the correctness and integrity of the data written into the memory space.

[0093] Step 7: When the number of events reaches the set threshold, the hardware acquisition mechanism sends an overflow signal to the memory analysis tool to notify the memory analysis tool to process the data. Configure the trigger conditions and processing mechanism of the overflow signal to ensure that the memory analysis tool can receive the overflow signal in time and prepare to process the data.

[0094] Step 8: After receiving the signal, the memory analysis tool reads the memory space and analyzes the event data. The memory analysis tool reads the event data in the memory space, performs preliminary data cleaning and formatting, executes detailed analysis code, calculates the stride between access addresses, and identifies the memory access mode through stride and address access frequency. For example, if the stride is fixed each time and the address is only accessed once, it is a sequential access or a jump access. The memory analysis tool can predict the next access address based on the memory access mode. If the stride is irregular and the address is only accessed once, it is a random access. The analysis results are recorded. The memory analysis tool is developed based on the underlying hardware mechanism (PEBS).

[0095] The following is a system embodiment corresponding to the above method embodiment. This embodiment can be implemented in conjunction with the above embodiment. The relevant technical details mentioned in the above embodiment are still valid in this embodiment. In order to reduce repetition, they are not repeated here. Accordingly, the relevant technical details mentioned in this embodiment can also be applied in the above embodiment.

[0096] like Figure 7 As shown, the present invention also proposes a memory access pattern analysis device combining software and hardware, which includes:

[0097] The initial module obtains the hardware platform used to execute the application program, queries the event type list of the performance counter in the hardware platform, and obtains the event type set supported by the performance hardware counter; based on the event type set, calls the system interface of the hardware platform to obtain the event code;

[0098] The setting module configures the hardware collection mechanism using the system interface according to the preset event collection threshold and collection frequency; allocates storage space for storing event data in the hardware platform;

[0099] The acquisition module, the hardware platform runs the hardware acquisition mechanism, collects the event data generated when the application accesses the memory according to the event acquisition threshold and the acquisition frequency, and writes the event data into the storage space;

[0100] Analysis module, when the number of events in the storage space reaches the set value, the memory analysis tool processes the event data in the storage space, calculates the step length between access addresses, and determines the memory access pattern of the application through the step length and address access frequency.

[0101] The memory access pattern analysis device combined with software and hardware, wherein the hardware platform has two logical threads, namely a memory analysis thread and an application thread, the memory analysis tool runs on the memory analysis thread, the application runs on the application thread, and the memory analysis thread and the application thread run on two logical processors respectively;

[0102] The memory analysis tool runs on the logical processor where the application thread is located, and shares the same physical processor resources with the application.

[0103] The memory access pattern analysis device combining software and hardware, wherein the event data includes: register value, timestamp, thread number, and accessed memory address.

[0104] like Figure 8 As shown, the present invention further proposes a first electronic device A in another embodiment, comprising the above-mentioned memory access pattern analysis device.

[0105] like Fig. 9As shown, the first electronic device A can also be connected to the data acquisition device C and the information display device D through a wired or wireless information transmission scheme. The data acquisition device C is used to collect and obtain the application program to be analyzed for memory access pattern, such as an image classification program, and the information display device D is used to display the memory access pattern analysis results obtained by the present invention.

[0106] The information display device D can process the data output by the first electronic device A based on the information display mechanism to improve the readability of the data output by the first electronic device A. The information display mechanism can be manually preset, for example, the data output by the first electronic device A is visually displayed, which can be based on the display parameters and / or attributes set by the user. The display parameters can be, for example, the display data range, and the display attributes can be, for example, the display font, color, whether to scroll and play, etc. The user is presented with the key information specified by the user, such as the image classification results and the memory access mode corresponding to the image classification program, etc. The user can understand this information more timely without having to access the secondary page or scroll the page, saving the user's operation. Or the information display mechanism can be an artificial intelligence AI display model, which can learn the user's key information based on the user's previous usage habits, such as viewing time, number of clicks, number of edits, etc., and then automatically present rich and necessary key information to the user.

[0107] The present invention also provides a computer program product, which includes a computer program. The computer program can be stored in a readable storage medium. When the computer program is executed by a processor, the computer can execute the memory access pattern analysis method provided by the above methods.

[0108] The present invention also proposes a storage medium VIII in another embodiment for storing a computer program for executing the memory access pattern analysis method. It should be understood that the storage medium in the embodiment of the present invention may be a volatile memory or a non-volatile memory, or may include both volatile and non-volatile memories. Among them, the non-volatile memory may be a read-only memory (ROM), a programmable read-only memory (PROM), an erasable programmable read-only memory (EPROM), an electrically erasable programmable read-only memory (EEPROM), or a flash memory. The volatile memory may be a random access memory (RAM), which is used as an external cache. By way of example and not limitation, many forms of random access memory (RAM) are available, such as static RAM (SRAM), dynamic random access memory (DRAM), synchronous DRAM (SDRAM), double data rate synchronous dynamic random access memory (DDR SDRAM), enhanced synchronous dynamic random access memory (ESDRAM), synchronous link DRAM (SLDRAM), and direct rambus RAM (DRRAM).

[0109] Fig.10 A schematic block diagram of a second electronic device 1000 that can be used to implement an embodiment of the present invention is shown. The second electronic device 1000 electronic device is intended to represent various forms of digital computers, such as laptop computers, desktop computers, workbenches, personal digital assistants, servers, blade servers, mainframe computers, and other suitable computers. The second electronic device 1000 can also represent various forms of mobile devices, such as personal digital processing, cellular phones, smart phones, wearable devices, and other similar computing devices. The components shown herein, their connections and relationships, and their functions are merely examples, and are not intended to limit the implementation of the present invention described and / or required herein. The second electronic device 1000 may be the same or different from the first electronic device A.

[0110] The second electronic device 1000 includes a computing unit I, which can perform various appropriate actions and processes according to a computer program stored in a read-only memory II (ROM) or a computer program loaded from a storage medium VIII into a random access memory (RAM) III. In RAM III, various programs and data required for the operation of the device 1000 can also be stored. The computing unit I, ROM II, and RAM III are connected to each other via a bus IV. An input / output (I / O) interface V is also connected to the bus IV.

[0111] A plurality of components in the second electronic device 1000 are connected to the I / O interface V, including: an input unit VI, such as a keyboard, a mouse, etc.; an output unit VII, such as various types of displays, speakers, etc.; a storage medium VIII, such as a disk, an optical disk, etc.; and a communication unit IX, such as a network card, a modem, a wireless communication transceiver, etc. The communication unit IX allows the second electronic device 1000 to exchange information / data with other devices through a computer network such as the Internet and / or various telecommunication networks.

[0112] The computing unit I may be a variety of general and / or special processing components with processing and computing capabilities. Some examples of computing unit I include, but are not limited to, a central processing unit (CPU), a graphics processing unit (GPU), various dedicated artificial intelligence (AI) computing chips, various computing units running machine learning model algorithms, digital signal processors (DSPs), and any appropriate processors, controllers, microcontrollers, etc. The computing unit I performs the various methods and processes described above, such as method steps S1-S4. For example, in some embodiments, the method may be implemented as a computer software program, which is tangibly contained in a machine-readable medium, such as a storage medium VIII. In some embodiments, part or all of the computer program may be loaded and / or installed on the device 1000 via ROM II and / or a communication unit IX. When the computer program is loaded into RAM III and executed by the computing unit I, one or more steps of the method described above may be performed. Alternatively, in other embodiments, the computing unit I may be configured to execute the method in any other appropriate manner (e.g., by means of firmware).

[0113] Although the embodiments of the present invention have been disclosed as above, they are not limited to the applications listed in the specification and the implementation modes, and they can be fully applied to various fields suitable for the present invention. For those familiar with the art, additional modifications can be easily implemented. Therefore, without departing from the general concept defined by the claims and the scope of equivalents, the present invention is not limited to the specific details and the illustrations shown and described herein.

Claims

1. A memory access pattern analysis method combining software and hardware, characterized in that: include: The initial step is to obtain a hardware platform for executing the application program, query the event type list of the performance counter in the hardware platform, and obtain the event type set supported by the performance hardware counter; according to the event type set, call the system interface of the hardware platform to obtain the event code; The setting step is to configure the hardware collection mechanism using the system interface according to the preset event collection threshold and collection frequency; and to allocate storage space for storing event data in the hardware platform; In a collection step, the hardware platform runs the hardware collection mechanism to collect event data generated when the application accesses the memory according to the event collection threshold and the collection frequency, and writes the event data into the storage space; Analysis step, when the number of events in the storage space reaches a set value, the memory analysis tool processes the event data in the storage space, calculates the step length between access addresses, and determines the memory access pattern of the application program through the step length and address access frequency.

2. The memory access pattern analysis method combining software and hardware as claimed in claim 1, characterized in that: The hardware platform has two logical threads, namely a memory analysis thread and an application thread. The memory analysis tool runs on the memory analysis thread, the application runs on the application thread, and the memory analysis thread and the application thread run on two logical processors respectively.

3. The memory access pattern analysis method combining software and hardware as described in claim 1 or 2, characterized in that: The event data includes: register value, timestamp, thread number, and accessed memory address.

4. The memory access pattern analysis method combining software and hardware as claimed in claim 2, characterized in that: The memory analysis tool runs on the logical processor where the application thread is located, sharing the same physical processor resources as the application.

5. A memory access pattern analysis device combining software and hardware, characterized in that: include: The initial module obtains the hardware platform used to execute the application program, queries the event type list of the performance counter in the hardware platform, and obtains the event type set supported by the performance hardware counter; based on the event type set, calls the system interface of the hardware platform to obtain the event code; The setting module configures the hardware collection mechanism using the system interface according to the preset event collection threshold and collection frequency; allocates storage space for storing event data in the hardware platform; The acquisition module, the hardware platform runs the hardware acquisition mechanism, collects the event data generated when the application accesses the memory according to the event acquisition threshold and the acquisition frequency, and writes the event data into the storage space; Analysis module, when the number of events in the storage space reaches the set value, the memory analysis tool processes the event data in the storage space, calculates the step length between access addresses, and determines the memory access pattern of the application through the step length and address access frequency.

6. The memory access pattern analysis device combining software and hardware as claimed in claim 5, characterized in that: The hardware platform has two logical threads, namely a memory analysis thread and an application thread. The memory analysis tool runs on the memory analysis thread, the application runs on the application thread, and the memory analysis thread and the application thread run on two logical processors respectively. The memory analysis tool runs on the logical processor where the application thread is located, and shares the same physical processor resources with the application.

7. The memory access pattern analysis device combining software and hardware as claimed in claim 5 or 6, characterized in that: The event data includes: register value, timestamp, thread number, and accessed memory address.

8. An electronic device, characterized in that: It includes a memory access pattern analysis device as described in claims 5-7, and the electronic device is connected to an information display device, and the information display device is used to display the memory access pattern according to display parameters and attributes set by the user or through an artificial intelligence model.

9. A computer-readable storage medium having a computer program stored thereon, wherein when the computer program is executed by a processor, the steps of the memory access pattern analysis method described in any one of claims 1 to 4 are implemented.

10. A computer program product, comprising a computer program, characterized in that When the computer program is executed by a processor, the steps of the memory access pattern analysis method described in any one of claims 1 to 4 are implemented.

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