Cache consistency control method and device in multi-core processor system

Abstract

The invention discloses a cache consistency control method and device in a multi-core processor system. The method comprises the following steps: sending a read request of a current processor core for a cache line to an interconnection network node; other permission states, sent by the interconnection network node, of other processor cores to the cache line are received, and the other processor cores are processor cores except the current processor core in the multiple processor cores in the multi-core processor system; according to other permission states of the cache line checked by other processors, the current permission state of the cache line checked by the current processor is determined, and the current permission state is an exclusive state higher than the sharing state. According to the method and the device, the technical problem that in the related technology, when data sharing is realized in a multi-core processor system, at least two times of interaction exist during writing processing of data sent by each processor core, and excessive communication resources are occupied is solved.

Description

Technical Field

[0001] The present invention relates to the field of computer technology, and in particular to a cache consistency control method and device in a multi-core processor system. Background Art

[0002] As the amount of computing tasks increases, high-performance multi-core processor systems have been used more and more widely. In a multi-core processor system, each core is usually equipped with an independent private cache. In a multi-core processor system, when a processor core accesses a private cache, due to the limited capacity of its private cache, when its private cache does not have enough space to accommodate the accessed cache line, it is necessary to access the cache line in a way that multiple processor cores share the cache line. Therefore, when multiple processor cores in a multi-core processor system share cache lines, cache consistency control is required between the multiple processor cores to ensure cache consistency between the multiple processor cores.

[0003] In the related art, the cache consistency control method usually adopts a bus method, and sends cache consistency control information between multiple processor cores to the interconnected network nodes communicating between the multiple processor cores through the bus, which consumes too many communication resources.

[0004] Read-Modify-Write (RMW) is a common memory access operation scenario in current multi-core processor systems. When processing this scenario based on a multi-core consistency protocol (for example, the MESI protocol (an abbreviation of the four states Modified, Exclusive, Shared, and Invalid in the protocol)), it is necessary to first obtain read permission for the cacheline (cache block, or cache line, the basic unit of memory access), then obtain exclusive permission for the cacheline, modify the cacheline, and then obtain write permission through the bus before writing it back.

[0005] Therefore, when data sharing is implemented in a multi-core processor system, there are at least two interactions when a data write process is initiated by each processor core, which occupies too many communication resources.

[0006] To address the above-mentioned problems, no effective solution has been proposed yet. Summary of the invention

[0007] An embodiment of the present invention provides a cache consistency control method and device in a multi-core processor system to at least solve the technical problem in the related art that when data sharing is implemented in a multi-core processor system, there are at least two interactions when data write processing is initiated by each processor core, which occupies too many communication resources.

[0008] According to one aspect of an embodiment of the present invention, a cache consistency control method in a multi-core processor system is provided, comprising: sending a read request for a cache line by a current processor core to an interconnected network node, wherein the interconnected network node is used to maintain consistency of the cache line among multiple processor cores in the multi-core processor system; receiving other permission states of the cache line from other processor cores sent by the interconnected network node, wherein the other processor cores are processor cores other than the current processor core among the multiple processor cores in the multi-core processor system; determining a current permission state of the current processor core to the cache line based on the other permission states of the other processor cores to the cache line, wherein the current permission state is an exclusive state higher than a shared state.

[0009] Optionally, determining the current permission state of the current processor core with respect to the cache line based on the other permission states of the other processor cores with respect to the cache line includes: determining that the current permission state of the current processor core with respect to the cache line is an exclusive state when the other permission state represents that none of the other processor cores holds the cache line; or determining that the current permission state of the current processor core with respect to the cache line is an exclusive state when the other permission state represents that none of the other processor cores holds the cache line in a modified state.

[0010] Optionally, the method further includes: when the other permission status indicates that a processor core among the other processor cores holds the cache line in a shared state or an exclusive state, determining that the current permission status of the current processor core to the cache line is a shared state.

[0011] Optionally, the method further includes: receiving a sniffing request sent from the interconnected network node; and in response to the sniffing request, determining the sniffer permission state of the sniffer according to the permission state of the current processor core as the sniffer.

[0012] Optionally, in response to the sniffing request, the sniffer permission state of the sniffer is determined according to the permission state of the current processor core as the sniffer, including at least one of the following: when the permission state of the current processor core as the sniffer is an invalid state characterizing that the current processor core does not hold the cache line, maintaining the sniffer permission state of the sniffer to an invalid state; when the permission state of the current processor core as the sniffer is a shared state or an exclusive state, updating the sniffer permission state of the sniffer to a shared state; when the permission state of the current processor core as the sniffer is a modified state, updating the sniffer permission state of the sniffer to an invalid state.

[0013] Optionally, after determining the sniffer permission status of the sniffer based on the permission status of the current processor core as the sniffer in response to the sniffing request, the method further includes: sending a sniffing response to the interconnected network node, wherein the sniffing response carries the status of the sniffer before being sniffed and / or the updated status after being sniffed.

[0014] Optionally, after determining the current permission status of the current processor for checking the cache line based on the other permission status of the other processors for checking the cache line, it also includes: sending a read request response to the interconnection network node, wherein the read request response carries the current permission status of the current processor for checking the cache line.

[0015] According to another aspect of the present invention, a cache consistency control method in a multi-core processor system is provided, comprising: receiving a read request for a cache line sent by a current processor core; obtaining other permission states of other processor cores in the multi-core processor system for the cache line, wherein the other processor cores are processor cores other than the current processor core among multiple processor cores in the multi-core processor system; sending the other permission states of the other processor cores for the cache line to the current processor core, wherein the other permission states of the other processor cores for the cache line are used to determine the current permission state of the current processor core for the cache line, wherein the current permission state is an exclusive state higher than a shared state.

[0016] Optionally, obtaining other permission states of other processor cores in the multi-core processor system for the cache line includes: sending a sniff request to other processor cores in the multi-core processor system; receiving a sniff response fed back by the other processor cores, wherein the sniff response carries the state of the other processor core before being sniffed and / or the updated state after being sniffed.

[0017] Optionally, the method further includes: receiving a read request response fed back by the current processor core, wherein the read request response carries a current permission status of the current processor core to the cache line.

[0018] According to another aspect of the present invention, a cache consistency control device in a multi-core processor system is provided, comprising: a first sending module, used to send a read request of a current processor core for a cache line to an interconnected network node, wherein the interconnected network node is used to maintain the consistency of the cache line among multiple processor cores in the multi-core processor system; a first receiving module, used to receive other permission states of the cache line sent by other processor cores of the interconnected network node, wherein the other processor cores are processor cores other than the current processor core among the multiple processor cores in the multi-core processor system; a first determining module, used to determine the current permission state of the current processor core for the cache line according to the other permission states of the other processor cores for the cache line, wherein the current permission state is an exclusive state higher than the shared state.

[0019] According to another aspect of the present invention, a cache consistency control device in a multi-core processor system is provided, comprising: a second receiving module, used to receive a read request for a cache line sent by a current processor core; an acquisition module, used to acquire other permission states of other processor cores in the multi-core processor system for the cache line, wherein the other processor cores are processor cores other than the current processor core among multiple processor cores in the multi-core processor system; a second sending module, used to send other permission states of the other processor cores for the cache line to the current processor core, wherein the other permission states of the other processor cores for the cache line are used to determine the current permission state of the current processor core for the cache line, wherein the current permission state is an exclusive state higher than the shared state.

[0020] According to yet another aspect of the present invention, a processor is provided, comprising: a plurality of processor cores, wherein the processor is configured to execute any one of the above methods.

[0021] According to another aspect of the present invention, there is provided a system on chip, comprising: one or more hardware units, a processor, and an interconnection device for communicating between the hardware units or between the hardware units and the processors, wherein the processor comprises multiple processor cores, and the processor is used to execute any one of the methods described above.

[0022] According to another aspect of the present invention, there is provided a computing device, comprising: a memory and a processor, wherein the memory stores a computer program; the processor is used to execute the computer program stored in the memory, and when the computer program is run, the processor executes any one of the methods described above.

[0023] According to another aspect of the present invention, there is provided a computer storage medium on which a computer program is stored, and when the program is executed by a processor, any one of the methods described above is implemented.

[0024] According to another aspect of the present invention, a computer program product is provided, comprising computer instructions, which implement any one of the above methods when executed by a processor.

[0025] In an embodiment of the present invention, after sending a read request for a cache line, the current permission state of the current processor core with respect to the cache line is determined according to the other permission states of the other processor cores with respect to the cache line, wherein the current permission state is an exclusive state higher than the shared state. Since the determined current permission state is higher than the exclusive state of the shared state, the purpose of writing to the cache line can be achieved when sending a read request once, thereby achieving the technical effect of reducing the communication overhead in cache consistency maintenance and improving the overall performance of the system, and further solving the technical problem in the related art that when implementing data sharing in a multi-core processor system, there are at least two interactions for data write processing initiated by each processor core, which occupies too many communication resources. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] The drawings described herein are used to provide a further understanding of the present invention and constitute a part of this application. The exemplary embodiments of the present invention and their descriptions are used to explain the present invention and do not constitute an improper limitation of the present invention. In the drawings:

[0027] Figure 1 A schematic diagram of the hardware structure of a system on chip for implementing cache coherence control in a multi-core processor system is shown;

[0028] Figure 2 is a schematic diagram of a MESI consistency protocol solution in a related art for comparison in Example 1 of the present invention;

[0029] Figure 3 is a flowchart of a cache consistency control method 1 in a multi-core processor system according to embodiment 1 of the present invention;

[0030] Figure 4 is a flowchart of a second cache consistency control method in a multi-core processor system according to embodiment 1 of the present invention;

[0031] Figure 5 is a schematic diagram of a multi-core processor system with data consistency according to Embodiment 1 of the present invention;

[0032] Figure 6 is a schematic diagram of a cache consistency control method in a multi-core processor system provided according to an optional embodiment of the present invention Figure 1 ;

[0033] Figure 7 is a schematic diagram of a cache consistency control method in a multi-core processor system provided according to an optional embodiment of the present invention Figure 2 ;

[0034] Figure 8 is a structural block diagram of a cache consistency control device in a multi-core processor system provided by an embodiment of the present invention;

[0035] Fig. 9 is a structural block diagram of a second cache consistency control device in a multi-core processor system provided in an embodiment of the present invention;

[0036] Fig.10 is a structural block diagram of a computer device according to an embodiment of the present invention. DETAILED DESCRIPTION

[0037] In order to enable those skilled in the art to better understand the scheme of the present invention, the technical scheme in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the present invention.

[0038] It should be noted that the terms "first", "second", etc. in the specification and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged where appropriate, so that the embodiments of the present invention described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units that are clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0039] First, some nouns or terms that appear in the description of the embodiments of the present application are subject to the following explanations:

[0040] Multi-core Read-Modify-Write scenario: refers to the situation in which multiple processor cores in a multi-core processor system access and modify shared data at the same time. In this scenario, the processor cores need to read and write shared data to achieve parallel computing and data sharing.

[0041] Shared data: refers to data that can be accessed by multiple processor cores in a multi-core processor system.

[0042] Multi-core consistency: refers to the ability to maintain data consistency and synchronization between multiple processor cores in a multi-core processor system. In a multi-core processor system, each processor core can execute tasks independently, but multiple processor cores need to share certain data and resources. In order to ensure the correctness and performance of the system, multi-core consistency needs to be achieved, among which cache consistency is one aspect involved.

[0043] Cache consistency: In a multi-core processor system, each processor core may have its own cache. When one processor core modifies data, other processor cores need to be able to see the change to maintain data consistency. This is usually achieved through a cache consistency protocol such as the MESI protocol ((Modified, Exclusive, Shared, Invalid) - the four states involved in the protocol)).

[0044] Cache Coherence Protocol: It is a mechanism used to ensure that the data stored in the cache of each processor core in a multi-core processor system remains consistent. In a multi-core processor system, each processor core has its own cache to store a copy of shared data. When one processor core modifies shared data, the data in the cache of other processor cores may become outdated. The main purpose of the cache consistency protocol is to ensure that all processor cores can obtain the latest copy of the data when accessing shared data. For example, the cache consistency protocol (MESI protocol) divides the states of cache lines into four types: Modified, Exclusive, Shared, and Invalid. Through these four states, the MESI protocol can effectively manage the consistency of cache lines.

[0045] Cache line (or cache block): refers to the fact that in the cache system of the processor core, data is divided into fixed-size units, which are called cache lines. The size of a cache line can be 32 bytes, 64 bytes, or 128 bytes, etc. When the processor core accesses memory, it loads data into cache lines instead of single bytes or words. Cache line is the smallest data unit for consistency protocol operations.

[0046] A processor core refers to two or more complete computing engines (cores) integrated into a processor (i.e., a multi-core processor). In this case, the processor can support multiple processor cores on the system bus, and the bus controller provides all bus control signals and command signals. Multi-core systems are easier to expand and can incorporate more powerful processing performance in a more compact form factor. This approach uses less power and generates less heat from computing power consumption.

[0047] The processor, generally the central processing unit (CPU), is the computing and control core of the computer system and the final execution unit for information processing and program running. The CPU is one of the main devices of an electronic computer and the core component of a computer device. Its main function is to interpret computer instructions and process data in computer software. The CPU is the core component of the computer responsible for reading instructions, decoding instructions and executing instructions. The central processing unit core mainly includes two parts, namely the controller and the arithmetic unit, which also includes a cache memory and a data and control bus that realizes the connection between them. The three core components of an electronic computer are the CPU, internal memory, and input / output devices. The functions of the central processing unit core are mainly to process instructions, execute operations, control time, and process data. In computer architecture, the CPU is the core hardware unit that controls and allocates all hardware resources of the computer (such as memory, input and output units) and performs general operations. The CPU is the computing and control core of the computer. The operations of all software layers in the computer system will eventually be mapped to the operations of the CPU through the instruction set. There are many types of processors. For example, according to the number of processing cores, they can be divided into single-core processors and multi-core processors.

[0048] System on Chip (SoC) is a system-level chip, which means it is a product, an integrated circuit with a dedicated purpose, which contains all the contents of a complete system and embedded software. It is a technology used to achieve the whole process from determining the system function to the software / hardware division and completing the design. SoC fully integrates the main chip of CPU, communication and other modules.

[0049] MESI status explanation:

[0050] M: Modified, indicating that this cacheilne has been modified in the processor core and does not appear in other processor cores;

[0051] E: Exclusive, indicating that this cacheline is exclusive to the processor core and does not appear in other processor cores, but has not been modified;

[0052] S: Shared, indicating that this cacheline may appear in multiple processor cores and has not been modified;

[0053] I: Invalid, indicating that the cacheline does not exist in this processor core;

[0054] Clean: Indicates that the cacheline is consistent with the value in the next level of storage structure. It can also indicate that the cacheline has not been modified.

[0055] Dirty: Indicates that the cacheline is inconsistent with the value in the next layer of storage structure. It can also mean that the cacheline has been modified.

[0056] Data Migration: Based on the data access mode, complete the pre-movement of data and the movement of permissions. Data migration includes: selecting, extracting, preparing and converting data, and transferring data from one computer storage system to another.

[0057] Example 1

[0058] According to an embodiment of the present invention, a method embodiment of a cache consistency control method in a multi-core processor system is also provided. It should be noted that the steps shown in the flowchart of the accompanying drawings can be executed in a computer system such as a set of computer executable instructions, and although the logical order is shown in the flowchart, in some cases, the steps shown or described can be executed in an order different from that shown here.

[0059] The method embodiment provided in Embodiment 1 of the present application can be executed in a mobile terminal, a computer terminal or a similar computing device. Figure 1 FIG. 1 shows a hardware structure block diagram of a system on chip for implementing a cache consistency control method in a multi-core processor system. Figure 1 As shown, the system on chip may include a multi-core processor 102 (including processor core 102a, processor core 102b, ..., processor core 102n, the processor core may include but is not limited to a processing device such as a microprocessor MCU or a programmable logic device FPGA), a memory 104 for storing data, and a transmission device for communication functions. In addition, it may also include: an input / output interface (I / O interface), a universal serial bus (USB) port (which may be included as one of the ports of the BUS bus), and a network interface. It can be understood by those skilled in the art that Figure 1 The structure shown is for illustration only and does not limit the above structure. Figure 1 More or fewer components as shown, or with Figure 1 Different configurations are shown.

[0060] It should be noted that the one or more processor cores and / or other data processing circuits described above may generally be referred to herein as "data processing circuits". The data processing circuits may be embodied in whole or in part as software, hardware, firmware, or any other combination thereof. In addition, the data processing circuit may be a single independent processing module, or may be incorporated in whole or in part into any of the other components of the system on chip. As involved in the embodiments of the present application, the data processing circuit acts as a processor core control (e.g., selection of a variable resistor terminal path connected to an interface).

[0061] The memory 104 can be used to store software programs and modules of application software, such as program instructions / data storage devices corresponding to the cache consistency control method in the multi-core processor system in the embodiment of the present invention. The processor core executes various functional applications and data processing by running the software programs and modules stored in the memory 104, that is, the cache consistency control method in the multi-core processor system of the above-mentioned application is realized. The memory 104 may include a high-speed random access memory, and may also include a non-volatile memory, such as one or more magnetic storage devices, flash memory, or other non-volatile solid-state memory. In some instances, the memory 104 may further include a memory remotely arranged relative to the processor core, and these remote memories may be connected to the system on chip via a network. The above-mentioned network interface is used to connect to various types of networks. For example, examples of networks include but are not limited to the Internet, corporate intranets, local area networks, mobile communication networks, and combinations thereof.

[0062] As mentioned above, for shared data, there are generally multiple different processor cores in a multi-core processor system, which write to the same cacheline at different times. In this scenario, since one RMW needs to send two requests to the on-chip interconnect network, as well as the possible associated snoop (sniffing, detecting the status of other processor cores) requests, the pressure on the interconnect network will be greatly increased. In addition, the delay caused by the two permission requests is also relatively large, which will have a relatively large negative impact on the overall performance.

[0063] Figure 2 is a schematic diagram of a MESI consistency protocol solution in a related art for comparison in Example 1 of the present invention, such as Figure 2 As shown, taking a dual-core system as an example, in the RMW scenario, the MESI consistency protocol solution (or baseline solution) is processed as follows:

[0064] In the process of this solution, Core0 and Core1 perform RMW operations successively. When Core0 performs the operation, because the cacheline being operated at this time is not in any processor core, that is, in any processor core in the system, the status of this cacheline is Invalid. The operation performed by Core0 at this time will not involve other snoops on the processor core, which can be considered as the most ideal state. It is necessary to obtain permissions twice. The first time is when the load instruction is executed, the S (shared, read only) state is obtained from the bus, and the second time is when the modify instruction is executed, the E (exclusive, readable and writable) state is obtained from the bus. However, when Core1 performs the operation, since Core0 in the system holds a valid cacheline (that is, in any state of M / S / E), in order to maintain the cache consistency of the system, each request of Core1 will generate a snoop at the system bus, resulting in additional time consumption, which will have a greater negative impact on the overall performance of the system.

[0065] To solve the above problems, the present application provides Figure 3 The method shown. Figure 3 is a flow chart of a cache consistency control method 1 in a multi-core processor system according to Embodiment 1 of the present invention. Figure 3 As shown, the process includes the following steps:

[0066] Step S302, sending a read request of the current processor core for the cache line to an interconnection network node, wherein the interconnection network node is used to maintain consistency of cache lines among multiple processor cores in a multi-core processor system;

[0067] Step S304, receiving other permission states of other processor cores to the cache line sent by the interconnection network node, wherein the other processor cores are processor cores other than the current processor core among multiple processor cores in the multi-core processor system;

[0068] Step S306 , determining the current permission state of the current processor core with respect to the cache line according to other permission states of other processor cores with respect to the cache line, wherein the current permission state is an exclusive state higher than a shared state.

[0069] In an embodiment of the present invention, after sending a read request for the current processor core to the cache line, the current permission state of the current processor core to the cache line is determined according to other permission states of other processor cores to the cache line, wherein the current permission state is an exclusive state higher than the shared state. Since the determined current permission state is higher than the exclusive state of the shared state, the purpose of cache line write processing can be achieved when sending a read request once, thereby achieving the technical effect of reducing the communication overhead in cache consistency maintenance and improving the overall performance of the system, and further solving the technical problem in the related art that when data sharing is realized in a multi-core processor system, there are at least two interactions for the data write processing initiated by each processor core, which occupies too many communication resources.

[0070] As an optional embodiment, the execution subject of the cache consistency control method 1 in the multi-core processor system can be each processor core in the multi-core processor system. Each processor core sends a read request to the interconnected network node in the multi-core processor system, and then determines the permission status of each processor core itself to the cache line based on the permission status of other processor cores sent by the interconnected network node. After that, corresponding processing can be performed based on the permission status of each processor core itself to the cache line. It should be noted that each processor core can be applied to a variety of data processing, and the data type can also be multiple. For example, it can be text, it can also be an image, it can also be voice, video, etc. In addition, the read request sent by the above-mentioned processor cores to the interconnected network node can be a read request that is different from the read request that initiates data sharing under the MESI protocol in the related technology. The read request can be a request to request the status of other processor cores from the interconnected network node.

[0071] As an optional embodiment, when receiving other permission states of cache lines sent by other processor cores of the interconnected network node, multiple methods can be used. For example, after receiving the read request sent by the current processor core, a sniffing request can be sent to one or more other processor cores respectively to request to obtain the state of the cache line of the one or more other processor cores. When receiving the state of the cache line fed back by the one or more other processor cores, the interconnected network node can directly send the state of the cache line fed back by the one or more other processor cores to the current processor core, and the current processor core sorts out the state of the cache line fed back by the one or more other processor cores to obtain other permission states of the cache line of the one or more other processor cores, where the other permission state can be a sorting result that characterizes the state of the cache line of the one or more other processor cores. For another example, after receiving the read request sent by the current processor core, a sniffing request can be sent to one or more other processor cores respectively to request to obtain the state of the cache line of the one or more other processor cores. When receiving the state of the cache line fed back by the one or more other processor cores, the interconnected network node sorts out the state of the cache line fed back by the one or more other processor cores received, obtains the sorting result, and sends the sorting result to the current processor core. Since the previous interconnected network node has sorted out the state of the cache line for the one or more other processor cores, the current processor core can directly receive the sorted result. Compared with directly receiving the state of the cache line for the one or more other processor cores, the current processor core receives the sorted result of the previous interconnected network node. Since the sorting of the interconnected network node is relatively faster, the current processor core directly receives the sorted result in a more efficient manner.

[0072] As an optional embodiment, when determining the current permission state of the current processor core to the cache line based on other permission states of other processor cores to the cache line, if the other permission states of other processor cores to the cache line are different, the current permission state of the cache line corresponding to the current processor core may also be different. For example, when the other permission states represent that no processor core in other processor cores holds the cache line, the current permission state of the current processor core to the cache line is determined to be an exclusive state; or, when the other permission states represent that a processor core in other processor cores holds the cache line in a modified state, the current permission state of the current processor core to the cache line is determined to be an exclusive state. By sorting out the states of other processor cores to the cache line, the current permission state of the current processor core to the cache line can be directly determined, and the determined current permission state can be an exclusive state, that is, the cache line can be directly modified and written without sending a write request again to obtain write permission.

[0073] As an optional embodiment, the method further includes: when other permission states represent that a processor core in other processor cores holds the cache line in a shared state or an exclusive state, determining that the current permission state of the current processor core to the cache line is a shared state. Therefore, for this special scenario, the current permission state of the current processor core to the cache line can be directly determined as a shared state. This effectively involves various states in the multi-core processor system where the current processor core is located.

[0074] As an optional embodiment, the current processor core may initiate a read request, and of course, before or after sending the read request, it may also accept status detection of other processor cores. For example, the method may also include: receiving a sniffing request sent from an interconnected network node; in response to the sniffing request, determining the sniffed permission state of the sniffer according to the permission state of the current processor core as the sniffer.

[0075] As an optional embodiment, in response to a sniffing request, when determining the sniffed permission state of the sniffer according to the permission state of the current processor core as the sniffer, the determined permission state of the sniffer may also be different according to the different permission states of the current processor core. For example, it may include at least one of the following: when the permission state of the current processor core as the sniffer is an invalid state indicating that the current processor core does not hold a cache line, the sniffer permission state of the sniffer is maintained in an invalid state; when the permission state of the current processor core as the sniffer is a shared state or an exclusive state, the sniffer permission state of the sniffer is updated to a shared state; when the permission state of the current processor core as the sniffer is a modified state, the sniffer permission state of the sniffer is updated to an invalid state. With the above processing, when the current processor core is the object of sniffing, when receiving a sniffing request initiated by other processor cores, that is, a read request initiated by other processor cores, a corresponding change is made to its own state. For example, when the current processor core is currently processing an invalid state, the invalid state is maintained; when the current processor core is in a shared state or an exclusive state, it is updated to a shared state; when the current processor core is in a modified state, it is updated to an invalid state, that is, the modification authority is transferred to the requester who initiated the read request, that is, the other processor core that initiated the read request.

[0076] As an optional embodiment, in response to the sniffing request, after determining the sniffed permission state of the sniffer according to the permission state of the current processor core as the sniffer, the method further includes: sending the sniffing response to the interconnected network node, wherein the sniffing response carries the state of the sniffer before being sniffed and / or the updated state after being sniffed. With the above processing, when the current processor core is the object to be sniffed, the state of the current processor core after being sniffed is updated and synchronized to the interconnected network node, and the interconnected network node uniformly maintains the states of each processor core in the multi-core processor system.

[0077] As an optional embodiment, after determining the current permission state of the current processor core to the cache line according to other permission states of other processor cores to the cache line, it also includes: sending a read request response to an interconnection network node, wherein the read request response carries the current permission state of the current processor core to the cache line. With the above processing, when the current processor core initiates a read request, the determined state of the current processor core is synchronized to the interconnection network node, and the interconnection network node uniformly maintains the states of each processor core in the multi-core processor system.

[0078] In an embodiment of the present invention, a cache consistency control method in a multi-core processor system is also provided. Figure 4 is a flow chart of a second cache consistency control method in a multi-core processor system according to Embodiment 1 of the present invention. Figure 4 As shown, the process includes the following steps:

[0079] Step S402, receiving a read request for a cache line sent by the current processor core;

[0080] Step S404, obtaining other permission states of other processor cores in the multi-core processor system for the cache line, wherein the other processor cores are processor cores other than the current processor core among the multiple processor cores in the multi-core processor system;

[0081] Step S406, sending other permission states of other processor cores to the cache line to the current processor core, wherein other permission states of other processor cores to the cache line are used to determine the current permission state of the current processor core to the cache line, wherein the current permission state is an exclusive state higher than the shared state.

[0082] As an optional embodiment, the execution subject of the cache consistency control method 1 in the multi-core processor system may be an interconnection network node in the multi-core processor system. The interconnection network node is used to maintain the consistency of cache lines of multiple processor cores in the multi-core processor system.

[0083] As an optional embodiment, obtaining other permission states of cache lines of other processor cores in a multi-core processor system includes: sending a sniff request to other processor cores in the multi-core processor system; receiving a sniff response fed back by other processor cores, wherein the sniff response carries the state of other processor cores before being sniffed and / or the updated state after being sniffed. With the above processing, the interconnected network nodes can, on the one hand, promptly learn the permission states of other processor cores by receiving the updated states of other processor cores after being sniffed, and send the permission states to the current processor core, so that the current processor core can promptly determine the current permission state based on the permission state. On the other hand, the interconnected network nodes can also effectively maintain the consistency of the multi-core processor system based on the obtained permission states of other processor cores.

[0084] As an optional embodiment, the method further includes: receiving a read request response fed back by the current processor core, wherein the read request response carries the current permission status of the current processor core to the cache line. By receiving the current permission status of the current processor core to the cache line, the interconnected network node can effectively maintain the consistency of data of each processor core in the multi-core processor system.

[0085] In the above-mentioned embodiment and optional embodiments, compared with the baseline solution in the related art which first obtains a data copy and then invalidates the copies in other processor cores through snoop to obtain the processing flow of permissions, the present application proposes a data migration idea, that is, through the analysis of the data access mode (that is, the permissions actually required for the data in multiple processor cores), if it is considered that the data access meets the characteristics of RMW, then the data will be directly migrated to the processor core that requests this cacheline.

[0086] That is, based on data migration and according to the data access mode, a data consistency protocol solution with low latency and low implementation cost is provided. Compared with the consistency protocol in the related art, the data consistency protocol solution provided by the embodiment of the present invention can determine the access mode of the processor core to the data based on the state of the cacheline in the current processor core. According to the access mode of the processor core to the data, it is determined whether the data should be shared among multiple cores or migrated exclusively to other processor cores.

[0087] As described in the above-mentioned embodiments and optional embodiments, the data consistency protocol scheme provided by the embodiments of the present invention includes: processing of cacheline state changes on the processor core side, processing of requests sent by loadmiss (read miss) on the processor core side, and processing of operations after the interconnection network side (interconnection network node) responds to the read request.

[0088] In combination with the above embodiment and the optional embodiment, an optional implementation manner is provided.

[0089] Figure 5 is a schematic diagram of a multi-core processor system with data consistency according to Embodiment 1 of the present invention, such as Figure 5 As shown, the system includes:

[0090] 110: Processor core.

[0091] 120: Private cache of the processor core.

[0092] 130: A consistency maintenance node connected to the processor core and the private cache of the processor core.

[0093] 140: A channel for consistency maintenance nodes and on-chip interconnections, including a bidirectional request path, a bidirectional data path, and a bidirectional response path.

[0094] 150: An on-chip interconnection network (interconnection network node) for maintaining data consistency between multiple processor cores.

[0095] 160: A multi-core shared cache structure connected to the interconnection network.

[0096] In this system, the processor core side cache state transition follows the following principles:

[0097] Table 1 is a table of cache state changes caused by the read operation of this core (this processor core), as shown in Table 1,

[0098]

[0099]

[0100] Table 1

[0101] Table 2 is a table of cache state changes caused by external read operations. As shown in Table 2,

[0102]

[0103] Table 2

[0104] Figure 6 is a schematic diagram of a cache consistency control method in a multi-core processor system provided according to an optional embodiment of the present invention Figure 1 ,like Figure 6 As shown, in this method, for all load accesses (referred to as load accesses or read requests), a Read_Prefer_EorM transaction is used to obtain a copy, wherein the method includes:

[0105] 210:Read_Prefer_EorM is a read request sent from a consistency node to the interconnect network, following the following principles:

[0106] When no other member (other consistency node) in the system holds this cache block, the requester will finally get the cache block in Exclusive state;

[0107] When there are other members in the system that hold this cache block in the Shared state or the Exclusive state, the requester will eventually get the cache block in the Shared state;

[0108] When there are other members in the system that hold this cache block in the Modified state, the requester will eventually get the cache block in the Exclusive state.

[0109] 220: Indicates the data and completion identifier returned by the interconnection network, as well as the final status of the requester (Exclusive).

[0110] 310: SnoopRespData_S, indicating a snoop response with data, and the final state of the sniffer is Shared.

[0111] 320: CompData_S: indicates a request response with data, and the final status of the requester is Shared.

[0112] 330:Read_E: Indicates requesting permission for this cacheline Exclusive.

[0113] 340:Snoop_E: indicates the snoop request derived from Read_E, and the final requester status is Exclusive.

[0114] 350:SnoopResp_I: indicates a snoop response without data, and the final status of the sniffer is Invalid.

[0115] 360:Comp_E: Indicates a request response without data, and the final status of the requester is Exclusive.

[0116] 230: Indicates that the requester has received a completion flag, which is used to maintain order, that is, to ensure that requests to the same address are processed in the order in which they are received in the interconnected network.

[0117] 240: Snoop_Prefer_EorM is a sniff request generated by 210, which is used to detect the status of this cache block in other nodes and follows the following principles:

[0118] When the sniffer's status is Invalid, it returns a response to the bus, indicating that it is Invalid, and its own cache block status remains unchanged;

[0119] When the sniffer's state is Shared or Exclusive, it changes its own cache block state to Shared, returns a response (or a response with data) to the bus, indicating to the bus that its own cache block state is finally Shared;

[0120] When the sniffer's state is Modified, it changes the state of its own cache block to Invalid, returns a response with data to the bus, and indicates to the bus that the state of its own cache block is finally Invalid.

[0121] 250: Sniffing response with data, indicating that the last status of the sniffer is Invalid.

[0122] 260: Completion response with data, indicating that the requester's final status is Exclusive.

[0123] Figure 7 is a schematic diagram of a cache consistency control method in a multi-core processor system provided according to an optional embodiment of the present invention Figure 2 ,like Figure 7 As shown, in this method, for a snoop request of the Snoop_Prefer_EorM type, when the corresponding cacheline state of the sniffer is in the Exclusive / Shared state, there are the following processes, including:

[0124] In the above process, since the state of the sniffer is Exclusive / Shared, the data has not changed compared to the shared cache / main memory. In this embodiment, such a scenario is considered not to be in the RMW scenario, and this cacheline is likely to be shared between multiple processor cores, and they all only need the read permission of this cacheline, so the final state of the sniffer and the requester will be changed to Shared. If a processor core needs write permission to operate, it needs to re-initiate the Read_E operation, which has no additional performance loss compared to the baseline solution in the related technology.

[0125] It should be noted that for the detection of RMW scenarios, currently only the state of the cache block is simply referenced for judgment. However, when the processor core processes load-store pairs with overlapping addresses, there may be a situation where the sniff request is executed between the load-store pairs, resulting in performance that is not as good as expected. Additional structures can be used for training to predict whether there is an RMW scenario, so as to maintain the atomicity between load-store pairs as much as possible and reduce the extra time consumed on the interconnection network.

[0126] In the scheme in the related art, obtaining permissions requires two steps (first obtaining load permissions, then obtaining store permissions), and the steps for obtaining permissions in this scheme are relatively complicated. The two-step permission request approach also introduces more transmission on the interconnected network, which wastes a lot of bandwidth, and the permission request process will bring about a large delay, which also has a large negative impact on performance. In addition, the scheme in the related art also has a lag in detecting the change of data from shared to exclusive. Only when a processor core initiates a write permission request will the data become exclusive, resulting in the processor core that does not need the cache block holding the cache block in a shared state, resulting in a waste of space.

[0127] The above-mentioned solution of the optional implementation mode has the following advantages compared with the solution in the related art:

[0128] In the case of a read cache miss, the processor core will try to request a higher priority for the interconnect bus. Since write permission can be applied for, the subsequent instructions can reduce the number of permission requests, which can reduce latency and bandwidth usage.

[0129] In the case of space waste, since the processor core sends fewer read permission requests to the bus, the proportion of shared copies appearing in the private cache of each processor core is reduced, thereby reducing space waste.

[0130] Therefore, the consistency maintenance method provided in the optional implementation of the present invention simplifies the process of obtaining permissions, tries to obtain higher permissions, reduces the number of bus requests, and reduces processing delays. Based on the multi-core Read-Modify-Write scenario, it is optimized at the consistency protocol level, reducing the bandwidth pressure on the interconnected network and the delay in obtaining the corresponding cacheline write permission, and has good prospects in large-scale applications such as data centers.

[0131] It should be noted that, for the above-mentioned method embodiments, for the sake of simplicity, they are all described as a series of action combinations, but those skilled in the art should know that the present invention is not limited by the described action sequence, because according to the present invention, certain steps can be performed in other sequences or simultaneously. Secondly, those skilled in the art should also know that the embodiments described in the specification are all preferred embodiments, and the actions and modules involved are not necessarily required by the present invention.

[0132] Through the description of the above implementation methods, those skilled in the art can clearly understand that the method according to the above embodiment can be implemented by means of software plus a necessary general hardware platform, and of course can also be implemented by hardware, but in many cases the former is a better implementation method. Based on such an understanding, the technical solution of the present invention, or the part that contributes to the prior art, can be embodied in the form of a software product, which is stored in a computer storage medium (such as ROM / RAM, magnetic disk, optical disk), and includes a number of instructions for a terminal device (which can be a mobile phone, a computer, a server, or a network device, etc.) to execute the methods of various embodiments of the present invention.

[0133] Example 2

[0134] According to an embodiment of the present invention, a device for implementing the cache consistency control method 1 in the multi-core processor system is also provided. The device can be applied to a processor core in the multi-core processor system. Figure 8 is a structural block diagram of a cache consistency control device in a multi-core processor system provided according to an embodiment of the present invention, such as Figure 8 As shown, the device includes: a first sending module 82, a first receiving module 84 and a first determining module 86. The device is described below.

[0135] A first sending module 82 is used to send a read request of the current processor core for the cache line to the interconnected network node, wherein the interconnected network node is used to maintain the consistency of cache lines among multiple processor cores in a multi-core processor system; a first receiving module 84 is connected to the above-mentioned first sending module 82, and is used to receive other permission states of other processor cores for the cache line sent by the interconnected network node, wherein the other processor cores are processor cores other than the current processor core among multiple processor cores in the multi-core processor system; a first determining module 86 is connected to the above-mentioned first receiving module 84, and is used to determine the current permission state of the current processor core for the cache line according to other permission states of other processor cores for the cache line, wherein the current permission state is an exclusive state higher than the shared state.

[0136] It should be noted here that the above-mentioned first sending module 82, first receiving module 84 and first determining module 86 correspond to steps S302 to S306 in Example 1, and the instances and application scenarios implemented by the two modules and the corresponding steps are the same, but are not limited to the contents disclosed in the above-mentioned Example 1.

[0137] According to an embodiment of the present invention, a device for implementing the second cache consistency control method in the multi-core processor system is also provided. The device can be applied to the bus end (i.e., the interconnection network (node) end) in the multi-core processor system. Fig. 9 is a structural block diagram of a cache consistency control device 2 in a multi-core processor system provided according to an embodiment of the present invention, such as Fig. 9 As shown, the device includes: a second receiving module 92, an acquisition module 94 and a second sending module 96. The device is described below.

[0138] A second receiving module 92 is used to receive a read request for a cache line sent by the current processor core; an acquisition module 94 is connected to the second receiving module 92, and is used to obtain other permission states of other processor cores in the multi-core processor system for the cache line, wherein the other processor cores are processor cores other than the current processor core among the multiple processor cores in the multi-core processor system; a second sending module 96 is connected to the acquisition module 94, and is used to send other permission states of other processor cores for the cache line to the current processor core, wherein the other permission states of other processor cores for the cache line are used to determine the current permission state of the current processor core for the cache line, wherein the current permission state is an exclusive state higher than the shared state.

[0139] It should be noted here that the above-mentioned second receiving module 92, acquisition module 94 and second sending module 96 correspond to steps S402 to S406 in Example 1, and the instances and application scenarios implemented by the two modules and the corresponding steps are the same, but are not limited to the contents disclosed in the above-mentioned Example 1.

[0140] Example 3

[0141] The embodiment of the present invention may provide a computing device, which may be any computing device in a computing device group. Optionally, in this embodiment, the computing device may also be replaced by a terminal device such as a mobile terminal.

[0142] Optionally, in this embodiment, the computing device may be located in at least one network device among a plurality of network devices of the computing network.

[0143] In this embodiment, the above-mentioned computing device can execute the program code of the following steps in the cache consistency control method in the multi-core processor system of the application: sending a read request for a cache line by the current processor core to an interconnected network node, wherein the interconnected network node is used to maintain the consistency of cache lines among multiple processor cores in the multi-core processor system; receiving other permission states of cache lines from other processor cores sent by the interconnected network node, wherein the other processor cores are processor cores other than the current processor core among multiple processor cores in the multi-core processor system; determining the current permission state of the current processor core to the cache line based on the other permission states of the other processor cores to the cache line, wherein the current permission state is an exclusive state higher than the shared state.

[0144] Optionally, Fig.10 is a structural block diagram of a computing device according to an embodiment of the present invention. Fig.10 As shown, the computing device may include: Figure 1 The system-on-chip (SOC) chip of the structure shown includes: one or more (only one is shown in the figure) processor cores 102, a memory 104, etc.

[0145] Among them, the memory can be used to store software programs and modules, such as the program instructions / modules corresponding to the cache consistency control method and device in the multi-core processor system in the embodiment of the present invention. The processor core executes various functional applications and data processing by running the software programs and modules stored in the memory, that is, the cache consistency control method in the multi-core processor system mentioned above is realized. The memory may include a high-speed random access memory, and may also include a non-volatile memory, such as one or more magnetic storage devices, flash memory, or other non-volatile solid-state memory. In some instances, the memory may further include a memory remotely arranged relative to the processor core, and these remote memories may be connected to the computing device via a network. Examples of the above-mentioned network include, but are not limited to, the Internet, an intranet, a local area network, a mobile communication network, and combinations thereof.

[0146] The processor core can call the information and application programs stored in the memory through the transmission device to perform the following steps: send a read request for a cache line by the current processor core to an interconnected network node, wherein the interconnected network node is used to maintain the consistency of cache lines among multiple processor cores in a multi-core processor system; receive other permission states of cache lines from other processor cores sent by the interconnected network node, wherein the other processor cores are processor cores other than the current processor core among multiple processor cores in the multi-core processor system; determine the current permission state of the current processor core to the cache line based on the other permission states of the other processor cores to the cache line, wherein the current permission state is an exclusive state higher than a shared state.

[0147] Optionally, the processor core may also execute program code of the following steps: determining the current permission state of the current processor core to the cache line based on other permission states of other processor cores to the cache line, including: when the other permission states represent that no processor core in other processor cores holds the cache line, determining that the current permission state of the current processor core to the cache line is an exclusive state; or, when the other permission states represent that a processor core in other processor cores holds the cache line in a modified state, determining that the current permission state of the current processor core to the cache line is an exclusive state.

[0148] Optionally, the processor core may also execute the following program code: when other permission states indicate that other processor cores hold cache lines in a shared state or an exclusive state, determine that the current permission state of the current processor core for the cache line is a shared state.

[0149] Optionally, the processor core may also execute program code of the following steps: receiving a sniffing request sent from an interconnected network node; and in response to the sniffing request, determining the sniffer permission status of the sniffer according to the permission status of the current processor core as the sniffer.

[0150] Optionally, the processor core may also execute the following program code: in response to a sniffing request, determining the sniffer permission state of the sniffer according to the permission state of the current processor core as the sniffer, including at least one of the following: when the permission state of the current processor core as the sniffer is an invalid state indicating that the current processor core does not hold a cache line, maintaining the sniffer permission state of the sniffer as an invalid state; when the permission state of the current processor core as the sniffer is a shared state or an exclusive state, updating the sniffer permission state of the sniffer to a shared state; when the permission state of the current processor core as the sniffer is a modified state, updating the sniffer permission state of the sniffer to an invalid state.

[0151] Optionally, the processor core may also execute the program code of the following steps: after responding to a sniffing request and determining the permission status of the sniffer according to the permission status of the current processor core as the sniffer, it also includes: sending a sniffing response to an interconnected network node, wherein the sniffing response carries the status of the sniffer before being sniffed and / or the updated status after being sniffed.

[0152] Optionally, the processor core may also execute the following program code: after determining the current permission status of the current processor core to the cache line based on other permission statuses of the cache lines of other processor cores, it also includes: sending a read request response to an interconnected network node, wherein the read request response carries the current permission status of the current processor core to the cache line.

[0153] The processor core can call the information and application programs stored in the memory through the transmission device to perform the following steps: receive a read request for a cache line sent by the current processor core; obtain other permission states of other processor cores in the multi-core processor system for the cache line, wherein the other processor cores are processor cores other than the current processor core among the multiple processor cores in the multi-core processor system; send other permission states of the other processor cores for the cache line to the current processor core, wherein the other permission states of the other processor cores for the cache line are used to determine the current permission state of the current processor core for the cache line, wherein the current permission state is an exclusive state higher than the shared state.

[0154] Optionally, the above-mentioned processor core can also execute the program code of the following steps: obtaining other permission states of cache lines by other processor cores in the multi-core processor system, including: sending a sniff request to other processor cores in the multi-core processor system; receiving a sniff response fed back by other processor cores, wherein the sniff response carries the state of other processor cores before being sniffed and / or the updated state after being sniffed.

[0155] Optionally, the processor core may further execute program code of the following steps: receiving a read request response fed back by the current processor core, wherein the read request response carries a current permission status of the current processor core to the cache line.

[0156] According to an embodiment of the present invention, after sending a read request for a cache line, the current permission state of the current processor core to the cache line is determined according to other permission states of other processor cores to the cache line, wherein the current permission state is an exclusive state higher than the shared state. Since the determined current permission state is higher than the exclusive state of the shared state, the purpose of writing to the cache line can be achieved when sending a read request once, thereby achieving the technical effect of reducing the communication overhead in cache consistency maintenance and improving the overall performance of the system, and further solving the technical problem in the related art that when data sharing is realized in a multi-core processor system, there are at least two interactions for the data write processing initiated by each processor core, which occupies too many communication resources.

[0157] It can be understood by those skilled in the art that Fig.10 The schematic diagram of the computing device structure shown is only for the purpose of illustration, and is not intended to limit the scope of this specification. Those skilled in the art can add or replace other components as needed.

[0158] Example 4

[0159] The embodiment of the present invention further provides a computer storage medium. Optionally, in this embodiment, the computer storage medium can be used to store the program code executed by the cache consistency control method in the multi-core processor system provided in the above embodiment 1.

[0160] Optionally, in this embodiment, the computer storage medium may be located in any one of the computing devices in the computing device group in the computer network, or in any one of the mobile terminals in the mobile terminal group.

[0161] Optionally, in this embodiment, the computer storage medium is configured to store program code for executing the following steps: sending a read request for a cache line from the current processor core to an interconnected network node, wherein the interconnected network node is used to maintain consistency of cache lines among multiple processor cores in a multi-core processor system; receiving other permission states for cache lines from other processor cores sent by the interconnected network node, wherein the other processor cores are processor cores other than the current processor core among multiple processor cores in the multi-core processor system; determining a current permission state of the current processor core for the cache line based on the other permission states for the cache line from other processor cores, wherein the current permission state is an exclusive state that is higher than a shared state.

[0162] Optionally, in this embodiment, the computer storage medium is also configured to store program code for executing the following steps: determining the current permission state of the current processor core to the cache line based on other permission states of other processor cores to the cache line, including: when the other permission states represent that no processor core in other processor cores holds the cache line, determining that the current permission state of the current processor core to the cache line is an exclusive state; or, when the other permission states represent that a processor core in other processor cores holds the cache line in a modified state, determining that the current permission state of the current processor core to the cache line is an exclusive state.

[0163] Optionally, in this embodiment, the computer storage medium is also configured to store program code for executing the following steps: when other permission states represent that there are processor cores in other processor cores holding the cache line in a shared state or an exclusive state, determining that the current permission state of the current processor core for the cache line is a shared state.

[0164] Optionally, in this embodiment, the computer storage medium is also configured to store program code for executing the following steps: receiving a sniffing request sent from an interconnected network node; in response to the sniffing request, determining the sniffer permission status of the sniffer based on the permission status of the current processor core as the sniffer.

[0165] Optionally, in this embodiment, the computer storage medium is also configured to store program code for executing the following steps: in response to a sniffing request, determining the sniffer permission state of the sniffer according to the permission state of the current processor core as the sniffer, including at least one of the following: when the permission state of the current processor core as the sniffer is an invalid state characterizing that the current processor core does not hold a cache line, maintaining the sniffer permission state of the sniffer as an invalid state; when the permission state of the current processor core as the sniffer is a shared state or an exclusive state, updating the sniffer permission state of the sniffer to a shared state; when the permission state of the current processor core as the sniffer is a modified state, updating the sniffer permission state of the sniffer to an invalid state.

[0166] Optionally, in this embodiment, the computer storage medium is also configured to store program code for executing the following steps: after determining the sniffer permission status of the sniffer based on the permission status of the current processor core as the sniffer in response to the sniffing request, the method also includes: sending the sniffing response to the interconnected network node, wherein the sniffing response carries the status of the sniffer before being sniffed and / or the updated status after being sniffed.

[0167] Optionally, in this embodiment, the computer storage medium is also configured to store program code for executing the following steps: after determining the current permission state of the cache line of the current processor core based on other permission states of the cache lines of other processor cores, it also includes: sending a read request response to an interconnected network node, wherein the read request response carries the current permission state of the cache line of the current processor core.

[0168] Optionally, in this embodiment, the computer storage medium is configured to store program code for performing the following steps: receiving a read request for a cache line sent by the current processor core; obtaining other permission states of other processor cores in the multi-core processor system for the cache line, wherein the other processor cores are processor cores other than the current processor core among multiple processor cores in the multi-core processor system; sending other permission states of the other processor cores for the cache line to the current processor core, wherein the other permission states of the other processor cores for the cache line are used to determine the current permission state of the current processor core for the cache line, wherein the current permission state is an exclusive state that is higher than the shared state.

[0169] Optionally, in this embodiment, the computer storage medium is also configured to store program code for executing the following steps: obtaining other permission states of cache lines by other processor cores in the multi-core processor system, including: sending a sniff request to other processor cores in the multi-core processor system; receiving a sniff response fed back by other processor cores, wherein the sniff response carries the state of the other processor cores before being sniffed and / or the updated state after being sniffed.

[0170] Optionally, in this embodiment, the computer storage medium is further configured to store program code for executing the following steps: receiving a read request response fed back by the current processor core, wherein the read request response carries the current permission status of the current processor core to the cache line.

[0171] The serial numbers of the above embodiments of the present invention are only for description and do not represent the advantages or disadvantages of the embodiments.

[0172] In the above embodiments of the present invention, the description of each embodiment has its own emphasis. For parts that are not described in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0173] In the several embodiments provided in this application, it should be understood that the disclosed technical content can be implemented in other ways. Among them, the device embodiments described above are only schematic. For example, the division of the units is only a logical function division. There may be other division methods in actual implementation. For example, multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, indirect coupling or communication connection of units or modules, which can be electrical or other forms.

[0174] The units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0175] In addition, each functional unit in each embodiment of the present invention may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit. The above-mentioned integrated unit may be implemented in the form of hardware or in the form of software functional units.

[0176] If the integrated unit is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present invention, in essence, or the part that contributes to the prior art, or all or part of the technical solution can be embodied in the form of a software product, and the computer software product is stored in a computer storage medium, including a number of instructions for a computer device (which can be a personal computer, a server or a network device, etc.) to perform all or part of the steps of the method described in each embodiment of the present invention. The aforementioned computer storage medium includes: U disk, read-only memory (ROM, Read-Only Memory), random access memory (RAM, Random Access Memory), mobile hard disk, disk or optical disk and other media that can store program codes.

[0177] The above is only a preferred embodiment of the present invention. It should be pointed out that for ordinary technicians in this technical field, several improvements and modifications can be made without departing from the principle of the present invention. These improvements and modifications should also be regarded as the scope of protection of the present invention.

Claims

1. A cache consistency control method in a multi-core processor system, characterized in that: include: Sending a read request of the current processor core for the cache line to an interconnection network node, wherein the interconnection network node is used to maintain consistency of the cache line among multiple processor cores in the multi-core processor system; Receiving other permission states of other processor cores to the cache line sent by the interconnection network node, wherein the other processor cores are processor cores other than the current processor core in the multiple processor cores in the multi-core processor system; The current permission state of the current processor core with respect to the cache line is determined according to the other permission states of the other processor cores with respect to the cache line, wherein the current permission state is an exclusive state higher than a shared state.

2. The method according to claim 1, characterized in that The determining, according to the other permission states of the other processors checking the cache line, the current permission state of the current processor checking the cache line comprises: In a case where the other permission states represent that none of the other processor cores holds the cache line, determining that the current permission state of the current processor core to the cache line is an exclusive state; or In a case where the other permission states represent that a processor core among the other processor cores holds the cache line in a modified state, it is determined that the current permission state of the current processor core to the cache line is an exclusive state.

3. The method according to claim 1, characterized in that The method further comprises: When the other permission states represent that a processor core among the other processor cores holds the cache line in a shared state or an exclusive state, it is determined that the current permission state of the current processor core to the cache line is a shared state.

4. The method according to claim 1, characterized in that: The method further comprises: Receiving a sniffing request sent from the interconnected network node; In response to the sniffing request, the sniffee permission state of the sniffer is determined according to the permission state of the current processor core as the sniffer.

5. The method according to claim 4, characterized in that The step of determining the sniffer permission state of the sniffer according to the permission state of the current processor core as the sniffer in response to the sniffer request includes at least one of the following: When the permission state of the current processor core as the sniffer is an invalid state indicating that the current processor core does not hold the cache line, the sniffer permission state of the sniffer is kept in an invalid state; When the permission state of the current processor core as the sniffer is a shared state or an exclusive state, updating the sniffer permission state of the sniffer to a shared state; When the permission state of the current processor core as the sniffer is in the modified state, the sniffer permission state of the sniffer is updated to the invalid state.

6. The method according to claim 4, characterized in that After determining the sniffer permission state of the sniffer according to the permission state of the current processor core as the sniffer in response to the sniffer request, the method further includes: A sniffing response is sent to the interconnected network node, wherein the sniffing response carries the state of the sniffer before being sniffed and / or the updated state after being sniffed.

7. The method according to any one of claims 1 to 6, characterized in that After determining the current permission state of the cache line checked by the current processor according to the other permission states of the cache line checked by the other processors, the method further includes: A read request response is sent to the interconnection network node, wherein the read request response carries a current permission status of the current processor core to the cache line.

8. A cache consistency control method in a multi-core processor system, characterized in that: include: Receive a read request for a cache line sent by the current processor core; Acquire other permission states of other processor cores in the multi-core processor system to the cache line, wherein the other processor cores are processor cores other than the current processor core among the multiple processor cores in the multi-core processor system; The other permission states of the other processor cores for the cache line are sent to the current processor core, wherein the other permission states of the other processor cores for the cache line are used to determine the current permission state of the current processor core for the cache line, wherein the current permission state is an exclusive state higher than a shared state.

9. The method according to claim 8, characterized in that The obtaining other permission states of other processor cores in the multi-core processor system to the cache line includes: Sending a sniffing request to other processor cores in the multi-core processor system; Receive a sniff response fed back by the other processor cores, wherein the sniff response carries the state of the other processor cores before being sniffed and / or the updated state after being sniffed.

10. The method according to claim 8 or 9, characterized in that: The method further comprises: A read request response fed back by the current processor core is received, wherein the read request response carries a current permission status of the current processor core to the cache line.

11. A cache consistency control device in a multi-core processor system, characterized in that: include: A first sending module, configured to send a read request of a current processor core for a cache line to an interconnection network node, wherein the interconnection network node is configured to maintain consistency of the cache line among multiple processor cores in the multi-core processor system; A first receiving module, configured to receive other permission states of other processor cores to the cache line sent by the interconnection network node, wherein the other processor cores are processor cores other than the current processor core in the multiple processor cores in the multi-core processor system; The first determination module is used to determine the current permission state of the current processor core to the cache line according to the other permission states of the other processor cores to the cache line, wherein the current permission state is an exclusive state higher than a shared state.

12. A cache consistency control device in a multi-core processor system, characterized in that: include: A second receiving module, configured to receive a read request for a cache line sent by a current processor core; An acquisition module, configured to acquire other permission states of other processor cores in the multi-core processor system to the cache line, wherein the other processor cores are processor cores other than the current processor core among the multiple processor cores in the multi-core processor system; A second sending module is used to send other permission states of the other processor cores to the cache line to the current processor core, wherein the other permission states of the other processor cores to the cache line are used to determine the current permission state of the current processor core to the cache line, wherein the current permission state is an exclusive state higher than the shared state.

13. A processor, characterized in that: include: A plurality of processor cores, wherein the processors are configured to execute the method according to any one of claims 1 to 11.

14. A system on chip, characterized in that: include: One or more hardware units, a processor, and an interconnection device for communicating between hardware units or between hardware units and processors, wherein the processor includes multiple processor cores, and the processor is used to execute the method described in any one of claims 1 to 11.

15. A computing device, characterized in that: include: A memory and a processor, wherein The memory stores a computer program; The processor is used to execute the computer program stored in the memory, and when the computer program is run, the processor is enabled to execute the method according to any one of claims 1 to 11.

16. A computer program product, characterized in that The method comprises computer instructions, which, when executed by a processor, implement the method according to any one of claims 1 to 11.

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