Processor verification system, method and platform

Abstract

The invention discloses a processor verification system and method and a verification platform, and the system comprises a to-be-verified processor, a first storage unit and the verification platform, the to-be-verified processor executes an operation to generate a character string, converts the character string into an ASCII code, and stores the ASCII code in the first storage unit; therefore, the verification platform can print the character string converted from the ASCII code stored in the first storage unit, whether the to-be-verified processor is abnormal or not in the operation execution process can be determined based on the printing result, the abnormal position can be directly positioned based on the printing result when the abnormal position exists, the verification process is simplified, and the verification efficiency is improved. And the user experience is improved.

Description

Technical Field

[0001] The present application relates to the field of communication technology, and in particular to a processor verification system, method and verification platform. Background Art

[0002] For verification of an integrated processor, a verification staff usually writes test cases, which are then executed by a designated core of the integrated processor to implement verification of the designated core in the integrated processor.

[0003] However, this method for verifying integrated processors usually does not support the common formatted output function printf, which will result in the verification personnel not knowing where the execution is during the verification process, making it difficult to locate abnormal problems. Summary of the invention

[0004] In view of this, the present application provides a processor verification system, method and verification platform, and its specific solutions are as follows:

[0005] A processor verification system, comprising:

[0006] The processor to be verified is capable of executing the operation, obtaining the character string generated by executing the operation, and converting the character string into ASCII code;

[0007] A first storage unit, used for storing the ASCII code converted from the character string generated by the operation performed by the processor to be verified;

[0008] A verification platform is used for, when it is determined that the ASCII code is stored in the first storage unit, converting the target data stored in the first storage unit into a character string, and printing the character string to obtain a printing result; if it is determined based on the printing result that there is an abnormality in the data stored in the first storage unit, it is determined that there is an abnormality in the processor to be verified.

[0009] Furthermore, it also includes:

[0010] A second storage unit, used to obtain and store a verification instruction packet output by the verification platform when the verification condition is met;

[0011] The processor to be verified obtains the verification instruction package stored in the second storage unit, executes the verification instruction package, and stores the execution result in the second storage unit;

[0012] The verification platform obtains the execution result stored in the second storage unit, and determines whether the processor to be verified has an abnormality based on the execution result.

[0013] Furthermore, the verification instruction package output by the verification platform when the verification conditions are met includes:

[0014] The verification platform monitors the working state of the processor to be verified, and when determining that the processor to be verified is in an idle state, generates and outputs a verification instruction packet.

[0015] Furthermore, the verification platform generates and outputs a verification instruction package, including:

[0016] The verification platform determines the address value and operation data of the instruction to be executed in the processor to be verified. If there are multiple address values ​​and operation data for the instruction to be executed, and the multiple address values ​​are continuous, the first address value of the multiple address values ​​is stored in the address segment, and the multiple operation data are stored in the data segment in sequence. A verification instruction package consisting of multiple verification instructions is generated based on the address segment and the data segment, and the verification instruction package is output so that the verification processor can execute the multiple verification instructions in sequence based on the first address value stored in the address segment and the multiple operation data stored in the data segment.

[0017] Further, the processor to be verified obtains the verification instruction package stored in the second storage unit and executes the verification instruction package, including:

[0018] The processor to be verified reads the verification instruction package stored in the second storage unit to determine whether the verification instruction package is valid. If it is determined that the verification instruction package is valid, it is determined whether the processor to be verified is the processor specified by the verification instruction package. If the processor to be verified is the processor specified by the verification instruction package, the processor to be verified executes the verification instruction in the verification instruction package.

[0019] Further, the processor to be verified executes the verification instruction in the verification instruction package, including:

[0020] If the verification instruction in the verification instruction package is a read instruction, the processor to be verified executes the read instruction. When it is determined that the actual data read by executing the read instruction does not meet the requirement data of the read instruction, the actual data and the requirement data are converted into ASCII codes and stored in the first storage unit, so that the verification platform can print the character string converted from the ASCII code in the first storage unit.

[0021] Furthermore, it also includes:

[0022] If it is determined that the processor to be verified is different from the processor specified by the verification instruction packet, the processor to be verified executes a low power consumption instruction and enters a low power consumption state.

[0023] A processor verification method, comprising:

[0024] Monitoring whether an ASCII code is stored in the first storage unit, wherein the ASCII code is: a character string generated during the operation of the processor to be verified is converted into an ASCII code and stored in the first storage unit;

[0025] If it is determined that the ASCII code is stored in the first storage unit, convert the ASCII code into a character string, print the character string, and obtain a print result;

[0026] If it is determined based on the print result that the data stored in the first storage unit has an abnormality, it is determined that the processor to be verified has an abnormality.

[0027] Furthermore, it also includes:

[0028] When the verification conditions are met, a verification instruction packet is generated;

[0029] storing the verification instruction package in a second storage unit so that the processor to be verified specified by the verification instruction package can obtain and execute the verification instruction package;

[0030] Obtaining the execution result of the verification instruction packet executed by the processor to be verified stored in the second storage unit;

[0031] It is determined whether the processor has an abnormality based on the execution result.

[0032] A verification platform, characterized by comprising:

[0033] A monitoring unit, used to monitor whether an ASCII code is stored in the first storage unit, wherein the ASCII code is: a character string generated during the operation of the processor to be verified is converted into an ASCII code and stored in the first storage unit;

[0034] A printing unit, configured to convert the ASCII code into a character string when it is determined that the ASCII code is stored in the first storage unit, and print the character string to obtain a printing result;

[0035] a first determining unit, configured to determine that an abnormality exists in the processor to be verified when it is determined based on the printing result that an abnormality exists in the data stored in the first storage unit;

[0036] The verification platform also includes:

[0037] An instruction packet generating unit, configured to generate a verification instruction packet when a verification condition is met; and store the verification instruction packet in a second storage unit so that the processor to be verified specified by the verification instruction packet can obtain and execute the verification instruction packet;

[0038] The second determining unit is used to obtain the execution result of the processor to be verified stored in the second storage unit executing the verification instruction package; and determine whether the processor is abnormal based on the execution result.

[0039] It can be seen from the above technical scheme that the processor verification system, method and verification platform disclosed in the present application include: a processor to be verified, a first storage unit and a verification platform, wherein the processor to be verified can perform an operation, obtain a string generated by performing the operation, and convert the string into ASCII code; the first storage unit is used to store the ASCII code converted from the string generated by the processor to be verified performing the operation; the verification platform is used to convert the target data stored in the first storage unit into a string when it is determined that the ASCII code is stored in the first storage unit, and print the string to obtain the print result, if it is determined based on the print result that the data stored in the first storage unit is abnormal, it is determined that the processor to be verified is abnormal. In this scheme, after the processor to be verified performs an operation to generate a string and converts it into ASCII code, it is stored in the first storage unit, so that the verification platform can print the string converted from the ASCII code stored in the first storage unit, and based on the print result, it can be determined whether the processor to be verified has an abnormality in the process of performing the operation, and if there is an abnormality, the position of the abnormality can be directly located based on the print result, which simplifies the verification process and improves the user experience. BRIEF DESCRIPTION OF THE DRAWINGS

[0040] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the related technologies, the drawings required for use in the embodiments or the related technical descriptions are briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0041] Figure 1 A schematic diagram of the structure of a processor verification system disclosed in an embodiment of the present application;

[0042] Figure 2 A structural block diagram of a print verification process for a processor to be verified disclosed in an embodiment of the present application;

[0043] Figure 3 A schematic diagram of the structure of a processor verification system disclosed in an embodiment of the present application;

[0044] Figure 4 A schematic diagram of a verification instruction packet stored in a second storage unit disclosed in an embodiment of the present application;

[0045] Figure 5 A flowchart of a processor verification method disclosed in an embodiment of the present application;

[0046] Figure 6 A schematic diagram of the structure of a verification platform disclosed in an embodiment of the present application. DETAILED DESCRIPTION

[0047] The following describes the embodiments of the present application in conjunction with the drawings in the embodiments of the present application. The terms used in the implementation method section of the present application are only used to explain the specific embodiments of the present application, and are not intended to limit the present application.

[0048] The embodiments of the present application are described below in conjunction with the accompanying drawings. Those skilled in the art will appreciate that, with the development of technology and the emergence of new scenarios, the technical solutions provided in the embodiments of the present application are also applicable to similar technical problems.

[0049] The terms "first", "second", etc. in the specification and claims of the present application and the above-mentioned drawings are used to distinguish similar objects, and need not be used to describe a specific order or sequential order. It should be understood that the terms used in this way can be interchangeable under appropriate circumstances, which is only to describe the distinction mode adopted by the objects of the same attributes when describing in the embodiments of the present application. In addition, the terms "including" and "having" and any of their variations are intended to cover non-exclusive inclusions, so that the process, method, system, product or equipment comprising a series of units need not be limited to those units, but may include other units that are not clearly listed or inherent to these processes, methods, products or equipment.

[0050] The present application discloses a processor verification system, and its structural diagram is as follows: Figure 1 As shown, including:

[0051] A processor to be verified 11 , a first storage unit 12 and a verification platform 13 .

[0052] The processor 11 to be verified is capable of executing the operation, obtaining the character string generated by executing the operation, and converting the character string into ASCII code;

[0053] The first storage unit 12 is used to store the ASCII code converted from the character string generated by the operation performed by the processor 11 to be verified;

[0054] The verification platform 13 is used to convert the target data stored in the first storage unit into a character string when it is determined that ASCII code is stored in the first storage unit 12, and print the character string to obtain a printing result. If it is determined based on the printing result that there is an abnormality in the data stored in the first storage unit 12, it is determined that there is an abnormality in the processor 11 to be verified.

[0055] For verification of an integrated processor, a verification staff usually writes test cases, which are then executed by a designated core of the integrated processor to implement verification of the designated core in the integrated processor.

[0056] However, this method for verifying integrated processors usually does not support the common formatted output function printf, which will result in the verification personnel not knowing where the execution is during the verification process, making it difficult to locate abnormal problems.

[0057] Currently, waveforms are usually used to check whether there are problems in the execution process of the processor to be verified. However, the operation of waveform checking is relatively cumbersome and does not allow for rapid completion of processor verification.

[0058] Based on this, in this solution, during the process of the processor to be verified executing the operation, the ASCII code corresponding to the string generated by the execution of the operation is stored, and the verification platform converts the stored ASCII code into a string, and then prints the string, so as to determine whether the string is abnormal based on the printing result, and determine whether the processor to be verified is abnormal based on whether the string is abnormal.

[0059] During operation, the processor executes its pending operations, such as text processing, network communication, database operation, graphics rendering, script execution, etc.

[0060] When the processor is executing its operation to be executed, a character string is generated, such as writing the character string "HELLO". If the processor is a processor to be verified, the generated character string needs to be converted into ASCII code and the ASCII code is stored in the first storage unit.

[0061] The first storage unit may be a register or an address segment in the memory, as long as it can be accessed by the verification platform. The first storage unit is only used to store the ASCII code converted from the character string generated by the processor that needs to be verified by the verification platform.

[0062] The verification platform may access the first storage unit in real time, or the verification platform may access the first storage unit periodically so that the verification platform can verify the data stored in the first storage unit.

[0063] When the verification platform determines that ASCII code is stored in the first storage unit, the ASCII code stored in the first storage unit is read, and then the read ASCII code is converted into a character string, and the converted character string is printed to obtain a printing result, which presents the character string converted from the ASCII code read from the first storage unit.

[0064] Based on the printing result, it is determined whether there is an abnormality in the data stored in the first storage unit. If it is determined that there is an abnormality, it can be directly determined that there is an abnormality in the processor to be verified; if it is determined based on the printing result that there is no abnormality in the data stored in the first storage unit, it can be determined that there is no abnormality in the processor to be verified at present, and the processor to be verified can continue to be verified using the method disclosed in this embodiment to determine that when an abnormality occurs in the processor to be verified, the verification platform can directly determine based on the printing result, and the verification method is simple and convenient.

[0065] Among them, determining whether there is an abnormality in the data stored in the first storage unit based on the printing result can be specifically as follows: obtaining instruction information when controlling the processor to be verified to perform an operation, analyzing the instruction information, and determining the character string that needs to be generated by the processor to be verified to perform the operation based on the instruction information, wherein the instruction information controls the processor to be verified to perform an operation to generate a character string, and after the character string is generated, it is converted into ASCII code and stored in the first storage unit, and the verification platform reads the ASCII code, converts it into a character string, and prints it.

[0066] After the verification platform converts the ASCII code read from the first storage unit into a character string, it can determine whether there is an error indicator in the character string. If there is an error indicator, the verification platform prints the error information. If there is no error indicator, the verification platform prints directly. The error indicator can be "ERROR" included in the character string, or other specific information, which is not specifically limited here.

[0067] like Figure 2 As shown, it is a structural block diagram of printing verification for the processor to be verified. The processor CoreX to be verified can be a single-core processor or a processing core X in a multi-core processor. After executing the operation to generate a character string, it will call the API (Application Programming Interface) function. The API function is an application programming interface function. The API function can convert the character string into ASCII code and store the converted ASCII code in the first storage unit.

[0068] The monitoring module Monitor in the verification platform monitors the first storage unit. If it is determined that data is written in the first storage unit, the printing module in the verification platform converts the ASCII code in the first storage unit into a string ASCII2String, prints the string, and stores the printed information in a log file, such as: tw_displaylog file. At the same time, the verification result obtained by verifying the processor to be verified based on the printing result is stored in the testlog file.

[0069] In addition, the maximum string printing length of words can be constrained in the monitoring module Monitor to avoid endless information reporting when an abnormality occurs in the processor.

[0070] In the processor verification system disclosed in this embodiment, the verification platform prints the character string generated during the execution of the processor to be verified so as to verify it, thereby achieving accurate and timely determination of the status of the processor to be verified and simplifying the verification process.

[0071] The processor verification system disclosed in this embodiment includes: a processor to be verified, a first storage unit and a verification platform, wherein the processor to be verified can perform operations, obtain a character string generated by performing the operations, and convert the character string into ASCII code; the first storage unit is used to store the ASCII code converted from the character string generated by the processor to be verified performing the operations; the verification platform is used to convert the target data stored in the first storage unit into a character string when it is determined that the ASCII code is stored in the first storage unit, and print the character string to obtain a print result, and if it is determined based on the print result that the data stored in the first storage unit is abnormal, it is determined that the processor to be verified is abnormal. In this solution, after the processor to be verified performs the operation to generate a character string and converts it into ASCII code, it is stored in the first storage unit, so that the verification platform can print the character string converted from the ASCII code stored in the first storage unit, and based on the print result, it can be determined whether the processor to be verified has an abnormality in the process of performing the operation, and if there is an abnormality, the position of the abnormality can be directly located based on the print result, which simplifies the verification process and improves the user experience.

[0072] This embodiment discloses a processor verification system, and its structural diagram is shown in FIG. Figure 3 As shown, including:

[0073] A processor to be verified 31 , a first storage unit 32 , a verification platform 33 and a second storage unit 34 .

[0074] In addition to the same structure as the previous embodiment, a second storage unit is added in this embodiment.

[0075] The second storage unit is used to obtain and store the verification instruction package output by the verification platform when the verification condition is met.

[0076] The processor to be verified 31 obtains the verification instruction package stored in the second storage unit 34, executes the verification instruction package, and stores the execution result in the second storage unit 34;

[0077] The verification platform 33 obtains the execution result stored in the second storage unit 34, and determines whether there is an abnormality in the processor to be verified based on the execution result.

[0078] The second storage unit can be a register or an address segment in the memory, as long as it can store the instruction package and be accessed by the verification platform. The second storage unit is used to output the verification instruction package when the verification platform meets the verification conditions, and store the execution result obtained by the processor to be verified executing the verification instruction package.

[0079] The verification platform determines when to verify which processor or processors need to be verified, such as: the verification platform determines that the first processor needs to be verified for abnormality at a first moment, and determines that the second processor needs to be verified for abnormality at a second moment.

[0080] When the verification platform determines that a processor needs to be verified and determines that the verification conditions are currently met, it outputs a verification instruction package to the second storage unit. After the second storage unit obtains the verification instruction package, it stores it so that the processor to be verified can read the corresponding verification instruction package from the second storage unit.

[0081] The processor to be verified can read the information in the second storage unit in real time, or it can read the information in the second storage unit at a fixed time, or it can monitor the second storage unit using the monitoring module in the verification platform. As long as it is determined that information is stored in the second storage unit, it will read the relevant information from the second storage unit.

[0082] After the processor to be verified reads the verification instruction package from the second storage unit, it executes the verification instruction package read. After execution, an execution result will be obtained, and the execution result will be stored in the second storage unit. Of course, the execution result can also be stored in a third storage unit, which is different from the second storage unit.

[0083] Regardless of whether the execution result is stored in the second storage unit or the third storage unit, the verification platform will read the execution result from the storage unit storing the execution result, and analyze the execution result to determine whether there is an abnormality in the processor to be verified that executes the verification instruction package. If there is an abnormality in the processor to be verified, there must be a problem in the process or result of its execution of the verification instruction package. If there is no abnormality in the processor to be verified, the process and result of its execution of the verification instruction package must be normal. Therefore, when the execution result indicates that there is no problem with the process and result of the processor to be verified executing the verification instruction package, it can be determined that there is no abnormality in the processor to be verified. If the execution result indicates that there is a problem with the process or result of the processor to be verified executing the verification instruction package, it can be determined that there is an abnormality in the processor to be verified.

[0084] The processor verification system disclosed in this embodiment includes: a processor to be verified, a first storage unit, a verification platform and a second storage unit, wherein the second storage unit is used to obtain and store a verification instruction package output by the verification platform when the verification condition is met; the processor to be verified obtains the verification instruction package stored in the second storage unit, executes the verification instruction package, and stores the execution result in the second storage unit; the verification platform obtains the execution result stored in the second storage unit, and determines whether the processor to be verified has an abnormality based on the execution result. This solution stores the verification instruction package through the second storage unit, so that the processor to be verified reads the verification instruction package in the second storage unit and executes it to obtain the execution result, and the verification platform analyzes the execution result to determine whether the processor to be verified has an abnormality, thereby realizing the verification of whether the processor to be verified has an abnormality and simplifying the verification process.

[0085] Furthermore, in the processor verification system disclosed in this embodiment, the verification platform outputs a verification instruction packet when the verification condition is met, which may be specifically:

[0086] The verification platform monitors the working state of the processor to be verified, and when it is determined that the processor to be verified is in an idle state, generates and outputs a verification instruction packet.

[0087] When the verification platform has a verification requirement for a certain processor, it can monitor the working status of the processor to determine whether it is in an idle state. If the processor is not in an idle state, in order to ensure the normal operation of the processor, it will not be verified. Instead, the verification of the processor will be started only when it is determined that the processor is in an idle state.

[0088] The verification of the processor is started, that is, the verification instruction packet is sent to the second storage unit, so that the processor to be verified can read the verification instruction packet stored in the second storage unit when monitoring the second storage unit, so as to execute the verification instruction packet.

[0089] The verification instruction package can be generated when it is determined that the processor to be verified is in an idle state. When the processor to be verified is determined to be in an idle state, the verification instruction package is generated and the generated verification instruction package is sent to the second storage unit for storage; or the verification instruction package can be generated as long as the verification platform determines that there is a verification requirement for the processor, and then when it is determined that the processor is in an idle state, the verification instruction package is sent to the second storage unit for storage.

[0090] Specifically, the verification platform generates a verification instruction package by: determining the identification information of the processor to be verified, determining the instructions required for the processor to be verified to execute the verification process, determining the address and data of the processor to be verified to execute the verification process, etc., and combining this information can generate a verification instruction package.

[0091] Among them, the number of instructions that the processor needs to execute to perform the verification process is limited, such as: read and check, read no check, write, flush, invalid, etc. However, for different processors, due to different identification information, different selections of instructions to be executed, different addresses for executing the verification process, and different data for executing the verification process, the generated verification instruction packages are different. Therefore, different verification instruction packages are generated for different processors to be verified, but the number of instructions that need to be maintained by the verification platform is limited, and it does not require a large amount of memory or network maintenance of more instructions.

[0092] For operations other than CMO (Cache Maintenance Operation), the verification platform needs to store the address of the instruction to be executed in the address segment, store the operation data in the data segment, and package them in the Command format according to the verification requirements, where the address of the instruction to be executed is the address to be accessed. When the processor to be verified is a single-core processor or a processing core in a multi-core processor, due to the particularity of the processor to be verified, for active user operations of the processor to be verified, that is, non-processor-initiated cache operations such as perfetch, the amount of operation data per clock of the processor depends on the bit width of its data bus, such as: when the bit width is 128 bits, a maximum of 16 bytes of data can be loaded / stored at a time; when the bit width is 64 bits, a maximum of 8 bytes of data can be loaded / stored at a time.

[0093] For COM operation, only the identification information, address and the number or size of the address bits that need to be maintained for consistency of the processor to be verified need to be provided.

[0094] In order to reduce the interaction between the processor and the verification platform as much as possible and save verification time, this solution can be set to access a specific number of 16-Byte data at a time, and the specific number can be 32.

[0095] If the number of instructions to be accessed is small, or the addresses of the instructions to be executed are not continuous, a discrete mode is adopted for execution, that is, multiple addresses and multiple operation data of the instructions to be executed are obtained respectively, and the multiple operation data are stored in the data segment respectively, and the multiple addresses are stored in the address segment respectively, and a verification instruction packet is generated based on this;

[0096] If the multiple addresses of the instructions to be accessed are continuous, they can be executed in continuous mode, that is:

[0097] The verification platform determines the address value and operation data of the instruction to be executed in the processor to be verified. If there are multiple address values ​​and operation data for the instruction to be executed, and the multiple address values ​​are continuous, the first address value of the multiple address values ​​is stored in the address segment, and the multiple operation data are stored in the data segment in sequence. A verification instruction package consisting of multiple verification instructions is generated based on the address segment and the data segment, and the verification instruction package is output so that the verification processor can execute the multiple verification instructions in sequence based on the first address value stored in the address segment and the multiple operation data stored in the data segment.

[0098] In order to reduce the operations on continuous address segments in discrete mode, the present embodiment supports continuous mode, that is, in the case of multiple continuous data accesses, as long as the first address value of the access memory is given in the address segment, that is, as long as the first address value is stored in the address segment, the subsequent operation addresses do not need to be stored in the address segment, nor do they need to be obtained from the address segment. The processor to be verified directly calculates the subsequent address values ​​based on the first address value, thereby reducing the memory occupancy.

[0099] Furthermore, in the processor verification system disclosed in this embodiment, the processor to be verified obtains the verification instruction package stored in the second storage unit and executes the verification instruction package, which may be specifically:

[0100] The processor to be verified reads the verification instruction package stored in the second storage unit to determine whether the verification instruction package is valid. If the verification instruction package is valid, it is determined whether the processor to be verified is the processor specified by the verification instruction package. If the processor to be verified is the processor specified by the verification instruction package, the processor to be verified executes the verification instruction in the verification instruction package.

[0101] Each processor connected to the verification platform will periodically or in real time determine whether a verification instruction package is stored in the second storage unit, or each processor will monitor whether a verification instruction package is stored in the second storage unit through a monitoring module. When the processor determines that a verification instruction package is stored in the second storage unit, it reads the verification instruction package and determines whether the read verification instruction package is valid. Only when the read verification instruction package is valid will it continue with subsequent operations.

[0102] The determination of whether the verification instruction packet is valid can be determined by the value of a specific position in the verification instruction packet, such as whether the highest bite storage of the verification instruction packet is valid. If the verification instruction packet is determined to be valid at this position, the subsequent operation is continued, that is, whether the current processor is the processor specified in the verification instruction packet.

[0103] For example, the processors connected to the verification platform include a first processor and a second processor, both of which can read data in a second storage unit, and the verification platform can verify the above processors based on the data in the second storage unit. The first processor and the second processor both read data from the second storage unit in real time or periodically to determine whether a verification instruction package is stored in the second storage unit.

[0104] If the first processor determines that a verification instruction packet is stored in the second storage unit, the first processor reads the verification instruction packet, analyzes the verification instruction packet, determines that the verification instruction packet is valid, and then determines the identification information of the processor to be verified specified in the verification instruction packet, and determines that the identification information of the first processor is different from the identification information of the processor to be verified specified in the verification instruction packet, then it can be determined that the verification instruction packet is not an instruction packet for verifying the first processor;

[0105] If the second processor determines that a verification instruction package is stored in the second storage unit, the second processor reads the verification instruction package, analyzes the verification instruction package, determines that the verification instruction package is valid, and then determines the identification information of the processor to be verified specified in the verification instruction package, and determines that the identification information of the second processor is the same as the identification information of the processor to be verified specified in the verification instruction package, then it can be determined that the verification instruction package is an instruction package to verify the second processor.

[0106] That is, after the processor determines that a verification instruction package is stored in the second storage unit, it must first determine whether the verification instruction package is valid. If it is determined that the verification instruction package is valid, it continues to determine whether the current processor is the processor to be verified specified in the verification instruction package. Only when it is determined that the current processor is the processor to be verified specified in the verification instruction package, the current processor will continue to perform the verification operation.

[0107] If it is determined that the current processor is different from the processor specified in the verification instruction packet, the current processor will not perform subsequent verification operations, but execute low-power instructions to put the current processor into a low-power state.

[0108] When the current processor determines that it is different from the processor specified in the verification instruction package, it can directly execute the wfe instruction (Wait For Event, low-power instruction). The wfe instruction is used to make the processor enter the WFE state, that is, the low-power standby mode, and wait for the wake-up of other processors. Therefore, each time a processor completes an instruction, it will wake up other processors to wake up other processors from the WFE state; other processors actively check whether the processor specified in the verification instruction package is the current processor. If not, the processor still enters the WFE state.

[0109] When the current processor determines that it is the same as the processor specified in the verification instruction package, the current processor needs to verify the data segment and address segment required by the instruction package, obtain relevant information according to the needs, and perform storage or load. Specific operations can be performed according to the main operation op and the sub-operation sub_op to implement the verification process of the current processor. After executing the instructions in the verification instruction package, the sev instruction (Set Event, wake-up instruction) can be output. The sev instruction is used to wake up the processor or processing core that is waiting for an event.

[0110] In the processor verification system disclosed in this embodiment, the schematic diagram of the verification instruction packet stored in the second storage unit can be as follows: Figure 4 As shown, taking the second storage unit as register CtrlReg as an example, when the verification instruction packet is stored in register CtrlReg, the highest bit (such as bit 31) is used to indicate whether the verification instruction packet is valid, bits 29-30 are used to indicate the type of operation; bits 25-28 are used to indicate the sub-operation under the operation ( Figure 4 The table in the lower right corner shows the specific actions corresponding to the operations and sub-operations of bits 25-30); bit 24 is used to indicate whether it is continuous mode or discrete mode; bits 19-23 are length, which indicates how many operations the processor needs to do. If it is 1 operation, length=0, and if it is 2 operations, length=1. If it is determined that 2 operations are required, for discrete mode, it is necessary to read the address segment 2 times, read the data segment 2 times, and perform write / read 2 times; bits 16-18 are size, which indicates that the processor accesses size for each operation. The processor can issue 1 byte read / write, or 2, 4, ..., 8, 16 byte operations. When writing firmware in C, it depends on the pointer specified when the processor operates; bits 5-15 can be used for extension; bits 0-4 are used to represent the identification information of the processor to be verified.

[0111] After reading the verification instruction packet stored in the second storage unit, each processor can Figure 4 As shown, the highest bit is first read to determine whether the verification instruction package is valid. If valid, the lowest bit is read to determine whether the processor specified by the verification instruction package is consistent with the current processor. If not, the low-power instruction is executed to enter the low-power state. If consistent, other data in the verification instruction package is read, such as the verification instruction, to complete the verification operation.

[0112] The verification instruction may be a read instruction, a write instruction, a consistency maintenance instruction, a print instruction, etc.

[0113] If the verification instruction is a read instruction, the processor to be verified executes the read instruction, and a judgment can be made based on the values ​​of op and sub_op. If it is a read and a check, the read data is compared, that is, whether the actual data read is consistent with the required data of the read instruction. When it is determined that the actual data read by executing the read instruction does not meet the required data of the read instruction, the actual data and the required data are converted into ASCII code and stored in the first storage unit, so that the verification platform can print the character string converted from the ASCII code in the first storage unit;

[0114] In addition, if it is determined that the current operation is not a read or a check according to the values ​​of op and sub_op, then only the data needs to be read without subsequent judgment. If the read data does not need to be checked, then the read data does not need to be stored and is only used by the processor itself, and there is no need to inform the verification platform.

[0115] After any processor completes an instruction packet, it will access the instruction register address that it read previously and write the vld bit corresponding to the instruction register to 0, indicating that the operation corresponding to the instruction has been completed.

[0116] If the read data needs to be checked, it is necessary to determine whether the read data is consistent with the required data of the read instruction, and if so, determine that the processor execution is completed. Based on the execution result, determine whether the processor to be verified executes the read instruction abnormally, thereby determining whether the processor to be verified is abnormal; if not, it is necessary to convert the actual data read and the required data of the read instruction into ASCII code, and store the converted ASCII code in the first storage unit, so that the verification platform can convert the ASCII code stored in the first storage unit into a character string, and print the character string, so as to determine whether the processor to be verified is abnormal based on the printing result.

[0117] If the verification instruction is a write instruction, the processor to be verified executes the operation of writing to the memory, and after the operation of writing to the memory is completed, it is determined that the processor execution is completed. The verification platform needs to check from the second storage unit to determine whether the execution result is stored. If the execution result is stored, the execution result is obtained from the second storage unit, and based on the execution result, it is determined whether the processor to be verified executes the read instruction abnormally, thereby determining whether the processor to be verified is abnormal.

[0118] Correspondingly, if it is a consistency maintenance instruction, the processor to be verified performs a consistency maintenance operation, and after the consistency maintenance operation is completed, it is determined that the processor execution is completed. The verification platform needs to check from the second storage unit to determine whether the execution result is stored. If the execution result is stored, the execution result is obtained from the second storage unit, and based on the execution result, it is determined whether the processor to be verified executes the read instruction abnormally, thereby determining whether the processor to be verified is abnormal.

[0119] The processor verification system disclosed in the present embodiment can not only store the ASCII code converted from the character string generated during the operation of the processor to be verified in the first storage unit, and then the verification platform reads the ASCII code stored in the first storage unit and prints it after converting it into a character string, so as to intuitively, quickly and accurately determine whether the processor to be verified has an abnormality through the printing result; it can also store the verification instruction package and the execution result of the processor to be verified after executing the verification instruction package in the second storage unit, so that the verification platform can determine whether the processor to be verified has an abnormality based on the execution result. Since the verification instruction package stored in the second storage unit is generated based on the requirements of the processor to be verified, the system disclosed in the present embodiment does not need to maintain a large number of test cases, and the verification operations that the processor to be verified needs to execute are all issued by the verification platform through the verification instruction package, which has strong randomness, ensuring that the verification of the processor is more complete; in addition, since the system disclosed in the present embodiment is insensitive to instruction reception and transmission and processor type, all instruction operations that depend on the processor architecture can be defined as macros, and only one set of firmware needs to be maintained. Therefore, when the architecture of the processor is changed, only the instruction macro based on the architecture needs to be redefined, so the cost of changing the architecture of the processor to be verified is relatively small.

[0120] This embodiment discloses a processor verification method, and its flow chart is as follows: Figure 5 As shown, including:

[0121] Step S51, monitoring whether the first storage unit stores ASCII code, wherein the ASCII code is: a character string generated during the operation of the processor to be verified is converted into ASCII code and stored in the first storage unit;

[0122] Step S52: if it is determined that the first storage unit stores an ASCII code, convert the ASCII code into a character string, print the character string, and obtain a print result;

[0123] Step S53: If it is determined based on the printing result that the data stored in the first storage unit is abnormal, it is determined that the processor to be verified is abnormal.

[0124] Furthermore, the processor verification method disclosed in this embodiment may also include:

[0125] When the verification conditions are met, a verification instruction packet is generated;

[0126] Storing the verification instruction package in the second storage unit so that the processor to be verified specified by the verification instruction package can obtain and execute the verification instruction package;

[0127] Obtaining the execution result of the verification instruction packet executed by the processor to be verified stored in the second storage unit;

[0128] It is determined whether the processor has an exception based on the execution result.

[0129] Furthermore, when the verification condition is met, a verification instruction packet is output, including:

[0130] The working state of the processor to be verified is monitored, and when it is determined that the processor to be verified is in an idle state, a verification instruction packet is generated and output.

[0131] Further, a verification instruction package is generated and output, including:

[0132] Determine the address value and operation data of the instruction to be executed in the processor to be verified. If there are multiple address values ​​and operation data for the instruction to be executed, and the multiple address values ​​are continuous, store the first address value of the multiple address values ​​into the address segment, store the multiple operation data into the data segment in sequence, generate a verification instruction package consisting of multiple verification instructions based on the address segment and the data segment, and output the verification instruction package so that the verification processor can execute the multiple verification instructions in sequence based on the first address value stored in the address segment and the multiple operation data stored in the data segment.

[0133] The processor verification method disclosed in this embodiment is implemented based on the processor verification system disclosed in the above embodiment, and will not be described in detail here.

[0134] The processor verification method disclosed in this embodiment monitors whether ASCII code is stored in the first storage unit, wherein the ASCII code is: the character string generated during the operation of the processor to be verified is converted into ASCII code and then stored in the first storage unit; if it is determined that ASCII code is stored in the first storage unit, the ASCII code is converted into a character string, the character string is printed, and a print result is obtained; if it is determined based on the print result that the data stored in the first storage unit is abnormal, it is determined that the processor to be verified is abnormal. In this solution, the processor to be verified generates a character string during the operation and converts it into ASCII code and stores it in the first storage unit, so that the verification platform can print the character string converted from the ASCII code stored in the first storage unit, and based on the print result, it can be determined whether there is an abnormality in the operation of the processor to be verified, and if there is an abnormality, the position of the abnormality can be directly located based on the print result, which simplifies the verification process and improves the user experience.

[0135] This embodiment discloses a verification platform, and its structural diagram is as follows: Figure 6 As shown, including:

[0136] A monitoring unit 61 , a printing unit 62 and a first determining unit 63 .

[0137] The monitoring unit 61 is used to monitor whether the first storage unit stores ASCII code, wherein the ASCII code is: the character string generated during the operation of the processor to be verified is converted into ASCII code and stored in the first storage unit;

[0138] The printing unit 62 is used to convert the ASCII code into a character string when it is determined that the ASCII code is stored in the first storage unit, and print the character string to obtain a printing result;

[0139] The first determining unit 63 is used to determine that the processor to be verified has an abnormality when it is determined based on the printing result that the data stored in the first storage unit has an abnormality.

[0140] Furthermore, the verification platform disclosed in this embodiment may also include:

[0141] An instruction packet generating unit, configured to generate a verification instruction packet when a verification condition is met; and store the verification instruction packet in a second storage unit so that the processor to be verified specified by the verification instruction packet can obtain and execute the verification instruction packet;

[0142] The second determining unit is used to obtain the execution result of the verification instruction package executed by the processor to be verified stored in the second storage unit; and determine whether the processor is abnormal based on the execution result.

[0143] Furthermore, the instruction packet generation unit is used to:

[0144] The working state of the processor to be verified is monitored, and when it is determined that the processor to be verified is in an idle state, a verification instruction packet is generated and output.

[0145] Furthermore, the instruction packet generation unit is used to:

[0146] Determine the address value and operation data of the instruction to be executed in the processor to be verified. If there are multiple address values ​​and operation data for the instruction to be executed, and the multiple address values ​​are continuous, store the first address value of the multiple address values ​​into the address segment, store the multiple operation data into the data segment in sequence, generate a verification instruction package consisting of multiple verification instructions based on the address segment and the data segment, and output the verification instruction package so that the verification processor can execute the multiple verification instructions in sequence based on the first address value stored in the address segment and the multiple operation data stored in the data segment.

[0147] The verification platform disclosed in this embodiment is implemented based on the processor verification system disclosed in the above embodiments, which will not be described in detail here.

[0148] The verification platform disclosed in this embodiment monitors whether ASCII code is stored in the first storage unit, wherein the ASCII code is: the character string generated during the operation of the processor to be verified is converted into ASCII code and then stored in the first storage unit; if it is determined that ASCII code is stored in the first storage unit, the ASCII code is converted into a character string, the character string is printed, and a print result is obtained; if it is determined based on the print result that the data stored in the first storage unit is abnormal, it is determined that the processor to be verified is abnormal. In this solution, the processor to be verified generates a character string during the operation and converts it into ASCII code and stores it in the first storage unit, so that the verification platform can print the character string converted from the ASCII code stored in the first storage unit, and based on the print result, it can be determined whether there is an abnormality in the operation of the processor to be verified, and if there is an abnormality, the position of the abnormality can be directly located based on the print result, which simplifies the verification process and improves the user experience.

[0149] It should also be noted that the device embodiments described above are merely schematic, wherein the units described as separate components may or may not be physically separated, and the components displayed as units may or may not be physical units, that is, they may be located in one place, or they may be distributed over multiple network units. Some or all of the modules may be selected according to actual needs to achieve the purpose of the scheme of this embodiment. In addition, in the drawings of the device embodiments provided by the present application, the connection relationship between the modules indicates that there is a communication connection between them, which may be specifically implemented as one or more communication buses or signal lines.

[0150] Through the description of the above implementation mode, the technicians in the field can clearly understand that the present application can be implemented by means of software plus necessary general hardware, and of course, it can also be implemented by special hardware including special integrated circuits, special CPUs, special memories, special components, etc. In general, all functions completed by computer programs can be easily implemented by corresponding hardware, and the specific hardware structure used to implement the same function can also be various, such as analog circuits, digital circuits or special circuits. However, for the present application, software program implementation is a better implementation mode in more cases. Based on such an understanding, the technical solution of the present application is essentially or the part that contributes to the prior art can be embodied in the form of a software product, which is stored in a readable storage medium, such as a computer floppy disk, a U disk, a mobile hard disk, a ROM, a RAM, a disk or an optical disk, etc., including a number of instructions to enable a computer device (which can be a personal computer, a training device, or a network device, etc.) to execute the methods described in each embodiment of the present application.

[0151] In the above embodiments, all or part of the embodiments may be implemented by software, hardware, firmware or any combination thereof. When implemented by software, all or part of the embodiments may be implemented in the form of a computer program product.

[0152] The computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, the process or function described in the embodiment of the present application is generated in whole or in part. The computer may be a general-purpose computer, a special-purpose computer, a computer network, or other programmable devices. The computer instructions may be stored in a computer-readable storage medium, or transmitted from one computer-readable storage medium to another computer-readable storage medium. For example, the computer instructions may be transmitted from a website site, a computer, a training device, or a data center by wired (e.g., coaxial cable, optical fiber, digital subscriber line (DSL)) or wireless (e.g., infrared, wireless, microwave, etc.) mode to another website site, computer, training device, or data center. The computer-readable storage medium may be any available medium that a computer can store or a data storage device such as a training device, a data center, etc. that includes one or more available media integrations. The available medium may be a magnetic medium, (e.g., a floppy disk, a hard disk, a tape), an optical medium (e.g., a DVD), or a semiconductor medium (e.g., a solid-state drive (SSD)), etc.

Claims

1. A processor verification system, characterized in that: include: The processor to be verified is capable of executing the operation, obtaining the character string generated by executing the operation, and converting the character string into ASCII code; A first storage unit, used for storing the ASCII code converted from the character string generated by the operation performed by the processor to be verified; A verification platform is used for, when it is determined that the ASCII code is stored in the first storage unit, converting the target data stored in the first storage unit into a character string, and printing the character string to obtain a printing result; if it is determined based on the printing result that there is an abnormality in the data stored in the first storage unit, it is determined that there is an abnormality in the processor to be verified.

2. The system according to claim 1, characterized in that Also includes: A second storage unit, used to obtain and store a verification instruction packet output by the verification platform when the verification condition is met; The processor to be verified obtains the verification instruction package stored in the second storage unit, executes the verification instruction package, and stores the execution result in the second storage unit; The verification platform obtains the execution result stored in the second storage unit, and determines whether the processor to be verified has an abnormality based on the execution result.

3. The system according to claim 2, characterized in that The verification instruction package output by the verification platform when the verification condition is met includes: The verification platform monitors the working state of the processor to be verified, and when determining that the processor to be verified is in an idle state, generates and outputs a verification instruction packet.

4. The system according to claim 3, characterized in that The verification platform generates and outputs a verification instruction package, including: The verification platform determines the address value and operation data of the instruction to be executed in the processor to be verified. If there are multiple address values ​​and operation data for the instruction to be executed, and the multiple address values ​​are continuous, the first address value of the multiple address values ​​is stored in the address segment, and the multiple operation data are stored in the data segment in sequence. A verification instruction package consisting of multiple verification instructions is generated based on the address segment and the data segment, and the verification instruction package is output so that the verification processor can execute the multiple verification instructions in sequence based on the first address value stored in the address segment and the multiple operation data stored in the data segment.

5. The system according to claim 2, characterized in that The processor to be verified obtains the verification instruction package stored in the second storage unit and executes the verification instruction package, including: The processor to be verified reads the verification instruction package stored in the second storage unit to determine whether the verification instruction package is valid. If it is determined that the verification instruction package is valid, it is determined whether the processor to be verified is the processor specified by the verification instruction package. If the processor to be verified is the processor specified by the verification instruction package, the processor to be verified executes the verification instruction in the verification instruction package.

6. The system according to claim 5, characterized in that The processor to be verified executes the verification instruction in the verification instruction package, including: If the verification instruction in the verification instruction package is a read instruction, the processor to be verified executes the read instruction. When it is determined that the actual data read by executing the read instruction does not meet the requirement data of the read instruction, the actual data and the requirement data are converted into ASCII codes and stored in the first storage unit, so that the verification platform can print the character string converted from the ASCII code in the first storage unit.

7. The system according to claim 5, characterized in that Also includes: If it is determined that the processor to be verified is different from the processor specified by the verification instruction packet, the processor to be verified executes a low power consumption instruction and enters a low power consumption state.

8. A processor verification method, characterized in that: include: Monitoring whether an ASCII code is stored in the first storage unit, wherein the ASCII code is: a character string generated during the operation of the processor to be verified is converted into an ASCII code and stored in the first storage unit; If it is determined that the ASCII code is stored in the first storage unit, convert the ASCII code into a character string, print the character string, and obtain a print result; If it is determined based on the printing result that the data stored in the first storage unit has an abnormality, it is determined that the processor to be verified has an abnormality.

9. The method according to claim 8, characterized in that Also includes: When the verification conditions are met, a verification instruction packet is generated; storing the verification instruction package in a second storage unit so that the processor to be verified specified by the verification instruction package can obtain and execute the verification instruction package; Obtaining the execution result of the verification instruction packet executed by the processor to be verified stored in the second storage unit; It is determined whether the processor has an abnormality based on the execution result.

10. A verification platform, characterized in that: include: A monitoring unit, used to monitor whether an ASCII code is stored in the first storage unit, wherein the ASCII code is: a character string generated during the operation of the processor to be verified is converted into an ASCII code and stored in the first storage unit; A printing unit, configured to convert the ASCII code into a character string when it is determined that the ASCII code is stored in the first storage unit, and print the character string to obtain a printing result; a first determining unit, configured to determine that an abnormality exists in the processor to be verified when it is determined based on the printing result that an abnormality exists in the data stored in the first storage unit; The verification platform also includes: An instruction packet generating unit, configured to generate a verification instruction packet when a verification condition is met; and store the verification instruction packet in a second storage unit so that the processor to be verified specified by the verification instruction packet can obtain and execute the verification instruction packet; The second determining unit is used to obtain the execution result of the processor to be verified stored in the second storage unit executing the verification instruction package; and determine whether the processor is abnormal based on the execution result.

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