Protection circuit, chip and electronic equipment

Abstract

This application discloses a protection circuit, chip, and electronic device, belonging to the field of integrated circuit technology. The protection circuit includes: an equipotential line group, a control module, and a detection module; the equipotential line group is located in the shielding layer of the target chip; the equipotential line group covers the protected area; the control module is located in the protected area and is disposed in the routing layer below the shielding layer; the equipotential line group includes multiple equipotential lines; the input terminals of the equipotential lines receive a first detection signal; at reconstruction nodes, the equipotential lines are disconnected and electrically connected to the control module respectively; the control module is used to randomly control the routing path at the reconstruction node, the routing path is located in the protected area and disposed in the routing layer, including multiple equipotential line intersecting routing and / or independent routing; the detection module is used to output an alarm signal when the target chip is attacked, the second detection signal being the detection signal output by the equipotential lines to the detection module. This can increase the attack difficulty of the protection circuit, thereby improving the protection effect.

Description

Technical Field

[0001] This application belongs to the field of integrated circuit technology, specifically relating to a protection circuit, chip, and electronic device. Background Technology

[0002] Currently, invasive attacks on chips are also known as physical attacks, which can cause data loss in the chip.

[0003] In related technologies, a shielding layer can be added to the top layer of the chip. This shielding layer includes shielding wires, which are connected to a detection circuit to form a protective circuit. When the shielding wires of the shielding layer are detected or cut, the detection circuit can issue an alarm signal when it detects a change in the signal transmitted on the shielding wires. The chip's main control unit can then take protective measures based on the alarm signal.

[0004] However, existing shielding lines mainly use parallel equipotential lines, spiral lines, and other graphic topologies. These shielding lines are mostly single, symmetrical, or repeating patterns, and the shielding line is a complete line. If the beginning and end of the shielding line, i.e., the input and output ends, are short-circuited, the entire shielding line will lose its protective function. The chip area covered by the short-circuited shielding line is easily probed and important data can be lost. Summary of the Invention

[0005] The purpose of this application is to provide a protection circuit, chip, and electronic device that can solve the problems of low attack difficulty and poor protection effect of existing protection circuits.

[0006] In a first aspect, embodiments of this application provide a protection circuit, which includes: an equipotential line group, a control module, and a detection module;

[0007] The equipotential line group is located in the shielding layer of the target chip; the equipotential line group covers the protected area of ​​the target chip; the control module is located in the protected area and is disposed in the wiring layer below the shielding layer;

[0008] The equipotential line group includes multiple equipotential lines; the output end of the equipotential line is electrically connected to the detection module; the input end of the equipotential line is used to receive the first detection signal.

[0009] The equipotential line includes a reconstruction node; at the reconstruction node, the equipotential line is broken, and the two ends of the broken equipotential line are electrically connected to the control module respectively.

[0010] The control module is used to randomly control the routing path of the equipotential lines at the reconstruction node; wherein, the routing path is located in the protected area and is set in the routing layer; the routing path includes multiple intersecting routing of the equipotential lines, and / or, the equipotential lines are routing independently;

[0011] The detection module is used to receive the first detection signal, compare the first detection signal with the second detection signal, and output an alarm signal if the comparison result indicates that the target chip has been attacked; wherein, the second detection signal is the detection signal output by the equipotential line to the detection module.

[0012] Optionally, at the reconstructed node, the equipotential line includes a first end and a second end;

[0013] The first end is connected to the wiring layer through the first through hole of the shielding layer, and is electrically connected to the control module through the first wiring of the wiring layer;

[0014] The second end is connected to the wiring layer through the second through hole of the shielding layer, and is electrically connected to the control module through the second wiring of the wiring layer.

[0015] Optionally, the trace layer is the metal layer of the protected area; the first trace and the second trace are metal traces of the metal layer.

[0016] Optionally, the equipotential line group includes a first equipotential line and a second equipotential line; the first equipotential line and the second equipotential line are two adjacent equipotential lines in the equipotential line group;

[0017] The output terminals of the first equipotential line and the second equipotential line are respectively electrically connected to the detection module; the first equipotential line and the second equipotential line are respectively used to receive the first detection signal.

[0018] The reconstructed node of the first equipotential line is the first node; the reconstructed node of the second equipotential line is the second node; the straight-line distance between the first node and the second node is less than a preset distance threshold.

[0019] Optionally, the first node and the second node are located within the target area; the first equipotential line and the second equipotential line within the target area are parallel lines.

[0020] Optionally, the equipotential lines may further include confusion nodes;

[0021] At the obfuscation node, the equipotential line is broken, and the two ends of the broken equipotential line are connected to the trace layer through the through-hole of the shielding layer; the equipotential line is reconnected in the trace layer.

[0022] Optionally, at the confusion node, the equipotential line includes a third end and a fourth end;

[0023] The third end is connected to the wiring layer through a third through-hole on the shielding layer; the fourth end is connected to the wiring layer through a fourth through-hole on the shielding layer; the third end and the fourth end are reconnected through the third wiring of the wiring layer;

[0024] Alternatively, the third and fourth ends are connected to the trace layer through a fifth through-hole on the shielding layer, and the connection is restored in the trace layer.

[0025] Optionally, the protection circuit further includes a signal generation module, or the target chip includes the signal generation module;

[0026] The signal generation module is electrically connected to the input end of the equipotential line and the detection module, respectively, and is used to send the first detection signal to the equipotential line and the detection module.

[0027] Optionally, the signal generation module is also electrically connected to the control module for generating a random control signal and sending the random control signal to the control module; wherein the random control signal is used to instruct the control module to perform random control on the wiring path.

[0028] Optionally, the signal generation module is a random number generator, or a physically non-clonable function circuit.

[0029] Optionally, the signal generation module is located in the protected area;

[0030] The input end of the equipotential line is electrically connected to the signal generation module through a through-hole in the shielding layer.

[0031] Optionally, the detection module is located in the protected area;

[0032] The output end of the equipotential line is electrically connected to the detection module through the through-hole of the shielding layer.

[0033] Optionally, the shielding layer adopts a Hamiltonian loop structure;

[0034] The equipotential line group is composed of equipotential lines in the Hamiltonian circuit structure.

[0035] Secondly, embodiments of this application provide a chip that includes the protection circuit described in the first aspect.

[0036] Thirdly, embodiments of this application provide an electronic device, which includes the chip described in the second aspect.

[0037] The protection circuit, chip, and electronic device provided in this application have at least the following advantages: the protection circuit includes an equipotential line group, a control module, and a detection module; the equipotential line group is located in the shielding layer of the target chip; the equipotential line group covers the protected area of ​​the target chip; the control module is located in the protected area and is disposed in the wiring layer below the shielding layer; the equipotential line group includes multiple equipotential lines; the output end of the equipotential line is electrically connected to the detection module; the input end of the equipotential line is used to receive a first detection signal; the equipotential line includes a reconstruction node; at the reconstruction node, the equipotential line is disconnected, and the two ends of the disconnected equipotential line are respectively electrically connected to the control module. The control module is used to randomly control the routing path of the equipotential lines at the reconstruction node; wherein the routing path is located in the protected area and set in the routing layer; the routing path includes multiple intersecting equipotential lines, and / or, the equipotential lines are independently routed; the detection module is used to receive the first detection signal, compare the first detection signal with the second detection signal, and output an alarm signal if the comparison result indicates that the target chip has been attacked; wherein the second detection signal is the detection signal output by the equipotential lines to the detection module. In this way, the routing path of the control module and the reconstruction node is shielded and protected by the equipotential line group, and the attacker cannot easily distinguish the beginning and end and the broken end of the equipotential lines, making it difficult to directly short-circuit the input and output ends of the equipotential lines for rewiring attacks, thereby increasing the attack difficulty of the protection circuit. The control module randomly controls the routing path of the equipotential lines at the reconstructed nodes, making the routing path of the equipotential lines random. The detection module compares the first detection signal of the input equipotential line with the second detection signal of the output equipotential line, which can continuously detect whether the equipotential line is attacked. When attacked, an alarm signal is output, which can improve the protection effect of the protection circuit. Attached Figure Description

[0038] Figure 1 This is a schematic diagram of the topological structure of parallel equipotential lines in a shielding layer in a related technology.

[0039] Figure 2 This is a schematic diagram of the topology of other common shielding layers in related technologies;

[0040] Figure 3 This is a schematic diagram of the circuit structure of a protection circuit provided in an embodiment of this application;

[0041] Figure 4 This is a schematic diagram of an equipotential line group provided in an embodiment of this application;

[0042] Figure 5 This is a schematic diagram of the routing path of a reconstructed node provided in an embodiment of this application;

[0043] Figure 6 This is a schematic diagram of the routing path of an obfuscated node provided in an embodiment of this application;

[0044] Figure 7 This is a schematic diagram of the circuit structure of another protection circuit provided in an embodiment of this application;

[0045] Figure 8 This is a schematic diagram of a shielding layer topology provided in an embodiment of this application;

[0046] Figure 9 This is a schematic diagram of another shielding layer topology provided in an embodiment of this application. Detailed Implementation

[0047] The technical solutions of the embodiments of this application will be clearly described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this application. All other embodiments obtained by those skilled in the art based on the embodiments of this application are within the scope of protection of this application.

[0048] The terms "first," "second," etc., used in the specification and claims of this application are used to distinguish similar objects and not to describe a specific order or sequence. It should be understood that such use of data can be interchanged where appropriate so that embodiments of this application can be implemented in orders other than those illustrated or described herein, and the objects distinguished by "first," "second," etc., are generally of the same class and the number of objects is not limited; for example, the first object can be one or at least two. Furthermore, in the specification and claims, "and / or" indicates at least one of the connected objects, and the character " / " generally indicates that the preceding and following objects are in an "or" relationship.

[0049] First, the background technology involved in the embodiments of this application will be described.

[0050] In the field of integrated circuits, with the development of microelectronics technology, information security technology, and deep submicron process technology, chip security protection technology is constantly improving. For example, integrated circuit cards (IC cards), also known as smart cards, are widely used in communications, transportation, retail, and other fields.

[0051] Currently, the main attack methods against chips include non-invasive attacks, semi-invasive attacks, and invasive attacks (also known as physical attacks). Related technologies typically add an active shielding layer to the top layer of the chip to prevent invasive physical probing and tampering attacks. Specifically, the active shielding layer includes detection circuitry and metal shielding wires. When the active shielding wires of the active shielding layer are detected or cut, the detection circuitry detects a change in the signal transmitted on the shielding wires and immediately generates an alarm signal, informing the main control unit that the chip has been attacked. The main control unit can then take protective measures such as destroying critical data and passwords.

[0052] Figure 1 This is a schematic diagram of the topological structure of parallel equipotential lines in a shielding layer in related technologies. Figure 2 This is a schematic diagram of the topology of other common shielding layers in related technologies. Figure 2 (a) shows the helical topology. Figure 2 (b) shows the topology of the Hilbert curve. Figure 2 (c) illustrates the topology of the Peano curve. For example... Figure 1 and Figure 2 As shown, the shielding topology in related technologies is mostly a single symmetrical or repeating pattern, and the shielding line is a complete line, just arranged in a certain shape. Once the shielding layer is attacked by a probe that discovers the beginning and end of the shielding line and short-circuits them (i.e., performs a rewiring attack), the short-circuited portion of the entire shielding line will lose its protective function. The protected area of ​​the chip covered by the short-circuited shielding line can then be freely probed, resulting in the loss of important data.

[0053] The following description, in conjunction with the accompanying drawings, details a protection circuit 10, chip, and electronic device provided in this application through specific embodiments and application scenarios.

[0054] Figure 3 This is a schematic diagram of the circuit structure of a protection circuit 10 provided in an embodiment of this application, as shown below. Figure 3 As shown, the protection circuit 10 includes: an equipotential line group 101, a control module 102, and a detection module 103;

[0055] The equipotential line group 101 is located in the shielding layer of the target chip; the equipotential line group 101 covers the protected area of ​​the target chip; the control module 102 is located in the protected area and is set in the wiring layer below the shielding layer;

[0056] The equipotential line group 101 includes multiple equipotential lines 1011; the output end of the equipotential line 1011 is electrically connected to the detection module 103; the input end of the equipotential line 1011 is used to receive the first detection signal.

[0057] The equipotential line 1011 includes a reconstructed node 1011a; at the reconstructed node 1011a, the equipotential line 1011 is broken, and the two ends of the broken equipotential line 1011 are electrically connected to the control module 102 respectively.

[0058] The control module 102 is used to randomly control the routing path of the equipotential line 1011 at the reconstruction node 1011a; wherein the routing path is located in the protected area and set in the routing layer, and the routing path includes multiple equipotential lines 1011 intersecting routing, and / or, the equipotential lines 1011 are routing independently.

[0059] The detection module 103 is used to receive a first detection signal, compare the first detection signal with a second detection signal, and output an alarm signal when the comparison result indicates that the target chip has been attacked; wherein, the second detection signal is the detection signal output to the detection module 103 by the equipotential line 1011.

[0060] The protection circuit 10 of this embodiment can be applied to chips with high security requirements, i.e., to the target chip. The top metal layer of the target chip is filled with a shielding structure as a shielding layer, which is a patterned topology composed of multiple shielding lines. The shielding layer of the target chip covers the protected area of ​​the target chip. The protected area includes all hierarchical structures located below the shielding layer and completely covered by the shielding layer, thus providing protection for the protected area. The hierarchical structure below the shielding layer includes a metal layer, which may contain chip circuits, metal traces, etc., thereby providing shielding protection for the chip circuits, metal traces, etc., within the protected area of ​​the target chip.

[0061] In this embodiment, the multiple shielding lines of the shielding layer may include different equipotential lines 1011, where each equipotential line 1011 is a shielding line with equal potential. For the shielding layer of the target chip, multiple equipotential line groups 101 of the protection circuit 10 can be filled into the top metal layer of the target chip. The pattern topology formed by the multiple equipotential line groups 101 is called a shielding line structure. In this way, the filled top metal layer serves as the shielding layer of the target chip, covering the protected area of ​​the target chip, thereby providing shielding protection for the protected area of ​​the target chip.

[0062] Alternatively, equipotential lines 1011 can be selected from the shielding lines of the target chip's shielding layer to form an equipotential line group 101 of the protection circuit 10. That is, the equipotential line group 101 can be composed of multiple equipotential lines 1011 from the target chip's shielding layer, and the equipotential lines 1011 of the shielding layer are respectively connected to the control module 102 and the detection module 103 of the protection circuit 10. Furthermore, the selected equipotential lines 1011 themselves cover the protected area of ​​the target chip through their inherent graphic topology; that is, the equipotential line group 101 of the protection circuit 10 covers the protected area of ​​the target chip, thereby providing shielding protection to the protected area. This is merely an example, and the embodiments of this application do not impose limitations.

[0063] In this embodiment, the equipotential line group 101 includes multiple equipotential lines 1011. The equipotential lines 1011 in different equipotential line groups 101 may be the same or different. The input terminal of the equipotential line 1011 is used to receive a first detection signal. The first detection signal is transmitted through the equipotential line 1011 and output to the detection module 103 at the output terminal of the equipotential line 1011. The output detection signal is called the second detection signal.

[0064] In this embodiment, the control module 102 is located in the protected area of ​​the target chip and can be shielded and protected by the equipotential line group 101 covering the protected area. The control module 102 can be specifically located in a metal layer below the shielding layer. The equipotential lines 1011 can be restored to traces in the lower metal layer, which is called the trace layer. The protected area of ​​the target chip includes the area to be protected in the trace layer. The control module 102 and the trace path of the reconstructed node 1011a can be located in the protected area of ​​the trace layer, thus the equipotential line group 101 can shield and protect the control module 102 and the trace path.

[0065] In this embodiment, a reconstruction node 1011a is provided on the equipotential line 1011. At the reconstruction node 1011a, the equipotential line 1011 is broken, and both ends of the broken equipotential line 1011 are electrically connected to the control module 102 located in the routing layer. The two ends of the broken equipotential line 1011 can be inserted into the routing layer through holes and electrically connected to the control module 102 of the routing layer, and then randomly routed under the control of the control module 102. The routing layer can be one or more metal layers; this embodiment does not limit this.

[0066] Specifically, at reconstructed node 1011a, equipotential line 1011 can either restore its original routing (i.e., independent routing) or connect to the terminals of other equipotential lines 1011 at reconstructed node 1011a, performing cross routing. This makes the routing path of equipotential line 1011 at reconstructed node 1011a random, depending on the random control logic of control module 102. Furthermore, since the routing path is set at the routing layer, an attacker can only see the two ends of the broken equipotential line 1011, which can be confused with the original beginning and end of the equipotential line 1011, thus increasing the difficulty of short-circuiting the beginning and end of the equipotential line 1011 to send a rewiring attack.

[0067] In this embodiment, the detection module 103 compares the first detection signal with the second detection signal to obtain a comparison result. If the comparison result shows that the second detection signal output by the equipotential line 1011 is consistent with the original first detection signal, it indicates that the equipotential line 1011 has not been attacked. If the comparison result shows that the second detection signal is inconsistent with the first detection signal, it indicates that the equipotential line 1011 has been attacked, i.e., the target chip has been attacked. In this case, the detection module 103 can output an alarm signal to the chip's main control unit, which can then take protective measures to prevent data leakage, thereby improving the security of the target chip.

[0068] The first detection signal can be a digital signal emitted by any digital signal generator, and can be defined according to the actual application scenario, such as a random number generated by a random number generator. This is only an example, and the embodiments of this application do not impose any limitations on it.

[0069] In this embodiment, the protection circuit 10 includes: an equipotential line group 101, a control module 102, and a detection module 103; the equipotential line group 101 is located in the shielding layer of the target chip; the equipotential line group 101 covers the protected area of ​​the target chip; the control module 102 is located in the protected area and is disposed in the wiring layer below the shielding layer; the equipotential line group 101 includes multiple equipotential lines 1011; the output terminal of the equipotential line 1011 is electrically connected to the detection module 103; the input terminal of the equipotential line 1011 is used to receive a first detection signal; the equipotential line 1011 includes a reconstruction node 1011a; at the reconstruction node 1011a, the equipotential line 1011 is broken, and the broken equipotential line 1011 is disconnected. Both ends of line 1011 are electrically connected to control module 102. Control module 102 is used to randomly control the routing path of equipotential line 1011 at reconfiguration node 1011a. The routing path is located in the protected area and set in the routing layer. The routing path includes multiple equipotential lines 1011 intersecting and / or equipotential lines 1011 routing independently. Detection module 103 is used to receive a first detection signal, compare the first detection signal with a second detection signal, and output an alarm signal if the comparison result indicates that the target chip has been attacked. The second detection signal is the detection signal output by equipotential line 1011 to detection module 103. In this way, the routing path of control module 102 and reconfiguration node 1011a is shielded and protected by equipotential line group 101. From the attacker's perspective, it is not easy to distinguish the beginning and end and the disconnected end of equipotential line 1011, making it difficult to directly short-circuit the input and output ends of equipotential line 1011 for rewiring attacks, thus increasing the attack difficulty of protection circuit 10. The control module 102 randomly controls the routing path of the equipotential line 1011 at the reconstructed node 1011a, which makes the routing path of the equipotential line 1011 random. The detection module 103 compares the first detection signal input to the equipotential line 1011 with the second detection signal output by the equipotential line 1011, which can continuously detect whether the equipotential line 1011 is attacked. When attacked, an alarm signal is output, which can improve the protection effect of the protection circuit 10.

[0070] Optionally, at the reconstructed node 1011a, the equipotential line 1011 includes a first end and a second end;

[0071] The first end is connected to the wiring layer through the first through hole of the shielding layer, and is electrically connected to the control module 102 through the first wiring of the wiring layer.

[0072] The second end is connected to the wiring layer through the second through hole of the shielding layer, and is electrically connected to the control module 102 through the second wiring of the wiring layer.

[0073] In this embodiment, at the reconstructed node 1011a, the two ends of the broken equipotential line 1011 are a first end and a second end, respectively. The first end and the second end can respectively enter the wiring layer through holes and are electrically connected to the control module 102 through the metal traces of the wiring layer. Specifically, the shielding layer has a first through-hole at the first end. One end of the first through-hole connects to the first end of the equipotential line 1011, and the other end connects to one end of the first trace. The other end of the first trace is electrically connected to the control module 102. The second end is similarly connected, via a second through-hole in the shielding layer to the wiring layer, and electrically connected to the control module 102 through the second trace of the wiring layer.

[0074] Optionally, the trace layer is the metal layer of the protected area; the first trace and the second trace are metal traces of the metal layer.

[0075] In this embodiment, the wiring layer is a metal layer below the shielding layer of the target chip, and the wiring layer is located in the protected area covered by the equipotential line group 101. The wiring layer may include multiple metal traces, such as a first trace and a second trace.

[0076] In some embodiments, the control module 102 may be a multiplexer circuit, including multiple connection terminals, and the first and second ends of the equipotential line 1011 may be connected to the connection terminals of the multiplexer, respectively. Thus, the control module 102 can randomly control the equipotential lines 1011 to restore their connections by switching the switch; for example, the equipotential lines 1011 may be routed independently, or the first end of one equipotential line 1011 may be connected to the second end of another equipotential line 1011, i.e., multiple equipotential lines 1011 may be routed in a cross pattern. This is merely an example, and the embodiments of this application do not impose limitations.

[0077] In this embodiment, since the equipotential line group 101 covers the protected area of ​​the target chip, and the routing layer below the shielding layer is the metal layer of the protected area, and the first and second traces are metal traces of the metal layer, the equipotential line group 101 can cover the routing layer, thereby shielding and protecting the control module 102 and the metal traces in the routing layer.

[0078] In this embodiment, at reconstructed node 1011a, the first and second ends of the equipotential line 1011 are connected to the routing layer through the first and second vias of the shielding layer, respectively, and are electrically connected to the control module 102 located on the routing layer through the first and second traces, respectively. Thus, from an attacker's perspective, only the vias of the shielding layer are visible, and the routing path of the routing layer below the shielding layer cannot be seen, making it difficult to predict the routing path of the equipotential line 1011 at reconstructed node 1011a. Therefore, the difficulty of short-circuiting the beginning and end of the equipotential line 1011 is increased, thus increasing the difficulty of rewiring attacks.

[0079] In some embodiments, the routing paths of multiple equipotential lines 1011 in the equipotential line group 101 can include various forms. For example, several equipotential lines 1011 may be routed independently while other equipotential lines 1011 may intersect, or all equipotential lines 1011 may intersect. Specifically, the routing path where multiple equipotential lines 1011 intersect may be one equipotential line 1011 intersecting with multiple other equipotential lines 1011, or multiple equipotential lines 1011 intersecting with multiple other equipotential lines 1011. This is merely an illustrative example, and the embodiments of this application do not impose limitations on this.

[0080] Optionally, the equipotential line group 101 includes a first equipotential line and a second equipotential line; the first equipotential line and the second equipotential line are two adjacent equipotential lines 1011 in the equipotential line group 101.

[0081] The output terminals of the first equipotential line and the second equipotential line are electrically connected to the detection module 103, respectively; the first equipotential line and the second equipotential line are used to receive the first detection signal, respectively.

[0082] The reconstructed node 1011a of the first equipotential line is the first node; the reconstructed node 1011a of the second equipotential line is the second node; the straight-line distance between the first node and the second node is less than a preset distance threshold.

[0083] The following explanation uses the first and second equipotential lines as examples of two adjacent equipotential lines 1011 in the equipotential line group 101.

[0084] In this embodiment, the input terminals of the first equipotential line and the second equipotential line respectively receive the first detection signal, and the output terminals of the first equipotential line and the second equipotential line are electrically connected to the detection module 103. The first equipotential line and the second equipotential line respectively output the second detection signal to the detection module 103 so that the detection module 103 can detect whether the target chip has been attacked based on the second detection signal and the first detection signal.

[0085] Specifically, at the first node, the first equipotential line is disconnected, and the two ends of the disconnected first equipotential line are electrically connected to the control module 102 respectively; and at the second node, the second equipotential line is disconnected, and the two ends of the disconnected second equipotential line are electrically connected to the control module 102 respectively.

[0086] In this embodiment, for adjacent first and second equipotential lines in the equipotential line group 101, reconstruction nodes 1011a can be set at relatively close positions. This can shorten the routing distance of the first and second equipotential lines in the routing layer, thereby reducing the resource consumption of the routing layer. Specifically, the straight-line distance between the first node of the first equipotential line and the second node of the second equipotential line is less than a preset distance threshold. The preset distance threshold can be defined according to the actual application scenario, and this embodiment does not impose any restrictions on it.

[0087] Figure 4 This is a schematic diagram of the structure of an equipotential line group 101 provided in an embodiment of this application, as shown below. Figure 4 As shown, in the figure formed by two adjacent equipotential lines 1011, there are line segments that are parallel and perpendicular to each other. Reconstruction nodes 1011a can be set by drilling holes on two parallel or perpendicular line segments that are close to each other.

[0088] Optionally, the first node and the second node are located within the target area; the first equipotential line and the second equipotential line within the target area are parallel lines.

[0089] In this embodiment of the application, a reconstructed node 1011a can be set within a preset target range, wherein the target range can be the range within which the first equipotential line and the second equipotential line run parallel to each other. For example, Figure 4 The area shown in the dashed box is the target area, within which two adjacent equipotential lines 1011 run parallel to each other.

[0090] Figure 5 This is a schematic diagram of the routing path of a reconstructed node 1011a provided in an embodiment of this application. Figure 5 Two adjacent equipotential lines, the first and second, are shown in equipotential line group 101. At reconstruction node 1011a, the first and second equipotential lines run parallel to each other. Reconstruction node 1011a includes a first node of the first equipotential line and a second node of the second equipotential line; the first equipotential line is broken at the first node, and the second equipotential line is broken at the second node. Figure 5 The "black cross" indicates a through-hole in the shielding layer. Figure 5 (a) is the reconstructed node 1011a from the attacker's perspective, where only the shielding layer through holes at both ends of the broken equipotential line 1011 can be seen, namely the first through hole and the second through hole.

[0091] like Figure 5 As shown, the paths of the first and second equipotential lines include as follows: Figure 5 (b) shows the independent routing, or, as shown in the example Figure 5 The intersecting traces shown in (c) can be controlled using random numbers generated by a random number generator. Figure 5The routing paths of the first and second nodes in the system are defined. For example, if the random number is "0" at a certain moment, the control module 102 can control the first and second equipotential lines to run independently at the first and second nodes. If the random number is "1" at a certain moment, the control module 102 can control the first and second equipotential lines to run intersectingly at the first and second nodes. Because the random number generated by the random number generator is uncontrollable, the probability of each routing path occurring at a certain moment is 50%. The routing path at the reconstructed node 1011a is difficult to predict, thus increasing the difficulty of the attack.

[0092] In this embodiment, since the first equipotential line and the second equipotential line run parallel within the target range, setting the first node and the second node within the target range allows for convenient random control of the routing path at the first node and the second node, reducing the impact of intersecting routing on the first equipotential line and the second equipotential line.

[0093] In this embodiment of the application, a reconstruction node 1011a can be set on two adjacent equipotential lines 1011 in the equipotential line group 101, namely the first equipotential line and the second equipotential line. Since the straight-line distance between the reconstruction node 1011a on the first equipotential line and the second equipotential line, namely the first node and the second node, is less than a preset distance threshold, the routing distance at the reconstruction node 1011a can be reduced, which makes it easier for the control module 102 to randomly control the routing path, thereby reducing the resource consumption of the protection circuit 10 and improving the practicality of the protection circuit 10.

[0094] Optionally, the equipotential line 1011 also includes confusion nodes 1011b;

[0095] At the confusion node 1011b, the equipotential line 1011 is broken, and the two ends of the broken equipotential line 1011 are connected to the routing layer through the through-hole of the shielding layer; the equipotential line 1011 is reconnected in the routing layer.

[0096] In this embodiment, obfuscation nodes 1011b can be set on some equipotential lines 1011 of the equipotential line group 101. From an attacker's perspective, it is difficult to distinguish between the reconstructed node 1011a and the obfuscated node 1011b, which can further increase the difficulty of the attack. Similar to the reconstructed node 1011a, the equipotential lines 1011 are broken at the obfuscation node 1011b, and the two ends of the broken equipotential lines 1011 are connected to the wiring layer through the through-holes of the shielding layer. However, unlike the reconstructed node 1011a, at the obfuscation node 1011b, the two ends of the broken equipotential lines 1011 do not need to be connected to the control module 102, but are reconnected on the wiring layer.

[0097] At the obfuscated node 1011b, the two ends of the broken equipotential line 1011 can enter the routing layer through the via of the shielding layer, or, when the two ends of the broken equipotential line 1011 are very close, they can also enter the routing layer through the same via. This application embodiment does not limit this.

[0098] In some embodiments, the routing layer can be the second-to-top metal layer of the target chip. This is because there are few metal traces of other circuits in the second-to-top layer, so the impact on other circuits of the chip is smaller. This facilitates routing at the reconfiguration node 1011a and the obfuscation node 1011b, which can improve the practicality of the protection circuit 10.

[0099] Optionally, at the confusion node 1011b, the equipotential line 1011 includes a third end and a fourth end;

[0100] The third end is connected to the routing layer through the third through-hole on the shielding layer; the fourth end is connected to the routing layer through the fourth through-hole on the shielding layer; the third end and the fourth end are reconnected through the third trace of the routing layer;

[0101] Alternatively, the third and fourth ends can be connected to the routing layer through a fifth via on the shielding layer, and the connection can be restored on the routing layer.

[0102] In this embodiment, at the obfuscated node 1011b, the two ends of the broken equipotential line 1011 are a third end and a fourth end, respectively. A third through-hole is provided at the third end of the shielding layer, with one end connected to the third end of the equipotential line 1011 and the other end connected to one end of the third trace. Similarly, a fourth through-hole is provided at the fourth end of the shielding layer, with one end connected to the fourth end of the equipotential line 1011 and the other end connected to the other end of the third trace, thereby restoring the connection between the third end and the fourth end in the trace layer through the third trace.

[0103] Alternatively, the third and fourth ends can be connected to the routing layer through a fifth via, and the connection can be restored on the routing layer. At the fifth via, the routing layer can also have a fourth trace, allowing the third and fourth ends to be connected via the fourth trace.

[0104] Figure 6 This is a schematic diagram of the routing path of an obfuscated node 1011b provided in an embodiment of this application, as shown below. Figure 6 As shown, Figure 6 Two adjacent first and second equipotential lines in equipotential line group 101 are shown. Figure 6 Based on the reconstructed node 1011a shown in (a), both the first and second equipotential lines are set as follows: Figure 6 (b) Confusion node 1011b. At confusion node 1011b, the first and second equipotential lines are broken. Figure 6 The "black cross" indicates a through-hole in the shielding layer. Figure 6(b) Reconstruction node 1011a and obfuscation node 1011b from the attacker's perspective. The attacker can only see the shielding layer vias, making it difficult for the attacker to distinguish between reconstruction node 1011a and obfuscation node 1011b, further increasing the difficulty of the attack.

[0105] like Figure 6 As shown, at the obfuscation node 1011b, the two ends of the broken equipotential line 1011 can enter the routing layer through the vias of the shielding layer, or, if the two ends of the broken equipotential line 1011 are very close, they can also enter the routing layer through the same via, as shown. Figure 6 (c) shows the connection being restored on the routing layer.

[0106] In this embodiment of the application, at the confusion node 1011b, the third and fourth ends of the equipotential line 1011 can be flexibly connected to the third trace of the trace layer through the third and fourth through holes respectively, or connected together to the trace layer through the fifth through hole. The connection is restored in the trace layer, which can play a confusion role with the shielding layer through hole at the reconstructed node 1011a, thereby improving the practicality of the protection circuit 10.

[0107] In this embodiment, since the equipotential line 1011 is reconnected in the routing layer at the obfuscated node 1011b, by setting the obfuscated node 1011b on the equipotential line 1011, the equipotential line 1011 is disconnected at the obfuscated node 1011b and connected to the routing layer through the via of the shielding layer. In this way, it can obfuscate the equipotential line 1011 disconnected at the reconstructed node 1011a and the via of the shielding layer, making it difficult for the attacker to distinguish between the reconstructed node 1011a and the obfuscated node 1011b. This can increase the difficulty of attack and improve the anti-attack capability of the protection circuit 10.

[0108] Optionally, the protection circuit 10 may further include a signal generation module 104, or the target chip may include a signal generation module 104;

[0109] The signal generation module 104 is electrically connected to the input terminal of the equipotential line 1011 and the detection module 103, respectively, and is used to send the first detection signal to the equipotential line 1011 and the detection module 103, respectively.

[0110] In this embodiment, the protection circuit 10 itself may include a signal generation module 104, which generates a first detection signal and sends the first detection signal to the equipotential line 1011 and the detection module 103 respectively. Alternatively, the protection circuit 10 may utilize a module unit of the target chip itself as the signal generation module 104, which sends the first detection signal to the equipotential line 1011 and the detection module 103 respectively.

[0111] Optionally, the signal generation module 104 is also electrically connected to the control module 102 to generate a random control signal and send the random control signal to the control module 102; wherein the random control signal is used to instruct the control module 102 to perform random control on the wiring path.

[0112] In this embodiment, the control module 102 can be a multiplexed switch circuit, and the signal generation module 104 can be electrically connected to the control terminal of the control module 102, sending a random control signal to the control module 102. This causes the control module 102 to respond to the random control signal and randomly control the routing path of the equipotential line 1011 at the reconstructed node 1011a. The random control signal can be a random number generated by a random number generator. Since the random number generated by the random number generator is uncontrollable and cannot predict whether the next random number will be 1 or 0, the routing path at the reconstructed node 1011a is completely random under the control of the random number.

[0113] Specifically, the control module 102 can switch on and off in response to a random control signal, reconnecting the first and second ends of an equipotential line 1011, or connecting the first end of an equipotential line 1011 to the second end of another equipotential line 1011, i.e., the equipotential line 1011 at the random control reconstruction node 1011a can be routed independently or multiple equipotential lines 1011 can be routed at intersections.

[0114] In this embodiment, the signal generation module 104 can conveniently control the routing path of the equipotential line 1011 at the reconstructed node 1011a by sending a random control signal to the control module 102. The signal generation module 104 outputs a first detection signal and a random control signal, which can reduce the resource consumption of the protection circuit 10.

[0115] Optionally, the signal generation module 104 is a random number generator, or a physically non-clonable function circuit.

[0116] In this embodiment, the signal generation module 104 can be any structure used to generate unpredictable numbers, i.e., random numbers, such as a random number generator or a physically unclonable function (PUF) circuit. A portion of the random number generated by the signal generation module 104 can be used as a first detection signal input to the equipotential line 1011 and the detection module 103, while another portion can be used as a random control signal input to the control module 102 to control the routing path of the equipotential line 1011.

[0117] For example, 20 equipotential lines 1011 can be grouped in pairs to obtain 10 equipotential line groups 101. The signal generation module 104 is a 32-bit random number generator. The first 20 bits of the random number generator's result can be selected to obtain the first detection signal corresponding to each of the 20 equipotential lines 1011, and the last 10 bits of the random number generator's result can be used as the random control signal corresponding to each of the 10 equipotential line groups 101. Similarly, for 2 equipotential line groups 101 obtained by grouping 4 equipotential lines 1011 in pairs, the signal generation module 104 can be an 8-bit random number generator. The first 4 bits of the result can be selected as the first detection signal corresponding to each of the 4 equipotential lines 1011, and the last 2 bits of the result can be used as the random control signal corresponding to each of the 2 equipotential line groups 101. This is only an example for illustration, and the embodiments of this application do not limit this.

[0118] It should be noted that Physically Unclonable Function (PUF) circuits are highly sensitive to environmental factors. If the temperature or voltage exceeds the operating requirements of the PUF circuit, it may malfunction and fail to work properly. Even if the randomness of the generated random number generator is reduced due to the influence of environmental factors, the probability of the generated random numbers being constantly 0 or 1 is extremely low, and it is sufficient to meet the randomness requirements.

[0119] In this embodiment, the signal generation module 104 can select a random number generator or a physical non-cloning function circuit to generate random numbers, so that the routing path of the equipotential line 1011 at the reconstructed node 1011a is random, thereby improving the anti-attack capability of the protection circuit 10 and improving the security of the protected area of ​​the target chip.

[0120] Optionally, the signal generation module 104 is located in the protected area;

[0121] The input terminal of the equipotential line 1011 is electrically connected to the signal generation module 104 through the through-hole of the shielding layer.

[0122] In this embodiment, the signal generation module 104 can be located in the protected area covered by the equipotential line group 101, so that the equipotential line group 101 shields and protects the signal generation module 104. For example, the signal generation module 104 can be a random number generator in the protected area of ​​the target chip, thus utilizing the original random number generator of the target chip to achieve shielding and protection.

[0123] Specifically, the input terminal of the equipotential line 1011 can enter the trace layer through the through-hole of the shielding layer, and is connected to the signal generation module 104 of the protected area through the metal trace of the trace layer, so that the input terminal of the equipotential line 1011 is electrically connected to the signal generation module 104.

[0124] In this embodiment, the signal generation module 104 is set in the protected area of ​​the target chip. The input end of the equipotential line 1011 is electrically connected to the signal generation module 104 through the through hole of the shielding layer. In this way, the attacker cannot see the signal generation module 104 from the perspective of the attacker, but can only see the through hole of the shielding layer at the input end of the equipotential line 1011. This can confuse the attacker with the through hole of the shielding layer at the reconstruction node 1011a, greatly increasing the difficulty of rewiring attacks.

[0125] In this embodiment, the protection circuit 10 may include a signal generation module 104, or the module unit of the target chip may be used as the signal generation module 104. This can improve the practicality of the protection circuit 10 and reduce the resource consumption of the protection circuit 10.

[0126] Optionally, the detection module 103 is located in the protected area;

[0127] The output end of the equipotential line 1011 is electrically connected to the detection module 103 through the through hole of the shielding layer.

[0128] In this embodiment, the detection module 103 can be disposed in the protected area of ​​the target chip, such that the detection module 103 is covered by the equipotential line group 101. Specifically, the output end of the equipotential line 1011 can enter the wiring layer through the through-hole of the shielding layer, and is connected to the detection module 103 in the protected area through the metal wiring of the wiring layer, so that the output end of the equipotential line 1011 is electrically connected to the detection module 103.

[0129] For example, the detection module 103 can be a combinational logic circuit. The detection module 103 receives a random number sent by the signal generation module 104 as the first detection signal and receives a random number output by the equipotential line 1011 as the second detection signal. The first detection signal will reconstruct the trace path at node 1011a through the equipotential line 1011. The detection module 103 compares the random numbers at the input and output terminals of the equipotential line 1011. If they are consistent, it means that no attack has been carried out. If one or more of the multiple equipotential lines 1011 are inconsistent, it means that the target chip has been attacked.

[0130] In this embodiment, the detection module 103 is set in the protected area of ​​the target chip, and the output end of the equipotential line 1011 is electrically connected to the detection module 103 through the through hole of the shielding layer. In this way, the attacker cannot see the detection module 103 from the perspective of the attacker, but can only see the through hole of the shielding layer at the output end of the equipotential line 1011. This can confuse the attacker with the through hole of the shielding layer at the reconstructed node 1011a, greatly increasing the difficulty of rewiring attack.

[0131] Figure 7 This is a schematic diagram of the circuit structure of another protection circuit 10 provided in this application embodiment, as shown below. Figure 7As shown, the protection circuit 10 also includes a signal generation module 104. The control module 102, the detection module 103, and the signal generation module 104 are all located in the protected area of ​​the target chip. Figure 7 The protection circuit 10 shown fills the top metal layer of the target chip with multiple equipotential line groups 101 as a shielding layer for the target chip. The graphic topology structure formed by the multiple equipotential line groups 101 covers the protected area of ​​the target chip, thus shielding and protecting the protected area of ​​the target chip.

[0132] See Figure 7 The equipotential line group 101 covers the protected area. The signal generation module 104 is electrically connected to the input terminal of the equipotential line 1011, the control module 102, and the detection module 103, respectively. The input and output terminals of the equipotential line 1011 are connected to the detection module 103 and the signal generation module 104 through through-holes in the shielding layer, respectively. Figure 7 The black dots on the medium potential line 1011 indicate through holes in the shielding layer.

[0133] Optionally, the shielding layer adopts a Hamiltonian loop structure;

[0134] The equipotential line group 101 is composed of equipotential lines 1011 in the Hamiltonian circuit structure.

[0135] In this embodiment, multiple equipotential line groups 101 can be configured into a Hamiltonian circuit structure and filled into the top metal layer of the target chip as a shielding layer. This allows the shielding layer of the target chip to adopt a Hamiltonian circuit structure, providing shielding protection for the protected area of ​​the target chip. The equipotential lines 1011 in different equipotential line groups 101 can be the same or different; this embodiment does not impose any restrictions on this.

[0136] Alternatively, the shielding layer of the target chip itself is a Hamiltonian circuit structure, and the equipotential line group 101 can be composed of multiple equipotential lines 1011 in the Hamiltonian circuit structure. The equipotential lines 1011 in the equipotential line group 101 are connected to the control module 102 and the detection module 103 of the protection circuit 10 respectively. The equipotential line group 101 covers the protected area of ​​the target chip and can shield and protect the protected area.

[0137] In this embodiment of the application, the equipotential line group 101 of the protection circuit 10 can be composed of equipotential lines 1011 in the Hamiltonian circuit structure. This can increase the attack difficulty of the equipotential line group 101 by increasing the complexity of the Hamiltonian circuit structure, thereby improving the anti-attack capability of the protection circuit 10.

[0138] Figure 8 This is a schematic diagram of a shielding layer topology provided in an embodiment of this application, such as... Figure 8As shown, the shielding layer of the target chip adopts a Hamiltonian circuit structure, and the equipotential line group 101 is composed of multiple equipotential lines 1011 in the Hamiltonian circuit structure. An equipotential line 1011 may include a reconfiguration node 1011a and / or an obfuscation node 1011b. This embodiment does not limit the number or position of reconfiguration nodes 1011a and obfuscation nodes 1011b on an equipotential line 1011. It should be noted that the Hamiltonian circuit structure is highly complex, making rewiring attacks difficult. Attackers need to spend a significant amount of time finding the beginning and end of the equipotential lines 1011 to short-circuit them for a rewiring attack, resulting in high attack costs.

[0139] In this embodiment, when an attacker launches an attack on a target chip, they need to distinguish the vias at the reconstruction node 1011a and the obfuscated node 1011b from a large number of shielding vias, find the connection relationship of the equipotential lines 1011, and then find the true start and end points, i.e., the input and output points, of the equipotential lines 1011 from the connection relationship. Even if the start and end points of a certain equipotential line 1011 are found and shorted together, Figure 5 For example, the probability of the two routing paths controlled by random numbers is 50% each, so there is a 50% probability that it is wrong. Even if the connection is correct this time, the probability of error next time is still 50%.

[0140] Figure 9 This is a schematic diagram of another shielding layer topology provided in an embodiment of this application, as shown below. Figure 9 As shown, the shielding vias at the beginning and end of the equipotential line 1011, at the reconstruction node 1011a, and at the confusion node 1011b can be irregularly distributed on the top metal layer of the target chip, i.e., the shielding layer, to minimize the area of ​​the shielding line that is easily short-circuited. The control module 102, detection module 103, and signal generation module 104 in the protection circuit 10 can be set in the protected area covered by the equipotential line group 101, so that the attacker's perspective can only see the area shown in the diagram. Figure 9 The diagram shows the topological structure. An attacker attempting to connect all equipotential lines 1011 correctly has a probability of 50% to the power of n, which is close to 0, thus significantly increasing the difficulty of the attack. Once the protection circuit 10 is operational, the probability of a successful attack on the target chip is greatly reduced. The protection circuit 10 has the advantages of simple structure and high portability.

[0141] Furthermore, once an equipotential line 1011 is subjected to a rewiring attack, it will be detected by the detection module 103. The detection module 103 can output an alarm signal to remind the main control unit of the target chip. If the main control unit takes protective measures, such as overwriting important data in the protected area, it will be meaningless for the attacker to continue the attack, which can improve the security of the target chip.

[0142] This application provides a chip that includes the protection circuit 10 as described in the foregoing embodiments.

[0143] The chip in this application embodiment has the same advantages as the related technologies and circuit embodiments, which will not be repeated here.

[0144] This application provides an electronic device that includes the chip described in the foregoing embodiments.

[0145] The electronic device of this application has the same advantages as the related technologies and circuit embodiments, and will not be repeated here.

[0146] This application provides a protection circuit 10, a chip, and an electronic device. A Hamiltonian circuit structure is used to fill and cover the top metal layer of the chip, i.e., the shielding layer, thus shielding the protected area of ​​the target chip. An equipotential line group 101 is formed by multiple equipotential lines 1011 in the Hamiltonian circuit structure. By setting reconstruction nodes 1011a and / or confusion nodes 1011b on the equipotential lines 1011, and using random numbers generated by a signal generation module 104 (e.g., a random number generator) as the first detection signal and a random control signal, the control module 103 dynamically and randomly reconstructs the shielding layer topology in response to the random control signal. The detection module 103 compares the second detection signal output from the equipotential lines 1011 with the first detection signal for verification, continuously detecting physical attacks on the target chip. This achieves a dynamic active metal shielding layer structure, increasing the difficulty of attacks and improving the anti-attack capability of the protection circuit 10. It achieves good protection with limited resources, thereby improving the security of the target chip.

[0147] It should be noted that, in this document, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element. Furthermore, it should be noted that the scope of the methods and apparatuses in the embodiments of this application is not limited to performing functions in the order shown or discussed, but may also include performing functions substantially simultaneously or in the reverse order, depending on the functions involved. For example, the described methods may be performed in a different order than described, and various steps may be added, omitted, or combined. Additionally, features described with reference to certain examples may be combined in other examples.

[0148] The embodiments of this application have been described above with reference to the accompanying drawings. However, this application is not limited to the specific embodiments described above. The specific embodiments described above are merely illustrative and not restrictive. Those skilled in the art can make many other forms under the guidance of this application without departing from the spirit and scope of the claims, and all of these forms are within the protection scope of this application.

Claims

1. A protection circuit, characterized in that, The protection circuit includes: an equipotential line group, a control module, and a detection module; The equipotential line group is located in the shielding layer of the target chip; the equipotential line group covers the protected area of ​​the target chip; the control module is located in the protected area and is disposed in the wiring layer below the shielding layer; The equipotential line group includes multiple equipotential lines; the output end of the equipotential line is electrically connected to the detection module; the input end of the equipotential line is used to receive the first detection signal. The equipotential line includes a reconstruction node; at the reconstruction node, the equipotential line is broken, and the two ends of the broken equipotential line are electrically connected to the control module respectively. The control module is used to randomly control the routing path of the equipotential lines at the reconstruction node; wherein, the routing path is located in the protected area and is set in the routing layer; the routing path includes multiple intersecting routing of the equipotential lines, and / or, the equipotential lines are routing independently; The detection module is used to receive the first detection signal, compare the first detection signal with the second detection signal, and output an alarm signal if the comparison result indicates that the target chip has been attacked; wherein, the second detection signal is the detection signal output by the equipotential line to the detection module.

2. The protection circuit according to claim 1, characterized in that, At the reconstructed node, the equipotential line includes a first end and a second end; The first end is connected to the wiring layer through the first through hole of the shielding layer, and is electrically connected to the control module through the first wiring of the wiring layer; The second end is connected to the wiring layer through the second through hole of the shielding layer, and is electrically connected to the control module through the second wiring of the wiring layer.

3. The protection circuit according to claim 2, characterized in that, The trace layer is the metal layer of the protected area; the first trace and the second trace are metal traces of the metal layer.

4. The protection circuit according to claim 1, characterized in that, The equipotential line group includes a first equipotential line and a second equipotential line; the first equipotential line and the second equipotential line are two adjacent equipotential lines in the equipotential line group; The output terminals of the first equipotential line and the second equipotential line are respectively electrically connected to the detection module; the first equipotential line and the second equipotential line are respectively used to receive the first detection signal. The reconstructed node of the first equipotential line is the first node; The reconstructed node of the second equipotential line is the second node; The straight-line distance between the first node and the second node is less than a preset distance threshold.

5. The protection circuit according to claim 4, characterized in that, The first node and the second node are located within the target area; the first equipotential line and the second equipotential line within the target area are parallel lines.

6. The protection circuit according to claim 1, characterized in that, The equipotential lines also include confusion nodes; At the obfuscation node, the equipotential line is broken, and the two ends of the broken equipotential line are connected to the trace layer through the through-hole of the shielding layer; the equipotential line is reconnected in the trace layer.

7. The protection circuit according to claim 6, characterized in that, At the confusion node, the equipotential line includes a third end and a fourth end; The third end is connected to the wiring layer through a third through-hole on the shielding layer; the fourth end is connected to the wiring layer through a fourth through-hole on the shielding layer; the third end and the fourth end are reconnected through the third wiring of the wiring layer; Alternatively, the third and fourth ends are connected to the trace layer through a fifth through-hole on the shielding layer, and the connection is restored in the trace layer.

8. The protection circuit according to any one of claims 1-7, characterized in that, The protection circuit further includes a signal generation module, or the target chip includes the signal generation module; The signal generation module is electrically connected to the input end of the equipotential line and the detection module, respectively, and is used to send the first detection signal to the equipotential line and the detection module.

9. The protection circuit according to claim 8, characterized in that, The signal generation module is also electrically connected to the control module and is used to generate a random control signal and send the random control signal to the control module; wherein the random control signal is used to instruct the control module to perform random control on the wiring path.

10. The protection circuit according to claim 8, characterized in that, The signal generation module is a random number generator, or a physically non-clonable function circuit.

11. The protection circuit according to claim 8, characterized in that, The signal generation module is located in the protected area; The input end of the equipotential line is electrically connected to the signal generation module through a through-hole in the shielding layer.

12. The protection circuit according to any one of claims 1-7, characterized in that, The detection module is located in the protected area; The output end of the equipotential line is electrically connected to the detection module through the through-hole of the shielding layer.

13. The protection circuit according to any one of claims 1-7, characterized in that, The shielding layer adopts a Hamiltonian loop structure; The equipotential line group is composed of equipotential lines in the Hamiltonian circuit structure.

14. A chip, characterized in that, The chip includes the protection circuit as described in any one of claims 1-13.

15. An electronic device, characterized in that, The electronic device includes the chip as described in claim 14.

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