A multi-DIE low-power management system and method based on the Chiplet architecture

Abstract

The present invention discloses a multi-DIE low-power management system and method based on a chiplet architecture, which includes a main control MCU DIE, a controlled ASIC_MAIN DIE, and several controlled ASIC_SLV DIEs. The main control MCU DIE communicates with the controlled ASIC_MAIN DIE through signal TX and signal RX, and the controlled ASIC_MAIN DIE communicates with several controlled ASIC_SLV DIEs through signal TX32 and signal RX32. For the expansion of multiple DIEs, the present invention can manage the power supply and clock of each DIE from the system level and can meet the working scenario requirements of different DIEs.

Description

Technical Field

[0001] The present invention relates to a multi-DIE low-power management system and method, in particular to a multi-DIE low-power management system and method based on a Chiplet architecture, belonging to the technical field of semiconductor integrated circuits. Background Art

[0002] The development of semiconductor technology is changing with each passing day, and the complexity and integration of chips are also increasing exponentially. The traditional single-DIE SOC (system on chip) is increasingly difficult to meet diverse requirements. The Chiplet architecture is a new packaging technology that packages small chips with different functions and manufacturing processes together to form a heterogeneous chip. Chiplets can use different process nodes for different functional dielets, which can reduce costs and improve yield. However, while Chiplets have many advantages, they also face some challenges. Packaging and integrating multiple dielets together will inevitably pose a greater challenge to heat dissipation. Therefore, how to manage the power consumption of Chiplet chips has become a very important issue. Automotive chips require low standby power consumption to reduce the power consumption of the battery. Multiple different dielets often have different power consumption requirements due to different working scenarios. How to balance the performance and power consumption of the entire system has become a very important issue.

[0003] For the power management of multi-dielet Chiplet chips, there are mainly the following problems: 1. Different dielets often operate in different working modes and have different power supply and clock requirements. If each dielet has an internal power supply and clock and low-power circuit design is carried out, at the system level, there will be a large amount of redundant circuits, which is also a waste of area, that is, an increase in cost. 2. The traditional low-power design process for single-dielet chips usually requires the foundary to provide specific devices related to low-power design to support the design flow, and usually only one process can be used for a single dielet. However, Chiplet chips often have different processes for different dielets. Summary of the Invention

[0004] The technical problem to be solved by the present invention is to provide a multi-DIE low-power management system and method based on a Chiplet architecture to systematically manage the power supply and clock of each dielet.

[0005] To solve the above technical problems, the technical solution adopted by the present invention is:

[0006] A multi-DIE low-power management system based on a chiplet architecture, including a master MCU DIE, a controlled ASIC_MAIN DIE, and several controlled ASIC_SLV DIEs. The master MCU DIE communicates with the controlled ASIC_MAIN DIE through signal TX and signal RX, and the controlled ASIC_MAIN DIE communicates with several controlled ASIC_SLV DIEs through signal TX32 and signal RX32.

[0007] Further, the controlled ASIC_MAIN DIE includes an analog top-level module ANALOG_top and a digital top-level module DIGITAL_top.

[0008] Further, the analog top-level module ANALOG_top includes a power module LDO, a clock generation module OSC, and an off-chip LIN bus interaction module LINphy. The power module LDO provides power signals to each DIE, the clock generation module OSC provides clock signals to each DIE, and the off-chip LIN bus interaction module LINphy converts the LIN frames of the off-chip host into signal LIN_RXD and transmits it to the master MCU DIE.

[0009] Further, the digital top-level module DIGITAL_top includes a power management module PMU, a communication module COMU, and a digital core module DIG_core. The communication module COMU parses the instructions of the master MCU DIE and determines whether the instructions of the master MCU DIE are for the digital core module DIG_core, the controlled ASIC_SLV DIE, or the power management module PMU; when the communication module COMU parses that the device address in the instructions of the master MCU DIE corresponds to the controlled ASIC_MAIN DIE, it switches the communication line to the digital core module DIG_core; when the communication module COMU parses that the device address in the instructions of the master MCU DIE corresponds to the controlled ASIC_SLV DIE, it switches the communication line to the controlled ASIC_SLV DIE; when the communication module COMU parses that the instructions of the master MCU DIE act on the power management module PMU, it generates a corresponding request signal pd_req for the DIE to enter the low-power mode.

[0010] Further, the digital core module DIG_core is a power-down voltage domain, and the power management module PMU and the communication module COMU are always-on voltage domains.

[0011] A management method for a multi-DIE low-power management system based on a chiplet architecture, including the following steps:

[0012] When the digital core module DIG_core does not need to work, the main control MCU DIE sends an instruction to the communication module COMU. The communication module COMU generates a power-down request signal pulse to the power management module PMU. The power management module PMU first generates a clock gating enable signal CG to turn off the clock CK of the digital core module DIG_core, and then generates an iso signal to the isolation device ISOCELL to force the signal output from the voltage domain of the digital core module DIG_core to the always-on voltage domain to a fixed value of 1. Then the power management module PMU generates a power switch control signal sw to cut off the power of the digital core module DIG_core, so that the controlled ASIC_MAIN DIE enters the low-power state, and the entire chip is in the semi-sleep mode 1. When it is necessary to wake up the digital core module DIG_core from the power-down state, the off-chip host uses the LIN bus to send a wake-up frame with a low level of a specific duration to the off-chip LIN bus interface module LINphy. The power management module PMU parses the wake-up frame and then turns on the power of the digital core module DIG_core, then releases the iso signal of the isolation device ISO CELL, and finally releases the clock gating enable signal CG to turn on the clock of the digital core module DIG_core, and the digital core module DIG_core enters the normal working mode;

[0013] When the controlled ASIC_SLV DIE does not need to work, the main control MCU DIE sends an instruction to the communication module COMU. The communication module COMU generates a power-down request signal pulse to the power management module PMU module. The power management module PMU first generates a clock gating enable signal CG to turn off the clock CK of the controlled ASIC_SLV DIE, and then generates an iso signal to the isolation device ISO CELL to force the signal output from the controlled ASIC_SLV DIE to the controlled ASIC_MAIN DIE to a fixed value of 1. Then the power management module PMU generates a power switch control signal sw to cut off the power of the controlled ASIC_SLV DIE, so that the controlled ASIC_SLV DIE enters the low-power state, and the entire chip is in the semi-sleep mode 2. When it is necessary to wake up the controlled ASIC_SLV DIE from the power-down state, the off-chip host uses the LIN bus to send a wake-up frame with a low level of a specific duration to the off-chip LIN bus interface module LINphy. The power management module PMU parses the wake-up frame and then turns on the power of the controlled ASIC_SLV DIE, then releases the iso signal of the isolation device ISO CELL, and finally releases the clock gating enable signal CG to turn on the clock of the controlled ASIC_SLV DIE, and the controlled ASIC_SLV DIE enters the normal working mode;

[0014] When the controlled ASIC_SLV DIE is powered off and the controlled ASIC_MAIN DIE is in the normal working mode, the main control MCU DIE is also in the normal working mode; if the controlled ASIC_MAIN DIE does not need to work at this time, the main control MCU DIE sends a power-off request instruction to the communication module COMU, and the communication module COMU generates a power-off request pulse to the power management module PMU to turn off the power and clock of the digital core module DIG_core in the controlled ASIC_MAIN DIE and the main control MCU DIE, and the entire chip enters the deep sleep mode; if it is necessary to wake up from the deep sleep, the off-chip host uses the LIN bus to send a wake-up frame with a specific duration of low level to the off-chip LIN bus interface module LINphy, and the power management module PMU turns on the power and clock of the digital core module DIG_core, the controlled ASIC_SLV DIE, and the main control MCU DIE, and the entire chip returns to the normal working mode;

[0015] When the digital core module DIG_core of the controlled ASIC_MAIN DIE is powered off and the controlled ASIC_SLV DIE is in the normal working mode, the main control MCU DIE is also in the normal working mode; if the controlled ASIC_SLV DIE does not need to work at this time, the main control MCU DIE sends a power-off request instruction to the communication module COMU, and the communication COMU generates a power-off request pulse to the power management module PMU to turn off the power and clock of the controlled ASIC_SLV DIE and the main control MCU DIE, and the entire chip enters the deep sleep mode; if it is necessary to wake up from the deep sleep, the off-chip host uses the LIN bus to send a wake-up frame with a specific duration of low level to the off-chip LIN bus interface module LINphy, and the power management module PMU turns on the power and clock of the digital core module DIG_core, the controlled ASIC_SLV DIE, and the main control MCU DIE, and the entire chip returns to the normal working mode.

[0016] Compared with the prior art, the present invention has the following advantages and effects: The present invention provides a multi-DIE low-power management system and method based on a chiplet architecture. For the expansion of multiple DIEs, the power supply and clock of each DIE can be managed at the system level, meeting the working scenario requirements of different DIEs. Compared with the traditional chiplet integration low-power management scheme, the present invention only requires one DIE to provide power supply, clock, power management module, and wake-up logic, avoiding the redundancy of the circuit at the entire chip level and saving the area cost; the single-chiplet low-power design involves the front-end RTL plus UPF to the back-end power supply planning, placement and routing, and verification, with a cumbersome process and a relatively long time. Compared with the independent low-power design for each DIE, the present invention only has one DIE for the low-power design process while the other DIEs only need to perform conventional designs, so the development time cost can also be greatly saved. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figure 1 FIG. is a schematic diagram of a multi-DIE low-power management system based on a chiplet architecture of the present invention.

[0018] Figure 2 FIG. is a protocol timing diagram of the instruction operation of a multi-DIE low-power management method based on a chiplet architecture of the present invention.

[0019] Figure 3 FIG. is a state machine transition diagram of the PMU on the controlled ASIC_MAIN DIE side of the present invention.

[0020] Figure 4 FIG. is a timing diagram of the relevant signals of the power management module PMU for entering the semi-sleep mode 1 and restoring from the semi-sleep mode 1 to the normal working mode of the present invention.

[0021] Figure 5 FIG. is a timing diagram of the relevant signals of the power management module PMU for entering the semi-sleep mode 2 and restoring from the semi-sleep mode 2 to the normal working mode of the present invention.

[0022] Figure 6 FIG. is a timing diagram of the relevant signals of the power management module PMU for entering the deep sleep mode and restoring from the deep sleep mode to the normal working mode of the present invention.

[0023] Figure 7 FIG. is a timing diagram of the relevant signals of the power management module PMU for entering the deep sleep mode from the semi-sleep mode 1 and then restoring from the deep sleep mode to the normal working mode of the present invention. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0024] In order to elaborate in detail the technical solutions adopted by the present invention to achieve the predetermined technical objectives, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only partial embodiments of the present invention, rather than all embodiments. And, without creative efforts, the technical means or technical features in the embodiments of the present invention can be replaced. The present invention will be described in detail below with reference to the drawings and in conjunction with the embodiments.

[0025] As Figure 1 shown, a multi-DIE low-power management system based on a chiplet architecture of the present invention includes a main control MCU DIE, a controlled ASIC_MAIN DIE, and several controlled ASIC_SLV DIEs. The main control MCU DIE communicates with the controlled ASIC_MAIN DIE through signal TX and signal RX, and the controlled ASIC_MAIN DIE communicates with several controlled ASIC_SLV DIEs through signal TX32 and signal RX32.

[0026] Among them, signal TX, signal RX, signal TX32, and signal RX32 only represent signals and transmission directions, including but not limited to being transmitted through a single wire.

[0027] The controlled ASIC_MAIN DIE includes an analog top-level module ANALOG_top and a digital top-level module DIGITAL_top.

[0028] The analog top-level module ANALOG_top includes a power supply module LDO, a clock generation module OSC, and an off-chip LIN bus interaction module LINphy. The power supply module LDO provides power signals to each DIE, the clock generation module OSC provides clock signals to each DIE, and the off-chip LIN bus interaction module LINphy converts the LIN frames of the off-chip host into signal LIN_RXD and transmits it to the main control MCU DIE.

[0029] The digital top-level module DIGITAL_top includes a power management module PMU, a communication module COMU, and a digital core module DIG_core. The communication module COMU parses the instructions of the master MCU DIE and determines whether the instructions of the master MCU DIE are for the digital core module DIG_core, the controlled ASIC_SLV DIE, or the power management module PMU. When the communication module COMU parses that the device address in the instructions of the master MCU DIE corresponds to the controlled ASIC_MAIN DIE, it switches the communication line to the digital core module DIG_core. When the communication module COMU parses that the device address in the instructions of the master MCU DIE corresponds to the controlled ASIC_SLV DIE, it switches the communication line to the controlled ASIC_SLV DIE. When the communication module COMU parses that the instructions of the master MCU DIE act on the power management module PMU, it generates a corresponding request signal pd_req for the DIE to enter the low-power mode.

[0030] The digital core module DIG_core is a power-down voltage domain, and the power management module PMU and the communication module COMU are always-on voltage domains.

[0031] A management method for a multi-DIE low-power management system based on a chiplet architecture includes the following steps:

[0032] When the digital core module DIG_core does not need to work, the master MCU DIE sends instructions to the communication module COMU. The communication module COMU generates a power-down request signal pulse to the power management module PMU. The power management module PMU first generates a clock gating enable signal CG to turn off the clock CK of the digital core module DIG_core, and then generates an iso signal to the isolation device ISOCELL to force the signal output from the voltage domain of the digital core module DIG_core to the always-on voltage domain to a fixed value of 1. Then the power management module PMU generates a power switch control signal sw to cut off the power of the digital core module DIG_core, so that the controlled ASIC_MAIN DIE enters the low-power state, and the entire chip is in the semi-sleep mode 1. When it is necessary to wake up the digital core module DIG_core from the power-down state, the off-chip host uses the LIN bus to send a wake-up frame with a specific duration of low level to the off-chip LIN bus interface module LINphy. The power management module PMU parses the wake-up frame and then turns on the power of the digital core module DIG_core, then releases the iso signal of the isolation device ISO CELL, and finally releases the clock gating enable signal CG to turn on the clock of the digital core module DIG_core, and the digital core module DIG_core enters the normal working mode.

[0033] The power supply and clock of the controlled ASIC_SLV DIE are provided by the controlled ASIC_MAIN DIE and can be completely cut off. When the controlled ASIC_SLV DIE does not need to work, the main control MCU DIE sends an instruction to the communication module COMU. The communication module COMU generates a power-down request signal pulse to the power management module PMU. The power management module PMU first generates a clock gating enable signal CG to turn off the clock CK of the controlled ASIC_SLV DIE, and then generates an iso signal to the isolation device ISO CELL to force the signal output from the controlled ASIC_SLV DIE to the controlled ASIC_MAIN DIE to a fixed value of 1. Then the power management module PMU generates a power switch control signal sw to cut off the power supply of the controlled ASIC_SLV DIE, so that the controlled ASIC_SLV DIE enters the low-power state, and the whole chip is in the semi-sleep mode 2. When it is necessary to wake up the controlled ASIC_SLV DIE from the power-down state, the off-chip host uses the LIN bus to send a wake-up frame with a low level of a specific duration to the off-chip LIN bus interface module LINphy. The power management module PMU parses the wake-up frame, then turns on the power supply of the controlled ASIC_SLV DIE, then releases the iso signal of the isolation device ISO CELL, and finally releases the clock gating enable signal CG to turn on the clock of the controlled ASIC_SLV DIE, and the controlled ASIC_SLV DIE enters the normal working mode.

[0034] When the controlled ASIC_SLV DIE is powered down and the controlled ASIC_MAIN DIE is in the normal working mode, the main control MCU DIE is also in the normal working mode. If the controlled ASIC_MAIN DIE does not need to work at this time, the main control MCU DIE sends a power-down request instruction to the communication module COMU. The communication module COMU generates a power-down request pulse to the power management module PMU to turn off the power supply and clock of the digital core module DIG_core in the controlled ASIC_MAIN DIE and the main control MCU DIE, and the whole chip enters the deep sleep mode. If it is necessary to wake up from the deep sleep, the off-chip host uses the LIN bus to send a wake-up frame with a low level of a specific duration to the off-chip LIN bus interface module LINphy. The power management module PMU turns on the power supply and clock of the digital core module DIG_core, the controlled ASIC_SLV DIE, and the main control MCU DIE, and the whole chip returns to the normal working mode.

[0035] When the digital core module DIG_core of the controlled ASIC_MAIN DIE is powered off and the controlled ASIC_SLV DIE is in the normal working mode, the main control MCU DIE is also in the normal working mode; if the controlled ASIC_SLV DIE does not need to work at this time, the main control MCU DIE sends a power-off request instruction to the communication module COMU, and the communication COMU generates a power-off request pulse to the power management module PMU to turn off the power and clock of the controlled ASIC_SLV DIE and the main control MCU DIE, and the entire chip enters the deep sleep mode; if it is necessary to wake up from the deep sleep, the off-chip host uses the LIN bus to send a wake-up frame with a specific low-level duration to the off-chip LIN bus interaction module LINphy, and the power management module PMU turns on the power and clock of the digital core module DIG_core, the controlled ASIC_SLV DIE, and the main control MCU DIE, and the entire chip returns to the normal working mode.

[0036] During the working mode conversion, there is no instruction to directly switch between the semi-sleep mode 1 and the semi-sleep mode 2.

[0037] The present invention will be further described below through specific embodiments.

[0038] As Figure 2 shown, the DEVID byte represents the device address of the ASIC DIE. Therefore, the bit width of the DEVID determines the number of ASIC DIEs interconnected with the main control MCU DIE, including but not limited to more than two ASIC DIEs. The analog top module ANALOG_top in the controlled ASIC_MAIN DIE provides the power module LDO and the clock generation module OSC. The output power VDD_AO is a normally open power supply, and CK is a normally open clock; while the power VDD1 and the clock CK1 for the digital core module DIG_core can both be controlled and cut off by the power management module PMU; the power VDD2 and the clock CK2 for the controlled ASIC_SLV DIE can both be controlled and cut off by the power management module PMU; the power VDD3 and the clock CK3 for the main control MCU DIE can both be controlled and cut off by the power management module PMU.

[0039] The protocol for the master MCU DIE to send instructions to the ASIC DIE only represents the byte order and includes, but is not limited to, various serial buses or parallel buses. The MODE byte represents the operation mode of the master MCU DIE on the ASIC DIE. For example, when MODE = 0x7A, it represents entering the sleep mode; DEVID represents the device to be operated. For example, when DEVID is equal to 0x01, it represents that the object to be operated is the controlled ASIC_MAIN DIE; when DEVID is equal to 0x02, it represents that the object to be operated is the controlled ASIC_SLV DIE. When MODE = 0x7A, DEVID = 0x01, writing data WDATA = 0x55 to the register address 0xFF, and the CRC check value is also correct, it represents letting the controlled ASIC_MAIN DIE enter the sleep mode, that is, the semi-sleep mode 1. When MODE = 0x7A, DEVID = 0x02, writing data WDATA = 0x55 to the register address 0xFF, and the CRC check value is also correct, it represents letting the controlled ASIC_SLV DIE enter the sleep mode, that is, the semi-sleep mode 2. When MODE = 0x7A, the device address DEVID = 0xBF, writing data WDATA = 0x55 to the register address 0xFF, and the CRC check value is also correct, it represents letting both the controlled ASIC_MAIN DIE and the controlled ASIC_SLV DIE enter the sleep mode, that is, the deep sleep mode.

[0040] Figure 3 Describes the state machine conversion of the power management module PMU of the controlled ASIC_MAIN DIE, that is, the working mode switching of the entire system. Figures 4 to 7 Then it is the timing diagram of various control signals of the power management module PMU when switching between each working mode.

[0041] For example, when powered on and operating normally, the entire chip is in the normal operating mode, that is, each DIE is operating normally. When, at a certain moment, the digital core module DIG_core of the controlled ASIC_MAIN DIE has no data acquisition and transmission tasks, in order to save power, the master MCU DIE can send an instruction with the byte sequence MODE = 0x7A, DEVID = 0x01, REGADDR = 0xFF, WDATA = 0x55, and the CRC is automatically calculated. When the communication module COMU of the controlled ASIC_MAIN DIE receives and parses the correct bytes and checks the CRC, a high pulse of the sleep request signal pd_req1 will be generated. Subsequently, the power management module PMU will first pull down the clock gating enable signal CG1, then the clock CK1 of the digital core module DIG_core will be turned off; then the enable signal iso1 of the isolation device ISO CELL will be pulled high to clamp the signal output from the digital core module DIG_core to the Always on voltage domain to a fixed value; finally, the control signal sw1 of the power switch PSW will be pulled high to cut off the power VDD1 of the digital core module DIG_core, and the system will enter the semi-sleep mode 1. After a period of time, when it is desired for the digital core module DIG_core of the controlled ASIC_MAIN DIE to continue operating, that is, to resume from the semi-sleep mode to the normal operating mode, only an external host needs to send a low-level wake-up signal LIN_WK lasting 200 us to the LIN bus. When the power management module PMU parses the correct wake-up frame, it will first pull down the control signal sw1 of the power switch PSW to connect the power VDD1 of the digital core module DIG_core, then release the enable signal iso1 of the isolation device ISO CELL to no longer clamp the output of the digital core module DIG_core, and finally resume the clock CK1 of the digital core module DIG_core, and the system will enter the normal operating mode.

[0042] When the entire chip is in the normal working mode, and when at a certain moment, the controlled ASIC_SLV DIE has no data acquisition and transmission tasks, in order to save power consumption, the master MCU DIE can send an instruction. The byte sequence is MODE = 0x7A, DEVID = 0x02, REGADDR = 0xFF, WDATA = 0x55, and the CRC is automatically calculated. When the communication module COMU of the controlled ASIC_MAIN DIE receives and parses the correct bytes and checks the CRC, it will generate a high pulse of the sleep request signal pd_req2. Subsequently, the power management module PMU will first pull down the clock gating enable signal CG2, then the clock CK2 of the controlled ASIC_SLV DIE is turned off; then it will pull up the enable signal iso2 of the isolation device ISO CELL to clamp the signal output from the controlled ASIC_SLV DIE to a fixed value; finally, it will pull up the control signal sw2 of the power switch PSW to cut off the power VDD2 of the controlled ASIC_SLV DIE, and the system enters the semi-sleep mode 2. After a period of time, if you want the controlled ASIC_SLV DIE to continue working, that is, to resume from the semi-sleep mode 2 to the normal working mode, you only need to send a low-level wake-up signal LIN_WK lasting 200 us to the LIN bus from an off-chip host. When the power management module PMU parses the correct wake-up frame, it will first pull down the control signal sw2 of the power switch PSW to connect the power VDD2 of the controlled ASIC_SLV DIE, then release the enable signal iso2 of the isolation device ISO CELL to no longer clamp the output of the controlled ASIC_SLV DIE, and finally resume the clock CK2 of the controlled ASIC_SLV DIE, and the system enters the normal working mode.

[0043] When the entire chip is in the normal working mode, and when at a certain moment, there are no data acquisition and transmission tasks in the digital core modules DIG_core of the controlled ASIC_SLV DIE and the controlled ASIC_MAIN DIE, in order to save power consumption, the power supplies of the digital core module DIG_core, the controlled ASIC_SLV DIE, and the main control MCU DIE can be cut off. An instruction can be sent through the main control MCU DIE, with the byte sequence being MODE = 0x7A, DEVID = 0xBF, REGADDR = 0xFF, WDATA = 0x55, and the CRC is automatically calculated. When the communication module COMU of the controlled ASIC_MAIN DIE receives and parses the correct bytes and the CRC check is correct, high pulses of the sleep request signals pd_req1 and pd_req2 will be generated. Subsequently, the power management module PMU will first pull down the control clock gating enable signals CG1~3, then the clocks CK1~3 of the controlled ASIC_MAIN DIE, the controlled ASIC_SLV DIE, and the main control MCU DIE will be turned off; then the enable signals iso1~3 of the isolation devices ISO CELL will be pulled high, and finally the control signals sw1~3 of the power switch PSW will be pulled high to cut off the power supplies VDD1~3 of the controlled ASIC_MAIN DIE, the controlled ASIC_SLV DIE, and the main control MCU DIE, and the system will enter the deep sleep mode. After a period of time, when wanting to resume from the deep sleep mode to the normal working mode, only need the off-chip host to give a low-level wake-up signal LIN_WK lasting 200 us to the LIN bus. When the power management module PMU parses the correct wake-up frame, it will first pull down the control signals sw1~3 of the power switch PSW to connect the power supplies VDD1~3 of the controlled ASIC_MAIN DIE, the controlled ASIC_SLV DIE, and the main control MCU DIE, then release the enable signals iso1~3 of the isolation devices ISO CELL, and finally resume the clocks CK1~3 of the controlled ASIC_MAIN DIE, the controlled ASIC_SLV DIE, and the main control MCU DIE, and the system will enter the normal working mode.

[0044] When the system is in the semi-sleep mode 1, if the controlled ASIC_SLV DIE also has no data acquisition and transmission tasks and it is desired to further reduce power consumption, an instruction can be sent through the master MCU DIE. The byte sequence is MODE = 0x7A, DEVID = 0xBF, REGADDR = 0xFF, WDATA = 0x55, and the CRC is automatically calculated. When the communication module COMU of the controlled ASIC_MAIN DIE receives and parses the correct bytes and checks the CRC, high pulses of the sleep request signals pd_req1 and pd_req2 will be generated. The power management module PMU will switch CG2~3, iso2~3, and sw2~3 to further turn off the clocks and power supplies of the controlled ASIC_SLV DIE and the master MCU DIE, thereby entering the deep sleep mode. As Figure 7 shown is the PMU timing conversion diagram from the semi-sleep mode 1 to the deep sleep mode and then from the deep sleep mode back to the normal working mode.

[0045] Similarly, the conversion process from the semi-sleep mode 2 to the deep sleep mode can be obtained.

[0046] The present invention provides a multi-DIE low-power management system and method based on the chiplet architecture. For the expansion of multiple DIEs, the power supplies and clocks of each DIE can be managed at the system level, which can meet the working scenario requirements of different DIEs. Compared with the traditional chiplet integration low-power management scheme, the present invention only requires one DIE to provide power supply, clock, power management module, and wake-up logic, avoiding the redundancy of the circuits at the entire chip level and saving the area cost; the low-power design of a single chiplet involves the front-end RTL plus UPF to the back-end power supply planning, placement and routing, and verification, with a cumbersome process and a relatively long time. Compared with the low-power design of each DIE independently, the present invention only has one DIE for the low-power design process while the other DIEs only need to be designed conventionally. Therefore, the development time cost can also be greatly saved.

[0047] The above are only the preferred embodiments of the present invention and do not impose any form of limitation on the present invention. Although the present invention has been disclosed above with the preferred embodiments, it is not intended to limit the present invention. Any person skilled in the art can make some modifications or decorations to the above-disclosed technical content to make equivalent changes within the scope of the technical solution of the present invention. However, as long as the content of the technical solution of the present invention is not departed from, any simple modifications, equivalent replacements, and improvements made to the above embodiments within the spirit and principle of the present invention still fall within the protection scope of the technical solution of the present invention.

Claims

1. A multi-DIE low-power management system based on a chiplet architecture, characterized in that: It includes a master MCU DIE, a controlled ASIC_MAIN DIE, and several controlled ASIC_SLV DIEs. The master MCU DIE communicates with the controlled ASIC_MAIN DIE through signal TX and signal RX. The controlled ASIC_MAIN DIE communicates with several controlled ASIC_SLV DIEs through signal TX32 and signal RX32; The controlled ASIC_MAIN DIE includes an analog top-level module ANALOG_top and a digital top-level module DIGITAL_top. The analog top-level module ANALOG_top includes a power supply module LDO, a clock generation module OSC, and an off-chip LIN bus interaction module LINphy. The power supply module LDO provides power signals to each DIE. The clock generation module OSC provides clock signals to each DIE. The off-chip LIN bus interaction module LINphy converts the LIN frames of the off-chip host into signal LIN_RXD and transmits it to the master MCU DIE.

2. The multi-DIE low-power management system based on a chiplet architecture according to claim 1, wherein: The digital top-level module DIGITAL_top includes a power management module PMU, a communication module COMU, and a digital core module DIG_core. The communication module COMU parses the instructions of the master MCU DIE and determines whether the instructions of the master MCU DIE are for the digital core module DIG_core, the controlled ASIC_SLV DIE, or the power management module PMU. When the communication module COMU parses that the device address in the instructions of the master MCU DIE corresponds to the controlled ASIC_MAIN DIE, it switches the communication line to the digital core module DIG_core. When the communication module COMU parses that the device address in the instructions of the master MCU DIE corresponds to the controlled ASIC_SLV DIE, it switches the communication line to the controlled ASIC_SLV DIE. When the communication module COMU parses that the instructions of the master MCU DIE act on the power management module PMU, it generates a corresponding request signal pd_req for the DIE to enter the low-power mode.

3. The multi-DIE low-power management system based on the chiplet architecture according to claim 2, characterized in that: The digital core module DIG_core is a power-down voltage domain, and the power management module PMU and the communication module COMU are always-on voltage domains.

4. A management method for a multi-DIE low-power management system based on a chiplet architecture according to any one of claims 1-3, characterized in that It includes the following steps: When the digital core module DIG_core does not need to work, the main control MCU DIE sends an instruction to the communication module COMU. The communication module COMU generates a power-down request signal pulse to the power management module PMU. The power management module PMU first generates a clock gating enable signal CG to turn off the clock CK of the digital core module DIG_core, and then generates an iso signal to the isolation device ISO CELL, forcing the signal output from the voltage domain of the digital core module DIG_core to the always-on voltage domain to a fixed value of 1. Then the power management module PMU generates a power switch control signal sw to cut off the power supply of the digital core module DIG_core, so that the controlled ASIC_MAIN DIE enters the low-power state, and the whole chip is in the semi-sleep mode 1. When it is necessary to wake up the digital core module DIG_core from the power-down state, the off-chip host uses the LIN bus to send a low-level wake-up frame to the off-chip LIN bus interface module LINphy. The power management module PMU parses the wake-up frame and then turns on the power supply of the digital core module DIG_core, then releases the iso signal of the isolation device ISO CELL, and finally releases the clock gating enable signal CG to turn on the clock of the digital core module DIG_core, and the digital core module DIG_core enters the normal working mode; When the controlled ASIC_SLV DIE does not need to work, the main control MCU DIE sends an instruction to the communication module COMU. The communication module COMU generates a power-down request signal pulse to the power management module PMU module. The power management module PMU first generates a clock gating enable signal CG to turn off the clock CK of the controlled ASIC_SLV DIE, and then generates an iso signal to the isolation device ISO CELL, forcing the signal output from the controlled ASIC_SLV DIE to the controlled ASIC_MAIN DIE to a fixed value of 1. Then the power management module PMU generates a power switch control signal sw to cut off the power supply of the controlled ASIC_SLV DIE, so that the controlled ASIC_SLV DIE enters the low-power state, and the whole chip is in the semi-sleep mode 2. When it is necessary to wake up the controlled ASIC_SLV DIE from the power-down state, the off-chip host uses the LIN bus to send a low-level wake-up frame to the off-chip LIN bus interface module LINphy. The power management module PMU parses the wake-up frame and then turns on the power supply of the controlled ASIC_SLV DIE, then releases the iso signal of the isolation device ISO CELL, and finally releases the clock gating enable signal CG to turn on the clock of the controlled ASIC_SLV DIE, and the controlled ASIC_SLV DIE enters the normal working mode; When the controlled ASIC_SLV DIE is powered off and the controlled ASIC_MAIN DIE is in the normal working mode, the main control MCU DIE is also in the normal working mode; if the controlled ASIC_MAIN DIE does not need to work at this time, the main control MCU DIE sends a power-off request instruction to the communication module COMU, and the communication module COMU generates a power-off request pulse to the power management module PMU to turn off the power and clock of the digital core module DIG_core in the controlled ASIC_MAIN DIE and the main control MCU DIE, and the entire chip enters the deep sleep mode; if it is necessary to wake up from the deep sleep, the off-chip host uses the LIN bus to send a low-level wake-up frame to the off-chip LIN bus interface module LINphy, and the power management module PMU turns on the power and clock of the digital core module DIG_core, the controlled ASIC_SLV DIE, and the main control MCU DIE, and the entire chip returns to the normal working mode; When the digital core module DIG_core of the controlled ASIC_MAIN DIE is powered off and the controlled ASIC_SLV DIE is in the normal working mode, the main control MCU DIE is also in the normal working mode; if the controlled ASIC_SLV DIE does not need to work at this time, the main control MCU DIE sends a power-off request instruction to the communication module COMU, and the communication COMU generates a power-off request pulse to the power management module PMU to turn off the power and clock of the controlled ASIC_SLV DIE and the main control MCU DIE, and the entire chip enters the deep sleep mode; if it is necessary to wake up from the deep sleep, the off-chip host uses the LIN bus to send a low-level wake-up frame to the off-chip LIN bus interface module LINphy, and the power management module PMU turns on the power and clock of the digital core module DIG_core, the controlled ASIC_SLV DIE, and the main control MCU DIE, and the entire chip returns to the normal working mode.

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