Wiring method, apparatus, electronic device, and storage medium

Abstract

The application provides a wiring method, device, electronic equipment and storage medium, and belongs to the technical field of integrated circuits. In the wiring method, according to the pre-analysis result of each timing path, the logic stage number and / or logic resource of the timing path with tight timing is adjusted first, so as to reduce the congestion degree and logic stage number of the timing path, and then wiring is performed on the basis of the adjustment, so as to reduce the wiring failure probability. If there is a timing path with non-converged timing after wiring, and the re-adjustment condition is met, the step of analyzing the timing path is re-entered to perform a new round of wiring adjustment, until all timing paths achieve timing convergence, or the re-adjustment condition is not met. Therefore, the problems that the traditional FPGA wiring method cannot intervene in the timing pre-analysis result and cannot adjust the congestion degree are solved, the timing performance of the design is improved, the risk of wiring failure is reduced, and the design efficiency is improved, and the transformation of the design result is realized.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of integrated circuit technology, in particular to a wiring method and device, electronic equipment and storage medium. BACKGROUND

[0002] The development process of a Field Programmable Gate Array (FPGA) software tool mainly includes logic synthesis, layout, wiring, timing analysis and code stream generation. Among them, FPGA wiring is a process of selecting a suitable path from numerous wiring resources of an FPGA device for the connection between ports of each primitive (such as a lookup table, a register, etc.) in a user design netlist after layout.

[0003] In a traditional FPGA wiring method, after the layout of each primitive of an FPGA is completed, a path is found from an output port of each connection to an input port of the next primitive connected, starting from the output port of each connection, using available FPGA wiring resources, to meet the timing constraints as much as possible. This wiring method is extremely likely to make the wiring result unable to meet the timing convergence requirement, and even may have the risk of wiring failure. SUMMARY

[0004] Therefore, the purpose of the present application is to provide a wiring method, device, electronic equipment and storage medium to make the wiring result meet the timing convergence requirement and greatly reduce the risk of wiring failure.

[0005] To achieve the above purpose, the technical solutions adopted by the embodiments of the present application are as follows:

[0006] In a first aspect, the present application provides a wiring method, which comprises:

[0007] According to the layout result and the timing constraint information, pre-analyzing the timing paths of the design circuit to obtain the delay value and congestion degree of each timing path;

[0008] According to the delay value and the congestion degree, determining the timing stressed paths from each timing path and adjusting the logic stage number and / or logic resource of the timing stressed paths;

[0009] After all the adjustments are completed, wiring the design circuit;

[0010] After the wiring is completed, judging whether each timing path is timing convergent;

[0011] If not, it is determined whether a readjustment condition is met according to the timing path in which the timing does not converge.

[0012] If the readjustment condition is met, the step of pre-analyzing the timing paths of the design circuit according to the layout result and the timing constraint information to obtain the delay value and the congestion degree of each timing path is performed.

[0013] Optionally, the step of determining the timing critical path from each timing path according to the delay value and the congestion degree, and adjusting the logic stage number and / or the logic resource of the timing critical path comprises:

[0014] selecting, from each timing path, the timing path in which the delay value is greater than a first convergence threshold as the timing critical path;

[0015] for each timing critical path, reducing the logic stage number of the timing critical path;

[0016] taking the timing critical path in which the congestion degree is greater than a congestion threshold as a congestion path, and adjusting the logic resource of the congestion path.

[0017] Optionally, the step of reducing the logic stage number of the timing critical path comprises:

[0018] determining a connection coverage area of the timing critical path, and dividing the connection coverage area into a plurality of sub-areas;

[0019] calculating the congestion degree and the delay value of each sub-area;

[0020] taking the sub-area in which the delay value is not greater than a second convergence threshold as a convergence area;

[0021] taking the convergence area in which the congestion degree is the smallest as a target area, and inserting a level of virtual register into the target area.

[0022] Optionally, the step of adjusting the logic resource of the congestion path comprises:

[0023] selecting one primitive corresponding to each logic resource of the congestion path as a target object;

[0024] from each timing path of the design circuit, selecting a timing path in which the timing still converges after the target object is inserted and which is closest to the position of the target object as a hit path;

[0025] adjusting the position of the target object to the hit path.

[0026] Optionally, after the step of pre-analyzing the timing paths of the design circuit according to the layout result and the timing constraint information to obtain the delay value and the congestion degree of each timing path, and before the step of performing the wiring of the design circuit after all the adjustments are completed, the method further comprises:

[0027] For each of the timing paths, taking the priority corresponding to the delay value of the timing path as the connection priority of each primitive of the timing path;

[0028] The step of performing the wiring of the design circuit after all the adjustments are completed comprises:

[0029] After all the adjustments are completed, determining all the primitives of the design circuit;

[0030] According to the connection priority from high to low and a preset connection order, performing primitive connection by using wiring resources.

[0031] Optionally, the step of judging whether the re-adjustment condition is met according to the timing path that does not converge comprises:

[0032] From each of the timing paths that do not converge, selecting the timing path with the highest current delay value as a target path;

[0033] According to the primitives of the target path, judging whether the re-adjustment condition is met.

[0034] Optionally, the step of judging whether the re-adjustment condition is met according to the primitives of the target path comprises:

[0035] Obtaining the position and the number of each primitive of the target path, and the number of wiring nodes of the target path;

[0036] Taking the ratio of the position of the primitive to the preset timing constraint as a first factor, and taking the ratio of the number of the primitive to the number of the wiring nodes as a second factor;

[0037] Judging whether the first factor and the second factor are both greater than the respective adjustment threshold;

[0038] If yes, it is determined that the re-adjustment condition is not met;

[0039] If no, it is determined that the re-adjustment condition is met.

[0040] In a second aspect, the application provides a wiring device, comprising a pre-analysis module, an optimization adjustment module, a wiring module, a convergence judgment module and a polling module.

[0041] The pre-analysis module is configured to pre-analyze timing paths of the design circuit according to the layout result and the timing constraint information, and obtain a delay value and a congestion degree of each timing path.

[0042] The optimization adjustment module is configured to determine a timing critical path from each of the timing paths according to the delay value and the congestion degree, and adjust a logic stage number and / or a logic resource of the timing critical path.

[0043] The routing module is configured to perform routing of the design circuit after all the adjustments are completed.

[0044] The convergence judgment module is configured to judge whether each of the timing paths is timing convergent after the routing is completed.

[0045] The polling module is configured to judge whether a re-adjustment condition is met according to the timing path that is not timing convergent, if at least one of the timing paths is not timing convergent.

[0046] The polling module is further configured to control the pre-analysis module to return to performing the step of pre-analyzing the timing paths of the design circuit according to the layout result and the timing constraint information, and obtaining the delay value and the congestion degree of each timing path, if the re-adjustment condition is met.

[0047] In a third aspect, the present application provides an electronic device, which comprises a processor and a memory, the memory stores a computer program capable of being executed by the processor, and the processor can execute the computer program to implement the routing method according to the first aspect.

[0048] In a fourth aspect, the present application provides a storage medium, which stores a computer program, and the computer program is executed by a processor to implement the routing method according to the first aspect.

[0049] The routing method, device, electronic device and storage medium provided by the embodiments of the present application can pre-analyze timing paths of a design circuit to obtain a delay value and a congestion degree of each timing path, adjust a logic stage number and / or a logic resource of a timing critical path according to the delay value and the congestion degree, perform routing of the design circuit after all the adjustments are completed, and re-enter the step of analyzing the delay value and the congestion degree of the timing paths to perform a new round of routing adjustment, if it is determined that there is still a timing path that does not reach timing convergence after the routing is completed.

[0050] Thus, after the layout ends, according to the pre-analysis result, the logic stage number and / or logic resource of the timing path with tight timing are adjusted first to reduce the congestion degree of the timing path and make the timing path achieve timing convergence as much as possible, and then the layout is performed on the basis of the adjustment to reduce the probability of layout failure caused by congestion or timing divergence. In the case that the timing path still has timing divergence after the layout and meets the re-adjustment condition, the step of analyzing the timing path is re-entered to perform a new round of layout adjustment, that is, to perform disconnection and redistribution, until all timing paths achieve timing convergence, or when the re-adjustment condition is not met, the layout ends. Thus, the problem that the traditional FPGA layout method cannot intervene in the timing pre-analysis result and cannot adjust the congestion degree is solved, the timing performance of the design is improved, the risk of layout failure is greatly reduced, and thus the design efficiency is improved and the transformation of the design result is facilitated.

[0051] In order to make the above objectives, characteristics and advantages of the present application more apparent, the following will describe a preferred embodiment in detail with reference to the accompanying drawings. BRIEF DESCRIPTION OF DRAWINGS

[0052] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the following will briefly introduce the drawings needed to be used in the embodiments. It should be understood that the following drawings only show some of the embodiments of the present application, and therefore should not be considered as a limitation to the scope. For those skilled in the art, other related drawings can also be obtained without creative labor.

[0053] Figure 1 A block schematic diagram of a development design system provided by the embodiments of the present application is shown.

[0054] Figure 2 A block schematic diagram of an electronic device provided by the embodiments of the present application is shown.

[0055] Figure 3 A flowchart of one of the layout methods provided by the embodiments of the present application is shown.

[0056] Figure 4 A flowchart of the part of the sub-steps of step 13 in the method is shown. Figure 3

[0057] A flowchart of the part of the sub-steps of step 133 in the method is shown. Figure 5 Figure 4 A flowchart of the part of the sub-steps of step 135 in the method is shown.

[0058] Figure 6 Figure 4 A flowchart of the part of the sub-steps of step 135 in the method is shown.

[0059] Figure 7 ​​Fig. 2 shows a flowchart of a wiring method according to an embodiment of the present application.

[0060] Figure 8 Fig. 3 shows a flowchart of a part of the steps of the method of Fig. 2. Figure 7

[0061] Figure 9 Fig. 4 shows a flowchart of a part of the steps of the method of Fig. 2. Figure 3 Figure 7 Fig. 5 shows a flowchart of a part of the steps of the method of Fig. 2.

[0062] Figure 10 Fig. 6 shows a block diagram of a wiring device according to an embodiment of the present application.

[0063] Fig. 7 shows a block diagram of an electronic device according to an embodiment of the present application. DETAILED DESCRIPTION

[0064] The technical solutions in the embodiments of the present application will be clearly and completely described with reference to the accompanying drawings of the embodiments of the present application. Obviously, the described embodiments are only some of the embodiments of the present application, but not all of the embodiments of the present application. The components of the embodiments of the present application described and shown in the accompanying drawings can be arranged and designed in various different configurations.

[0065] Therefore, the detailed description of the embodiments of the present application provided in the accompanying drawings below is not intended to limit the scope of the claimed present application, but only represents selected embodiments of the present application. Based on the embodiments of the present application, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present application.

[0066] It should be noted that the relational terms such as first and second and the like are used only to distinguish one entity or operation from another, and do not necessarily require or imply that these entities or operations exist in any such actual relationship or order. Moreover, the terms "comprising", "including" or any other variant thereof are intended to cover non-exclusive inclusion, so that a process, method, article or apparatus that includes a list of elements not only includes those elements, but also includes other elements not expressly listed or inherent to such process, method, article or apparatus. Without more limitations, the element defined by the statement "comprising a" does not exclude the presence of additional identical elements in the process, method, article or apparatus that includes the element.​​

[0067] Firstly, several terms related to the embodiments of the application are introduced and explained.

[0068] Primitive: can be understood as an abstract representation of the logic resources of the FPGA, is the basic element of the logic block, including the logic resources such as LookUp Table (LUT), registor (reg), memory, etc. inside the FPGA chip.

[0069] Routing node: in the layout stage of the FPGA design process, the primitives are mapped to the specific physical location of the FPGA chip, which determines the distribution of the routing nodes. The routing node represents the connection point between each logic unit in the design.

[0070] Timing path: can be understood as the logic path passed through in the data signal propagation process in the design. Each timing path has a corresponding starting point and termination point, and is covered with multiple primitives.

[0071] The routing method provided by the embodiments of the application can be applied to Figure 1 As shown in the development design system 10, the development design system 10 includes an FPGA development board 110, a processing device 120 and an input device 130. The input device 130 can be connected with the processing device 120 through a network, WiFi, Bluetooth, wired connection, etc. The processing device 120 can be connected with the FPGA development board 110 through a downloader, etc. The FPGA development board 110 includes an FPGA chip.

[0072] The processing device 120 can be installed with development tools, such as routing and layout tools, synthesis tools, simulation tools and debugging verification tools, etc.

[0073] The input device 130 is used for inputting design requirements or design instructions, etc. to the processing device 120.

[0074] The processing device 120 is used for developing and designing the FPGA based on the development tools, combining the received design requirements or design instructions, and converting the design result into a bit stream file, and then downloading the bit stream file to the FPGA chip on the FPGA development board 110. Wherein, the development and design process of the FPGA includes: logic synthesis, layout, routing, timing analysis and bit stream generation.

[0075] The FPGA development board 110 is used for executing the bit stream file to perform hardware testing of the FPGA design.

[0076] Wherein, after the layout is completed, a layout result is obtained, which contains the number of primitives covered by each timing path of the designed circuit and the position of each primitive.

[0077] And after finishing the layout, the processing device 120 is configured to perform the steps of the routing method provided by the embodiments of the present application to route the FPGA.

[0078] The processing device 120 can be, but is not limited to, a personal computer, a notebook computer, a tablet computer, a server and a server cluster, etc., and the input device 130 can be, but is not limited to, a keyboard, a personal computer, a notebook computer, a tablet computer, a mobile phone, etc.

[0079] Please refer to Figure 2 , which is a block schematic diagram of an electronic device 20. The electronic device 20 can be, for example, the processing device 120 in the development and design system 10 shown in Figure 1 . The electronic device 20 includes a memory 210, a processor 220 and a communication module 230. The memory 210, the processor 220 and the communication module 230 are electrically connected with each other directly or indirectly to realize the transmission or interaction of data. For example, these elements can be electrically connected with each other through one or more communication buses or signal lines.

[0080] The memory 210 is configured to store programs or data. The memory 210 can be, but is not limited to, a random access memory, a read only memory, a programmable read only memory, an erasable programmable read only memory, an electrically erasable programmable read only memory, etc.

[0081] The processor 220 is configured to read / write the data or programs stored in the memory 210 and perform corresponding functions. For example, Figure 1 In the development and design system 10 shown in , the processor 220 of the processing device 120 executes the computer programs stored in the memory 210 to realize the routing method provided by the embodiments of the present application.

[0082] Figure 1 The communication module 230 is configured to establish a communication connection between the processing device 120 and other communication terminals and to receive and send data. For example, Figure 1 In the development and design system 10 shown in Figure 1 , the communication module 230 of the processing device 120 can receive and send data with the input device 130 through a network or with the FPGA development board 110.

[0083] It should be understood that, Figure 2 The structure shown in Figure 2 is only a schematic diagram of the structure of the electronic device 20. The electronic device 20 can include more or fewer components than those shown in Figure 2 or have a different configuration from Figure 2 . Figure 2 The components shown in may be realized by hardware, software or a combination thereof.

[0084] Figure 3The embodiment of the present application provides a wiring method, which comprises steps 11 to 19, and Figure 1 In the development design system 10 shown, the processing device 120 can Figure 2 In the structure shown, when the processor 220 executes the computer program stored in the memory 210, the steps 11 to 19 are implemented.

[0085] In step 11, according to the layout result and the timing constraint information, the timing paths of the design circuit are pre-analyzed to obtain the delay value and the congestion degree of each timing path.

[0086] In step 13, according to the delay value and the congestion degree, the timing critical paths are determined from the timing paths, and the logic stage number and / or the logic resource of the timing critical paths are adjusted.

[0087] In step 15, after all the adjustments are completed, the wiring of the design circuit is performed.

[0088] In step 17, after the wiring is completed, it is judged whether all the timing paths are timing convergent. If not, step 19 is executed, and if yes, the wiring is ended.

[0089] In step 19, according to the timing paths which are not timing convergent, it is judged whether the re-adjustment condition is met. If it is judged that the re-adjustment condition is met, step 11 is returned to perform the next round of wiring adjustment, and if it is judged that the re-adjustment condition is not met, the wiring is ended.

[0090] For example, in combination with Figure 1 In the development design system 10 shown, in the process of FPGA design, the designer or the user can input the project requirement to the processing device 120 through the input device 130. The designer manually analyzes the requirement, or the processing device 120 analyzes the requirement according to the input project requirement, formulates the target and requirement of the project, such as the performance index, the interface requirement, the power consumption limit, etc. Then, the designer or the processing device 120 designs the system architecture and the module division according to the requirement analysis result, and uses the hardware description language to write the code to describe the behavior, structure, etc. of the digital circuit (hereinafter referred to as the design circuit) to be designed. Further, the written code is reviewed or modified through manual review or automatic review of the processing device 120, etc. After the review of the code is completed, the processing device 120 uses the simulation tool to simulate the reviewed code to verify the correctness of the logic function. After the verification is passed, the processing device 120 uses the synthesis tool to convert the code into a gate-level netlist, and according to the synthesis result, performs design optimization to meet the timing requirement, the resource usage and the power consumption, etc.

[0091] After the design optimization of the synthesis result is completed, the processing device 120 maps the netlist to the physical resources of the FPGA chip in the FPGA development board 110 to perform placement. After the placement is completed, the processing device 120 performs pre-analysis on the timing paths of the design circuit according to the placement result and the timing constraint information to obtain the delay value and the congestion degree of each timing path. Then, the processing device 120 adjusts the logic stage number and / or the logic resource of the timing critical path according to the delay value and the congestion degree, and after all the adjustments are completed, performs routing of the design circuit. Thus, after the routing is completed, if the processing device 120 determines that there are still timing paths that do not reach timing convergence, the processing device 120 re-enters the step of analyzing the delay value and the congestion degree of the timing path under the condition of re-adjustment to perform a new round of routing adjustment. Until all the timing paths reach timing convergence or the re-adjustment condition is not met, the routing is completed. After the routing is completed, the processing device 120 can continue to perform timing analysis and bitstream generation and the like, which will not be described herein.

[0092] In the traditional FPGA routing method, after the placement of each primitive of the FPGA is completed, the routing resource available to each connection is routed from the output port of one primitive under the constraint of the timing requirement to find a path that meets the timing requirement as much as possible to the input port of another primitive connected thereto. This routing method has two defects: one is that when the positions of the input primitive and the output primitive connected thereto do not meet the timing requirement, there is no solution to the timing non-convergence caused thereby; and the other is that when the positions of the input primitive and the output primitive connected thereto are close to each other, but the layout primitives near the layout positions are congested, the congested primitives compete fiercely for the routing resource, and the traditional routing method cannot adjust the congested path, thereby causing timing non-convergence.

[0093] Compared with the traditional FPGA routing method, the routing method provided in the embodiment includes the steps 11 to 19, and after the placement is completed, the logic stage number and / or the logic resource of the timing critical path are adjusted according to the pre-analysis result to reduce the congestion degree of the timing path and make the timing path reach timing convergence as much as possible, and then the routing is performed on the basis of the adjustment to reduce the probability of routing failure caused by congestion or timing non-convergence.

[0094] In addition, in the case that the timing path still has a timing non-convergent after the routing and the re-adjustment condition is met, the step of analyzing the timing path is re-entered to perform a new round of routing adjustment, that is, to perform the disconnection and re-routing, until all timing paths reach the timing convergence or the re-adjustment condition is not met, and the routing is ended. Thus, the problem that the traditional FPGA routing method cannot intervene in the timing pre-analysis result and cannot adjust the congestion degree is solved, the timing performance of the design is improved, the risk of routing failure is greatly reduced, and thus the design efficiency is improved and the transformation of the design result is facilitated.

[0095] In the step 11, the delay value of each timing path can be obtained in a flexible manner. For example, for each timing path, the data arrival time, the clock arrival time, the data requirement time of the setup time, the data requirement time of the hold time, the timing margin and the clock uncertainty of the timing path can be calculated to obtain the delay value by addition or subtraction, or the delay value can be calculated according to a preset rule, and the implementation manner is not limited.

[0096] In order to more accurately estimate the delay value of the timing path, in the step 11, the starting primitive and the terminal primitive of the timing path are extracted from the layout result, and the relative distance between the starting primitive and the terminal primitive is obtained according to the position of the starting primitive and the position of the terminal primitive. Then, the delay value corresponding to the relative distance is calculated according to the unit delay value corresponding to the unit distance preset in the timing constraint information, so as to estimate the delay value of the timing path.

[0097] It should be noted that the unit delay value can be a value obtained by fitting the calibration experimental data, or a value set according to experience or historical data, and the obtaining manner is not limited herein.

[0098] In addition, for each timing path, the number of primitives and the number of routing nodes covered by the timing path can be queried from the layout result, and the ratio of the two is calculated to obtain the congestion degree of the timing path.

[0099] In the above manner, the delay value and the congestion degree of the timing path can be accurately estimated before the routing.

[0100] On the basis of the delay value and the congestion degree of each timing path, in the step 13, the timing path whose delay value or congestion degree does not meet the corresponding threshold can be regarded as the timing critical path, or the timing path whose delay value and congestion degree meet the preset relationship can be regarded as the timing critical path. The above manner is only an example, and the implementation manner is not limited.

[0101] In order to make the timing path reach timing convergence more quickly, the concept of reducing the number of logic stages of each timing critical path and adjusting the logic resources of the timing critical path with too high congestion is introduced in step 13. Referring to Figure 4 , step 13 can include steps 131 to 135.

[0102] Step 131, from each timing path, select the timing path with a delay value greater than the first convergence threshold as the timing critical path.

[0103] Wherein, the first convergence threshold of each timing path can be predefined in the timing constraint information, and the first convergence threshold of each timing path can be the same or different. In addition, the value of the first convergence threshold can be flexibly set, for example, it can be 3ns, or 5ns, which is different for different design projects (i.e. design circuit) and different functional requirements.

[0104] Step 133, for each timing critical path, reduce the number of logic stages of the timing critical path.

[0105] Step 135, adjust the logic resources of the timing critical path with congestion greater than the congestion threshold as the congestion path.

[0106] In step 133, the way to reduce the number of logic stages of the timing critical path can be flexibly selected, for example, the logic between two registers in the timing critical path can be evenly distributed, or the timing critical path can be logically flattened. And the above two ways are only examples, and the implementation way is not limited.

[0107] In order to avoid congestion in a certain area of the timing critical path during the process of reducing the number of logic stages, and to more reasonably reduce the number of logic stages of the timing critical path, the concept of inserting registers in the area with the lowest congestion after timing convergence is introduced in step 133. Referring to Figure 5 , the process of reducing the number of logic stages of the timing critical path in step 133 can include steps 1331 to 1337.

[0108] Step 1331, determine the connection coverage area of the timing critical path, and divide the connection coverage area into multiple sub-areas.

[0109] Wherein, the connection coverage area (i.e. BoundingBox) is the area where the primitives such as registers and lookup tables of the timing critical path are located, and the connection coverage area can be a regular geometric shape or an irregular shape. And the way to divide the connection coverage area can be flexibly selected, for example, it can be divided into equal-area rectangles, or it can be divided into equal-area irregular shapes, or it can be divided according to the number of primitives, and the division way is not limited.

[0110] Each sub-region obtained through the division has at least one primitive.

[0111] In step 1333, the congestion degree and the delay value of each sub-region are calculated.

[0112] Here, for each sub-region, the distribution information of the registers of the sub-region (which can be understood as the number, position, etc. of the registers) can be obtained, and according to the distribution information, the delay value and the congestion degree of the sub-region are calculated. The way of calculating the delay value and the congestion degree of the sub-region can be the same as the way of calculating the delay value and the congestion degree of the timing path in the foregoing. In addition, the number of registers can also be taken as the congestion degree of the sub-region, and the way of calculating the congestion degree in the present embodiment is not limited.

[0113] In step 1335, the sub-region whose delay value is not greater than the second convergence threshold is taken as a convergence region.

[0114] It should be understood that the second convergence threshold is a pre-set value, which can be a value specified in the timing constraint file. Different sub-regions can correspond to different second convergence thresholds, or can have the same second convergence threshold, and the present embodiment is not limited in this regard.

[0115] In step 1337, the convergence region with the minimum congestion degree is taken as a target region, and a first virtual register is inserted into the target region.

[0116] Here, the virtual register can be inserted before any register in the target region, or can be inserted at a fixed position (such as the input end or the output end of the target region), and the implementation manner is not limited.

[0117] Through the above steps 1331 to 1337, by analyzing the layout information of the registers of the timing critical path connected coverage region, the sub-region with the lowest congestion degree and the timing convergence is selected, and a first virtual register is inserted into the sub-region. The way of reducing the logic level of the timing critical path to reduce its delay value, and avoiding inserting a virtual register into a sub-region that does not converge or has a high congestion degree to cause the sub-region not to converge. In this way, the logic level of the timing critical path is more reasonably reduced, and the adjustment speed is improved, thereby helping to improve the wiring efficiency.

[0118] For the timing critical path (i.e. the timing path whose delay value is greater than the first convergence threshold), if its congestion degree is also greater than the pre-set congestion threshold (i.e. the timing critical path is a congestion path), the congestion degree is adjusted through step 135. In order to reduce the congestion degree of the congestion path and not affect the congestion degree and the delay value of other timing paths, the concept of adjusting the position of one primitive of the congestion path to the timing path that converges in timing is introduced in step 135. Referring to Figure 6 Step 135 can include steps 1351 to 1355.

[0119] Step 1351, selecting one primitive from the primitives corresponding to the logical resources of the congested path as a target object.

[0120] Step 1353, selecting a hit path from the timing paths of the designed circuit, which is still timing convergent after the insertion of the target object and is closest to the position of the target object.

[0121] Here, the timing convergent timing paths can be traversed in order from near to far according to the distance between the connection coverage of the congested path and the connection coverage of each timing convergent timing path. For each timing path traversed, the delay value after the insertion of a target object in the connection coverage area of the timing path is pre-calculated, and in the case where the delay value is not greater than the corresponding first convergence threshold, the timing path is selected as the hit path.

[0122] Wherein, when the constraint position of the target object is specified in the timing constraint file, the delay value of the timing path after the insertion of the target object is calculated by inserting the target object into the constraint position of the traversed timing path.

[0123] Step 1355, adjusting the position of the target object to the hit path.

[0124] Wherein, the target object can be moved to any position of the hit path, or it can be moved to a specified position of the hit path, and the selection of the moving position is not limited.

[0125] Through the above steps 1351 to 1355, one primitive of the congested path is inserted into a timing path which is timing convergent, still timing convergent after the insertion of the primitive and close to the congested path, so as to reduce the congestion of the congested path while avoiding affecting the timing convergence of the inserted timing path. Thus, it is helpful to quickly and efficiently route.

[0126] On the basis of the above, in order to improve the probability of reducing the delay value of the timing path, so as to make the timing path after routing have a lower delay value more quickly, the concept of primitive priority routing of the timing path with high congestion and not timing convergent is introduced in the routing process of step 15. Referring to Figure 7 After step 11 and before step 15, step 14 can also be included.

[0127] Step 14, for each timing path, the priority corresponding to the delay value of the timing path is taken as the connection priority of each primitive of the timing path.

[0128] On this basis, referring to Figure 8 In step 15, the process of routing can include the following steps 151 to 153.

[0129] Step 151, after all adjustments are completed, determine all primitives of the designed circuit.

[0130] Step 153, according to the connection priority from high to low and the preset connection order, use the routing resources to connect the primitives.

[0131] Here, the connection order of the primitives can be contained in the timing constraint file. Thus, the connection of the primitive with high priority has higher selection right of the routing node. From the start node of the primitive with the highest connection priority, the routing node that meets the timing constraint requirement is selected to connect the two primitives until the end node is connected.

[0132] For example, the primitive with the highest connection priority is selected from the unconnected primitives as the first primitive, and the primitive with the highest connection priority is selected from the remaining unconnected primitives as the second primitive. The output port of the first primitive is taken as the starting point, and the input port of the second primitive is taken as the end point. The routing node that meets the timing constraint requirement is selected to connect the two primitives. Then, the primitive with the highest connection priority is continuously selected from the remaining unconnected primitives as the third primitive, and the routing node is selected from the remaining routing nodes to connect the output port of the second primitive and the input port of the third primitive in the same principle as the connection of the first primitive and the second primitive. The cycle continues until the connection of all primitives is completed.

[0133] Through the above steps 151 to 153, the primitives of the timing path with high estimated delay value have the priority of routing, that is, more routing nodes can be selected for use. Thus, the timing path with high delay value is given priority to select the routing node that meets the timing constraint to complete the connection, thereby greatly reducing the delay value of the timing path to quickly and efficiently achieve timing convergence.

[0134] After the routing is completed through the above steps 151 to 153, if it is determined in step 17 that at least one timing path does not achieve timing convergence, step 19 is performed.

[0135] In step 19, the way to determine whether the re-adjustment condition is met can be flexibly set. For example, the adjustment factors of the timing paths that do not converge can be calculated, the adjustment factors are weighted and summed to obtain a comprehensive factor, and whether the re-adjustment condition is met is determined according to the comparison relationship between the comprehensive factor and the adjustment threshold. It can also be that any adjustment factor is selected to determine whether the re-adjustment condition is met according to the comparison relationship between the adjustment factor and the adjustment threshold. It can also be that the primitives of the timing paths that do not converge are input into a pre-trained neural network model, and whether the re-adjustment condition is met is determined by the neural network model. The above methods are examples, and the implementation manner is not limited.

[0136] In order to more accurately and quickly analyze and determine whether the re-adjustment condition is met, in step 19, the idea of judging whether the re-adjustment condition is met by the primitive of the timing path with the highest delay value in the timing path that does not reach timing convergence is introduced.

[0137] For example, in step 19, the timing path with the highest current delay value is selected as the target path from the timing paths that do not reach timing convergence, and whether the re-adjustment condition is met is determined according to the primitive of the target path.

[0138] In which, whether the re-adjustment condition is met can be determined according to whether the number or position of the primitive of the target path is greater than the corresponding threshold, or whether the re-adjustment condition is met can be determined according to the preset rule. The above-mentioned manner is only an example, and the setting of the re-adjustment condition is not limited.

[0139] In order to more comprehensively determine the re-adjustability, the idea of calculating the adjustment factor from the position of the primitive and the number of the primitive respectively, and comparing with the corresponding threshold to determine is introduced. Referring to Figure 9 , the implementation process of step 19 can include steps 191 to 196.

[0140] In step 191, the timing path with the highest current delay value is selected as the target path from the timing paths that do not reach timing convergence.

[0141] In step 192, the position and number of each primitive of the target path, and the number of the routing node of the target path are obtained.

[0142] In step 193, the ratio of the position of the primitive to the preset timing constraint is taken as the first factor, and the ratio of the number of the primitive to the number of the routing node is taken as the second factor.

[0143] In step 194, it is determined whether the first factor and the second factor are greater than the respective corresponding adjustment threshold. If yes, step 195 is executed, and if no, step 196 is executed.

[0144] In step 195, it is determined that the re-adjustment condition is not met.

[0145] In step 196, it is determined that the re-adjustment condition is met.

[0146] Through the above steps 191 to 196, whether the re-adjustment condition is met is judged by the primitive of the timing path with the highest delay value in the timing path that does not reach timing convergence, so that the calculation amount can be reduced, the judgment speed can be improved, and the representative and accurate result can be determined. And through steps 192 to 196, the position of the primitive and the number of the primitive are considered from two angles, so that the determination result is more comprehensive, and the discrimination accuracy is further improved.

[0147] Based on the same inventive concept as the above wiring method, referring to Figure 10 The embodiment of the present application also provides a wiring device 30 which can be applied to Figure 1 As shown in the processing device 120 of the development design system 10, the wiring device 30 comprises a pre-analysis module 310, an optimization adjustment module 320, a wiring module 330, a convergence judgment module 340 and a polling module 350.

[0148] The pre-analysis module 310 is used for pre-analyzing the timing paths of the design circuit according to the layout result and the timing constraint information, so as to obtain the delay value and the congestion degree of each timing path.

[0149] The optimization adjustment module 320 is used for determining the timing stressed paths from the timing paths according to the delay value and the congestion degree, and adjusting the logic stage number and / or the logic resource of the timing stressed paths.

[0150] The wiring module 330 is used for wiring the design circuit after all the adjustments are completed.

[0151] The convergence judgment module 340 is used for judging whether all the timing paths are timing convergent after the wiring is completed.

[0152] The polling module 350 is used for judging whether the re-adjustment condition is met according to the timing path which is not timing convergent, if at least one timing path is not timing convergent.

[0153] The polling module 350 is also used for controlling the pre-analysis module 310 to return to the step of pre-analyzing the timing paths of the design circuit according to the layout result and the timing constraint information, so as to obtain the delay value and the congestion degree of each timing path, if the re-adjustment condition is met.

[0154] The wiring device 30 described above can, through the cooperative action of the pre-analysis module 310, the optimization adjustment module 320, the wiring module 330, the convergence judgment module 340 and the polling module 350, after the layout is completed, adjust the logic stage number and / or the logic resource of the timing stressed timing paths according to the pre-analysis result, so as to reduce the congestion degree of the timing paths and make the timing paths reach the timing convergence as much as possible, and then perform the wiring on the basis of the adjustment, so as to reduce the wiring failure caused by the congestion or the timing non-convergence.

[0155] In addition, in the case that the timing path still does not converge after the wiring and the re-adjustment condition is met, the step of re-entering the analysis of the timing path is performed to perform a new round of wiring adjustment, that is, to perform the disconnection and re-wiring, until all timing paths reach the timing convergence or the re-adjustment condition is not met, and the wiring is ended. Thus, the problem that the traditional FPGA wiring method cannot intervene in the timing pre-analysis result and cannot adjust the congestion degree is solved, the timing performance of the design is improved, the risk of wiring failure is greatly reduced, and the design efficiency is improved and the transformation of the design result is facilitated.

[0156] The specific implementation and effects of the wiring device 30 can be referred to the description of the implementation of the wiring method, for example, the specific implementation and effects of the pre-analysis module 310 can be referred to the description of the step 11, the specific implementation and effects of the optimization adjustment module 320 can be referred to the description of the step 13, the specific implementation and effects of the wiring module 330 can be referred to the description of the step 15, the specific implementation and effects of the convergence judgment module 340 can be referred to the description of the step 17, and the specific implementation and effects of the polling module 350 can be referred to the description of the step 19, which will not be repeated here.

[0157] In addition, the modules of the wiring device 30 can be implemented by software, hardware, or a combination thereof. The modules can be embedded in or independent of the processor 220 in the electronic device 20 in hardware form, or stored in the memory 210 of the electronic device 20 in software form, so that the processor 220 can call and execute the operations corresponding to the modules to implement the wiring method as described above.

[0158] Based on the same inventive concept as the above wiring method, the embodiment of the present application also provides an electronic device 20, which includes a processor 220 and a memory 210. The memory 210 stores a computer program that can be executed by the processor 220. The processor 220 can execute the computer program to implement the wiring method as described in the embodiment of the present application.

[0159] The embodiment of the present application also provides a storage medium having a computer program stored thereon. The computer program is executed by the processor 220 to implement the wiring method as described in the embodiment of the present application.

[0160] In summary, the wiring method, device, electronic device, and storage medium provided by the embodiment of the present application perform pre-analysis on the layout result of the timing path, obtain the timing path that does not converge and the congestion path that does not converge and has high congestion degree, and adjust the logic level and primitive position of the related timing path to reduce the congestion degree of the timing path and achieve the timing convergence. The wiring method, device, electronic device, and storage medium at least have the following beneficial effects:

[0161] (1) solves the problem that the traditional FPGA wiring method cannot intervene in timing pre-analysis results and cannot adjust congestion;

[0162] (2) reduces the risk of wiring failure and effectively improves the wiring effect.

[0163] In several embodiments provided by the present application, it should be understood that the disclosed devices and methods can also be implemented in other ways. The device embodiments described above are only illustrative, for example, the flowcharts and block diagrams in the drawings show the possible implementation architecture, function and operation of the devices, methods and computer program products according to the embodiments of the present application. In this regard, each block in the flowchart or block diagram can represent a module, a program segment or a part of code, which includes one or more executable instructions for implementing the specified logic function. It should also be noted that in some alternative implementations, the functions noted in the blocks can occur in different order from that noted in the drawings. For example, two consecutive blocks can actually be executed substantially in parallel, and sometimes they can be executed in reverse order, depending on the functions involved. It should also be noted that each block in the block diagram and / or flowchart, and the combination of blocks in the block diagram and / or flowchart, can be implemented by a dedicated hardware-based system that performs the specified function or action, or can be implemented by a combination of dedicated hardware and computer instructions.

[0164] In addition, the functional modules in the various embodiments of the present application can be integrated together to form an independent part, or each module can exist independently, or two or more modules can be integrated to form an independent part.

[0165] If the functions are implemented in the form of software function modules and sold or used as independent products, they can be stored in a computer readable storage medium. Based on this understanding, the technical solutions of the present application can be embodied in the form of software products, which are stored in a storage medium and include a number of instructions for causing a computer device (which can be a personal computer, a server, or a network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of the present application. The aforementioned storage medium includes various media that can store program codes, such as U disk, mobile hard disk, read-only memory, random access memory, magnetic disk or optical disk, etc.

[0166] The above only describes the preferred embodiments of the present application and is not intended to limit the present application. For those skilled in the art, the present application can have various modifications and changes. Any modification, equivalent replacement, improvement, etc. made within the spirit and principles of the present application shall be included in the protection scope of the present application.

Claims

1. A wiring method characterized by comprising: The method comprises: pre-analyzing timing paths of a design circuit according to layout results and timing constraint information to obtain a delay value and a congestion degree of each timing path; determining timing critical paths from the timing paths according to the delay value and the congestion degree, and adjusting a logic stage number and / or a logic resource of the timing critical paths; performing wiring of the design circuit after completing all adjustments; judging whether all the timing paths are timing convergent after the wiring is completed; if not, judging whether a re-adjustment condition is met according to the timing paths that are not timing convergent; if the re-adjustment condition is met, returning to perform the step of pre-analyzing timing paths of a design circuit according to layout results and timing constraint information to obtain a delay value and a congestion degree of each timing path; the step of determining timing critical paths from the timing paths according to the delay value and the congestion degree, and adjusting a logic stage number and / or a logic resource of the timing critical paths comprises: selecting, from the timing paths, a timing path with a delay value greater than a first convergence threshold as a timing critical path; for each timing critical path, adjusting a logic stage number of the timing critical path; selecting, as a congestion path, a timing critical path with a congestion degree greater than a congestion threshold, and adjusting a logic resource of the congestion path; the step of adjusting the logic resource of the congestion path comprises: selecting one of primitives corresponding to each logic resource of the congestion path as a target object; selecting, from the timing paths of the design circuit, a timing path with a timing still convergent after the target object is inserted and closest to a position of the target object as a hit path; adjusting the position of the target object to the hit path.

2. The wiring method according to claim 1, wherein the step of adjusting the logic stage number of the timing critical path comprises: determining a connection coverage of the timing critical path, dividing the connection coverage into a plurality of sub-areas; calculating a congestion degree and a delay value of each sub-area; selecting, as a convergent area, a sub-area with a delay value not greater than a second convergence threshold; selecting, as a target area, a convergent area with a minimum congestion degree, and inserting a virtual register of one level into the target area.

3. The wiring method according to any one of claims 1 to 2, wherein, after the step of pre-analyzing timing paths of a design circuit according to layout results and timing constraint information to obtain a delay value and a congestion degree of each timing path, and before the step of performing wiring of the design circuit after completing all adjustments, the method further comprises: for each timing path, using a priority corresponding to the delay value of the timing path as a connection priority of each primitive of the timing path; the step of performing wiring of the design circuit after completing all adjustments comprises: after completing all adjustments, determining all primitives of the design circuit; performing primitive connection by using wiring resources in a descending order of the connection priority and a preset connection order.

4. The wiring method according to any one of claims 1 to 2, wherein the step of judging whether a re-adjustment condition is met according to the timing paths that are not timing convergent comprises: From the timing paths that do not converge, a timing path with a current highest delay value is selected as a target path; It is judged whether a re-adjustment condition is met according to a primitive of the target path.

5. The wiring method according to claim 4, wherein, The step of judging whether the re-adjustment condition is met according to the primitive of the target path comprises: acquiring a position and a number of primitives of the target path, and a number of wiring nodes of the target path; taking a ratio of the position of the primitive to a preset timing constraint as a first factor, and taking a ratio of the number of the primitive to the number of the wiring nodes as a second factor; judging whether the first factor and the second factor are both greater than respective adjustment thresholds; if yes, it is determined that the re-adjustment condition is not met; if no, it is determined that the re-adjustment condition is met.

6. A wiring device, characterized by The pre-analysis module, the optimization adjustment module, the wiring module, the convergence judgment module and the polling module are included. The pre-analysis module is configured to perform pre-analysis on timing paths of a design circuit according to layout results and timing constraint information, to obtain a delay value and a congestion degree of each timing path. The optimization adjustment module is configured to determine timing stressed paths from the timing paths according to the delay value and the congestion degree, and to adjust a logic stage number and / or a logic resource of the timing stressed paths. The wiring module is configured to perform wiring of the design circuit after all adjustments are completed. The convergence judgment module is configured to judge whether all the timing paths are timing convergent after the wiring is completed. The polling module is configured to judge whether a re-adjustment condition is met according to the timing paths that do not converge if at least one of the timing paths does not converge. The polling module is further configured to control the pre-analysis module to return to perform the pre-analysis on the timing paths of the design circuit according to the layout results and the timing constraint information to obtain the delay value and the congestion degree of each timing path if the re-adjustment condition is met. The optimization adjustment module is specifically configured to: select, from the timing paths, a timing path with a delay value greater than a first convergence threshold as a timing stressed path; lower, for each timing stressed path, a logic stage number of the timing stressed path; select, as a congestion path, a timing stressed path with a congestion degree greater than a congestion threshold, and adjust a logic resource of the congestion path; select, from primitives corresponding to each logic resource of the congestion path, a primitive as a target object; select, from the timing paths of the design circuit, a timing path that is still timing convergent after the target object is inserted and is closest to a position of the target object as a hit path; and adjust the position of the target object to the hit path.

7. An electronic device, comprising: The computer program is executed by the processor to implement the wiring method according to any one of claims 1 to 5.

8. A storage medium having stored thereon a computer program, characterized in that The computer program is executed by the processor to implement the wiring method according to any one of claims 1 to 5.

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