Method for introducing effective clock skew in chip layout stage

Abstract

The invention discloses a method for introducing effective clock skew in a chip layout stage, which comprises the following steps of: utilizing an optimized time sequence of the effective clock skew to enable clock signals to arrive at a time sequence unit in a staggered manner, and offering surplus time sequence resources on a non-critical path to an adjacent critical path. According to the method, the effective clock skew is improved into an active optimization strategy in the early stage, and the degree of freedom and effectiveness of optimization are improved; a clear and quantitative optimization target is provided for the clock tree synthesis tool, so that the balance operation has clear time sequence guidance quality, and resource waste on a non-critical path is avoided; the problem of time sequence violation is solved by utilizing time sequence information earlier and more effectively, and higher working frequency is achieved; or the time sequence convergence is realized with lower power consumption, and the chip performance is improved; through effective clock skew, effective linkage of a layout wiring stage, a clock tree synthesis stage, a clock path and a data path is realized, a new normal form of a physical design stage is formed, and seamless connection of different design stages is realized.

Description

Technical Field

[0001] This invention relates to the field of very large-scale integrated circuit design technology, and in particular to a method for introducing effective clock skew during the chip layout stage. Background Technology

[0002] As semiconductor processes advance to the deep submicron and even nanometer scale, the size and complexity of integrated circuits are growing exponentially, and timing convergence has become one of the most severe challenges in chip design. Clock Tree Synthesis (CTS) is a key step in the physical design flow, and its goal is to build a low-bias, low-latency global clock distribution network inside the chip to ensure that clock signals can reach all timing units as synchronously as possible.

[0003] Traditional clock tree synthesis processes typically occur between placement and routing, aiming to build a clock network with zero or minimal skew. Skew here refers to the earliest and latest time difference between the arrival of a clock signal at a timing cell. After placement, clock tree synthesis tools balance the delays from the clock source to all clock endpoints (i.e., the clock pins of all timing cells), ensuring clock signals arrive as simultaneously as possible. However, this strategy has inherent limitations: 1. Lack of forward-looking planning. In the early stages of clock tree synthesis, tools typically determine the basic topology of the clock tree only through the location distribution of timing cells. Without considering the estimation of timing slack for different paths, it may be impossible to determine the optimal clock tree topology for the current design. Blindly performing balancing operations on this basis often leads to missing the best timing optimization opportunities.

[0004] 2. Uneven timing path utilization. In a design, the timing requirements of different paths vary. Some critical paths have negative or near-zero timing margins, while other non-critical paths have ample timing margins. Forcing a uniform timing balance across all paths can waste valuable timing resources on non-critical paths, failing to improve the timing of critical paths and ultimately increasing overall latency and reducing chip efficiency.

[0005] 3. Limited optimization space. Once the clock tree synthesis is complete, the clock tree structure is basically determined. Backend tools mainly fix timing violations by adjusting cell size, changing threshold voltage, or performing local departmental optimizations. These methods often come at the cost of area and power consumption, and their optimization effect and flexibility are very limited. They may even introduce new timing violations, leading to an increase in iteration cycle and difficulty in convergence. Summary of the Invention

[0006] The purpose of this invention is to provide a method for introducing effective clock skew during the chip layout stage to solve the problems in the background art.

[0007] To address the aforementioned technical problems, this invention provides a method for introducing an effective clock skew during the chip layout stage, comprising: By optimizing timing with effective clock skew, clock signals arrive at timing units at different times, freeing up excess timing resources on non-critical paths for adjacent critical paths. The effective clock offset has two setting schemes: normal mode and extreme mode; In normal mode, all violation paths are traversed. At the starting pin of the path, it is checked whether there is a positive timing margin in the adjacent path. If there is, the corresponding effective clock offset is set on the clock pin corresponding to that pin. Timing is borrowed from the previous path, and the current offset is saved based on whether the timing result is improved. At the end pin of the path, check if there is a positive timing margin in the adjacent path. If there is, set the opposite effective clock offset on the clock pin corresponding to that pin, borrow timing from the subsequent path, and decide whether to save the current offset based on whether the timing result is improved. In extreme mode, find the path with the worst current timing margin and continuously find adjacent paths to form a path chain; On the path chain, the clock pins at the beginning and end of each path are traversed from far to near, attempting to borrow from each level to improve the timing of the worst path found earlier. On each level of the path, the clock deviation that borrows the current timing margin to zero is used as the initial deviation value. If the timing is improved, the value is saved. If there is no improvement, the deviation value is reduced and recalculated until the maximum deviation value that improves the timing is found, or until the deviation value is reduced to zero but there is still no improvement.

[0008] In one implementation, the specific deviation value calculation in the normal mode requires restoring the timing margin of the current path to zero, while ensuring that the timing margins of adjacent paths do not become negative.

[0009] In one implementation, in the extreme mode, the timing margin of a path that was originally non-negative becomes non-negative or positive after the timing margin is borrowed, thus realizing timing borrowing between multi-level paths on the entire path chain; this process is repeated several times on the path chain until the timing of the entire path chain is no longer improved.

[0010] In one implementation, the process of setting an effective clock skew in the extreme mode is combined with conventional timing improvement from the perspective of combinational logic in the data path, including: In each iteration, the timing optimization of the data path is performed first, and then the worst path and path chain are found to set an effective clock skew. At this point, a new optimizable path is exposed, and the data path is optimized again, setting an effective clock skew, until there is no optimization in this loop.

[0011] The present invention provides a method for introducing effective clock skew during the chip layout stage, which has the following beneficial effects: (1) The effective clock deviation is transformed from a passive repair method in the later stage to an active optimization strategy in the early stage, which greatly improves the freedom and effectiveness of optimization; (2) It provides clear and quantifiable optimization objectives for clock tree synthesis tools, making its balancing operation have clear timing orientation and avoiding wasting resources on non-critical paths; (3) By utilizing timing information earlier and more effectively, timing violations can be solved more cleverly, resulting in higher operating frequencies; or timing convergence can be achieved with lower power consumption, thereby improving chip performance. (4) By effectively controlling the clock offset, the clock path and data path are effectively linked in the layout and routing stage and the clock tree synthesis stage, forming a new paradigm in the physical design stage and achieving seamless connection between different design stages. Attached Figure Description

[0012] Figure 1 This is a schematic diagram illustrating timing borrowing.

[0013] Figure 2 This is a schematic diagram of the process for setting an effective clock offset in the normal mode provided by the present invention.

[0014] Figure 3 This is a schematic diagram of the process for setting an effective clock offset in extreme modes provided by the present invention.

[0015] Figure 4 This is a schematic diagram of the new layout and clock tree integration process. Detailed Implementation

[0016] The following detailed description, in conjunction with the accompanying drawings and specific embodiments, provides a method for introducing effective clock skew during the chip layout stage according to the present invention. The advantages and features of the present invention will become clearer from the following description. It should be noted that the drawings are all in a very simplified form and use non-precise proportions, and are only used to facilitate and clarify the illustration of the embodiments of the present invention.

[0017] This invention provides a method for introducing effective clock skew during the chip layout stage. The core idea is to proactively utilize clock skew to optimize timing, rather than blindly pursuing zero skew. Specifically, it intentionally allows the clock signal to arrive at some timing units earlier and others later, thereby "borrowing" surplus timing resources on some non-critical paths to adjacent critical paths, thus improving overall timing.

[0018] like Figure 1 As shown, assuming clock signals arrive at pins A, B, and C simultaneously, path AB has a timing margin of 0.5ps, meaning the data signal on AB arrives at B 0.5ps earlier than the clock signal on B; path BC has a timing margin of -0.3ps, meaning the data signal on BC arrives at C 0.3ps later than the clock signal on C. If the clock signal on pin B is artificially made to arrive 0.3ps earlier, the timing margin for path AB becomes 0.2ps, and the timing margin for path BC becomes 0ps. This is equivalent to borrowing 0.3ps of timing margin from path AB to correct the timing violation in path BC. This 0.3ps difference between clock pin B and clock pins A and C is the effective clock skew. Conversely, if path AB has a negative timing margin and path BC has a positive timing margin, the clock signal on pin B can be artificially made to arrive later, achieving the purpose of borrowing timing margin from path AB through path BC.

[0019] During the layout phase, this invention provides two schemes for setting an effective clock offset: normal mode and extreme mode.

[0020] like Figure 2 As shown, in normal mode, all violation paths are traversed. At the start pin of a path, it checks if the preceding adjacent path has a positive timing margin. If so, a corresponding effective clock offset is set on the clock pin corresponding to that pin, borrowing timing from the preceding path. Whether to save the current offset is determined based on whether the timing has improved. At the end pin of a path, it checks if the following adjacent path has a positive timing margin. If so, a negative effective clock offset is set on the clock pin corresponding to that pin, borrowing timing from the following path. Whether to save the current offset is determined based on whether the timing has improved. The specific offset calculation aims to restore the timing margin of the current path to zero as much as possible, while ensuring that the timing margins of the preceding and following adjacent paths do not become negative.

[0021] like Figure 3As shown, in extreme mode, the path with the worst current timing margin is found, and adjacent paths are continuously sought as much as possible to form a path chain. On the path chain, the starting and ending clock pins of each path are traversed from far to near, attempting to borrow timing margins level by level, ultimately improving the timing of the previously found worst path. On each level of the path, the clock offset that borrows the current timing margin to zero is used as the initial offset value. If the timing improves, this value is saved; otherwise, the offset value is reduced and recalculated until the maximum offset value that improves the timing is found, or until zero offset value is reached without improvement. In extreme mode, it is not required that the timing margin of a path that was originally non-negative remain non-negative after borrowing; therefore, timing borrowing between multiple levels of paths can be implemented throughout the entire path chain. This process is repeated several times on the path chain until the timing of the entire path chain shows no improvement.

[0022] Meanwhile, the layout phase typically employs conventional measures to improve timing from the perspective of combinatorial logic of data paths. The process of setting effective clock skew in extreme modes can be combined with these measures. In each loop, conventional data path timing optimization is performed first, then the worst-case path and path chain are identified, and effective clock skew is set. This may reveal new optimizable paths, leading to further data path optimization, setting effective clock skew, and so on, until no further optimization is achieved in the current loop. This forms a new approach to clock-concurrent optimization (CCO).

[0023] During the clock tree synthesis phase, the useful skew on the clock pin is directly converted into the latency offset of the current pin. The clock tree is then balanced while taking these latency offsets into account, resulting in a clock tree with the useful skew added.

[0024] Ultimately, the new layout and clock tree process is as follows: Figure 4 As shown, a connection process centered on effective clock skew has been added to the placement phase, resulting in deeper coupling between the placement and clock tree synthesis phases. The tool can obtain clearly quantified delay skew early in the clock tree synthesis process, making balancing operations more purposeful and targeted. Timing optimization based on data paths and timing optimization based on clock paths can be performed simultaneously, providing greater operational flexibility for fixing timing violations.

[0025] This invention employs simulations of different process technologies to test the effectiveness of the new process. The main metrics of interest are: Worst Negative Slack (WNS), Total Negative Slack (TNS), and Number of Violating Paths (NVP). These metrics indicate the current timing violation situation in the design. Worst Negative Slack and Total Negative Slack are negative values; the larger their absolute values, the more severe the timing violations. A higher number of violating paths indicates a greater number of timing violation paths.

[0026] Table 1 compares the quality of layout results with normal and extreme modes enabled but without enabling effective clock skew. The results in Table 1 show that enabling effective clock skew significantly improves timing performance during the placement phase, with a marked reduction in both the severity and number of timing violations. Enabling the normal mode outperforms the mode without effective clock skew, while enabling the extreme mode outperforms the normal mode. It's important to note that the clock skew value at this stage is merely a calibration value; the specific implementation of these skews through clock tree adjustments will be determined in the subsequent clock tree synthesis phase.

[0027] Table 2 Comparison of result quality after layout, clock tree synthesis, and routing with and without enabling effective clock skew. The results in Table 2 show that although the effective clock skew at the end of the layout is only a calibration value, the effective clock skew set according to the method of this invention does not present a significant bottleneck in the conversion from the calibration value to the actual clock delay during the clock tree synthesis stage. Throughout the entire physical design process, enabling the effective clock skew provides a clear advantage in timing results.

[0028] The above description is merely a description of preferred embodiments of the present invention and is not intended to limit the scope of the present invention in any way. Any changes or modifications made by those skilled in the art based on the above disclosure shall fall within the protection scope of the claims.

Claims

1. A method for introducing effective clock skew during the chip layout stage, characterized in that, By optimizing timing with effective clock skew, clock signals arrive at timing units at different times, freeing up excess timing resources on non-critical paths for adjacent critical paths. The effective clock offset has two setting schemes: normal mode and extreme mode; In normal mode, all violation paths are traversed. At the starting pin of the path, it is checked whether there is a positive timing margin in the adjacent path. If there is, the corresponding effective clock offset is set on the clock pin corresponding to that pin. Timing is borrowed from the previous path, and the current offset is saved based on whether the timing result is improved. At the end pin of the path, check if there is a positive timing margin in the adjacent path. If there is, set the opposite effective clock offset on the clock pin corresponding to that pin, borrow timing from the subsequent path, and decide whether to save the current offset based on whether the timing result is improved. In extreme mode, find the path with the worst current timing margin and continuously find adjacent paths to form a path chain; On the path chain, the clock pins at the beginning and end of each path are traversed from far to near, attempting to borrow from each level to improve the timing of the worst path found earlier. On each level of the path, the clock deviation that borrows the current timing margin to zero is used as the initial deviation value. If the timing is improved, the value is saved. If there is no improvement, the deviation value is reduced and recalculated until the maximum deviation value that improves the timing is found, or until the deviation value is reduced to zero but there is still no improvement.

2. The method for introducing an effective clock skew during the chip layout stage as described in claim 1, characterized in that, The specific deviation value calculation requirement in the normal mode is to restore the timing margin of the current path to zero, while ensuring that the timing margin of the adjacent paths before and after does not become negative.

3. The method for introducing an effective clock skew during the chip layout stage as described in claim 1, characterized in that, In the extreme mode, the timing margin of a path that was originally non-negative becomes non-negative or positive after the timing margin is borrowed. Therefore, timing borrowing between multi-level paths is realized on the entire path chain. This process is repeated several times on the path chain until the timing of the entire path chain is no longer improved.

4. The method for introducing an effective clock skew during the chip layout stage as described in claim 1, characterized in that, The process of setting an effective clock skew in the extreme mode is combined with conventional timing improvement from the perspective of combinational logic of the data path, including: In each iteration, the timing optimization of the data path is performed first, and then the worst path and path chain are found to set an effective clock skew. At this point, a new optimizable path is exposed, and the data path is optimized again, setting an effective clock skew, until there is no optimization in this loop.

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