Shift register circuit, display panel and display device

Abstract

The invention discloses a shift register circuit, a display panel and a display device, and relates to the technical field of display, and the shift register circuit uses a first node control module to control the potential of a first node, uses a second node control module to control the potential of a second node, and uses a third node control module to control the potential of a third node. The output module controls the output path of the first level signal according to the potential of the second node and controls the output path of the second level signal according to the potential of the third node; in the power-on stage of the display panel, the power of the second node is located at the second level signal through the reset module, and then the output module does not output the first level signal according to the potential of the second node, namely, does not output the enable level of the corresponding thin film transistor in the pixel circuit. The problems of splash screen or large-current burn and the like caused by abnormal opening of the thin film transistor in the pixel circuit are avoided, wires do not need to be independently arranged to control the reset module, the wires can be reduced, and the frame of the display panel is reduced.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to a shift register circuit, a display panel and a display device. Background Art

[0002] Display panels are widely used in electronic devices such as smartphones, tablet computers, and car navigation systems, becoming an indispensable device in people's lives and work.

[0003] In the display panel, the driver integrated circuit provides a drive control signal to the shift register circuit, and the shift register circuit provides a scan signal to each row of pixel circuits in the display area based on the drive control signal to control the working state of each row of pixel circuits so that the pixel circuit drives the light-emitting element for display.

[0004] The scanning signal provided by the shift register circuit to the pixel circuit includes an enable level and a non-enable level. During the power-on stage of the display panel, that is, the stage when the display panel transitions from a completely power-off state to a normal working state, the shift register circuit is required to provide a non-enable level to the pixel circuit to avoid abnormal opening of the thin film transistor in the pixel circuit of the display area, resulting in screen flickering or high current burns. Summary of the invention

[0005] In order to solve the above technical problems, the embodiments of the present application provide a shift register circuit, a display panel and a display device to ensure that the shift register circuit provides a non-enable level to the pixel circuit during the power-on stage of the display panel, thereby avoiding abnormal opening of the thin film transistor in the pixel circuit of the display area, resulting in screen flickering or high current burns.

[0006] To achieve the above objectives, the present application provides the following technical solutions:

[0007] A shift register circuit, comprising:

[0008] A first node control module is electrically connected to the first clock terminal, the first level terminal, the first node and the second node respectively, and is used to control the potential of the first node according to the first clock signal of the first clock terminal, the first level signal of the first level terminal and the potential of the second node;

[0009] A second node control module is electrically connected to the signal input terminal, the first clock terminal, the second clock terminal, the second level terminal, the first node, and the second node, respectively, and is used to control the potential of the second node according to the input signal of the signal input terminal, the first clock signal of the first clock terminal, the second clock signal of the second clock terminal, the second level signal of the second level terminal, and the potential of the first node;

[0010] a third node control module, electrically connected to the second clock end, the second level end, the first node, the second node and the third node, respectively, and configured to control the potential of the third node according to the second clock signal of the second clock end, the second level signal of the second level end, the potential of the first node and the potential of the second node;

[0011] A reset module, electrically connected to the second clock end, the second level end, the first node and the second node respectively, and used to control a transmission path of the second level signal of the second level end to the second node according to the second clock signal of the second clock end and the potential of the first node;

[0012] an output module, electrically connected to the first level end, the second level end, the second node, the third node and the signal output end, respectively, and used to control a transmission path of the first level signal of the first level end to the signal output end according to the potential of the second node, and to control a transmission path of the second level signal of the second level end to the signal output end according to the potential of the third node;

[0013] In the first mode, the first clock signal and the second clock signal are both at enable levels; in the second mode, the first clock signal and the second clock signal are pulse signals whose enable levels do not overlap with each other.

[0014] A display panel, comprising a plurality of pixel circuits arranged in an array and a plurality of shift register circuits connected in cascade, wherein the shift register circuit is any one of the shift register circuits described above;

[0015] The signal output end of each stage of the shift register circuit is electrically connected to at least one row of pixel circuits; except for the last stage of the shift register circuit, the signal output end of each of the remaining stages of the shift register circuit is also electrically connected to the signal input end of the next stage of the shift register circuit, and the signal input end of the first stage of the shift register circuit receives a starting input signal.

[0016] A display device comprises the above-mentioned display panel.

[0017] Compared with the prior art, the above technical solution has the following advantages:

[0018] The shift register circuit provided in the embodiment of the present application, under the drive of the first clock signal, the second clock signal, the first level signal, the second level signal and the input signal, uses the first node control module to control the potential of the first node, uses the second node control module to control the potential of the second node, and uses the third node control module to control the potential of the third node. Then, the output module controls whether the signal output end outputs the first level signal according to the potential of the second node, and controls whether the signal output end outputs the second level signal according to the potential of the third node; by setting a reset module to control the path of the second level signal to be transmitted to the second node, the potential of the second node can be set to the second level signal through the reset module during the power-on stage of the display panel. Then, the output module can control the signal output end not to output the first level signal according to the potential of the second node, wherein the first level signal is the enable level of the corresponding thin film transistor in the pixel circuit, so as to avoid problems such as screen flashing or large current burns caused by abnormal opening of the thin film transistor in the pixel circuit of the display area.

[0019] Furthermore, the reset module controls the transmission path of the second level signal of the second level end to the second node according to the second clock signal of the second clock end and the potential of the first node, and the second clock end and the first node are both existing nodes of the shift register circuit, that is, the reset module only needs to use the existing node potential of the shift register circuit to control the potential of the second node, and there is no need to set up a separate wiring to control the reset module, thereby reducing the wiring and further reducing the border of the display panel. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0021] Figure 1 A schematic diagram of the structure of a shift register circuit provided in an embodiment of the present application;

[0022] Figure 2 A schematic diagram of the structure of another shift register circuit provided in an embodiment of the present application;

[0023] Figure 3 A structural schematic diagram of another shift register circuit provided in an embodiment of the present application;

[0024] Figure 4 A schematic diagram of the structure of another shift register circuit provided in an embodiment of the present application;

[0025] Figure 5A structural schematic diagram of another shift register circuit provided in an embodiment of the present application;

[0026] Figure 6 A schematic diagram of the structure of another shift register circuit provided in an embodiment of the present application;

[0027] Figure 7 A structural schematic diagram of another shift register circuit provided in an embodiment of the present application;

[0028] Figure 8 A timing diagram of the shift register circuit provided in the embodiment of the present application in the second mode;

[0029] Fig. 9 A schematic diagram of the structure of another shift register circuit provided in an embodiment of the present application;

[0030] Fig.10 A schematic diagram of the structure of a display panel provided in an embodiment of the present application;

[0031] Fig.11 A schematic diagram of the structure of a display device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0032] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0033] In the following description, many specific details are set forth to facilitate a full understanding of the present application, but the present application may also be implemented in other ways different from those described herein, and those skilled in the art may make similar generalizations without violating the connotation of the present application. Therefore, the present application is not limited to the specific embodiments disclosed below.

[0034] Figure 1 FIG. 4 shows a schematic diagram of a structure of a shift register circuit provided in an embodiment of the present application. Figure 1 As shown, the shift register circuit includes a first node control module 100 , a second node control module 200 , a third node control module 300 , an output module 400 and a reset module 500 .

[0035] The first node control module 100 is electrically connected to the first clock terminal GL, the first level terminal CK, the first node N1 and the second node N2, respectively, and is used to control the potential of the first node N1 according to the first clock signal VGL of the first clock terminal GL, the first level signal VCK of the first level terminal CK and the potential of the second node N2;

[0036] The second node control module 200 is electrically connected to the signal input terminal In, the first clock terminal CK, the second clock terminal, the second level terminal, the first node and the second node respectively, and is used to control the potential of the second node N2 according to the input signal Vin of the signal input terminal, the first clock signal VGL of the first clock terminal CK, the second clock signal VXCK of the second clock terminal XCK, the second level signal VGH of the second level terminal GH and the potential of the first node N1;

[0037] The third node control module 300 is electrically connected to the second clock terminal XCK, the second level terminal GH, the first node N1, the second node N2 and the third node N3, respectively, and is used to control the potential of the third node N3 according to the second clock signal VXCK of the second clock terminal XCK, the second level signal VGH of the second level terminal GH, the potential of the first node N1 and the potential of the second node N2;

[0038] The output module 400 is electrically connected to the first level terminal GL, the second level terminal GH, the second node N2, the third node N3 and the signal output terminal OUT, respectively, and is used to control the path of the first level signal VGL of the first level terminal GL to be transmitted to the signal output terminal OUT according to the potential of the second node N2, and to control the path of the second level signal VGH of the second level terminal GH to be transmitted to the signal output terminal OUT according to the potential of the third node N3;

[0039] It can be understood that the first node control module 100 is used to control the potential of the first node N1, the second node control module 200 is used to control the potential of the second node N2, and the third node control module 300 is used to control the potential of the third node N3. Furthermore, the output module 400 is used to control the path of the first level signal VGL of the first level terminal GL to the signal output terminal OUT according to the potential of the second node N2, and to control the path of the second level signal VGH of the second level terminal GH to the signal output terminal OUT according to the potential of the third node N3. In this way, the signal output terminal OUT of the shift register circuit outputs the first level signal VGL or the second level signal VGH.

[0040] It should be noted that, in the present application, for the convenience of expression, nodes such as the first node, the second node and the third node are defined, and these nodes can be virtual connection nodes or actual connection nodes.

[0041] like Figure 1 As shown, the reset module 500 in the shift register circuit is electrically connected to the second clock terminal XCK, the second level terminal GH, the first node N1 and the second node N2, respectively, and is used to control the transmission path of the second level signal VGH of the second level terminal GH to the second node N2 according to the second clock signal VXCK of the second clock terminal XCK and the potential of the first node N1.

[0042] That is to say, the potential of the second node N2 can be set to the second level signal VGH through the reset module 500, and then the output module 400 can control the transmission path of the first level signal VGL of the first level terminal GL to the signal output terminal OUT according to the potential of the second node N2, that is, control whether the signal output terminal OUT outputs the first level signal VGL.

[0043] In this way, the first level signal VGL can be set as the enable level signal of the corresponding thin film transistor in the pixel circuit, and the second level signal VGH can be set as the non-enable level signal of the corresponding thin film transistor in the pixel circuit. In the power-on stage of the display panel, the potential of the second node N2 can be set to the second level signal VGH through the reset module 500, and then the output module 400 can block the path of the first level signal VGL of the first level terminal GL to the signal output terminal OUT according to the potential of the second node N2, so that the signal output terminal OUT will not output the first level signal VGL, thereby avoiding problems such as abnormal opening of the thin film transistor in the pixel circuit of the display area, resulting in screen flickering or large current burns.

[0044] Thus, in the first mode, the first mode corresponds to the power-on stage of the display panel, the first clock signal VCK and the second clock signal VXCK are both enable level signals, and the signal output terminal OUT of the shift register circuit can only output the second level signal VGH; in the second mode, the second mode corresponds to the stage in which the shift register circuit provides a scan signal to the pixel circuit, the first clock signal VCK and the second clock signal VXCK are pulse signals whose enable levels do not overlap with each other, and the signal output terminal OUT of the shift register circuit alternately outputs the first level signal VGL and the second level signal VGH, which constitute the scan signal of the corresponding thin film transistor of the pixel circuit.

[0045] Furthermore, the reset module 500 controls the transmission path of the second level signal VGH of the second level terminal GH to the second node N2 according to the second clock signal VXCK of the second clock terminal XCK and the potential of the first node N1, and the second clock terminal XCK and the first node N1 are both existing nodes of the shift register circuit, that is, the reset module 500 only needs to use the existing node potential of the shift register circuit to control the potential of the second node N2, and there is no need to set up a separate wiring to control the reset module 500, thereby reducing the wiring and further reducing the border of the display panel.

[0046] Optional, such as Figure 2 and Figure 3 As shown, the reset module 500 includes a first switch unit 510 and a second switch unit 520; one of the first switch unit 510 and the second switch unit 520 is opened under the control of the potential of the first node N1, and the other is opened under the control of the second clock signal VXCK of the second clock terminal XCK; when the first switch unit 510 and the second switch unit 520 are both opened, the second level signal VGH of the second level terminal GH is transmitted to the second node N2 through the first switch unit 510 and the second switch unit 520.

[0047] Further optional, such as Figure 2 and Figure 3 As shown, the first switch unit 510 may include a first switch transistor M1, and the second switch unit 520 may include a second switch transistor M2; the first electrode of the first switch transistor M1 is electrically connected to the second level terminal GH, the second electrode of the first switch transistor M1 is electrically connected to the first electrode of the second switch transistor M2, and the second electrode of the second switch transistor M2 is electrically connected to the second node N2; the control end of the first switch transistor M1 and the control end of the second switch transistor M2, one of which is electrically connected to the first node N1 to receive the potential of the first node N1, and the other is electrically connected to the second clock terminal XCK to receive the second clock signal VXCK.

[0048] Optional, such as Figure 2 As shown, the control end of the first switch transistor M1 is electrically connected to the first node N1, and receives the potential of the first node N1, and the control end of the second switch transistor M2 is electrically connected to the second clock end XCK, and receives the second clock signal VXCK; at this time, when the potential of the first node N1 is an enable level for the first switch transistor M1, and the second clock signal VXCK is an enable level for the second switch transistor M2, the first switch transistor M1 and the second switch transistor M2 are both turned on, and the second level signal VGH of the second level end GH can be transmitted to the second node N2 through the first switch transistor M1 and the second switch transistor M2.

[0049] Or, another option, such as Figure 3As shown, the control end of the first switch transistor M1 is electrically connected to the second clock end XCK to receive the second clock signal VXCK, and the control end of the second switch transistor M2 is electrically connected to the first node N1 to receive the potential of the first node N1; at this time, when the second clock signal VXCK is at an enable level for the first switch transistor M1, and the potential of the first node N1 is at an enable level for the second switch transistor M2, the first switch transistor M1 and the second switch transistor M2 are both turned on, and the second level signal VGH of the second level end GH can be transmitted to the second node N2 through the first switch transistor M1 and the second switch transistor M2.

[0050] Through the above circuit design of the reset module 500, only when the first switch unit 510 and the second switch unit 520 are both turned on, the second level signal VGH of the second level end GH can be transmitted to the second node N2 through the first switch unit 510 and the second switch unit 520. In this way, in the first mode, that is, the power-on stage of the display panel, the first switch unit 510 and the second switch unit 520 are both turned on, and the second level signal VGH of the second level end GH is transmitted to the second node N2 through the first switch unit 510 and the second switch unit 520, and the second node N2 is set to the second level signal VGH; and in the second mode, that is, the stage where the shift register circuit provides the scan signal to the pixel circuit, at least one of the first switch unit 510 and the second switch unit 520 is turned off, which will no longer affect the potential of the second node N2, or even if the first switch unit 510 and the second switch unit 520 are both turned on, it is because the potential of the second node N2 needs to be set to the second level signal VGH, and the potential of the second node N2 will not be changed.

[0051] Optional, such as Figure 4 As shown, the first node control module 100 includes a first control unit 110 and a second control unit 120 .

[0052] The first control unit 110 is electrically connected to the first clock terminal CK, the first level terminal GL and the first node N1 respectively, and is used to control the transmission path of the first level signal VGL of the first level terminal GL to the first node N1 according to the first clock signal VCK of the first clock terminal CK.

[0053] The second control unit 120 is electrically connected to the first clock terminal CK, the first node N1 and the second node N2 respectively, and is used to control a transmission path of the first clock signal VCK from the first clock terminal CK to the first node N1 according to the potential of the second node N2.

[0054] Further optional, such as Figure 4As shown, the first control unit 110 includes a third switch transistor M3, a first electrode of the third switch transistor M3 is electrically connected to the first level end GL, a second electrode of the third switch transistor M3 is electrically connected to the first node N1, and a control end of the third switch transistor M3 is electrically connected to the first clock end CK; thus, when the first clock signal VCK is at an enable level for the third switch transistor M3, the third switch transistor M3 is turned on, allowing the first level signal VGL of the first level end GL to be transmitted to the first node N1.

[0055] like Figure 4 As shown, the second control unit 120 includes a fourth switch transistor M4, a first electrode of the fourth switch transistor M4 is electrically connected to the first clock terminal CK, a second electrode of the fourth switch transistor M4 is electrically connected to the first node N1, and a control terminal of the fourth switch transistor M4 is electrically connected to the second node N2; thus, when the potential of the second node N2 is at an enable level for the fourth switch transistor M4, the first clock signal VCK of the first clock terminal CK is transmitted to the first node N1.

[0056] Further optional, such as Figure 4 As shown, the fourth switch transistor M4 includes a first sub-switch transistor M41 and a second sub-switch transistor M42.

[0057] A first electrode of the first sub-switch transistor M41 is electrically connected to the first clock terminal CK, a second electrode of the first sub-switch transistor M41 is electrically connected to a first electrode of the second sub-switch transistor M42, and a second electrode of the second sub-switch transistor M42 is electrically connected to the first node N1;

[0058] The control end of the first sub-switch transistor M41 and the control end of the second sub-switch transistor M42 are both electrically connected to the second node N2.

[0059] Optional, such as Figure 5 As shown, the second node control module 200 includes a third control unit 210 , a first charge pump unit 220 , a third switch unit 230 and a fourth switch unit 240 .

[0060] The third control unit 210 is electrically connected to the signal input terminal In, the first clock terminal CK and the second node N2 respectively, and is used to control the transmission path of the input signal Vin of the signal input terminal In to the second node N2 according to the first clock signal VCK of the first clock terminal CK.

[0061] A first end of the first charge pump unit 220 is electrically connected to the fourth node N4 , a second end of the first charge pump unit 220 is electrically connected to the second node N2 , and the first charge pump unit 220 is used to control the amount of a signal coupled from the fourth node N4 to the second node N2 .

[0062] The third switch unit 230 is electrically connected to the second level terminal GH, the first node N1 and the fourth node N4 respectively, and is used to control a transmission path of the second level signal VGH of the second level terminal GH to the fourth node N4 according to the potential of the first node N1.

[0063] The fourth switch unit 240 is electrically connected to the second clock terminal XCK, the second node N2 and the fourth node N4 respectively, and is used to control a transmission path of the second clock signal VXCK from the second clock terminal XCK to the fourth node N4 according to the potential of the second node N2.

[0064] Further optional, such as Figure 5 As shown, the third control unit 210 includes a fifth switch transistor M5, a first electrode of the fifth switch transistor M5 is electrically connected to the signal input terminal In, a second electrode of the fifth switch transistor M5 is electrically connected to the second node N2, and a control terminal of the fifth switch transistor M5 is electrically connected to the first clock terminal CK; thus, when the first clock signal XCK of the first clock terminal CK is at an enable level for the fifth switch transistor M5, the fifth switch transistor M5 is turned on, and the input signal Vin of the signal input terminal In is transmitted to the second node N2 through the fifth switch transistor M5.

[0065] like Figure 5 As shown, the first charge pump unit 220 includes a first capacitor C1, a first plate of the first capacitor C1 is electrically connected to the fourth node N4, and a second plate of the first capacitor C2 is electrically connected to the second node N2.

[0066] The third switch unit 230 includes a sixth switch transistor M6, a first electrode of the sixth switch transistor M6 is electrically connected to the second level terminal GH, a second electrode of the sixth switch transistor M6 is electrically connected to the fourth node N4, and a control terminal of the sixth switch transistor M6 is electrically connected to the first node N1.

[0067] The fourth switch unit 240 includes a seventh switch transistor M7, a first electrode of the seventh switch transistor M7 is electrically connected to the second clock terminal XCK, a second electrode of the seventh switch transistor M7 is electrically connected to the fourth node N4, and a control terminal of the seventh switch transistor M7 is electrically connected to the second node N2.

[0068] Thus, when the potential of the first node N1 is at an enable level for the sixth switch transistor M6, the sixth switch transistor M6 is turned on, and the second level signal VGH of the second level terminal GH is transmitted to the fourth node N4 through the sixth switch transistor M6; when the potential of the second node N2 is at an enable level for the seventh switch transistor M7, the second clock signal VXCK of the second clock terminal XCK is transmitted to the fourth node N4 through the seventh switch transistor M7; and further, the first capacitor C1 controls the amount of the signal coupled from the fourth node N4 to the second node N2 according to the potential of the fourth node N4.

[0069] It is understandable that, due to the coupling effect of the first capacitor C1, when the potential of the fourth node N4 changes, the potential of the second node N2 will also change accordingly, so as to ensure that the potential difference between the two plates of the first capacitor C1 is fixed.

[0070] Optional, such as Figure 6 As shown, the third node control module 300 includes a fourth control unit 310 and a fifth control unit 320 .

[0071] Among them, the fourth control unit 310 is electrically connected to the second clock terminal XCK, the first node N1 and the third node N3 respectively, and is used to control the transmission path of the second clock signal VXCK of the second clock terminal XCK to the third node N3 according to the potential of the first node N1 and the second clock signal VXCK of the second clock terminal XCK.

[0072] The fifth control unit 320 is electrically connected to the second level terminal GH, the second node N2 and the third node N3 respectively, and is used to control a transmission path of the second level signal VGH from the second level terminal GH to the third node N3 according to the potential of the second node N2.

[0073] Further optional, such as Figure 6 As shown, the fourth control unit 310 includes an eighth switch transistor M8, a ninth switch transistor M9 and a second capacitor C2.

[0074] The first electrode of the eighth switch transistor M8 is electrically connected to the second clock terminal XCK, the second electrode of the eighth switch transistor M8 is electrically connected to the fifth node N5, and the control terminal of the eighth switch transistor M8 is electrically connected to the first node N1.

[0075] A first plate of the second capacitor C2 is electrically connected to the first node N1 , and a second plate of the second capacitor C2 is electrically connected to the fifth node N5 .

[0076] A first electrode of the ninth switch transistor M9 is electrically connected to the fifth node N5 , a second electrode of the ninth switch transistor M9 is electrically connected to the third node N3 , and a control terminal of the ninth switch transistor M9 is electrically connected to the second clock terminal XCK.

[0077] In this way, when the potential of the first node N1 is the enable level of the eighth switch transistor M8, and the second clock signal VXCK of the second clock terminal XCK is the enable level of the ninth switch transistor M9, the eighth switch transistor M8 and the ninth switch transistor M9 are turned on, and the second clock signal VXCK of the second clock terminal XCK is transmitted to the third node N3 through the eighth switch transistor M8 and the ninth switch transistor M9.

[0078] It can be understood that the second capacitor C2 can keep the potential difference between the two plates of the second capacitor C2 constant.

[0079] like Figure 6 As shown, the fifth control unit 320 includes a tenth switch transistor M10, a first electrode of the tenth switch transistor M10 is electrically connected to the second level terminal GH, a second electrode of the tenth switch transistor M10 is electrically connected to the third node N3, and a control terminal of the tenth switch transistor is electrically connected to the second node N2.

[0080] Thus, when the potential of the second node N2 is the enable level of the tenth switch transistor M10, the tenth switch transistor M10 is turned on, and the second level signal VGH of the second level terminal GH is transmitted to the third node N3 through the tenth switch transistor M10.

[0081] Optional, such as Figure 7 As shown, the output module 400 includes an eleventh switch transistor M11, a twelfth switch transistor M12 and a third capacitor C3.

[0082] The first electrode of the eleventh switch transistor M11 is electrically connected to the first level end GL, the second electrode of the eleventh switch transistor M11 is electrically connected to the signal output end OUT, and the control end of the eleventh switch transistor M11 is electrically connected to the second node N2.

[0083] A first electrode of the twelfth switch transistor M12 is electrically connected to the second level terminal GH, a second electrode of the twelfth switch transistor M12 is electrically connected to the signal output terminal OUT, and a control terminal of the twelfth switch transistor M12 is electrically connected to the third node N3;

[0084] A first plate of the third capacitor C3 is electrically connected to the second level terminal GH, and a second plate of the third capacitor C3 is electrically connected to the third node N3.

[0085] Thus, when the potential of the second node N2 is the enable level of the eleventh switch transistor M11, the eleventh switch transistor M11 is turned on, and the first level signal VGL of the first level terminal GL is transmitted to the signal output terminal OUT through the eleventh switch transistor M11, so that the signal output terminal OUT outputs the first level signal VGL.

[0086] When the potential of the third node N3 is the enable level of the twelfth switch transistor M12, the twelfth switch transistor M12 is turned on, and the second level signal VGH of the second level terminal GH is transmitted to the signal output terminal OUT through the twelfth switch transistor M12, so that the signal output terminal OUT outputs the second level signal VGH.

[0087] In the present application, the first clock signal VCK is a pulse signal in which a high level signal and a low level signal are alternately performed. Similarly, the second clock signal VXCK is also a pulse signal in which a high level signal and a low level signal are alternately performed.

[0088] The first level signal VGL of the first level terminal GL and the second level signal of the second level terminal GH are fixed signals; optionally, the first level signal VGL of the first level terminal GL is a low level signal, and the second level signal of the second level terminal GH is a high level signal; another optional, the first level signal VGL of the first level terminal GL is a high level signal; the second level signal of the second level terminal GH is a low level signal.

[0089] In order to better understand the present application, the first level signal VGL of the first level terminal GL is a low level signal, the second level signal of the second level terminal GH is a high level signal, the above-mentioned switching transistors are PMOS tubes, and the enable level signal is a low level signal, that is, the switching transistor is turned on under the control of the low level signal. For example, the shift register circuit (such as Figure 7 The working process of the device is described as shown in FIG.

[0090] In the first mode, i.e., the power-on stage of the display panel, the first clock signal VCK and the second clock signal VXCK are both at the enable level, i.e., the first clock signal VCK and the second clock signal VXCK are both at the low level. Thus, the first clock terminal CK is the first clock signal VCK at the low level, which turns on the third switch transistor M3. Thus, the first level signal VGL at the first level terminal GL is transmitted to the first node N1 through the third switch transistor M3, which makes the potential of the first node N1 at the low level. Then, the low level of the first node N1 turns on the eighth switch transistor M8, and due to the first The second clock signal VXCK of the second clock terminal XCK is at a low level, so that the ninth switch transistor M9 is also turned on. Therefore, the second clock signal VXCK of the second clock terminal XCK, which is at a low level, is transmitted to the third node N3 through the eighth switch transistor M8 and the ninth switch transistor M9, so that the potential of the third node N3 is at a low level; furthermore, the low level of the third node N3 turns on the twelfth switch transistor M12, and the second level signal VGH of the second level terminal GH is transmitted to the signal output terminal OUT through the twelfth switch transistor M12, so that the signal output terminal OUT outputs a high level signal.

[0091] At the same time, the first clock terminal CK is at a low level, and the first clock signal VCK turns on the fifth switch transistor M5. Thus, the input signal Vin at the signal input terminal In is at a high level, which is transmitted to the second node N2 through the fifth switch transistor M5, so that the potential of the second node N2 is at a high level. Furthermore, the low level of the first node N1 turns on the sixth switch transistor M6, and the second level signal VGH at the second level terminal GH is transmitted to the fourth node N4 through the sixth switch transistor M6. Meanwhile, the high level of the second node N2 turns off the seventh switch transistor M7. Therefore, the potential of the fourth node N4 is at a high level, and the potential of the second node N2 is kept at a high level through the coupling effect of the first capacitor C1. Furthermore, the high level of the second node N2 turns off the eleventh switch transistor M11, and the first level signal VGL at the first level terminal GL will not be transmitted to the signal output terminal OUT.

[0092] Furthermore, the low level of the first node N1 turns on the first switch transistor M1, and the second clock signal VXCK at the second clock terminal XCK being a low level turns on the second switch transistor M2. Thus, the second level signal VGH at the second level terminal GH is transmitted to the second node N2 through the first switch transistor M1 and the second switch transistor M2 of the reset module 500, further maintaining the potential of the second node N2 at a high level, thereby avoiding turning on the eleventh switch transistor M11 and causing the first level signal VGL at the first level terminal GL to be transmitted to the signal output terminal OUT, i.e. avoiding the signal output terminal OUT from outputting a low level, thereby avoiding problems such as screen flickering or large current burns caused by abnormal opening of the thin film transistor in the pixel circuit of the display area.

[0093] In addition, since the potential of the second node N2 is at a high level, the first sub-switch transistor M41 and the second sub-switch transistor M42 in the fourth switch transistor M4 are both turned off, and the tenth switch transistor M10 is also turned off.

[0094] Figure 8 1 shows a timing diagram of the shift register circuit provided in the embodiment of the present application in the second mode, wherein Vout is the signal output from the signal output terminal, such as Figure 8 As shown, the working process of the shift register circuit provided in the embodiment of the present application in the second mode, that is, in the stage where the shift register circuit provides a scanning signal to the pixel circuit, is as follows:

[0095] In the T1 period, the first clock signal VCK of the first clock terminal CK is at a low level, the second clock signal VXCK of the second clock terminal XCK is at a high level, and the input signal Vin of the signal input terminal In is at a high level. Thus, the third switch transistor M3 is turned on, and the first level signal VGL (low level) of the first level terminal GL is transmitted to the first node N1 through the third switch transistor M3, so that the potential of the first node N1 is at a low level, and then the eighth switch transistor M8 is turned on, so that the second clock signal VXCK is transmitted to the fifth node N5 through the eighth switch transistor M8, so that the potential of the fifth node N5 is at a high level, and the two plates of the second capacitor C2 have a potential difference; however, the second clock signal VXCK at a high level turns off the ninth switch transistor M9, and the third node N3 maintains the potential (high level) of the previous frame, and the potential difference between the two plates of the third capacitor C3 also keeps the potential of the third node N3 at a high level, thereby turning off the twelfth switch transistor M12, and the second level signal VGH (high level) of the second level terminal GH will not be transmitted to the signal output terminal OUT.

[0096] At the same time, the low-level first clock signal VCK turns on the fifth switch transistor M5, and the high-level input signal Vin at the signal input terminal In is transmitted to the second node N2 through the fifth switch transistor M5, so that the potential of the second node N2 is high, thereby turning off the eleventh switch transistor M11, and the first-level signal VGL (low level) of the first level terminal GL will not be transmitted to the signal output terminal OUT; and the low level of the first node N1 turns on the sixth switch transistor M6, and the high level of the second node N2 turns off the seventh switch transistor M7, and the second-level signal VGH (high level) of the second level terminal GH is transmitted to the fourth node N4 through the sixth switch transistor M6, so that the potential of the fourth node N4 is high, and then the potential of the second node N2 is kept high through the potential difference between the two plates of the first capacitor C1; the high level of the second node N2 turns off the first sub-switch transistor M41 and the second sub-switch transistor M42 in the fourth switch transistor M4, and also turns off the tenth switch transistor M10.

[0097] Furthermore, the low level of the first node N1 turns on the first switch transistor M1 , but the high level of the second clock signal VXCK turns off the second switch transistor M2 , and the reset module 500 does not affect the potential of the second node N2 .

[0098] Therefore, during the T1 period, the signal output terminal OUT of the shift register circuit keeps outputting the low level of the previous frame, and the reset module 500 does not affect the potential of the second node N2.

[0099] During the T12 period, the first clock signal VCK of the first clock terminal CK and the second clock signal VXCK of the second clock terminal XCK are both at high levels, and the input signal Vin of the signal input terminal In is at a high level. Thus, the third switch transistor M3 is turned off, but the potential of the first node N1 is still kept at a low level due to the second capacitor C2, so that the eighth switch transistor M8 is turned on, but the second clock signal VXCK (high level) turns off the ninth switch transistor M9, so the potential of the third node N3 is still kept at a high level, so that the twelfth switch transistor M12 is turned off, and thus the second level signal VGH (high level) of the second level terminal GH will not be transmitted to the signal output terminal OUT.

[0100] At the same time, the high-level first clock signal VCK turns off the fifth switch transistor M5, the low-level signal of the first node N1 turns on the sixth switch transistor M6, and the second-level signal VGH (high-level) of the second-level terminal GH is transmitted to the fourth node N4 through the sixth switch transistor M6, so that the potential of the fourth node N4 is high-level, and then the potential difference between the two plates of the first capacitor C1 keeps the potential of the second node N2 at a high level. The high-level of the second node N2 turns off the eleventh switch transistor M11, and the first-level signal VGL (low-level) of the first-level terminal GL will not be transmitted to the signal output terminal OUT; the high-level of the second node N2 also turns off the seventh switch transistor M7, the tenth switch transistor M10, and the first sub-switch transistor M41 and the second sub-switch transistor M42 in the fourth switch transistor M4.

[0101] Furthermore, the low level of the first node N1 turns on the first switch transistor M1 , but the high level of the second clock signal VXCK turns off the second switch transistor M2 , and the reset module 500 does not affect the potential of the second node N2 .

[0102] Therefore, during the T12 period, the signal output terminal OUT of the shift register circuit keeps outputting a low level, and the reset module 500 does not affect the potential of the second node N2.

[0103] During the T2 period, the first clock signal VCK of the first clock terminal CK is at a high level, the second clock signal VXCK of the second clock terminal XCK is at a low level, and the input signal Vin of the signal input terminal In is at a high level. Thus, the third switch transistor M3 is turned off, but due to the potential difference between the two plates of the second capacitor C2, the potential of the first node N1 is still kept at a low level, so that the eighth switch transistor M8 is turned on, and the second clock signal VXCK (low level) turns on the ninth switch transistor M9, so that the second clock signal VXCK (low level) is transmitted to the third node N3 through the eighth switch transistor M8 and the ninth switch transistor M9, so that the potential of the third node N3 becomes a low level, thereby turning on the twelfth switch transistor M12, and the second level signal VGH (high level) of the second level terminal GH is transmitted to the signal output terminal OUT.

[0104] At the same time, the first clock signal VCK at a high level turns off the fifth switch transistor M5, the low level of the first node N1 turns on the sixth switch transistor M6, the potential of the fourth node N4 is at a high level, and then the potential difference between the two plates of the first capacitor C1 keeps the potential of the second node N2 at a high level, the high level of the second node N2 turns off the eleventh switch transistor M11, and the first level signal VGL (low level) of the first level terminal GL will not be transmitted to the signal output terminal OUT; the high level of the second node N2 also turns off the seventh switch transistor M7, the tenth switch transistor M10, and the first sub-switch transistor M41 and the second sub-switch transistor M42 in the fourth switch transistor M4.

[0105] Furthermore, the low level of the first node N1 turns on the first switch transistor M1, and the second clock signal VXCK which is a low level turns on the second switch transistor M2. The second level signal VGH (high level) of the second level terminal GH is transmitted to the second node N2 through the first switch transistor M1 and the second switch transistor M2 in the reset module 500, keeping the potential of the second node N2 at a high level, and also does not affect the potential of the second node N2.

[0106] Therefore, starting from the T2 period, the signal output terminal OUT of the shift register circuit turns to output a high level, and the reset module 500 does not affect the potential of the second node N2.

[0107] During the T23 period, the first clock signal VCK of the first clock terminal CK and the second clock signal VXCK of the second clock terminal XCK are both at high levels, and the input signal Vin of the signal input terminal In is at a high level. Thus, the third switch transistor M3 is turned off, but due to the potential difference between the two plates of the second capacitor C2, the potential of the first node N1 is still kept at a low level, so that the eighth switch transistor M8 is turned on, but the second clock signal VXCK (high level) turns off the ninth switch transistor M9, so the potential of the third node N3 is still kept at a low level, so that the twelfth switch transistor M12 is turned on, and the second level signal VGH (high level) of the second level terminal GH is transmitted to the signal output terminal OUT.

[0108] At the same time, the high-level first clock signal VCK turns off the fifth switch transistor M5, the low-level signal of the first node N1 turns on the sixth switch transistor M6, and the second-level signal VGH (high-level) of the second-level terminal GH is transmitted to the fourth node N4 through the sixth switch transistor M6, so that the potential of the fourth node N4 is high-level, and then the potential difference between the two plates of the first capacitor C1 keeps the potential of the second node N2 at a high level. The high-level of the second node N2 turns off the eleventh switch transistor M11, and the first-level signal VGL (low-level) of the first-level terminal GL will not be transmitted to the signal output terminal OUT; the high-level of the second node N2 also turns off the seventh switch transistor M7, the tenth switch transistor M10, and the first sub-switch transistor M41 and the second sub-switch transistor M42 in the fourth switch transistor M4.

[0109] Furthermore, the low level of the first node N1 turns on the first switch transistor M1 , but the high level of the second clock signal VXCK turns off the second switch transistor M2 , and the reset module 500 does not affect the potential of the second node N2 .

[0110] Therefore, during the T23 period, the signal output terminal OUT of the shift register circuit keeps outputting a high level, and the reset module 500 does not affect the potential of the second node N2.

[0111] During the T3 period, the first clock signal VCK of the first clock terminal CK is at a low level, the second clock signal VXCK of the second clock terminal XCK is at a high level, and the input signal Vin of the signal input terminal In is at a high level. Thus, the third switch transistor M3 is turned on, so that the potential of the first node N1 is at a low level, and then the eighth switch transistor M8 is turned on, so that the second clock signal VXCK is transmitted to the fifth node N5 through the eighth switch transistor M8, so that the potential of the fifth node N5 is at a high level, and the two plates of the second capacitor C2 have a potential difference; but the second clock signal VXCK at a high level turns off the ninth switch transistor M9, and the third node N3 remains at a low level, thereby causing the twelfth switch transistor M12 to continue to be turned on, and the second level signal VGH (high level) of the second level terminal GH is transmitted to the signal output terminal OUT.

[0112] At the same time, the low-level first clock signal VCK turns on the fifth switch transistor M5, and the high-level input signal Vin at the signal input terminal In is transmitted to the second node N2 through the fifth switch transistor M5, so that the potential of the second node N2 is high, thereby turning off the eleventh switch transistor M11, and the first-level signal VGL (low level) of the first level terminal GL will not be transmitted to the signal output terminal OUT; and the low level of the first node N1 turns on the sixth switch transistor M6, and the high level of the second node N2 turns off the seventh switch transistor M7, and the second-level signal VGH (high level) of the second level terminal GH is transmitted to the fourth node N4 through the sixth switch transistor M6, so that the potential of the fourth node N4 is high, and then the potential of the second node N2 is kept high through the potential difference between the two plates of the first capacitor C1; the high level of the second node N2 turns off the first sub-switch transistor M41 and the second sub-switch transistor M42 in the fourth switch transistor M4, and also turns off the tenth switch transistor M10.

[0113] Furthermore, the low level of the first node N1 turns on the first switch transistor M1 , but the high level of the second clock signal VXCK turns off the second switch transistor M2 , and the reset module 500 does not affect the potential of the second node N2 .

[0114] Therefore, during the T3 period, the signal output terminal OUT of the shift register circuit keeps outputting a high level, and the reset module 500 does not affect the potential of the second node N2.

[0115] In the T34 stage, the first clock signal VCK of the first clock terminal CK and the second clock signal VXCK of the second clock terminal XCK are both at high levels, and the input signal Vin of the signal input terminal In is at a high level. Thus, the third switch transistor M3 is turned off, but due to the potential difference between the two plates of the second capacitor C2, the potential of the first node N1 is still kept at a low level, so that the eighth switch transistor M8 is turned on, but the second clock signal VXCK (high level) enables the ninth switch transistor M9, so the potential of the third node N3 is still kept at a low level, so that the twelfth switch transistor M12 is turned on, and then the second level signal VGH (high level) of the second level terminal GH is transmitted to the signal output terminal OUT.

[0116] At the same time, the high-level first clock signal VCK turns off the fifth switch transistor M5, the low-level signal of the first node N1 turns on the sixth switch transistor M6, and the second-level signal VGH (high-level) of the second-level terminal GH is transmitted to the fourth node N4 through the sixth switch transistor M6, so that the potential of the fourth node N4 is high-level, and then the potential difference between the two plates of the first capacitor C1 keeps the potential of the second node N2 at a high level. The high-level of the second node N2 turns off the eleventh switch transistor M11, and the first-level signal VGL (low-level) of the first-level terminal GL will not be transmitted to the signal output terminal OUT; the high-level of the second node N2 also turns off the seventh switch transistor M7, the tenth switch transistor M10, and the first sub-switch transistor M41 and the second sub-switch transistor M42 in the fourth switch transistor M4.

[0117] Furthermore, the low level of the first node N1 turns on the first switch transistor M1 , but the high level of the second clock signal VXCK turns off the second switch transistor M2 , and the reset module 500 does not affect the potential of the second node N2 .

[0118] Therefore, during the T34 period, the signal output terminal OUT of the shift register circuit keeps outputting a high level, and the reset module 500 does not affect the potential of the second node N2.

[0119] In the T4 stage, the first clock signal VCK of the first clock terminal CK is at a high level, the second clock signal VXCK of the second clock terminal XCK is at a low level, and the input signal Vin of the signal input terminal In is at a low level. Thus, the third switch transistor M3 is turned off, but due to the potential difference between the two plates of the second capacitor C2, the potential of the first node N1 is still kept at a low level, so that the eighth switch transistor M8 is turned on, and the second clock signal VXK (low level) turns on the ninth switch transistor M9, so that the second clock signal VXCK (low level) is transmitted to the third node N3 through the eighth switch transistor M8 and the ninth switch transistor M9, so that the potential of the third node N3 is still at a low level, thereby turning on the twelfth switch transistor M12, and the second level signal VGH (high level) of the second level terminal GH continues to be transmitted to the signal output terminal OUT.

[0120] At the same time, the first clock signal VCK at a high level turns off the fifth switch transistor M5, the low level of the first node N1 turns on the sixth switch transistor M6, the potential of the fourth node N4 is at a high level, and then the potential difference between the two plates of the first capacitor C1 keeps the potential of the second node N2 at a high level, the high level of the second node N2 turns off the eleventh switch transistor M11, and the first level signal VGL (low level) of the first level terminal GL will not be transmitted to the signal output terminal OUT; the high level of the second node N2 also turns off the seventh switch transistor M7, the tenth switch transistor M10, and the first sub-switch transistor M41 and the second sub-switch transistor M42 in the fourth switch transistor M4.

[0121] Furthermore, the low level of the first node N1 turns on the first switch transistor M1, and the second clock signal VXCK which is a low level turns on the second switch transistor M2. The second level signal VGH (high level) of the second level terminal GH is transmitted to the second node N2 through the first switch transistor M1 and the second switch transistor M2 in the reset module 500, keeping the potential of the second node N2 at a high level, and also does not affect the potential of the second node N2.

[0122] Therefore, in the T4 phase, the signal output terminal OUT of the shift register circuit still maintains outputting a high level, and the reset module 500 does not affect the potential of the second node N2.

[0123] During the T45 period, the first clock signal VCK of the first clock terminal CK and the second clock signal VXCK of the second clock terminal XCK are both at a high level, and the input signal Vin of the signal input terminal In is at a low level. Thus, the third switch transistor M3 is turned off, but due to the potential difference between the two plates of the second capacitor C2, the potential of the first node N1 is still kept at a low level, so that the eighth switch transistor M8 is turned on, but the second clock signal VXCK (high level) enables the ninth switch transistor M9, so the potential of the third node N3 is still kept at a low level, so that the twelfth switch transistor M12 is turned off, and the second level signal VGH (high level) of the second level terminal GH will not be transmitted to the signal output terminal OUT.

[0124] At the same time, the high-level first clock signal VCK turns off the fifth switch transistor M5, the low-level signal of the first node N1 turns on the sixth switch transistor M6, and the second-level signal VGH (high-level) of the second-level terminal GH is transmitted to the fourth node N4 through the sixth switch transistor M6, so that the potential of the fourth node N4 is high-level, and then the potential difference between the two plates of the first capacitor C1 keeps the potential of the second node N2 at a high level. The high-level of the second node N2 turns off the eleventh switch transistor M11, and the first-level signal VGL (low-level) of the first-level terminal GL will not be transmitted to the signal output terminal OUT; the high-level of the second node N2 also turns off the seventh switch transistor M7, the tenth switch transistor M10, and the first sub-switch transistor M41 and the second sub-switch transistor M42 in the fourth switch transistor M4.

[0125] Furthermore, the low level of the first node N1 turns on the first switch transistor M1 , but the high level of the second clock signal VXCK turns off the second switch transistor M2 , and the reset module 500 does not affect the potential of the second node N2 .

[0126] Therefore, during the T45 period, the signal output terminal OUT of the shift register circuit keeps outputting a high level, and the reset module 500 does not affect the potential of the second node N2.

[0127] During the T5 period, the first clock signal VCK of the first clock terminal CK is at a low level, the second clock signal VXCK of the second clock terminal XCK is at a high level, and the input signal Vin of the signal input terminal In is at a low level. Thus, the fifth switching transistor M5 is turned on, and the input signal Vin of the signal input terminal In is at a low level. This is transmitted to the second node N2 through the fifth switching transistor M5, so that the potential of the second node N2 is at a low level, thereby turning on the eleventh switching transistor M11, and the first level signal VGL (low level) of the first level terminal GL is transmitted to the signal output terminal OUT.

[0128] At the same time, the low level of the second node N2 turns on the tenth switch transistor M10, and the second level signal VGH (high level) of the second level terminal GH is transmitted to the third node N3 through the tenth switch transistor M10, so that the third node N3 is at a high level, thereby turning off the twelfth switch transistor M12, and the second level signal VGH (high level) of the second level terminal GH will not be transmitted to the signal output terminal OUT; and the first clock signal VCK at a low level turns on the third switch transistor M3, so that the potential of the first node N1 is at a low level, and the low level of the second node N2 also turns on the first sub-switch transistor M4 in the fourth switch transistor M4. 1 and the second sub-switch transistor M42 are turned on, and the low-level first clock signal VCK is transmitted to the first node N1 through the first sub-switch transistor M41 and the second sub-switch transistor M42, so that the potential of the first node N1 is also low, and then the eighth switch transistor M8 is turned on, so that the second clock signal VXCK is transmitted to the fifth node N5 through the eighth switch transistor M8, so that the potential of the fifth node N5 is high, and the two plates of the second capacitor C2 have a potential difference; but the high-level second clock signal VXCK turns off the ninth switch transistor M9, so the third node N3 is still high due to the conduction of the tenth switch transistor M10.

[0129] Furthermore, the low level of the first node N1 turns on the first switch transistor M1 , but the high level of the second clock signal VXCK turns off the second switch transistor M2 , and the reset module 500 does not affect the potential of the second node N2 .

[0130] Therefore, during the T5 period, the signal output terminal OUT of the shift register circuit outputs a low level instead, and the reset module 500 does not affect the potential of the second node N2.

[0131] In the T56 stage, the first clock signal VCK of the first clock terminal CK and the second clock signal VXCK of the second clock terminal XCK are both high level, and the input signal Vin of the signal input terminal In is low level. In this way, the fifth switching transistor M5 is turned off, the second node N2 maintains a low level, and the eleventh switching transistor M11 is turned on, and the first level signal VGL (low level) of the first level terminal GL is transmitted to the signal output terminal OUT.

[0132] At the same time, the low level of the second node N2 turns on the first sub-switch transistor M41 and the second sub-switch transistor M42 in the fourth switch transistor M4, and the high-level first clock signal VCK is transmitted to the first node N1, so that the potential of the first node N1 is high, thereby turning off the eighth switch transistor M8, and the ninth switch transistor M9 is also turned off because the second clock signal VXCK is high; the low level of the second node N2 also turns on the tenth switch transistor M10, and the high-level second-level signal VGH is transmitted to the third node N3 through the tenth switch transistor M10, so that the third node N3 is still high, thereby turning off the twelfth switch transistor M12, and the second-level signal VGH (high level) of the second level terminal GH will not be transmitted to the signal output terminal OUT; and the high level of the first node N1 also turns off the sixth switch transistor M6, and the low level of the second node N2 turns on the seventh switch transistor M7, and the high-level second clock signal VXCK is transmitted to the fourth node N4, and the potential difference between the two plates of the first capacitor C1 keeps the potential of the second node N2 at a low level.

[0133] Furthermore, the high level of the first node N1 turns off the first switch transistor M1 , and the high level of the second clock signal VXCK turns off the second switch transistor M2 , and the reset module 500 does not affect the potential of the second node N2 .

[0134] Therefore, in the T56 stage, the signal output terminal OUT of the shift register circuit keeps outputting a low level, and the reset module 500 does not affect the potential of the second node N2.

[0135] In the T6 stage, the first clock signal VCK of the first clock terminal CK is at a high level, the second clock signal VXCK of the second clock terminal XCK is at a low level, and the input signal Vin of the signal input terminal In is at a low level. In this way, the second node N2 maintains a low level, so that the eleventh switching transistor M11 is turned on, and the first level signal VGL (low level) of the first level terminal GL is transmitted to the signal output terminal OUT.

[0136] At the same time, the low level of the second node N2 turns on the first sub-switch transistor M41 and the second sub-switch transistor M42 in the fourth switch transistor M4, and the high-level first clock signal VCK is transmitted to the first node N1, so that the potential of the first node N1 is high, thereby turning off the eighth switch transistor M8, and the ninth switch transistor M9 is also turned off because the second clock signal VXCK is high; the low level of the second node N2 also turns on the tenth switch transistor M10, and the high-level second level signal VGH is transmitted to the third node N3 through the tenth switch transistor M10. , so that the third node N3 is still at a high level, thereby turning off the twelfth switch transistor M12, and the second level signal VGH (high level) of the second level terminal GH will not be transmitted to the signal output terminal OUT; and the high level of the first node N1 also turns off the sixth switch transistor M6, and the low level of the second node N2 turns on the seventh switch transistor M7, and the low-level second clock signal VXCK is transmitted to the fourth node N4, and the potential difference between the two plates of the first capacitor C1 further lowers the potential of the second node N2, which is beneficial to improving the driving ability of the eleventh switch transistor M11.

[0137] Furthermore, the second clock signal VXCK at a low level turns on the second switch transistor M2 , but the high level of the first node N1 turns off the first switch transistor M1 , and the reset module 500 does not affect the potential of the second node N2 .

[0138] Therefore, in the T8 phase, the signal output terminal OUT of the shift register circuit keeps outputting a low level, and the reset module 500 does not affect the potential of the second node N2.

[0139] And so on.

[0140] Through the above analysis, it can be known that when the potential of the second node N2 is at a high level and the eleventh switch transistor M11 is turned off, the potential of the first node N1 is basically at a low level, and the sixth switch transistor M6 is controlled to be turned on, so that the second level signal VGH (high level) of the second level end GH is transmitted to the fourth node N4 through the sixth switch transistor M6, and then the potential of the second node N2 is stabilized by the potential difference between the two plates of the first capacitor C1; since the second level signal VGH is a fixed potential signal, the potential of the second node N2 can be kept stable at this stage, and the potential of the second node N2 will not be affected by the change of the second clock signal VXCK.

[0141] When the potential of the second node N2 is at a low level and the eleventh switch transistor M11 is turned on, the low level of the second node N2 also turns on the seventh switch transistor M7, thereby transmitting the second clock signal VXCK to the fourth node N4 through the seventh switch transistor M7. In this way, when the second clock signal VXCK is at a low level, the potential of the second node N2 can be further lowered through the first capacitor C1, thereby improving the driving capability of the eleventh switch transistor M11.

[0142] Similarly, the second capacitor C2 also has a similar function. When the potential of the first node N1 is at a low level, the eighth switch transistor M8 is turned on. When the second clock signal VXCK is at a low level, the potential of the first node N1 can be further lowered through the second capacitor C2, thereby improving the driving capability of the eighth switch transistor M8.

[0143] It should also be noted that, referring to the initial time T2, the second clock signal VXCK changes from a high level to a low level, and since the low level of the first node N1 turns on the eighth switch transistor M8, the potential of the fifth node N5 also changes from a high level to a low level along with the second clock signal VXCK, and thus, due to the potential difference between the two plates of the second capacitor C2, the potential of the first node N1 is further pulled down. However, the first clock signal VCK is at a high level at this time, and for the third switch transistor M3, the control terminal (gate) of the third switch transistor M3 is at a high level, and the second electrode (source) of the third switch transistor M3 is at a low level that is further pulled down, and the third switch transistor M3 is a PMOS tube, which may cause the third switch transistor M3 to break down, and may also cause the threshold voltage Vth to be too large due to the gate-source voltage difference Vgs, which may easily cause the third switch transistor M3 to fail to turn off and output abnormally.

[0144] Based on this, further optional, such as Fig. 9 As shown, the first node control module 100 also includes a first voltage-stabilizing transistor T1, the first node N1 includes a first sub-node N11 and a second sub-node N12, the first control unit 110 and the second control unit 120 are both electrically connected to the first sub-node N11; the first electrode of the first voltage-stabilizing transistor T1 is electrically connected to the first sub-node N11, the second electrode of the first voltage-stabilizing transistor T2 is electrically connected to the second sub-node N12, the control end of the first voltage-stabilizing transistor T1 is electrically connected to the first level end GL, and is in an on state under the control of the first level signal VGL.

[0145] Taking the first voltage-stabilizing transistor T1 as a PMOS tube as an example, it is in a conducting state under the control of the first level signal VGL of a low level, that is, it is in a normally open state, so that the first voltage-stabilizing transistor T1 can be used to stabilize the potentials of the first sub-node N11 and the second sub-node N12, and the potential of the first sub-node N11 can be approximately equal to the potential of the second sub-node N12, that is, the potential of the first node N1.

[0146] Similarly, if Fig. 9 As shown, the second node control module 200 also includes a second voltage-stabilizing transistor T2, the second node N2 includes a third sub-node N21 and a fourth sub-node N22, the third control unit 210 is electrically connected to the third sub-node N21, and the second end of the first charge pump unit 220 is electrically connected to the fourth sub-node N22; the first electrode of the second voltage-stabilizing transistor T2 is electrically connected to the third sub-node N21, the second electrode of the second voltage-stabilizing transistor T2 is electrically connected to the fourth sub-node N22, and the control end of the second voltage-stabilizing transistor T2 is electrically connected to the first level end GL, and is in an on state under the control of the first level signal VGL.

[0147] Taking the second voltage-stabilizing transistor T2 as a PMOS tube as an example, it is in a conducting state under the control of the first level signal VGL of a low level, that is, it is in a normally open state, so that the second voltage-stabilizing transistor T2 can be used to stabilize the potentials of the third sub-node N21 and the fourth sub-node N22, and the potential of the third sub-node N21 can be approximately equal to the potential of the fourth sub-node N22, that is, the potential of the second node N2.

[0148] Based on the same inventive concept, the embodiment of the present application further provides a display panel, such as Fig.10 As shown, the display panel 1000 includes a plurality of pixel circuits Pixel arranged in an array and a plurality of cascaded shift register circuits VSR, wherein the shift register circuit VSR is a shift register circuit provided by any of the above embodiments. The signal output end of each shift register circuit VSR is electrically connected to at least one row of pixel circuits Pixel to provide a scanning signal for the pixel circuits Pixel; except for the last shift register circuit VSR, the signal output end of each shift register circuit VSR of the remaining stages is also electrically connected to the signal input end of the next shift register circuit VSR, and the signal input end of the first shift register circuit VSR receives a start input signal.

[0149] like Fig.10As shown, the display panel also includes a first clock signal line LCK for providing a first clock signal VCK to a first clock terminal CK of each stage of the shift register circuit VSR, a second clock signal line LXCK for providing a second clock signal VXCK to a second clock terminal XCK of each stage of the shift register circuit VSR, a first level signal line LGL for providing a first level signal VGL to a first level terminal GL of each stage of the shift register circuit VSR, and a second level signal line LGH for providing a second level signal VGH to a second level terminal GH of each stage of the shift register circuit VSR; the first stage of the shift register circuit VSR receives a start input signal input by a start input signal line LIn, and then, starting from the second stage of the shift register circuit VSR, a signal output by a signal output terminal OUT of each stage of the shift register circuit VSR is used as a signal Vin input by a signal input terminal In of a next stage of the shift register circuit VSR.

[0150] As mentioned above, the reset module 500 can control the potential of the second node N2 by using the existing node potential of the shift register circuit, and does not need to set up a separate wiring to control the reset module 500, thereby reducing the wiring and further reducing the border of the display panel.

[0151] It can be understood that the signal output from the signal output terminal OUT of the shift register circuit VSR can be a light-emitting control signal (also a scanning signal) for controlling the light-emitting control transistor in the pixel circuit Piexl to be turned on or off, or it can be a scanning signal for controlling the gate reset transistor, anode reset transistor and threshold compensation transistor in the pixel circuit Piexl to be turned on or off, or it can be a scanning signal for controlling the bias transistor in the pixel circuit Piexl to be turned on or off, depending on the specific circumstances.

[0152] Among them, taking the signal output by the shift register circuit VSR as the light control signal for controlling the light control transistor in the pixel circuit Pixel to be turned on or off as an example, the signal input terminal IN of the first-stage shift register circuit VSR is electrically connected to the starting input signal line LIn for transmitting the starting input signal, and the signal input terminal IN of each stage of the shift register circuit VSR from the second-stage shift register circuit to the n-th stage shift register circuit is electrically connected to the signal output terminal OUT of the previous stage shift register circuit, so that the starting input signal transmitted by the starting input signal line LIn controls the start time and end time of the enable level of the light control signal output by the first-stage shift register circuit, and in other stages of the shift register circuit, the light control signal output by the signal output terminal OUT of the previous stage shift register circuit controls the start time and end time of the light control signal outputted by it, so that each stage of the shift register circuit starts to output the enable level of the light control signal in turn, and stops outputting the enable level of the light control signal in turn, thereby completing the sequential scanning of each row of pixel circuits.

[0153] Accordingly, the embodiment of the present application further provides a display device, such as Fig.11 As shown, the display device 2000 includes the above-mentioned display panel 1000. The display device 2000 can be any electronic device with a display function, such as a touch screen, a mobile phone, a tablet computer, a notebook computer, an e-book or a television.

[0154] The various parts in this manual are described in a combination of parallel and progressive ways. Each part focuses on the differences from other parts, and the same or similar parts between the various parts can be referenced to each other.

[0155] With respect to the above description of the disclosed embodiments, the features described in the embodiments in this specification may be replaced or combined with each other, so that professionals in the field can implement or use the present application. Various modifications to these embodiments will be apparent to professionals in the field, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present application. Therefore, the present application will not be limited to the embodiments shown herein, but will conform to the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A shift register circuit, characterized in that: include: A first node control module is electrically connected to the first clock end, the first level end, the first node and the second node respectively, and is used to control the potential of the first node according to the first clock signal of the first clock end, the first level signal of the first level end and the potential of the second node; a second node control module, electrically connected to the signal input terminal, the first clock terminal, the second clock terminal, the second level terminal, the first node, and the second node, respectively, and configured to control the potential of the second node according to the input signal of the signal input terminal, the first clock signal of the first clock terminal, the second clock signal of the second clock terminal, the second level signal of the second level terminal, and the potential of the first node; a third node control module, electrically connected to the second clock end, the second level end, the first node, the second node and the third node respectively, and configured to control the potential of the third node according to the second clock signal of the second clock end, the second level signal of the second level end, the potential of the first node and the potential of the second node; a reset module, electrically connected to the second clock end, the second level end, the first node and the second node respectively, and configured to control a path for the second level signal of the second level end to be transmitted to the second node according to the second clock signal of the second clock end and the potential of the first node; an output module, electrically connected to the first level end, the second level end, the second node, the third node and the signal output end, respectively, and configured to control a path for the first level signal of the first level end to be transmitted to the signal output end according to the potential of the second node, and to control a path for the second level signal of the second level end to be transmitted to the signal output end according to the potential of the third node; In the first mode, both the first clock signal and the second clock signal are at enable levels; In the second mode, the first clock signal and the second clock signal are pulse signals whose enable levels do not overlap with each other.

2. The shift register circuit according to claim 1, characterized in that: The reset module includes a first switch unit and a second switch unit; One of the first switch unit and the second switch unit is turned on under the control of the potential of the first node, and the other is turned on under the control of the second clock signal of the second clock terminal; When the first switch unit and the second switch unit are both turned on, the second level signal at the second level end is transmitted to the second node through the first switch unit and the second switch unit.

3. The shift register circuit according to claim 2, characterized in that: The first switch unit includes a first switch transistor, and the second switch unit includes a second switch transistor; The first electrode of the first switch transistor is electrically connected to the second level end, the second electrode of the first switch transistor is electrically connected to the first electrode of the second switch transistor, and the second electrode of the second switch transistor is electrically connected to the second node; One of the control end of the first switch transistor and the control end of the second switch transistor is electrically connected to the first node, and the other is electrically connected to the second clock end.

4. The shift register circuit according to claim 1, wherein: The first node control module includes a first control unit and a second control unit; The first control unit is electrically connected to the first clock end, the first level end and the first node respectively, and is used to control a path for transmitting the first level signal of the first level end to the first node according to the first clock signal of the first clock end; The second control unit is electrically connected to the first clock end, the first node and the second node respectively, and is used to control a transmission path of the first clock signal from the first clock end to the first node according to the potential of the second node.

5. The shift register circuit according to claim 4, characterized in that: The first control unit includes a third switch transistor, a first electrode of the third switch transistor is electrically connected to the first level end, a second electrode of the third switch transistor is electrically connected to the first node, and a control end of the third switch transistor is electrically connected to the first clock end.

6. The shift register circuit according to claim 4, characterized in that: The second control unit includes a fourth switch transistor, a first electrode of the fourth switch transistor is electrically connected to the first clock end, a second electrode of the fourth switch transistor is electrically connected to the first node, and a control end of the fourth switch transistor is electrically connected to the second node.

7. The shift register circuit according to claim 6, characterized in that: The fourth switch transistor includes a first sub-switch transistor and a second sub-switch transistor; The first electrode of the first sub-switch transistor is electrically connected to the first clock terminal, the second electrode of the first sub-switch transistor is electrically connected to the first electrode of the second sub-switch transistor, and the second electrode of the second sub-switch transistor is electrically connected to the first node; The control end of the first sub-switch transistor and the control end of the second sub-switch transistor are both electrically connected to the second node.

8. The shift register circuit according to claim 4, characterized in that: The first node control module also includes a first voltage stabilizing transistor; The first node includes a first sub-node and a second sub-node, and the first control unit and the second control unit are both electrically connected to the first sub-node; The first electrode of the first voltage stabilizing transistor is electrically connected to the first subnode, the second electrode of the first voltage stabilizing transistor is electrically connected to the second subnode, the control end of the first voltage stabilizing transistor is electrically connected to the first level end, and is in an on state under the control of the first level signal.

9. The shift register circuit according to claim 1, characterized in that: The second node control module includes a third control unit, a first charge pump unit, a third switch unit and a fourth switch unit; The third control unit is electrically connected to the signal input terminal, the first clock terminal and the second node respectively, and is used to control the transmission path of the input signal of the signal input terminal to the second node according to the first clock signal of the first clock terminal; The first end of the first charge pump unit is electrically connected to the fourth node, the second end of the first charge pump unit is electrically connected to the second node, and the first charge pump unit is used to control the amount of the signal coupled from the fourth node to the second node; The third switch unit is electrically connected to the second level end, the first node and the fourth node respectively, and is used to control the transmission path of the second level signal of the second level end to the fourth node according to the potential of the first node; The fourth switch unit is electrically connected to the second clock end, the second node and the fourth node respectively, and is used to control a transmission path of the second clock signal from the second clock end to the fourth node according to the potential of the second node.

10. The shift register circuit according to claim 9, characterized in that: The third control unit includes a fifth switch transistor, a first electrode of the fifth switch transistor is electrically connected to the signal input terminal, a second electrode of the fifth switch transistor is electrically connected to the second node, and a control terminal of the fifth switch transistor is electrically connected to the first clock terminal.

11. The shift register circuit according to claim 9, characterized in that: The first charge pump unit includes a first capacitor, a first plate of the first capacitor is electrically connected to the fourth node, and a second plate of the first capacitor is electrically connected to the second node; The third switch unit includes a sixth switch transistor, a first electrode of the sixth switch transistor is electrically connected to the second level end, a second electrode of the sixth switch transistor is electrically connected to the fourth node, and a control end of the sixth switch transistor is electrically connected to the first node; The fourth switch unit includes a seventh switch transistor, a first electrode of the seventh switch transistor is electrically connected to the second clock end, a second electrode of the seventh switch transistor is electrically connected to the fourth node, and a control end of the seventh switch transistor is electrically connected to the second node.

12. The shift register circuit according to claim 9, characterized in that: The second node control module also includes a second voltage stabilizing transistor; The second node includes a third sub-node and a fourth sub-node, the third control unit is electrically connected to the third sub-node, and the second end of the first charge pump unit is electrically connected to the fourth sub-node; The first electrode of the second voltage stabilizing transistor is electrically connected to the third subnode, the second electrode of the second voltage stabilizing transistor is electrically connected to the fourth subnode, the control end of the second voltage stabilizing transistor is electrically connected to the first level end, and is in an on state under the control of the first level signal.

13. The shift register circuit according to claim 1, characterized in that: The third node control module includes a fourth control unit and a fifth control unit; The fourth control unit is electrically connected to the second clock terminal, the first node and the third node respectively, and is used to control a transmission path of the second clock signal of the second clock terminal to the third node according to the potential of the first node and the second clock signal of the second clock terminal; The fifth control unit is electrically connected to the second level end, the second node and the third node respectively, and is used to control a transmission path of the second level signal of the second level end to the third node according to the potential of the second node.

14. The shift register circuit according to claim 13, characterized in that: The fourth control unit includes an eighth switch transistor, a ninth switch transistor and a second capacitor; A first electrode of the eighth switch transistor is electrically connected to the second clock terminal, a second electrode of the eighth switch transistor is electrically connected to the fifth node, and a control terminal of the eighth switch transistor is electrically connected to the first node; The first electrode plate of the second capacitor is electrically connected to the first node, and the second electrode plate of the second capacitor is electrically connected to the fifth node; A first electrode of the ninth switch transistor is electrically connected to the fifth node, a second electrode of the ninth switch transistor is electrically connected to the third node, and a control terminal of the ninth switch transistor is electrically connected to the second clock terminal.

15. The shift register circuit according to claim 13, characterized in that: The fifth control unit includes a tenth switch transistor, a first electrode of the tenth switch transistor is electrically connected to the second level end, a second electrode of the tenth switch transistor is electrically connected to the third node, and a control end of the tenth switch transistor is electrically connected to the second node.

16. The shift register circuit according to claim 1, characterized in that: The output module includes an eleventh switch transistor, a twelfth switch transistor and a third capacitor; The first electrode of the eleventh switch transistor is electrically connected to the first level end, the second electrode of the eleventh switch transistor is electrically connected to the signal output end, and the control end of the eleventh switch transistor is electrically connected to the second node; The first electrode of the twelfth switch transistor is electrically connected to the second level end, the second electrode of the twelfth switch transistor is electrically connected to the signal output end, and the control end of the twelfth switch transistor is electrically connected to the third node; The first plate of the third capacitor is electrically connected to the second level end, and the second plate of the third capacitor is electrically connected to the third node.

17. A display panel, characterized in that: Comprising a plurality of pixel circuits arranged in an array and a plurality of shift register circuits connected in cascade, wherein the shift register circuit is the shift register circuit according to any one of claims 1 to 16; The signal output end of the shift register circuit of each level is electrically connected to at least one row of the pixel circuits; except for the shift register circuit of the last level, the signal output end of each of the remaining shift register circuits is also electrically connected to the signal input end of the shift register circuit of the next level, and the signal input end of the shift register circuit of the first level receives a starting input signal.

18. A display device, characterized in that: Comprising the display panel as claimed in claim 17.

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