Display panel and display device

Abstract

The present disclosure provides a display device and a display panel, the display device and the display panel including: a substrate including a display area and a non-display area outside the display area; a transistor disposed over the substrate; a base voltage line disposed over the substrate; a planarization layer disposed on the transistor and the base voltage line; a pixel electrode disposed on the planarization layer; a bank disposed on the pixel electrode and including an opening exposing a portion of the pixel electrode; an element intermediate layer on the pixel electrode through an opening of the bank in the light emitting region, and extending along the bank in the non-light emitting region; a common electrode provided on the element intermediate layer; and a link area configured to electrically interconnect the base voltage line and the common electrode, and disposed in the display area.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the priority of Korean Patent Application No. 10-2023-0098653 filed in the Korean Intellectual Property Office on July 28, 2023, the entire contents of which are hereby expressly incorporated by reference into this application. Technical Field

[0003] The present disclosure relates to electronic devices having displays, and more particularly, to display panels and display devices. Background Art

[0004] An organic light-emitting display device is a self-luminous display device and is a display device that emits light using an organic light-emitting element. An organic light-emitting diode (OLED) emits light when an exciton, which is a combination of electrons and holes injected into an emission layer by an electrode for electron injection (e.g., cathode) and an electrode for hole injection (e.g., anode), drops from an excited state to a ground state.

[0005] The organic light emitting display device may be configured with a top emission structure, a bottom emission structure, or a dual emission structure according to a direction of light emission, and may be driven by a passive matrix technology or an active matrix technology.

[0006] Compared to other types of display devices such as liquid crystal display (LCD) devices, organic light emitting display devices can be thinner and lighter because they do not require a separate backlight. In addition, organic light emitting display devices can consume less power due to low operating voltage characteristics, and can have excellent color reproduction, faster response speed, wider viewing angle, and higher contrast when compared to other types of display devices. Due to such excellent performance, work on developing such light emitting display devices that can provide various advantages as next-generation displays has been progressing.

[0007] In order to provide high resolution and high brightness, the number of pixels per unit area included in an organic light emitting display device has been increased. However, due to the light emitting structure of the organic light emitting display device, the amount of current that can flow through the unit area may be limited. In fact, the increase in applied current may cause the reliability of the organic light emitting display device to decrease and the power consumption of the organic light emitting display device to increase.

[0008] In order to solve this problem, various structures for improving the light emitting efficiency and lifespan of an organic light emitting display device and reducing power consumption have been proposed.

[0009] In an organic light emitting display device, each of a plurality of sub-pixels included in each pixel may include an organic light emitting element such as an organic light emitting diode and a pixel circuit, and each organic light emitting element may be independently driven by each pixel circuit to emit light.

[0010] However, since each organic light emitting element included in a plurality of sub-pixels includes an element intermediate layer, such an organic light emitting display device may suffer from leakage current, such as lateral current flowing between adjacent sub-pixels through the element intermediate layer. Such lateral current may be referred to as horizontal leakage current.

[0011] For example, when the sub-pixels of each pixel include a turn-on sub-pixel and a turn-off sub-pixel, as the current flowing in the turn-on sub-pixel leaks to the turn-off sub-pixel adjacent to the turn-on sub-pixel through the element intermediate layer, the brightness of the turn-on sub-pixel may decrease. Therefore, gray levels, especially low gray levels, may not be fully presented, or the brightness presented by the display panel may not be uniform over the entire display area of ​​the display panel. Summary of the invention

[0012] The present inventors have attempted to solve the problem of horizontal leakage current flowing between adjacent sub-pixels through an element intermediate layer in a structure in which each organic light emitting element included in a sub-pixel includes an element intermediate layer.

[0013] The inventors have invented a display panel and a display device capable of cutting off leakage current flowing between sub-pixels.

[0014] One or more aspects of the present disclosure may provide a display panel and a display device configured to have a narrow bezel structure.

[0015] One or more aspects of the present disclosure may provide a display panel and a display device having high transmittance.

[0016] One or more aspects of the present disclosure may provide a display panel and a display device configured with a structure in which a common electrode and a base voltage line are connected.

[0017] According to one or more example embodiments of the present disclosure, a display device may be provided, the display device comprising: a substrate comprising a display area and a non-display area outside the display area; a transistor disposed above the substrate; a base voltage line disposed above the substrate; a planarization layer disposed on the transistor and the base voltage line; a pixel electrode disposed on the planarization layer; a dam disposed on the pixel electrode and comprising an opening for exposing a portion of the pixel electrode; an element intermediate layer located on the pixel electrode through the opening of the dam in the light-emitting area and extending along the dam in the non-light-emitting area; a common electrode disposed on the element intermediate layer; and a linking area configured to electrically interconnect the base voltage line and the common electrode and disposed in the display area.

[0018] According to one or more example embodiments of the present disclosure, a display panel may be provided, the display panel comprising: a substrate comprising a display area and a non-display area outside the display area; a transistor disposed above the substrate; a base voltage line disposed above the substrate; a planarization layer disposed on the transistor and the base voltage line; a pixel electrode disposed on the planarization layer; a levee disposed on the pixel electrode and comprising an opening for exposing a portion of the pixel electrode; an element intermediate layer, which is located on the pixel electrode through the opening of the levee in the light-emitting area, extends along the levee in the non-light-emitting area, and comprises a hole formed on the levee; a common electrode disposed on the element intermediate layer; and a linking area configured to electrically interconnect the base voltage line and the common electrode through the hole in the element intermediate layer.

[0019] According to one or more aspects of the present disclosure, a display panel and a display device capable of cutting off leakage current flowing between sub-pixels may be provided.

[0020] According to one or more aspects of the present disclosure, a display panel and a display device configured to have a narrow bezel structure may be provided.

[0021] According to one or more aspects of the present disclosure, a display panel and a display device having high transmittance may be provided.

[0022] According to one or more aspects of the present disclosure, a display panel and a display device may be provided, which are configured with a structure in which a common electrode and a base voltage line are connected in a display area and thus can reduce a bezel.

[0023] According to one or more aspects of the present disclosure, a display panel and a display device can be provided, which can stably supply a basic voltage to a common electrode by applying an example structure in which a common electrode and a basic voltage line are connected. According to one or more aspects of the present disclosure, a display panel and a display device can be provided, which can reduce the resistance on a path through which a basic voltage is supplied and reduce power consumption, and thus facilitate driving with low power. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] Figure 1 An example system configuration of a display device according to aspects of the present disclosure is shown.

[0025] Figure 2 Example configurations of display panels according to aspects of the present disclosure are shown.

[0026] Figure 3 A vertical structure of an example display area of ​​a display panel according to aspects of the present disclosure is shown.

[0027] Figure 4 is an example plan view of a display area of ​​a display panel according to aspects of the present disclosure.

[0028] Figure 5 is a cross-sectional view of an example stacking configuration of a display panel according to aspects of the present disclosure.

[0029] Figure 6 is a cross-sectional view of an example stacking configuration of a display panel according to aspects of the present disclosure.

[0030] Figure 7 is a cross-sectional view of an example stacking configuration of a display panel according to aspects of the present disclosure.

[0031] Figure 8 is an example plan view of a display area of ​​a display panel according to aspects of the present disclosure. DETAILED DESCRIPTION

[0032] Reference will now be made in detail to example embodiments of the present disclosure, examples of which may be illustrated in the accompanying drawings.

[0033] In the following description, unless otherwise specified, the structures, embodiments, implementations, methods and operations described herein are not limited to one or more specific examples set forth herein and may be modified as known in the art. Unless otherwise specified, the same reference numerals always indicate the same elements. The names of the various elements used in the following description are selected only for the convenience of writing the present disclosure and may therefore be different from those used in the actual product. The advantages and features of the present disclosure and its implementation methods will be illustrated by the example implementations described below with reference to the accompanying drawings. However, the present disclosure may be implemented in different forms and should not be interpreted as being limited to the example implementations set forth herein. On the contrary, these example implementations are provided so that the present disclosure is sufficiently thorough and complete to help those skilled in the art fully understand the scope of the present disclosure. In addition, the scope of protection of the present disclosure is defined by the claims and their equivalents. In the following description, in the case where a detailed description of a related known function or configuration may unnecessarily obscure various aspects of the present disclosure, a detailed description of such a known function or configuration may be omitted. The shapes, sizes, ratios, angles, numbers, etc. of various exemplary implementations for describing the present disclosure shown in the accompanying drawings are given only as examples. Therefore, the present disclosure is not limited to the illustrations in the accompanying drawings. Where the terms “comprising,” “having,” “including,” “containing,” “consisting of,” “composed of,” “formed of,” etc. are used, one or more other elements may be added unless a term such as “only” is used. Elements described in the singular are intended to include plural elements and vice versa unless the context clearly indicates otherwise.

[0034] Although the terms "first", "second", A, B, (a), (b), etc. may be used herein to describe various elements, these elements should not be construed as being limited by these terms because they are not used to define a specific order or priority. These terms are only used to distinguish one element from another. For example, a first element may be referred to as a second element, and similarly, a second element may be referred to as a first element without departing from the scope of the present disclosure.

[0035] When it is mentioned that a first element is “connected or coupled to” a second element, “contacts or overlaps” the second element, etc., it should be understood that not only the first element can be “directly connected or coupled to” the second element, “directly contact or overlaps” the second element, but also a third element can be “inserted” between the first element and the second element, or the first element and the second element can be “connected or coupled to”, “contacts or overlaps”, etc., each other via a fourth element. Here, the second element can be included in at least one of the two or more elements that are “connected or coupled to”, “contacts or overlaps”, etc., each other.

[0036] In the case of describing a positional relationship, for example, when using "on", "above", "below", "above", "below", "beside", "near", etc. to describe the positional relationship between two parts, unless more restrictive terms such as "immediately", "directly", or "adjacent" are used, one or more other parts may be located between the two parts. For example, in the case where an element or layer is arranged "on" another element or layer, a third element or layer may be inserted therebetween. In addition, the terms "left", "right", "top", "bottom", "downward", "upward", "up", "down", etc. refer to an arbitrary reference system.

[0037] In addition, when referring to any dimension, relative size, etc., it should be considered that the numerical value or corresponding information (such as level, range, etc.) of the element or feature includes the tolerance or error range that may be caused by various factors (such as process factors, internal or external influences, noise, etc.), even if no relevant description is specified. In addition, the term "may" fully encompasses all meanings of the term "can".

[0038] Hereinafter, various exemplary embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.

[0039] Figure 1 The configuration of an example display device 100 according to aspects of the present disclosure is shown. All components of each display device according to all embodiments of the present disclosure are operably coupled and configured.

[0040] Reference Figure 1 In one or more example embodiments, the display device 100 may include a display panel 110 and a display driving circuit as components for displaying an image. The display driving circuit may be a circuit for driving the display panel 110, and includes a data driving circuit 120, a gate driving circuit 130, a display controller 140, and other circuit components.

[0041] The display panel 110 may include a substrate 111 and a plurality of sub-pixels SP disposed on the substrate 111 .

[0042] The substrate 111 of the display panel 110 may include a display area DA allowing an image to be displayed and a non-display area NDA located outside the display area DA.

[0043] In one or more aspects, the non-display area NDA of the display panel 110 may have a very small area compared to the display area DA. However, embodiments of the present disclosure are not limited thereto.

[0044] For example, the non-display area NDA may include a first non-display area located outside the display area DA in a first direction, a second non-display area located outside the display area DA in a second direction crossing the first direction, a third non-display area located outside the display area DA in a direction opposite to the first direction, and a fourth non-display area located outside the display area DA in a direction opposite to the second direction. One or two of the first to fourth non-display areas may include a pad area to which the data driving circuit 120 is connected or bonded. In one or more aspects, each of the remaining two or three non-display areas excluding the pad area in the first to fourth non-display areas may have a very small size compared to the one or two non-display areas.

[0045] In one or more aspects, a boundary area between the display area DA and the non-display area NDA may be curved, and thus, the non-display area NDA may be located below the display area DA. In this implementation, when a user views the display device 100 in front of the display device 100, all or most of the non-display area NDA may not be visible to the user.

[0046] Various types of signal lines for driving the plurality of sub-pixels SP may be disposed on the substrate 111 of the display panel 110 .

[0047] In one or more aspects, the display device 100 may be a liquid crystal display device, etc., or a self-luminous display device in which light is emitted from the display panel 110 itself. In an example in which the display device 100 according to aspects of the present disclosure is a self-luminous display device, each of the plurality of sub-pixels SP may include a light-emitting element. However, embodiments of the present disclosure are not limited thereto.

[0048] For example, the display device 100 according to various aspects of the present disclosure may be an organic light-emitting display device implemented using an organic light-emitting diode (OLED) as a light-emitting element. In another example, the display device 100 according to various aspects of the present disclosure may be an inorganic light-emitting display device implemented using a light-emitting diode based on an inorganic material as a light-emitting element. In yet another example, the display device 100 according to various aspects of the present disclosure may be a quantum dot display device implemented using quantum dots as self-luminous semiconductor crystals as light-emitting elements.

[0049] The structure of each sub-pixel SP among the plurality of sub-pixels SP may depend on the type of the display device 100. For example, when the display device 100 is a self-luminous display device including self-luminous sub-pixels SP, each sub-pixel SP may include a self-luminous light-emitting element, one or more transistors, and one or more capacitors. However, embodiments of the present disclosure are not limited thereto.

[0050] The various types of signal lines may include, for example, a plurality of data lines DL for carrying data signals (which may be referred to as data voltages or image signals), a plurality of gate lines GL for carrying gate signals (which may be referred to as scan signals), and the like.

[0051] In one or more aspects, a plurality of data lines DL and a plurality of gate lines GL may cross each other. For example, a plurality of data lines DL and a plurality of gate lines GL may cross each other at a predetermined angle. Each of the plurality of data lines DL may be configured to extend in a first direction, and each of the plurality of gate lines GL may be configured to extend in a second direction. For example, the first direction may be a column direction or a vertical direction, and the second direction may be a row direction or a horizontal direction. In another example, the first direction may be a row direction or a horizontal direction, and the second direction may be a column direction or a vertical direction. Hereinafter, for ease of explanation, a discussion may be provided based on an example in which each of the plurality of data lines DL is arranged in a column direction and each of the plurality of gate lines GL is arranged in a row direction, but example embodiments of the present disclosure are not limited thereto.

[0052] The data driving circuit 120 may be a circuit for driving the plurality of data lines DL, and may output data signals to the plurality of data lines DL.

[0053] The data driving circuit 120 may receive image data DATA in a digital form from the display controller 140 , convert the received image data DATA into a data signal in an analog form, and output the converted data signal to a plurality of data lines DL.

[0054] In one or more aspects, the data driving circuit 120 can be connected to the display panel 110 via tape automated bonding (TAB) technology, or connected to a conductive pad such as a bonding pad of the display panel 110 via chip on glass (COG) technology or chip on panel (COP) technology, or connected to the display panel 110 via chip on film (COF) technology.

[0055] The data driving circuit 120 may be located in only one side or portion (e.g., the upper edge or the lower edge) of the display panel 110 and / or electrically connected to only one side or portion (e.g., the upper edge or the lower edge) of the display panel 110, but is not limited thereto. In one or more aspects, according to a driving scheme, a panel design scheme, or other design requirements, the data driving circuit 120 may be disposed in and / or electrically connected to both sides or portions (e.g., the upper edge and the lower edge) of the display panel 110 or at least two sides or portions of the four sides or portions (e.g., the upper edge, the lower edge, the left edge, and the right edge) of the display panel 110, but is not limited thereto.

[0056] The data driving circuit 120 may be connected to the outside or edge of the display area DA of the display panel 110 , or disposed in the display area DA of the display panel 110 .

[0057] The gate driving circuit 130 may be a circuit for driving a plurality of gate lines GL, and may output gate signals to the plurality of gate lines GL. The gate driving circuit 130 may receive various types of gate driving control signals GCS, and may also receive a first gate voltage corresponding to an on-level voltage and a second gate voltage corresponding to an off-level voltage. Therefore, the gate driving circuit 130 may generate a gate signal, and supply the generated gate signal to the plurality of gate lines GL.

[0058] In one or more aspects, the gate driving circuit 130 included in the display device 100 may be embedded in the display panel 110 through a gate-in-panel (GIP) technology. In an example where the gate driving circuit 130 is implemented through a gate-in-panel (GIP) technology, the gate driving circuit 130 may be disposed on a substrate 111 of the display panel 110 during a manufacturing process of the display panel 110 or the display device 100. In one aspect, the gate driving circuit 130 included in the display device 100 may be disposed in a display area DA of the display panel 110. In this implementation, for example, the gate driving circuit 130 may be disposed in a first area (e.g., a left area or a right area of ​​the display area DA) of the display panel 110 and / or electrically connected to the first area (e.g., a left area or a right area of ​​the display area DA) of the display panel 110, but is not limited thereto. In another example, the gate driving circuit 130 can be disposed in a first area (e.g., a left area or a right area of ​​the display area DA) and a second area (e.g., a right area or a left area of ​​the display area DA) of the display area DA of the display panel 110 and / or electrically connected to the first area (e.g., a left area or a right area of ​​the display area DA) and a second area (e.g., a right area or a left area of ​​the display area DA) of the display panel 110, but is not limited thereto.

[0059] Herein, the gate driving circuit 130 embedded in the display panel 110 using the gate-in-panel (GIP) technology may also be referred to as a “gate-in-panel circuit”.

[0060] The display controller 140 may be a device for controlling the data driving circuit 120 and the gate driving circuit 130 , and may control a driving timing of a plurality of data lines DL and a driving timing of a plurality of gate lines GL.

[0061] The display controller 140 may supply the data driving control signal DCS to the data driving circuit 120 to control the data driving circuit 120 , and supply the gate driving control signal GCS to the gate driving circuit 130 to control the gate driving circuit 130 .

[0062] The display controller 140 may receive image data input from the host system 150 and supply image data DATA, which may be read by the data driving circuit 120 , to the data driving circuit 120 based on the input image data.

[0063] The display controller 140 may be implemented as a separate component from the data driving circuit 120 , or incorporated in the data driving circuit 120 , and thus implemented in an integrated circuit.

[0064] The display controller 140 may be a timing controller used in a typical display technology, or a controller or control device capable of performing other control functions in addition to the functions of a typical timing controller. In one or more embodiments, the display controller 140 may be a controller or control device different from a timing controller, or a circuit system or component included in a controller or control device. The display controller 140 may be implemented using various circuits or electronic components such as an integrated circuit (IC), a field programmable gate array (FPGA), an application specific integrated circuit (ASIC), a processor, etc. However, the embodiments of the present disclosure are not limited thereto.

[0065] The display controller 140 may be mounted on a printed circuit board, a flexible printed circuit, or the like, and electrically connected to the gate driving circuit 120 and the data driving circuit 130 through the printed circuit board, the flexible printed circuit, or the like.

[0066] The display controller 140 may send signals to the data driving circuit 120 and receive signals from the data driving circuit 120 via one or more predefined interfaces. For example, such interfaces may include a low voltage differential signaling (LVDS) interface, an embedded clock point-to-point interface (EPI), a serial peripheral interface (SPI), etc. However, example embodiments of the present disclosure are not limited thereto.

[0067] In one or more aspects, in order to provide a touch sensing function as well as an image display function, the display device 100 may include a touch sensor and a touch sensing circuit configured to sense the touch sensor and detect whether the touch is applied by an object such as a finger, a pen, etc. or detect the position of the touch.

[0068] The touch sensing circuit may include: a touch driving circuit configured to drive and sense the touch sensor and generate and output touch sensing data; and a touch controller capable of detecting whether a touch is applied or detecting a position of a touch using the touch sensing data.

[0069] The touch sensor may include a plurality of touch electrodes and may further include a plurality of touch wires for electrically connecting the plurality of touch electrodes to a touch driving circuit.

[0070] The touch sensor may be implemented in the form of a touch panel outside the display panel 110, or may be integrated inside the display panel 110. In an example where the touch sensor is implemented in the form of a touch panel outside the display panel 110, such a touch sensor may be referred to as an add-on type. In an example where an add-on type touch sensor is provided in the display device 100, the touch panel and the display panel 110 may be manufactured separately and combined during assembly.

[0071] The add-on type touch panel may include a touch panel substrate and a plurality of touch electrodes disposed on the touch panel substrate.

[0072] In an example where the touch sensor is disposed inside the display panel 110 , the touch sensor may be formed on a substrate together with signal lines and electrodes related to display driving during a manufacturing process of the display panel 110 .

[0073] The touch driving circuit may supply a touch driving signal to at least one of the plurality of touch electrodes and generate touch sensing data by sensing at least one of the plurality of touch electrodes.

[0074] The touch sensing circuit may perform touch sensing through self-capacitance sensing technology or mutual capacitance sensing technology.

[0075] In an example where the touch sensing circuit performs touch sensing by self-capacitance sensing technology, the touch sensing circuit may perform touch sensing based on the capacitance between each touch electrode and a touch object (e.g., a finger, a pen, etc.). According to the self-capacitance sensing technology, each of the plurality of touch electrodes may be used as both a driving touch electrode and a sensing touch electrode. The touch drive circuit may drive all or one or more of the plurality of touch electrodes, and sense all or one or more of the plurality of touch electrodes.

[0076] In an example where the touch sensing circuit performs touch sensing through mutual capacitance sensing technology, the touch sensing circuit may perform touch sensing based on the capacitance between touch electrodes. According to the mutual capacitance sensing technology, a plurality of touch electrodes may be divided into driving touch electrodes and sensing touch electrodes. The touch driving circuit may drive the driving touch electrodes and sense the sensing touch electrodes.

[0077] In one or more aspects, the touch driving circuit and the touch controller included in the touch sensing circuit may be implemented in separate devices or may be implemented in a single device. In one or more aspects, the touch driving circuit and the data driving circuit may be implemented in separate devices or may be implemented in a single device.

[0078] The display device 100 may also include a power supply circuit for supplying various types of power to the display drive circuit and / or the touch sensing circuit. In one or more aspects, the display device 100 may represent but is not limited to a mobile terminal (e.g., a smart phone, a tablet computer, etc.), a monitor, a television (TV), etc. The example embodiments of the present disclosure are not limited thereto. In one or more aspects, the display device 100 may be a display device or include displays of various types, sizes, and shapes for displaying information or images.

[0079] In one or more example embodiments, the display device 100 may further include an electronic device, such as a camera (e.g., an image sensor), a sensor capable of detecting an object, etc. For example, the sensor may be a sensor capable of detecting an object or a human body by receiving light such as infrared light, ultrasonic light, ultraviolet light, etc. However, embodiments of the present disclosure are not limited thereto.

[0080] Figure 2 An example configuration of the display panel 110 according to aspects of the present disclosure is shown.

[0081] Reference Figure 2 , the display panel 110 may include a substrate 111 on which a plurality of sub-pixels SP are disposed and an encapsulation layer 220 over the substrate 111. The encapsulation layer 220 may also be referred to as an encapsulation substrate or an encapsulation stack.

[0082] Reference Figure 2 In an example where the display device 100 is a self-luminous display device, each of the plurality of sub-pixels SP disposed on the substrate 111 may include a light emitting element ED and a sub-pixel circuit SPC for driving the light emitting element ED.

[0083] Reference Figure 2 , the sub-pixel circuit SPC may include a plurality of pixel driving transistors for driving the light emitting element ED and at least one capacitor.

[0084] The sub-pixel circuit SPC may drive the light emitting element ED by supplying a driving current to the light emitting element ED at a predetermined time. The light emitting element ED may emit light by being driven by the driving current.

[0085] The plurality of pixel driving transistors may include a driving transistor DT for driving the light emitting element ED and a scanning transistor ST configured to be turned on or off by a scanning signal SC. The scanning transistor ST may be configured to control the electrical state of a corresponding node in the sub-pixel circuit SPC or control the state or operation of the driving transistor DT.

[0086] The at least one capacitor may include a storage capacitor Cst configured to maintain a constant voltage during a display frame or a specific period of the display frame.

[0087] In order to drive one or more sub-pixels SP, at least one data signal VDATA as an image signal and at least one scan signal SC as a gate signal may be applied to the one or more sub-pixels SP. In addition, at least one common pixel driving voltage including a first driving voltage VDD and a second driving voltage VSS may be applied to the one or more sub-pixels SP.

[0088] The light emitting element ED may include a pixel electrode AND, an element intermediate layer EL, and a common electrode CAT. The element intermediate layer EL may be disposed between the pixel electrode AND and the common electrode CAT, and include an emission layer EML.

[0089] In an example where the light emitting element ED is an organic light emitting diode, the element intermediate layer EL may include an emission layer EML, a first common layer COM1 between the pixel electrode AND and the emission layer EML, and a second common layer COM2 between the emission layer EML and the common electrode. The emission layer EML may be disposed in each sub-pixel SP. The first common layer COM1 and the second common layer COM2 may be commonly disposed across all or some of the plurality of sub-pixels SP. The emission layer EML may be disposed in each sub-pixel SP, and the first common layer COM1 and the second common layer COM2 may be commonly disposed across a plurality of light emitting regions and non-light emitting regions.

[0090] For example, the first common layer COM1 may include a hole injection layer (HIL) and a hole transport layer (HTL), and the second common layer COM2 may include an electron transport layer (ETL) and an electron injection layer (EIL). The hole injection layer may inject holes from the pixel electrode AND into the hole transport layer, the hole transport layer may transport holes to the emission layer EML, the electron injection layer may inject electrons from the common electrode CAT into the electron transport layer, and the electron transport layer may transport electrons to the emission layer EML.

[0091] For example, the common electrode CAT may be electrically connected to a second driving voltage line VSSL. A second driving voltage VSS, which is one kind of common pixel driving voltage, may be applied to the common electrode CAT through the second driving voltage line VSSL.

[0092] The pixel electrode AND may be electrically connected to the first node N1 of the corresponding driving transistor DT of each sub-pixel SP. Herein, the second driving voltage VSS may also be referred to as a "base voltage", and the second driving voltage line VSSL may also be referred to as a "base voltage line".

[0093] For example, the pixel electrode AND may be an anode electrode disposed in each sub-pixel SP, and the common electrode CAT may be a cathode electrode commonly disposed in a plurality of sub-pixels SP. In another example, the common electrode CAT may be an anode electrode disposed in each sub-pixel SP, and the pixel electrode AND may be a cathode electrode commonly disposed in a plurality of sub-pixels SP. Hereinafter, for ease of explanation, a discussion may be provided based on an example in which the pixel electrode AND is an anode electrode and the common electrode CAT is a cathode electrode.

[0094] Each light emitting element ED may be configured by respective portions of a corresponding pixel electrode AND, a corresponding portion of the element intermediate layer EL, and a corresponding portion of the common electrode CAT overlapping each other. A corresponding light emitting region may be formed by each light emitting element ED. For example, a corresponding light emitting region of each light emitting element ED may include a region where a corresponding pixel electrode AND, a corresponding portion of the element intermediate layer EL, and a corresponding portion of the common electrode CAT overlap each other.

[0095] In one or more aspects, the light emitting element ED may be an organic light emitting diode (OLED), an inorganic material-based light emitting diode (LED), or a quantum dot light emitting element. For example, when the light emitting element ED is an organic light emitting diode OLED, the element intermediate layer EL of the light emitting element ED may be an organic element intermediate layer including an organic material. However, the embodiments of the present disclosure are not limited thereto.

[0096] The driving transistor DT may be a transistor configured to supply a driving current to the light emitting element ED. The driving transistor DT may be connected between the first driving voltage line VDDL and the light emitting element ED.

[0097] The driving transistor DT may include a first node N1 electrically connected to the light emitting element ED, a second node N2 to which the data signal VDATA is applied, and a third node N3 to which a driving voltage VDD is applied from a driving voltage line DVL (eg, a first driving voltage line VDDL).

[0098] In the driving transistor DT, the second node N2 may be a gate node, the first node N1 may be a source node or a drain node, and the third node N3 may be a drain node or a source node. Hereinafter, for ease of explanation only, a discussion may be provided based on an example in which the first node N1, the second node N2, and the third node N3 of the driving transistor DT are a source node, a gate node, and a drain node, respectively. However, embodiments of the present disclosure are not limited thereto.

[0099] Figure 2 The scan transistor ST included in the illustrated sub-pixel circuit SPC may be a switching transistor for allowing the data signal VDATA, which is an image signal, to be supplied to the second node N2, which is a gate node of the driving transistor DT.

[0100] The scan transistor ST may be turned on or off by a scan signal SC as a gate signal applied through a scan line SCL as a gate line GL, and controls electrical connection between the second node N2 of the driving transistor DT and the data line DL.

[0101] A drain electrode or a source electrode of the scan transistor ST may be electrically connected to the data line DL. A source electrode or a drain electrode of the scan transistor ST may be electrically connected to the second node N2 of the drive transistor DT. A gate electrode of the scan transistor ST may be electrically connected to the scan line SCL.

[0102] The storage capacitor Cst may be electrically connected between the first node N1 and the second node N2 of the driving transistor DT. The storage capacitor Cst may include: a first capacitor electrode electrically connected to the first node N1 of the driving transistor DT or corresponding to the first node N1 of the driving transistor DT; and a second capacitor electrode electrically connected to the second node N2 of the driving transistor DT or corresponding to the second node N2 of the driving transistor DT.

[0103] In one or more aspects, the storage capacitor Cst that may exist between the first node N1 and the second node N2 of the driving transistor DT may be an external capacitor that is intentionally configured or designed to be located outside the driving transistor DT, rather than an internal capacitor such as a parasitic capacitor (e.g., a gate-source capacitance Cgs, a gate-drain capacitance Cgd, etc.).

[0104] Each of the driving transistor DT and the scanning transistor ST may be an n-type transistor or a p-type transistor.

[0105] For example, at least a portion of the sub-pixel circuit SPC may overlap at least a portion of the light emitting element ED in the vertical direction. In another example, the sub-pixel circuit SPC may not overlap the light emitting element ED in the vertical direction. However, embodiments of the present disclosure are not limited thereto.

[0106] like Figure 2 As shown, the sub-pixel circuit SPC may include two transistors (2T: DT and ST) and a capacitor (1C: Cst) (which may be referred to as a "2T1C structure"), and in some implementations, may also include one or more transistors, or may also include one or more capacitors.

[0107] For example, the sub-pixel circuit SPC may have an 8T1C structure including 8 transistors and 1 capacitor. In another example, the sub-pixel circuit SPC may have a 6T2C structure including 6 transistors and 2 capacitors. In yet another example, the sub-pixel circuit SPC may have a 7T1C structure including 7 transistors and 1 capacitor.

[0108] The type and number of gate signals supplied to the sub-pixel SP and / or the type and number of gate lines connected to the sub-pixel SP may vary according to the structure of the corresponding sub-pixel circuit SPC.

[0109] In addition, the type and number of common pixel driving voltages supplied to the sub-pixels SP may vary according to the structure of the corresponding sub-pixel circuit SPC.

[0110] Since the circuit element (e.g., the light emitting element ED such as an organic light emitting diode (OLED) including an organic material) in each sub-pixel SP is susceptible to external moisture or oxygen, the encapsulation layer 220 may be provided in the display panel 110 to prevent external moisture or oxygen from penetrating into the circuit element (e.g., the light emitting element ED). The encapsulation layer 220 may be provided in various shapes or configurations to prevent the light emitting element ED from contacting moisture or oxygen.

[0111] In one or more aspects, the display panel 110 may have a top emission structure or a bottom emission structure.

[0112] In one or more aspects, the display device 100 may have an extremely narrow bezel structure in which the non-display area NDA of the display panel 110 is very small or almost non-existent.

[0113] Figure 3 and Figure 4 A vertical structure and a structure in a plan view of an example display region of the display panel 110 according to aspects of the present disclosure are shown.

[0114] Reference Figure 3 In one or more example embodiments, the display panel 110 may include a substrate 1000, a base voltage line (VSSL, 200), a link region LA, a common electrode 500, etc. It should be noted that Figure 3 In the figure, for the convenience of explanation, other elements included in the display panel 110 are omitted.

[0115] Reference Figure 3 The link area LA may exist in a vertical direction from the base voltage line (VSSL, 200) to the common electrode 500. For example, the link area LA may electrically interconnect the base voltage line (VSSL, 200) and the common electrode 500 through at least one electrode in at least one layer formed between the base voltage line (VSSL, 200) and the common electrode 500. In various embodiments of the present disclosure, the display area DA may include one or more link areas LA and one or more light-emitting areas Lea. The display area DA may be inserted between opposite non-display areas NDA, wherein the link area LA and the light-emitting areas Lea may be arranged sequentially and / or alternately in one or more directions.

[0116] Reference Figure 4In the plan view, the link area LA may be arranged in the form of running between the plurality of light emitting elements 10, 11, 12, 13, 14, 15, 16 and 17 in the display area DA in the first direction and the second direction. It should be noted that Figure 4 An example connection structure of the link area LA is shown, but the example implementation of the present disclosure is not limited thereto. Figure 8 As shown, the link area LA may be disposed between some of the plurality of light emitting elements 10, 11, 12, 13, 14, 15, 16, and 17, but not between all of the plurality of light emitting elements 10, 11, 12, 13, 14, 15, 16, and 17. One or more regions where the link area LA is not disposed between the light emitting elements may be referred to as non-link areas NLA1, NLA2, and NLA3. Each light emitting element may be connected to a corresponding adjacent portion of the link area LA in the vertical structure. Figure 4 , R represents red, G represents green, and B represents blue.

[0117] Reference Figure 4 In a plan view of the display area DA, the link area LA may be arranged in a matrix shape, wherein the link area LA or its extension may extend in at least one of a first direction and a second direction, wherein the first direction and the second direction intersect. When the link area LA is arranged in a matrix shape, one or more of the plurality of light emitting elements may be surrounded by the link area LA (see light emitting elements 13 and 14) or may be partially surrounded by the link area (see light emitting elements 10, 11, 12, 15, 16, and 17), so that one or more sides of the light emitting element may be open, but other sides of the light emitting element are surrounded. In addition, the arrangement of the link area LA may be symmetrical in the display area DA.

[0118] In various embodiments of the present disclosure, the link area LA may include the second auxiliary electrode 420, the bridge electrode 310 and / or the first auxiliary electrode, or one or more portions thereof. Therefore, the link area LA may also be referred to as a link area structure.

[0119] Figure 5 and Figure 6 is a cross-sectional view illustrating an example stacking configuration of a display panel 110 according to aspects of the present disclosure. Figure 5 It is along Figure 4 A cross-sectional view taken along line AA'.

[0120] Reference Figure 5 In one or more example embodiments, the display panel 110 may include a display area DA and a non-display area NDA. The display area DA may be located between portions of the non-display area NDA.

[0121] Reference Figure 5 , the display panel 110 may include a substrate 1100 , a double polyimide (PI) substrate 1200 , a base circuit layer 1300 , a planarization layer 1400 , a bank 300 , an element intermediate layer 400 , a common electrode 500 , and a link area LA.

[0122] The substrate 1100 may include a display area DA and a non-display area NDA.

[0123] The substrate 1100 may include glass, and may be removed after a process of manufacturing the display panel 110 is completed.

[0124] The double PI substrate 1200 may include a flexible plastic material, such as polyimide (PI). However, the embodiments of the present disclosure are not limited thereto. When the double PI substrate 1200 is configured with a polyimide layer, moisture may penetrate into the substrate configured with the polyimide (PI) layer and affect the thin film transistor or light emitting element located on the substrate.

[0125] To prevent this, the double PI substrate 1200 may have a stack of two base layers, and a silicon oxide (SiOx) layer having excellent moisture permeability may be disposed between the two base layers. The silicon oxide (SiOx) layer may prevent moisture from entering the lower base layer of the double PI substrate 1200, and may improve the performance and reliability of the display panel 110. However, embodiments of the present disclosure are not limited thereto, and other materials may be used.

[0126] like Figure 5 and Figure 6 As shown, the double PI substrate 1200 may be configured with two base layers including a polyimide material, and may further include an intermediate layer including a material such as silicon oxide or an inorganic material between the two layers.

[0127] The basic circuit layer 1300 may be disposed on the double PI substrate 1200 and may include a thin film transistor (TFT) or the like disposed in the display area DA.

[0128] The planarization layer 1400 may be configured to have a flat surface on the transistors disposed on the substrate 1100. Each transistor may be an n-type transistor or a p-type transistor. The planarization layer 1400 may include an insulating material, and may be an inorganic layer or an organic layer.

[0129] The bank 300 may be disposed on the planarization layer 1400 and may define the emission area EA and the non-emission area of ​​each sub-pixel in the display area DA. Figure 5The bank 300 can define a portion in the display region where the light emitting layer is disposed between the pixel electrode and the common electrode as a light emitting region, and define a portion in the display region where the light emitting layer is not disposed between the pixel electrode and the common electrode as a non-light emitting region.

[0130] For example, the bank 300 may be disposed on the pixel electrode, and may include an opening exposing a portion of the pixel electrode.

[0131] The element intermediate layer 400 may be disposed on the pixel electrode and include a first common layer extending to the top of the bank 300, an emission layer disposed on the first common layer, and a second common layer disposed on the emission layer and extending along the first common layer, wherein the first common layer extends to the top of the bank. A hole may be formed in the first common layer and the second common layer on the top of the bank, and the link region may electrically interconnect the common electrode 500 and the base voltage line VSSL through the hole.

[0132] Reference Figure 5 and Figure 6 , the two pixel electrodes 320 and 330 and the bridge electrode 310 disposed on the planarization layer 1400 may be insulated from each other by the bank 300 .

[0133] Figure 6 A cross-sectional view of an example portion of the display area DA shows light emitting areas (EA(B) and EA(G)) located on both sides and a non-light emitting area as a remaining area except the light emitting areas (EA(B) and EA(G)). The link area LA may be disposed in the non-light emitting area of ​​the display area DA.

[0134] The light emitting region may be defined by an opening on the bank. The opening of the bank 300 may correspond to the light emitting region. The bank may also be referred to as a light emitting portion defining layer.

[0135] Reference Figure 5 and Figure 6 , the bank 300 may be located on the pixel electrodes 320 and 330, and may include an opening exposing portions of the pixel electrodes 320 and 330. The opening of the bank 300 may correspond to a light emitting region.

[0136] The display panel 110 may include a link area LA configured to electrically interconnect the common electrode 500 (eg, cathode) and the base voltage line VSSL in the display area DA.

[0137] Reference Figure 5 , the link area LA may include at least one first auxiliary electrode 210 located below the planarization layer 1400 and a second auxiliary electrode 420 located on the bank 300 and electrically interconnecting the common electrode 500 and the first auxiliary electrode 210 .

[0138] The second auxiliary electrode 420 may electrically interconnect the common electrode 500 and the first auxiliary electrode 210 through a hole. The first auxiliary electrode 210 may be a base voltage line VSSL or an electrode electrically connected to the base voltage line VSSL. The link region LA may further include at least one bridge electrode 310 for electrically interconnecting the first auxiliary electrode 210 and the second auxiliary electrode 420. The bridge electrode 310 may be located between the planarization layer 1400 and the bank 300. The bridge electrode 310 may include the same material as the pixel electrode.

[0139] The first auxiliary electrode 210 may include the same material as that included in a source electrode or a drain electrode of a transistor, or may include the same material as that included in an electrode electrically connected to the source electrode or the drain electrode of the transistor.

[0140] Reference Figure 5 The common electrode 500 may be electrically connected to the second auxiliary electrode 420 through the hole of the element intermediate layer EL, the second auxiliary electrode 420 may be electrically connected to the bridge electrode 310 through the hole H1 of the bank 300 , and the bridge electrode 310 may be electrically connected to the first auxiliary electrode 210 through the hole H2 of the planarization layer 1400 .

[0141] The second auxiliary electrode 420 connected to the common electrode 500 may be disposed in a region where a portion of the element intermediate layer 400 is removed based on a sub-pixel. For example, the second auxiliary electrode 420 may be disposed inside the hole. For example, the second auxiliary electrode 420 may contact one or more side portions of the hole H1. However, embodiments of the present disclosure are not limited thereto.

[0142] Reference Figure 5 , the vertical arrangement of the holes H1 and H2 may be offset so that the holes H1 and H2 are not vertically aligned. However, the embodiments of the present disclosure are not limited thereto, and in other embodiments, the holes H1 and H2 may be vertically aligned. In this regard, the first auxiliary electrode 210, the bridge electrode 310, and the second auxiliary electrode 420 may also be aligned, or may not overlap each other, or may not overlap one or more of the holes H1 and H2.

[0143] like Figure 5 As shown, the second auxiliary electrode 420 may be disposed on side surfaces of the first common layer COM1 and the second common layer COM2.

[0144] For example, the second auxiliary electrode 420 may contact side surfaces of the first common layer COM1 and the second common layer COM2 .

[0145] In another example, if Figure 6 As shown, the second auxiliary electrode 420 may be spaced apart from side surfaces of the first common layer COM1 and the second common layer COM2.

[0146] The common electrode 500 may be disposed on the link area LA. The common electrode 500 may be in the form of a surface electrode. The common electrode 500 may be configured with a transparent electrode.

[0147] The link area LA may be disposed to be spaced apart from a region in the display area DA where the light emitting element ED is formed. The link area LA may be commonly connected to the common electrode 500 together with the light emitting element ED.

[0148] The link area LA may include a material having a higher resistivity than that of the common electrode 500 .

[0149] At least one first auxiliary electrode 210 , at least one bridge electrode 310 , and at least one second auxiliary electrode 420 may be arranged in a vertical direction to be electrically connected to each other.

[0150] The first auxiliary electrode 210 may be a basic voltage line VSSL to which the basic voltage VSS is applied, or may be an electrode connected to the basic voltage line VSSL.

[0151] Reference Figure 2 , the display panel 110 may further include a plurality of sub-pixels SP, and each of the plurality of sub-pixels may include a light-emitting element and one or more transistors. Each light-emitting element may be configured by overlapping a pixel electrode, an element intermediate layer, and a common electrode. The linking area LA may be located between a light-emitting area of ​​a first sub-pixel and a light-emitting area of ​​a second sub-pixel in the plurality of sub-pixels.

[0152] As described above, in one or more aspects, one or more portions of the element intermediate layer 400 disposed adjacent to the sub-pixel can be removed by a laser process. Therefore, the current path in the element intermediate layer 400 can be cut off, which prevents leakage current. By applying this configuration, damage caused by leakage current between different sub-pixels can be prevented. By cutting off the leakage current between sub-pixels, an OLED panel with high efficiency and reduced power consumption can be achieved.

[0153] Reference Figure 5 and Figure 6 Since the link area LA is provided so that two or more auxiliary electrodes (i.e., the first auxiliary electrode 210 and the second auxiliary electrode 420, or the first auxiliary electrode 210 and the second auxiliary electrode 420 and the bridge electrode 310) are directly in contact with and connected to the common electrode 500, the common electrode contact area may not be provided in the bezel area of ​​the display panel 110. Therefore, the bezel area may be reduced by about 200 μm, and a narrow bezel may be achieved.

[0154] Meanwhile, there is a trade-off between the resistance and transmittance of the metal of the common electrode 500 provided in the display panel 110. In an example where an element is connected to the common electrode 500 in the display panel 110 configured with a top emission structure, as the metal thickness of the common electrode 500 increases, the corresponding resistance may decrease, and thus the IR rise phenomenon may be improved. On the contrary, as the metal thickness of the common electrode 500 increases, the transmittance of the display panel may decrease.

[0155] To solve this problem, since the link area LA configured with two or more auxiliary electrodes (i.e., the first auxiliary electrode 210 and the second auxiliary electrode 420, or the first auxiliary electrode 210 and the second auxiliary electrode 420 and the bridge electrode 310) is connected to the lower portion of the common electrode 500, the display panel can provide an advantage of increasing the sheet resistance of the common electrode 500. Therefore, the thickness of the common electrode 500 can be reduced relative to the increased resistance, and the transmittance of the display panel 110 can be increased.

[0156] Reference Figure 4 , since the link area LA is provided in the form of a line in a plan view, this implementation can be applied to a display panel 110 configured to have a large area. Therefore, since the thickness of the common electrode in the display panel 110 having such a large area can be reduced, this implementation can help improve the transmittance of the display panel 110.

[0157] Return to reference Figure 5 In an example embodiment, the second auxiliary electrode 420 may be formed in a portion of the element intermediate layer 400 removed by a laser process and formed in or on an upper portion of the embankment 300 , and thus, a side surface of the second auxiliary electrode 420 may contact the element intermediate layer EL.

[0158] Reference Figure 6In one example embodiment, after removing a portion of the element intermediate layer 400 by a laser lift-off process, the second auxiliary electrode 420 may be formed in a portion of the element intermediate layer 400 and in or on an upper portion of the bank 300, and therefore, the side surface of the second auxiliary electrode 420 may not contact the element intermediate layer EL. For example, the second auxiliary electrode 420 and each element intermediate layer EL may be spaced apart from each other. In this implementation, a trench T may be formed between the second auxiliary electrode 420 and each element intermediate layer EL, but embodiments of the present disclosure are not limited thereto, and, for example, a non-conductive material may be positioned between the second auxiliary electrode 420 and each element intermediate layer EL to fill the trench T. In various embodiments of the present disclosure, the size or width of the trench T may be substantially the same as the hole H2, but embodiments of the present disclosure are not limited thereto, and the size or width of the trench T may be different from the size or width of the hole H2. In other embodiments of the present disclosure, the total size or width of the trench and the second auxiliary electrode 420 may be substantially equal to or less than the total size or width of the bridge electrode 310, but embodiments of the present disclosure are not limited thereto.

[0159] For example, the second auxiliary electrode 420 may be formed using a photolithography mask having better tolerance than laser processing.

[0160] In addition, since the second auxiliary electrode 420 and each element intermediate layer EL are spaced apart to be insulated from each other, leakage current can be effectively cut off, and noise generation can be eliminated or reduced.

[0161] Figure 7 is a cross-sectional view of an example stacking configuration of a display panel 110 according to aspects of the present disclosure. Figure 7 The components shown have Figure 5 and Figure 6 Some elements shown with the same reference numerals may be the same elements or have the same function.

[0162] Reference Figure 7 In one or more example embodiments, the display panel 110 may include a substrate 1100, a double PI substrate 1200, a base circuit layer 1300, a planarization layer 1400, a bank 300, an element intermediate layer EL, a common electrode 500, and a link area LA.

[0163] The substrate 1100 may include a display area DA and a non-display area NDA.

[0164] The substrate 1100 may include glass, and may be removed after a process of manufacturing the display panel 110 is completed.

[0165] The double PI substrate 1200 may include a flexible plastic material, such as polyimide (PI). However, the embodiments of the present disclosure are not limited thereto. When the double PI substrate 1200 is configured with a polyimide layer, moisture may penetrate into the substrate configured with the polyimide (PI) layer and affect the thin film transistor or light emitting element located on the substrate.

[0166] To prevent this, the double PI substrate 1200 may have a stack of two base layers, and a silicon oxide (SiOx) layer having excellent moisture permeability may be disposed between the two base layers. The silicon oxide (SiOx) layer may prevent moisture from entering the lower base layer of the double PI substrate 1200, and may improve the performance and reliability of the display device 100 or the display panel 110. However, embodiments of the present disclosure are not limited thereto, and other materials may be used.

[0167] like Figure 7 As shown, the double PI substrate 1200 may be configured with two base layers including a polyimide material, and may further include an intermediate layer including a material such as silicon oxide or an inorganic material between the two layers.

[0168] The basic circuit layer 1300 may be disposed on the double PI substrate 1200 and may include a thin film transistor (TFT) or the like disposed in the display area DA.

[0169] The planarization layer 1400 may be configured to have a flat surface on the transistors disposed on the substrate 1100. Each transistor may be an n-type transistor or a p-type transistor. The planarization layer 1400 may include an insulating material, and may be an inorganic layer or an organic layer.

[0170] The bank 300 may be disposed on the planarization layer 1400 and may define a light emitting area EA and a non-light emitting area in the display area DA. The bank 300 may define a portion in the display area where the light emitting layer is disposed between the pixel electrode and the common electrode as the light emitting area, and define a portion in the display area where the light emitting layer is not disposed between the pixel electrode and the common electrode as the non-light emitting area.

[0171] The two pixel electrodes 320 and 330 and the bridge electrode 310 disposed on the planarization layer 1400 may be insulated from each other by the bank 300 .

[0172] For example, the light emitting region may be defined by an opening on the bank. The opening of the bank 300 may correspond to the light emitting region. The bank may also be referred to as a light emitting portion defining layer.

[0173] The bank 300 may be located on the planarization layer 1400, and may have an opening exposing a portion of each pixel electrode 320. The opening of the bank 300 may correspond to a light emitting region.

[0174] The display panel 110 may include a second link area LA′ configured to interconnect the common electrode 500 (eg, cathode) in the display area DA and the base voltage line VSSL.

[0175] Reference Figure 7 , the second link region LA' may include at least one first auxiliary electrode 210 located below the planarization layer 1400, and at least one hole electrode 610 located on the bank 300 and electrically interconnecting the common electrode 500 and the first auxiliary electrode 210, or one or more portions thereof. The second link region LA' may also be referred to as a link region structure.

[0176] Reference Figure 7 , the hole electrode 610 may be formed such that the common electrode 500 extends into the hole formed in the corresponding portions of the element intermediate layer EL and the bank 300 .

[0177] The hole electrode 610 may electrically interconnect the common electrode 500 and the first auxiliary electrode 210 through the hole.

[0178] The second link region LA' may further include at least one bridge electrode 310 for electrically interconnecting the at least one first auxiliary electrode 210 and the at least one hole electrode 610. The bridge electrode 310 may be located between the planarization layer 1400 and the bank 300. The bridge electrode 310 may include the same material as the pixel electrode.

[0179] The first auxiliary electrode 210 may include the same material as that included in a source electrode or a drain electrode of a transistor, or may include the same material as that included in an electrode electrically connected to the source electrode or the drain electrode of the transistor.

[0180] The hole electrode 610 may be electrically connected to the bridge electrode 310 through holes formed in corresponding portions of the element intermediate layer EL and the bank 300 , and the bridge electrode 310 may be connected to the first auxiliary electrode 210 through the hole of the planarization layer 1400 .

[0181] The common electrode 500 may be disposed on the second link area LA'. The common electrode 500 may be in the form of a surface electrode. The common electrode 500 may be configured with a transparent electrode.

[0182] The second link area LA′ may be disposed to be spaced apart from a region in the display area DA where the light emitting element ED is formed.

[0183] The second link area LA′ may include a material having a higher resistivity than that of the common electrode 500 .

[0184] At least one first auxiliary electrode 210 , at least one bridge electrode 310 , and at least one hole electrode 610 may be arranged in a vertical direction to be electrically connected to each other.

[0185] The first auxiliary electrode 210 may be a basic voltage line VSSL to which the basic voltage VSS is applied, or may be an electrode connected to the basic voltage line VSSL.

[0186] In an example where the display panel 110 is configured with a top emission structure, a transparent electrode may be used as the common electrode 500, and the resistance of the transparent electrode may be greater than that of a typical metal. Figure 7 The transparent electrode 610 is even formed inside the hole compared to the structure using Figure 5 and Figure 6 The structure in which the second auxiliary electrode 420 is connected disclosed in the embodiment of the present invention can maximize the reduction in the resistance of the auxiliary electrode.

[0187] In addition, due to Figure 5 and Figure 6 The auxiliary electrode in the embodiment has a structure in which the first auxiliary electrode and the second auxiliary electrode are arranged in parallel with each other, so Figure 7 Compared with the structure including only the first auxiliary electrode, Figure 5 and Figure 6 The configuration including the two auxiliary electrodes 210 and 420 may have reduced resistance and be advantageous in terms of IR drop.

[0188] and Figure 5 and Figure 6 Compared with the display panel structure, Figure 7 The display panel structure may be more easily formed in terms of a manufacturing process because deposition of the common electrode 500 extends to the holes formed in respective portions of the bank 300 and the element intermediate layer 400 .

[0189] Figure 7 The display panel structure can improve leakage current by removing a portion of the element intermediate layer (400 or EL) around or adjacent to the sub-pixel through a laser process and thus cutting off the current path in the element intermediate layer 400. By applying this configuration, damage due to leakage current between different sub-pixels can be prevented. By cutting off the leakage current between sub-pixels, an OLED panel with high efficiency and reduced power consumption can be achieved.

[0190] Reference Figure 7 and Figure 8Since the second link area LA' is provided so that the auxiliary electrode 210, the bridge electrode 310 and the hole electrode 610 directly contact and are connected to the common electrode 500, the common electrode contact area may not be provided in the frame area of ​​the display panel 110. Therefore, the frame area may be reduced by about 200 μm, and a narrow frame may be achieved.

[0191] Since the second link area LA' configured with the single auxiliary electrode 210, the bridge electrode 310, and the hole electrode 610 is connected to the lower portion of the common electrode 500, the display panel can provide an advantage of increasing the sheet resistance of the common electrode 500. Therefore, the thickness of the common electrode 500 can be reduced relative to the increased resistance, and the transmittance of the display panel 110 can be increased.

[0192] Reference Figure 8 , since the second link area LA' is provided in the form of a line in a plan view, this implementation can be applied to a display panel 110 configured to have a large area. Therefore, since the thickness of the common electrode in the display panel 110 having such a large area can be reduced, this implementation can help improve the transmittance of the display panel 110.

[0193] The example implementations described herein can be briefly discussed as follows.

[0194] According to the example embodiments described herein, a display device may be provided, the display device comprising: a substrate comprising a display area and a non-display area outside the display area; a transistor disposed above the substrate; a base voltage line disposed above the substrate; a planarization layer disposed on the transistor and the base voltage line; a pixel electrode disposed on the planarization layer; a dam disposed on the pixel electrode and comprising an opening for exposing a portion of the pixel electrode; an element intermediate layer located on the pixel electrode through the opening of the dam in the light-emitting area and extending along the dam in the non-light-emitting area; a common electrode disposed on the element intermediate layer; and a linking area configured to electrically interconnect the base voltage line and the common electrode and disposed in the display area.

[0195] In one or more aspects, the element intermediate layer may include a hole formed on the bank, and the link region may electrically interconnect the base voltage line and the common electrode through the hole.

[0196] In one or more aspects, the link region may include: a first auxiliary electrode located below the planarization layer; and a second auxiliary electrode located on the bank and electrically interconnecting the common electrode and the first auxiliary electrode. The second auxiliary electrode may electrically interconnect the common electrode and the first auxiliary electrode through a hole, and the first auxiliary electrode may be a basic voltage line or an electrode electrically connected to the basic voltage line. In one or more aspects, the second auxiliary electrode may be disposed inside the hole.

[0197] In one or more aspects, the second auxiliary electrode may be spaced apart from one or more sides of the hole. In one or more aspects, the second auxiliary electrode may contact one or more sides of the hole.

[0198] In one or more aspects, the link region may further include a bridge electrode for electrically interconnecting the first auxiliary electrode and the second auxiliary electrode, and the bridge electrode may be located between the planarization layer and the bank.

[0199] In one or more aspects, the bridge electrode may include the same material as the pixel electrode.

[0200] In one or more aspects, the first auxiliary electrode may include the same material as a source electrode or a drain electrode of the transistor, or include the same material as an electrode electrically connected to the source electrode or the drain electrode of the transistor.

[0201] In one or more aspects, the common electrode may be composed of a transparent electrode.

[0202] In one or more aspects, the link region may include a material having a higher resistivity than the common electrode.

[0203] In one or more aspects, the display device may further include a plurality of sub-pixels, and each of the plurality of sub-pixels may include a light-emitting element and a transistor. The light-emitting element may be configured by overlapping a pixel electrode, an element intermediate layer, and a common electrode with each other, and the link region may be located between a first sub-pixel and a second sub-pixel in the plurality of sub-pixels.

[0204] According to the example embodiments described herein, a display panel may be provided, the display panel comprising: a substrate comprising a display area and a non-display area outside the display area; a transistor disposed above the substrate; a base voltage line disposed above the substrate; a planarization layer disposed on the transistor and the base voltage line; a pixel electrode disposed on the planarization layer; a levee disposed on the pixel electrode and comprising an opening for exposing a portion of the pixel electrode; an element intermediate layer, which is located on the pixel electrode through the opening of the levee in the light-emitting area, extends along the levee in the non-light-emitting area, and comprises a hole formed on the levee; a common electrode disposed on the element intermediate layer; and a linking area configured to electrically interconnect the base voltage line and the common electrode through the hole in the element intermediate layer.

[0205] In one or more aspects, the link region may include: a first auxiliary electrode located below the planarization layer; and a second auxiliary electrode located on the bank and electrically interconnecting the common electrode and the first auxiliary electrode. The second auxiliary electrode may electrically interconnect the common electrode and the first auxiliary electrode through a hole, and the first auxiliary electrode may be a basic voltage line or an electrode electrically connected to the basic voltage line.

[0206] In one or more aspects, the second auxiliary electrode may be disposed inside the hole. In one or more aspects, the second auxiliary electrode may be spaced apart from one or more sides of the hole. In one or more aspects, the second auxiliary electrode may contact one or more sides of the hole.

[0207] In one or more aspects, the link region may further include a bridge electrode for electrically interconnecting the first auxiliary electrode and the second auxiliary electrode, and the bridge electrode may be located between the planarization layer and the bank.

[0208] In one or more aspects, the bridge electrode may include the same material as the pixel electrode.

[0209] In one or more aspects, the first auxiliary electrode may include the same material as a source electrode or a drain electrode of the transistor, or include the same material as an electrode electrically connected to the source electrode or the drain electrode of the transistor.

[0210] In one or more aspects, the common electrode may be composed of a transparent electrode.

[0211] In one or more aspects, the link region may include a material having a higher resistivity than the common electrode. In one or more aspects, the link region may be located in the display region.

[0212] The above description is presented to enable any person skilled in the art to make, use and practice the technical features of the present invention, and has been provided as examples in the context of specific applications and their requirements. Various modifications, additions and substitutions to the described embodiments will be apparent to those skilled in the art, and the principles described herein may be applied to other embodiments and applications without departing from the scope of the present invention. The above description and accompanying drawings provide examples of the technical features of the present invention for illustrative purposes only. For example, the disclosed embodiments are intended to illustrate the scope of the technical features of the present invention.

Claims

1. A display device, comprising: a substrate comprising a display area and a non-display area outside the display area; a transistor disposed above the substrate; a base voltage line disposed above the substrate; a planarization layer disposed on the transistor and the base voltage line; A pixel electrode, which is disposed on the planarization layer; a bank portion disposed on the pixel electrode and including an opening exposing a portion of the pixel electrode; an element intermediate layer, which is located on the pixel electrode through the opening of the bank in the light emitting region and extends along the bank in the non-light emitting region; A common electrode, which is arranged on the element intermediate layer; as well as A link region is configured to electrically interconnect the base voltage line and the common electrode and is disposed in the display region.

2. The display device according to claim 1, wherein: The element intermediate layer includes a hole formed on the bank, and the link region electrically interconnects the base voltage line and the common electrode through the hole.

3. The display device according to claim 2, wherein: The link area includes: a first auxiliary electrode located below the planarization layer; and a second auxiliary electrode located on the bank and electrically interconnecting the common electrode and the first auxiliary electrode, wherein the second auxiliary electrode electrically interconnects the common electrode and the first auxiliary electrode through the hole, and The first auxiliary electrode is the basic voltage line or an electrode electrically connected to the basic voltage line.

4. The display device according to claim 3, wherein: The second auxiliary electrode is disposed inside the hole.

5. The display device according to claim 4, wherein: The second auxiliary electrode is spaced apart from one or more sides of the hole.

6. The display device according to claim 4, wherein: The second auxiliary electrode contacts one or more sides of the hole.

7. The display device according to claim 3, wherein: The link region further includes a bridge electrode for electrically interconnecting the first auxiliary electrode and the second auxiliary electrode, and Wherein, the bridge electrode is located between the planarization layer and the bank.

8. The display device according to claim 7, wherein: The bridge electrode includes the same material as the pixel electrode.

9. The display device according to claim 3, wherein: The first auxiliary electrode includes the same material as a source electrode or a drain electrode of the transistor, or includes the same material as an electrode electrically connected to the source electrode or the drain electrode of the transistor.

10. The display device according to claim 1, wherein: The common electrode is composed of a transparent electrode.

11. The display device according to claim 1, wherein: The link region includes a material having a higher resistivity than the common electrode.

12. The display device according to claim 1, further comprising a plurality of sub-pixels, in, Each of the plurality of sub-pixels includes a light emitting element and the transistor, and The light emitting element is configured by overlapping the pixel electrode, the element intermediate layer, and the common electrode, and the link region is located between a first sub-pixel and a second sub-pixel among the plurality of sub-pixels.

13. A display panel, comprising: a substrate comprising a display area and a non-display area outside the display area; a transistor disposed above the substrate; a base voltage line disposed above the substrate; a planarization layer disposed on the transistor and the base voltage line; A pixel electrode, which is disposed on the planarization layer; a bank portion disposed on the pixel electrode and including an opening exposing a portion of the pixel electrode; an element intermediate layer, which is located on the pixel electrode through the opening of the bank in the light emitting region, extends along the bank in the non-light emitting region, and includes a hole formed on the bank, A common electrode, which is arranged on the element intermediate layer; as well as A link region is configured to electrically interconnect the base voltage line and the common electrode through the hole of the element intermediate layer.

14. The display panel according to claim 13, wherein: The link area also includes: a first auxiliary electrode located below the planarization layer; and a second auxiliary electrode located on the bank and electrically interconnecting the common electrode and the first auxiliary electrode, wherein the second auxiliary electrode electrically interconnects the common electrode and the first auxiliary electrode through the hole, and The first auxiliary electrode is the basic voltage line or an electrode electrically connected to the basic voltage line.

15. The display panel according to claim 14, wherein: The second auxiliary electrode is disposed inside the hole.

16. The display panel according to claim 15, wherein: The second auxiliary electrode is spaced apart from one or more sides of the hole.

17. The display panel according to claim 15, wherein: The second auxiliary electrode contacts one or more sides of the hole.

18. The display panel according to claim 14, wherein the link area further comprises: a bridge electrode for electrically interconnecting the first auxiliary electrode and the second auxiliary electrode, and Wherein, the bridge electrode is located between the planarization layer and the bank.

19. The display panel according to claim 18, wherein: The bridge electrode includes the same material as the pixel electrode.

20. The display panel according to claim 14, wherein: The first auxiliary electrode includes the same material as a source electrode or a drain electrode of the transistor, or includes the same material as an electrode electrically connected to the source electrode or the drain electrode of the transistor.

21. The display panel according to claim 13, wherein: The common electrode is composed of a transparent electrode.

22. The display panel according to claim 13, wherein: The link region includes a material having a higher resistivity than the common electrode.

23. The display panel according to claim 13, wherein: The link area is located in the display area.

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