High-voltage LDO power supply circuit with fast dynamic response and control method thereof
By adopting a combination of slow loop and fast loop design in high-voltage LDO power circuit, the cost and space occupation problems of traditional high-voltage LDO power circuits in fast transient response are solved, and rapid dynamic response and reduced system costs are achieved. Effect.
Patent Information
- Application Number
- CN202510018932.7
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-01-07
- Publication Date
- 2025-02-11
- Estimated Expiration
- Not applicable · inactive patent
AI Technical Summary
When traditional high-voltage LDO power circuits achieve fast transient response, they need to increase hardware costs and occupy more board space, and the large amount of high-voltage devices will increase chip costs.
The combination of slow loop and fast loop is adopted. The slow loop is responsible for precise adjustment in steady state, and the fast loop is responsible for fast transient response. Through internal optimization design, no large off-chip capacitors are required. Key devices use high-voltage devices, while others use low-voltage devices to reduce system costs and complexity.
It realizes a high-voltage LDO power supply circuit with fast dynamic response, reduces the ripple of the output voltage, reduces the system cost and complexity, improves the reliability and stability of the system, and is suitable for miniaturization and integrated design.
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Figure CN119420177A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to a high-voltage LDO power supply circuit and a control method thereof, in particular to a high-voltage LDO power supply circuit with fast dynamic response and a control method thereof, belonging to the technical field of semiconductor integrated circuits. Background Art
[0002] With the advancement of semiconductor technology, the process nodes are constantly shrinking, and the voltage required by modern integrated circuits is gradually decreasing. Common operating voltages include 5V, 3.3V, 1.8V, 1.5V, and 1.2V. However, in practical applications, the system input power supply is often a high-voltage signal. For example, in the field of automotive electronics, the voltage of a car battery is usually around 12V or 24V, but under different operating conditions such as starting, accelerating, and idling, the voltage will fluctuate greatly. High-voltage LDO can stably convert these changing high-voltage signals into the low voltage required internally (such as 5V, 3.3V, etc.), thereby ensuring the stable operation of on-board electronic equipment.
[0003] With the miniaturization and high integration of electronic devices, traditional LDOs usually need to lead out a pin on the package to connect a large load capacitor (usually at the uF level) in order to achieve stability and fast transient response. This design not only increases hardware costs, but also takes up more circuit board space, which is not in line with the development trend of miniaturization.
[0004] In order to overcome the problems of traditional LDO in high-voltage applications, high-voltage processes are usually used to design LDO. However, compared with low-voltage devices, high-voltage devices have poor performance and large area. If high-voltage devices are used in large quantities, the chip cost will be greatly increased. Summary of the invention
[0005] The technical problem to be solved by the present invention is to provide a high-voltage LDO power supply circuit with fast dynamic response and a control method thereof, which reduces hardware cost and realizes fast transient response.
[0006] In order to solve the above technical problems, the technical solution adopted by the present invention is: A high-voltage LDO power supply circuit with fast dynamic response comprises a rough low-voltage power supply generation module, an error amplifier EA, a high-voltage transient enhancement circuit, a PMOS tube MP1, a feedback resistor RF1 and a feedback resistor RF2, wherein the input end of the rough low-voltage power supply generation module and the source of the PMOS tube MP1 are connected to an input power supply VIN, the output end of the rough low-voltage power supply generation module is connected to the power supply end of the error amplifier EA and generates an internal power supply VDD, the positive input end of the error amplifier EA is connected to a reference voltage VREF, the output end of the error amplifier EA is connected to the input end of the high-voltage transient enhancement circuit, the first output end of the high-voltage transient enhancement circuit is connected to the gate of the PMOS tube MP1, the second output end of the high-voltage transient enhancement circuit is connected to the drain of the PMOS tube MP1 and one end of the feedback resistor RF1 and generates an output voltage VOUT, the other end of the feedback resistor RF1 is connected to one end of the feedback resistor RF2 and the inverting input end of the error amplifier and generates a feedback voltage VFB, and the other end of the feedback resistor RF2 is grounded.
[0007] Furthermore, the rough low-voltage power supply generation module includes a resistor R2, an NMOS tube NM4 and a Zener diode D2, one end of the resistor R2 and the drain of the NMOS tube NM4 serve as the input end of the rough low-voltage power supply generation module and are connected to the input power supply VIN, the other end of the resistor R2 is connected to the gate of the NMOS tube NM4 and the cathode of the Zener diode D2 and generates a voltage signal VGD, the anode of the Zener diode D2 is grounded, and the source of the NMOS tube NM4 serves as the output end of the rough low-voltage power supply generation module and generates an internal power supply VDD.
[0008] Furthermore, the high-voltage transient enhancement circuit comprises an NMOS tube NM1, an NMOS tube NM2, an NMOS tube NM3, a PMOS tube PM2, a PMOS tube PM3, a PMOS tube PM4, a current source IP1, a current sink IN1, a current sink IN2, a Zener diode D1, a capacitor C1, a capacitor C2 and a resistor R1, one end of the current source IP1 is connected to an internal power supply VDD, the other end of the current source IP1 is connected to the drain of the NMOS tube NM1, the gate of the NMOS tube NM1 and the gate of the NMOS tube NM2, the source of the NMOS tube NM1 is grounded, the source of the NMOS tube NM2 is connected to one end of the capacitor C1, the drain of the PMOS tube MP2 and one end of the current sink IN1 and generates a voltage signal VS, the other end of the current sink IN1 is grounded, the gate of the PMOS tube MP2 is connected to one end of the capacitor C2 and serves as The input end of the high-voltage transient enhancement circuit generates a voltage signal VC, the source of the PMOS tube MP2 serves as the second output end of the high-voltage transient enhancement circuit, the drain of the NMOS tube NM2 is connected to the drain of the PMOS tube MP3, the other end of the capacitor C1, the anode of the Zener diode D1 and one end of the resistor R1 and serves as the first output end of the high-voltage transient enhancement circuit to generate a voltage signal VG, the source of the PMOS tube MP4, the source of the PMOS tube MP3, the cathode of the Zener diode D1 and the other end of the resistor R1 are connected to the input power supply VIN, the gate of the PMOS tube MP4 is connected to the gate of the PMOS tube MP3, the drain of the PMOS tube MP4 and the drain of the NMOS tube NM3, the gate of the NMOS tube NM3 is connected to the enable signal en, the source of the NMOS tube NM3 is connected to one end of the current sink IN2, and the other end of the current sink IN2 is grounded.
[0009] Furthermore, the NMOS tubes NM2, NMOS tubes NM3 and NMOS tubes NM4 are high-voltage NMOS tubes, the PMOS tube MP1 is a high-voltage PMOS tube, the PMOS tubes MP3 and PMOS tubes MP4 are low-voltage PMOS tubes in a high-voltage well, the NMOS tube NM1 is a low-voltage NMOS tube, and the PMOS tube MP2 is a low-voltage PMOS tube.
[0010] Furthermore, the PMOS transistor MP3 and the PMOS transistor MP4 form a current mirror.
[0011] Furthermore, the error amplifier EA, the PMOS transistor MP2, the feedback resistor RF1 and the feedback resistor RF2 form a slow loop, and the PMOS transistor MP2, the NMOS transistor NM2, the PMOS transistor MP3 and the capacitor C1 form a fast loop.
[0012] A control method for a high-voltage LDO power supply circuit with fast dynamic response comprises the following steps: When the load changes dynamically, if the load is switched from light load to heavy load, the output voltage VOUT starts to drop, that is, the source voltage of the PMOS tube MP2 drops, the voltage signal VS of the drain end of the PMOS tube MP2 drops along with the output voltage VOUT, the voltage signal VG of the drain end of the NMOS tube NM2 drops along with the voltage signal VS, the gate-source voltage VGS_MP1 of the PMOS tube MP1 increases, the driving current of the PMOS tube MP1 increases, and the load end is powered quickly to prevent the output voltage VOUT from being pulled down; If the load is switched from heavy load to light load, the output voltage VOUT overshoots, that is, the source voltage of the PMOS tube MP2 rises, the voltage signal VS of the drain end of the PMOS tube MP2 rises with the output voltage VOUT, the voltage signal VG of the drain end of the NMOS tube NM2 rises with the voltage signal VS, the gate-source voltage VGS_MP1 of the PMOS tube MP1 decreases, and the driving current of the PMOS tube MP1 decreases to prevent the output voltage from overshooting; When the load changes rapidly, causing the output voltage VOUT to change rapidly, and the voltage signal VS changes rapidly with the output voltage VOUT, the voltage signal VG follows the rapid change due to the small AC impedance of the capacitor C2 to improve the dynamic response speed.
[0013] Compared with the prior art, the present invention has the following advantages and effects: the present invention provides a high-voltage LDO power supply circuit with fast dynamic response and a control method thereof, adopts a combination of a slow loop and a fast loop, the slow loop is responsible for precise regulation in a steady state to ensure that the output voltage reaches a preset value, the fast loop is responsible for fast transient response, the fast loop has a higher bandwidth and a faster response speed, ensures that the output voltage is quickly stabilized when the load suddenly changes, and reduces the ripple of the output voltage; the high-voltage LDO without an external capacitor of the present invention does not require an external large capacitor through internal optimization design, key components use high-voltage components, and other components use low-voltage components, which reduces system cost and complexity, improves system reliability and stability, reduces external interference, and is conducive to miniaturization and integrated design. BRIEF DESCRIPTION OF THE DRAWINGS
[0014] Figure 1 It is a schematic diagram of a high-voltage LDO power supply circuit with fast dynamic response of the present invention.
[0015] Figure 2 The invention discloses a circuit diagram of a high-voltage LDO power supply circuit with fast dynamic response. DETAILED DESCRIPTION
[0016] In order to elaborate on the technical scheme adopted by the present invention to achieve the predetermined technical purpose, the technical scheme in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only partial embodiments of the present invention, rather than all embodiments, and the technical means or technical features in the embodiments of the present invention can be replaced without paying creative work. The present invention will be described in detail below with reference to the drawings and in conjunction with the embodiments.
[0017] like Figure 1 As shown, a high-voltage LDO power supply circuit with fast dynamic response of the present invention comprises a rough low-voltage power supply generation module, an error amplifier EA, a high-voltage transient enhancement circuit, a PMOS tube MP1, a feedback resistor RF1 and a feedback resistor RF2, the input end of the rough low-voltage power supply generation module and the source of the PMOS tube MP1 are connected to the input power supply VIN, the output end of the rough low-voltage power supply generation module is connected to the power supply end of the error amplifier EA and generates an internal power supply VDD, the positive input end of the error amplifier EA is connected to the reference voltage VREF, the output end of the error amplifier EA is connected to the input end of the high-voltage transient enhancement circuit, the first output end of the high-voltage transient enhancement circuit is connected to the gate of the PMOS tube MP1, the second output end of the high-voltage transient enhancement circuit is connected to the drain of the PMOS tube MP1 and one end of the feedback resistor RF1 and generates an output voltage VOUT, the other end of the feedback resistor RF1 is connected to one end of the feedback resistor RF2 and the inverting input end of the error amplifier and generates a feedback voltage VFB, and the other end of the feedback resistor RF2 is grounded.
[0018] The rough low-voltage power supply generation module converts the high-voltage input power supply VIN into a rough low-voltage internal power supply VDD, which is used to provide power supply voltage to low-voltage modules such as the reference voltage generation module and the reference current generation module. The power supply of the error amplifier is the internal power supply VDD.
[0019] The non-inverting input of the error amplifier EA is connected to the reference voltage VREF, and the inverting input is connected to the output feedback signal VFB. VFB = VOUT*RF2 / (RF1+RF2). The output of the error amplifier EA is connected to the high-voltage transient enhancement circuit. In a fixed application, RF2 / (RF1+RF2) and the reference voltage VREF are fixed values, so the output voltage VOUT is also fixed.
[0020] like Figure 2As shown, the rough low-voltage power supply generation module includes a resistor R2, an NMOS tube NM4 and a Zener diode D2. One end of the resistor R2 and the drain of the NMOS tube NM4 serve as the input end of the rough low-voltage power supply generation module and are connected to the input power supply VIN. The other end of the resistor R2 is connected to the gate of the NMOS tube NM4 and the cathode of the Zener diode D2 and generates a voltage signal VGD. The anode of the Zener diode D2 is grounded. The source of the NMOS tube NM4 serves as the output end of the rough low-voltage power supply generation module and generates an internal power supply VDD.
[0021] When the voltage of the input voltage VIN is lower than the clamping voltage VD of the Zener diode D2, VGD=VIN, VDD=VGD-VGS_NM4=VIN-VGS_NM4, where VGS_NM4 is the gate-source voltage of the NMOS tube NM4. When the voltage of the input voltage VIN is greater than the clamping voltage VD of the Zener diode D2, the Zener diode D2 works to clamp VGD at the clamping voltage VD of the Zener diode D2, that is, VGD=VD, VDD=VGD-VGS_NM4=VD-VGS_NM4. Because VGS_NM4 changes with the load, the internal voltage VDD is just a rough low-voltage power supply, which is used to provide power supply voltage to low-voltage modules such as the bias current IP1, IN1, and the reference voltage VREF generation module. The power supply of the error amplifier is the internal power supply VDD.
[0022] The high-voltage transient enhancement circuit comprises an NMOS tube NM1, an NMOS tube NM2, an NMOS tube NM3, a PMOS tube PM2, a PMOS tube PM3, a PMOS tube PM4, a current source IP1, a current sink IN1, a current sink IN2, a Zener diode D1, a capacitor C1, a capacitor C2 and a resistor R1, one end of the current source IP1 is connected to an internal power supply VDD, the other end of the current source IP1 is connected to the drain of the NMOS tube NM1, the gate of the NMOS tube NM1 and the gate of the NMOS tube NM2, the source of the NMOS tube NM1 is grounded, the source of the NMOS tube NM2 is connected to one end of the capacitor C1, the drain of the PMOS tube MP2 and one end of the current sink IN1 to generate a voltage signal VS, the other end of the current sink IN1 is grounded, the gate of the PMOS tube MP2 is connected to one end of the capacitor C2 and serves as a high-voltage transient. The input end of the high-voltage transient enhancement circuit generates a voltage signal VC, the source of the PMOS tube MP2 serves as the second output end of the high-voltage transient enhancement circuit, the drain of the NMOS tube NM2 is connected to the drain of the PMOS tube MP3, the other end of the capacitor C1, the anode of the Zener diode D1 and one end of the resistor R1 and serves as the first output end of the high-voltage transient enhancement circuit to generate a voltage signal VG, the source of the PMOS tube MP4, the source of the PMOS tube MP3, the cathode of the Zener diode D1 and the other end of the resistor R1 are connected to the input power supply VIN, the gate of the PMOS tube MP4 is connected to the gate of the PMOS tube MP3, the drain of the PMOS tube MP4 and the drain of the NMOS tube NM3, the gate of the NMOS tube NM3 is connected to the enable signal en, the source of the NMOS tube NM3 is connected to one end of the current sink IN2, and the other end of the current sink IN2 is grounded.
[0023] NMOS tubes NM2, NMOS tubes NM3 and NMOS tubes NM4 are high-voltage NMOS tubes, PMOS tube MP1 is a high-voltage PMOS tube, PMOS tubes MP3 and PMOS tubes MP4 are low-voltage PMOS tubes made in a high-voltage well, NMOS tube NM1 is a low-voltage NMOS tube, and PMOS tube MP2 is a low-voltage PMOS tube. NMOS tube NM2 uses a high-voltage NMOS tube to isolate the high-voltage signal at the drain end, and the gate of NMOS tube NM3 is connected to the enable signal en. When the enable signal en is at a high level, the LDO power supply circuit works, and when the enable signal en is at a low level, the LDO power supply circuit does not work.
[0024] The PMOS tube MP3 and the PMOS tube MP4 form a current mirror to provide current for the NMOS tube NM2. The Zener diode D1 is a clamping tube to protect the gate-source voltage of the PMOS tube MP1 from exceeding the withstand voltage value to prevent breakdown; the Zener diode D2 is a clamping tube to protect the gate-source voltage of the NMOS tube NM4 from exceeding the withstand voltage value to prevent breakdown. When the enable signal is low and the LDO is not working, the resistor R1 pulls up the gate voltage of the PMOS tube MP1 to VIN to turn off the PMOS tube MP1.
[0025] The error amplifier EA, PMOS tube MP2, feedback resistor RF1 and feedback resistor RF2 form a slow loop to generate a fixed output voltage. According to the short-circuit and virtual-break characteristics of the op amp, VFB=VREF, so VOUT=VREF*(RF2+RF1) / RF2. When the output voltage VOUT increases, the feedback power supply VFB increases, the voltage signal VC at the output end of the error amplifier EA decreases, and the output voltage VOUT decreases, realizing negative feedback regulation, so that the output voltage is stabilized at the preset value VREF*(RF2+RF1) / RF2. The error amplifier EA has a high gain, a large output impedance rout, and the output end is connected to the ground capacitor C2, so that the main pole is at the output end of the error amplifier EA, P1=1 / (rout×C2), the output node output impedance is small, and the secondary pole generated is at a high frequency.
[0026] PMOS tube MP2, NMOS tube NM2, PMOS tube MP3 and capacitor C1 form a fast loop. The slow loop has a slow response speed, and when the load switches quickly, it will cause a large output ripple. The high-voltage transient enhancement circuit is a fast loop that can quickly respond to load changes.
[0027] A control method for a high-voltage LDO power supply circuit with fast dynamic response comprises the following steps: When the load changes dynamically, if the load is switched from a light load to a heavy load, the output voltage VOUT starts to drop, that is, the source voltage of the PMOS tube MP2 drops, the voltage signal VS at the drain end of the PMOS tube MP2 drops along with the output voltage VOUT, the voltage signal VG at the drain end of the NMOS tube NM2 drops along with the voltage signal VS, the gate-source voltage VGS_MP1 of the PMOS tube MP1 increases, the driving current of the PMOS tube MP1 increases, and the load end is powered quickly to prevent the output voltage VOUT from being pulled down.
[0028] If the load is switched from heavy load to light load, the output voltage VOUT overshoots, that is, the source voltage of the PMOS tube MP2 rises, the voltage signal VS at the drain end of the PMOS tube MP2 rises following the output voltage VOUT, the voltage signal VG at the drain end of the NMOS tube NM2 rises following the voltage signal VS, the gate-source voltage VGS_MP1 of the PMOS tube MP1 decreases, and the driving current of the PMOS tube MP1 decreases to prevent the output voltage from overshooting.
[0029] When the load changes rapidly, causing the output voltage VOUT to change rapidly, and the voltage signal VS changes rapidly with the output voltage VOUT, the voltage signal VG follows the rapid change due to the small AC impedance of the capacitor C2 to improve the dynamic response speed.
[0030] The slow loop formed by EA and the fast loop formed by the high-voltage transient enhancement circuit are combined. The slow loop is responsible for precise regulation in steady state to ensure that the output voltage reaches the preset value. The fast loop is responsible for fast transient response. The fast loop has a higher bandwidth and faster response speed, ensuring that the output voltage stabilizes quickly when the load changes suddenly, reducing the ripple of the output voltage.
[0031] The present invention provides a high-voltage LDO power supply circuit with fast dynamic response and a control method thereof. The circuit adopts a combination of a slow loop and a fast loop. The slow loop is responsible for precise regulation in a steady state to ensure that the output voltage reaches a preset value. The fast loop is responsible for fast transient response. The fast loop has a higher bandwidth and a faster response speed to ensure that the output voltage is quickly stabilized when the load suddenly changes, and the ripple of the output voltage is reduced. The high-voltage LDO without an off-chip capacitor does not require an off-chip large capacitor through internal optimization design. Key components use high-voltage components, and other components use low-voltage components, thereby reducing system cost and complexity, improving system reliability and stability, reducing external interference, and being conducive to miniaturization and integrated design.
[0032] The above is only a preferred embodiment of the present invention and does not limit the present invention in any form. Although the present invention has been disclosed as a preferred embodiment as above, it is not used to limit the present invention. Any technician familiar with this profession can make some changes or modify the technical contents disclosed above into equivalent embodiments without departing from the scope of the technical solution of the present invention. However, any simple modification, equivalent replacement and improvement made to the above embodiments without departing from the content of the technical solution of the present invention, based on the technical essence of the present invention, within the spirit and principles of the present invention, still fall within the protection scope of the technical solution of the present invention.
Claims
1. A high voltage LDO power supply circuit with fast dynamic response, characterized in that: The invention comprises a rough low-voltage power supply generation module, an error amplifier EA, a high-voltage transient enhancement circuit, a PMOS tube MP1, a feedback resistor RF1 and a feedback resistor RF2. The input end of the rough low-voltage power supply generation module and the source of the PMOS tube MP1 are connected to an input power supply VIN. The output end of the rough low-voltage power supply generation module is connected to the power supply end of the error amplifier EA and generates an internal power supply VDD. The positive input end of the error amplifier EA is connected to a reference voltage VREF. The output end of the error amplifier EA is connected to the input end of the high-voltage transient enhancement circuit. The first output end of the high-voltage transient enhancement circuit is connected to the gate of the PMOS tube MP1. The second output end of the high-voltage transient enhancement circuit is connected to the drain of the PMOS tube MP1 and one end of the feedback resistor RF1 to generate an output voltage VOUT. The other end of the feedback resistor RF1 is connected to one end of the feedback resistor RF2 and the inverting input end of the error amplifier to generate a feedback voltage VFB. The other end of the feedback resistor RF2 is grounded.
2. The high-voltage LDO power supply circuit with fast dynamic response according to claim 1, characterized in that: The rough low-voltage power supply generation module includes a resistor R2, an NMOS tube NM4 and a Zener diode D2. One end of the resistor R2 and the drain of the NMOS tube NM4 serve as the input end of the rough low-voltage power supply generation module and are connected to the input power supply VIN. The other end of the resistor R2 is connected to the gate of the NMOS tube NM4 and the cathode of the Zener diode D2 and generates a voltage signal VGD. The anode of the Zener diode D2 is grounded. The source of the NMOS tube NM4 serves as the output end of the rough low-voltage power supply generation module and generates an internal power supply VDD.
3. The high-voltage LDO power supply circuit with fast dynamic response according to claim 2, characterized in that: The high-voltage transient enhancement circuit comprises an NMOS tube NM1, an NMOS tube NM2, an NMOS tube NM3, a PMOS tube PM2, a PMOS tube PM3, a PMOS tube PM4, a current source IP1, a current sink IN1, a current sink IN2, a Zener diode D1, a capacitor C1, a capacitor C2 and a resistor R1, one end of the current source IP1 is connected to an internal power supply VDD, the other end of the current source IP1 is connected to the drain of the NMOS tube NM1, the gate of the NMOS tube NM1 and the gate of the NMOS tube NM2, the source of the NMOS tube NM1 is grounded, the source of the NMOS tube NM2 is connected to one end of the capacitor C1, the drain of the PMOS tube MP2 and one end of the current sink IN1 to generate a voltage signal VS, the other end of the current sink IN1 is grounded, the gate of the PMOS tube MP2 is connected to one end of the capacitor C2 and serves as a high voltage The input end of the transient enhancement circuit generates a voltage signal VC, the source of the PMOS tube MP2 serves as the second output end of the high-voltage transient enhancement circuit, the drain of the NMOS tube NM2 is connected to the drain of the PMOS tube MP3, the other end of the capacitor C1, the anode of the Zener diode D1 and one end of the resistor R1 and serves as the first output end of the high-voltage transient enhancement circuit to generate a voltage signal VG, the source of the PMOS tube MP4, the source of the PMOS tube MP3, the cathode of the Zener diode D1 and the other end of the resistor R1 are connected to the input power supply VIN, the gate of the PMOS tube MP4 is connected to the gate of the PMOS tube MP3, the drain of the PMOS tube MP4 and the drain of the NMOS tube NM3, the gate of the NMOS tube NM3 is connected to the enable signal en, the source of the NMOS tube NM3 is connected to one end of the current sink IN2, and the other end of the current sink IN2 is grounded.
4. The high-voltage LDO power supply circuit with fast dynamic response according to claim 3, characterized in that: The NMOS tubes NM2, NMOS tubes NM3 and NMOS tubes NM4 are high-voltage NMOS tubes, the PMOS tube MP1 is a high-voltage PMOS tube, the PMOS tubes MP3 and PMOS tubes MP4 are low-voltage PMOS tubes made in a high-voltage well, the NMOS tube NM1 is a low-voltage NMOS tube, and the PMOS tube MP2 is a low-voltage PMOS tube.
5. The high-voltage LDO power supply circuit with fast dynamic response according to claim 3, characterized in that: The PMOS transistor MP3 and the PMOS transistor MP4 form a current mirror.
6. The high-voltage LDO power supply circuit with fast dynamic response according to claim 3, characterized in that: The error amplifier EA, the PMOS tube MP2, the feedback resistor RF1 and the feedback resistor RF2 form a slow loop, and the PMOS tube MP2, the NMOS tube NM2, the PMOS tube MP3 and the capacitor C1 form a fast loop.
7. A control method for a high-voltage LDO power supply circuit with fast dynamic response according to any one of claims 1 to 6, characterized in that The following steps are involved: When the load changes dynamically, if the load is switched from light load to heavy load, the output voltage VOUT starts to drop, that is, the source voltage of the PMOS tube MP2 drops, the voltage signal VS of the drain end of the PMOS tube MP2 drops along with the output voltage VOUT, the voltage signal VG of the drain end of the NMOS tube NM2 drops along with the voltage signal VS, the gate-source voltage VGS_MP1 of the PMOS tube MP1 increases, the driving current of the PMOS tube MP1 increases, and the load end is powered quickly to prevent the output voltage VOUT from being pulled down; If the load is switched from heavy load to light load, the output voltage VOUT overshoots, that is, the source voltage of the PMOS tube MP2 rises, the voltage signal VS of the drain end of the PMOS tube MP2 rises with the output voltage VOUT, the voltage signal VG of the drain end of the NMOS tube NM2 rises with the voltage signal VS, the gate-source voltage VGS_MP1 of the PMOS tube MP1 decreases, and the driving current of the PMOS tube MP1 decreases to prevent the output voltage from overshooting; When the load changes rapidly, causing the output voltage VOUT to change rapidly, and the voltage signal VS changes rapidly with the output voltage VOUT, the voltage signal VG follows the rapid change due to the small AC impedance of the capacitor C2 to improve the dynamic response speed.
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