Fully digital delay phase-locked loop circuit and calibration method

Abstract

The present application provides a fully digital delay phase-locked loop circuit and a calibration method, and relates to the technical field of integrated circuits. The fully digital delay phase-locked loop circuit includes: a frequency divider, a phase detector, a calibration logic circuit and a digitally controlled delay line; the input end of the frequency divider receives a reference clock signal, the first output end of the frequency divider is connected to the input end of the digitally controlled delay line, and provides a reference pulse signal; the second output end of the frequency divider is connected to the first input end of the phase detector, and provides a phase detection sampling pulse signal; the second input end of the phase detector is connected to the output end of the digitally controlled delay line, and receives a delayed pulse signal after the digitally controlled delay line delays the reference pulse signal; the output end of the phase detector is connected to the input end of the calibration logic circuit, and provides a phase detection result; the output end of the calibration logic circuit is connected to the control end of the digitally controlled delay line, and the delay step of the digitally controlled delay line is calibrated according to the phase detection result, so as to calibrate the delay of the delayed pulse signal. The present application can reduce the phase detection error and improve the calibration accuracy.

Description

Technical Field

[0001] The present application relates to the technical field of integrated circuits, and in particular to a fully digital delay locked loop circuit and a calibration method. Background Art

[0002] All Digital Delay Locked Loop (ADDLL) is widely used in the design of modern microcontroller chips and system-on-chip to achieve clock compensation and phase adjustment functions. Compared with analog delay locked loops, all digital delay locked loops are not sensitive to working environment, such as temperature and voltage changes, and are increasingly used in the field of digital timing.

[0003] As the working accuracy requirements of the fully digital delay-locked loop gradually increase, the length of the digitally controlled delay line continues to increase. Since there is an error in the delay between the reference clock and the delayed clock reaching the phase detector, the phase detection result will be biased, the calibration effect will deteriorate, and the stability of the fully digital delay-locked loop will be affected. Summary of the invention

[0004] The purpose of the present application is to provide a fully digital delay locked loop circuit and calibration method to address the deficiencies in the above-mentioned prior art, so as to reduce phase detection error and improve calibration accuracy.

[0005] To achieve the above purpose, the technical solution adopted in the embodiment of the present application is as follows:

[0006] In a first aspect, an embodiment of the present application provides a fully digital delay locked loop circuit, the circuit comprising: a frequency divider, a phase detector, a calibration logic circuit and a digitally controlled delay line;

[0007] The input end of the frequency divider is used to receive a reference clock signal, and the first output end of the frequency divider is connected to the input end of the digitally controlled delay line to provide a reference pulse signal for the digitally controlled delay line;

[0008] The second output end of the frequency divider is connected to the first input end of the phase detector, and is used to provide a phase detection sampling pulse signal for the phase detector, wherein the phase detection sampling pulse signal and the reference pulse signal are two frequency division signals of the reference clock signal;

[0009] The second input end of the phase detector is connected to the output end of the digitally controlled delay line, and is used to receive a delayed pulse signal after the digitally controlled delay line delays the reference pulse signal;

[0010] The output end of the phase detector is connected to the input end of the calibration logic circuit, and is used to provide the calibration logic circuit with a phase detection result of the reference pulse signal and the delayed pulse signal;

[0011] The output end of the calibration logic circuit is connected to the control end of the digitally controlled delay line, and is used to calibrate the delay step of the digitally controlled delay line according to the phase-locked result so as to calibrate the delay of the delayed pulse signal. The delay step indicates the number of effective delay units in the digitally controlled delay line.

[0012] Optionally, the third output terminal of the frequency divider is connected to the first control terminal of the calibration logic circuit, and is used to provide a state machine update pulse signal to the calibration logic circuit, so that the calibration logic circuit updates a step direction and a step length based on the state machine update pulse signal, the step direction is used to indicate an increase or decrease in the delay step length, and the step length is used to indicate an increase or decrease in the length of the delay step length;

[0013] The fourth output terminal of the frequency divider is connected to the second control terminal of the calibration logic circuit, and is used to provide a step update pulse signal to the calibration logic circuit, so that the calibration logic circuit calibrates the delay step of the digitally controlled delay line according to the step direction and the step size based on the step update pulse signal.

[0014] Optionally, the circuit further comprises: a result register, the digitally controlled delay line comprises: a reference digitally controlled delay line and an application digitally controlled delay line;

[0015] The output end of the calibration logic circuit is connected to the reference digitally controlled delay line;

[0016] The input end of the result register is connected to the output end of the phase detector, and is used to store the phase detection result, so that the preset calibration software reads the phase detection result from the result register, and provides a calibration step length for the calibration logic circuit according to the phase detection result, so as to calibrate the delay step length of the reference digital controlled delay line according to the calibration step length;

[0017] The preset calibration software is also used to calibrate the applied digital controlled delay line according to the calibration step length when the phase discrimination result after the step length calibration is correct.

[0018] Optionally, the phase detector comprises: a first trigger, a second trigger and a selector;

[0019] The input end of the first trigger serves as the second input end of the phase detector, the output end of the first trigger is connected to the first input end of the selector, the second input end of the selector is connected to the output end of the second trigger, the selection input end of the selector serves as the first input end of the phase detector, the output end of the selector is connected to the input end of the second trigger, and the output end of the second trigger serves as the output end of the phase detector.

[0020] Optionally, the phase detector comprises: a first trigger, a second trigger and a selector;

[0021] The selection input end of the selector serves as the first input end of the phase detector, the first input end of the selector serves as the second input end of the phase detector, the second input end of the selector is connected to the output end of the first trigger, the output end of the selector is connected to the input end of the first trigger, the output end of the first trigger is also connected to the input end of the second trigger, and the output end of the second trigger serves as the output end of the phase detector.

[0022] Optionally, the digitally controlled delay line comprises a first delay unit and a plurality of second delay units;

[0023] The first delay unit includes a first buffer, a first NAND gate and a second NAND gate, and each of the second delay units includes a second buffer, a third NAND gate and an AND gate;

[0024] The input end of the first buffer is used as the input end of the digitally controlled delay line, and the first buffer and the second buffers in the plurality of second delay units are sequentially connected in series;

[0025] The output end of the first buffer is connected to the first input end of the first NAND gate, the output end of the first NAND gate is connected to the first input end of the second NAND gate, and the output end of the second NAND gate serves as the output end of the digitally controlled delay line;

[0026] The second buffer in each of the second delay units is connected to the first input terminal of the corresponding third NAND gate, and the output terminal of the third NAND gate is connected to the first input terminal of the corresponding AND gate;

[0027] The second input terminal of each AND gate is connected to the output terminal of the next AND gate, the second input terminal of the last AND gate is a preset high level, and the output terminal of the first AND gate is connected to the second input terminal of the second NAND gate;

[0028] The second input end of the first NAND gate and the second input end of the third NAND gate serve as control ends of the digitally controlled delay line.

[0029] In a second aspect, an embodiment of the present application further provides a calibration method for a fully digital delay locked loop circuit, which is applied to the fully digital delay locked loop circuit as described in any one of the first aspects, and the method includes:

[0030] When the phase-comparison sampling pulse signal is valid, sampling the delayed pulse signal to obtain the phase-comparison result of the reference pulse signal and the delayed pulse signal;

[0031] Determine the delay step of the numerically controlled delay line according to the phase detection result and the step direction and step length, wherein the step direction is used to indicate an increase or decrease in the delay step, and the step length is used to indicate an increase or decrease in the length of the delay step;

[0032] The digitally controlled delay line is calibrated according to the delay step length to calibrate the delay of the delayed pulse signal of the digitally controlled delay line, and the delay step length indicates the number of effective delay units in the digitally controlled delay line.

[0033] Optionally, determining the delay step length of the digital controlled delay line according to the phase detection result, the step direction, and the step length includes:

[0034] Determining whether the step change direction indicated by the phase detection result is consistent with the step direction;

[0035] Update the step direction and the step length according to the judgment result;

[0036] The delay step length is determined according to the updated step direction and the target step length, and the target step length is the step length before the update or the step length after the update.

[0037] Optionally, updating the step direction and the step length according to the judgment result includes:

[0038] If the step length change direction is consistent with the step direction, determining that the step direction and the step length remain unchanged;

[0039] If the step length change direction is inconsistent with the step direction, the step direction is updated to the opposite direction, the step length is reduced, and the updated step length is determined.

[0040] Optionally, the method further comprises:

[0041] Repeat updating the step direction and the step length multiple times until the step length is equal to 1, and update the delay step length based on the last updated step direction and step length 1 until the step length change direction indicated by the phase detection result is reversed, thereby ending the calibration process.

[0042] Optionally, the method further comprises:

[0043] An offset step is added to the delay step as the delay step.

[0044] The beneficial effects of this application are:

[0045] The fully digital delay locked loop circuit and calibration method provided by the present application divide the reference clock signal based on a frequency divider to generate a reference pulse signal and a phase-locked sampling pulse signal, use the reference pulse signal as the input signal of the digital control delay line, and use the phase-locked sampling pulse signal to select the phase-locked sampling moment of the delayed pulse signal by the phase detector. Compared with the prior art that directly performs phase-locked detection on the reference clock signal and the delayed pulse signal, it avoids the situation where there is an error in the delay between the reference clock signal and the delayed pulse signal reaching the phase detector, ensures the accuracy of the phase-locked loop result, thereby ensuring the calibration effect and improving the stability of the fully digital delay locked loop circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0046] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for use in the embodiments will be briefly introduced below. It should be understood that the following drawings only show certain embodiments of the present application and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other related drawings can be obtained based on these drawings without paying creative work.

[0047] Figure 1 Schematic diagram of a fully digital delay locked loop circuit provided in an embodiment of the present application Figure 1 ;

[0048] Figure 2 Schematic diagram of a fully digital delay locked loop circuit provided in an embodiment of the present application Figure 2 ;

[0049] Figure 3 Schematic diagram of the phase detector provided in the embodiment of the present application Figure 1 ;

[0050] Figure 4 The working waveform diagram of the phase detector provided in the embodiment of the present application;

[0051] Figure 5 Schematic diagram of the phase detector provided in the embodiment of the present application Figure 2 ;

[0052] Figure 6 A schematic diagram of a digitally controlled delay line provided in an embodiment of the present application;

[0053] Figure 7 A schematic diagram of a calibration method for a fully digital delay locked loop circuit provided in an embodiment of the present application Figure 1 ;

[0054] Figure 8 A schematic diagram of a calibration method for a fully digital delay locked loop circuit provided in an embodiment of the present application Figure 2 ;

[0055] Fig. 9A schematic diagram of an update of a state machine provided in an embodiment of the present application;

[0056] Fig.10 This is a working waveform diagram of the calibration logic circuit provided in an embodiment of the present application. DETAILED DESCRIPTION

[0057] In order to make the purpose, technical solutions and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be clearly and completely described below in combination with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments.

[0058] Therefore, the following detailed description of the embodiments of the present application provided in the accompanying drawings is not intended to limit the scope of the present application for which protection is sought, but merely represents selected embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in the field without creative work are within the scope of protection of the present application.

[0059] In addition, the terms "first", "second", etc. in the specification and claims of the present application and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequential order. It should be understood that the data used in this way can be interchangeable where appropriate, so that the embodiments of the present application described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any of their variations are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device comprising a series of steps or units is not necessarily limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0060] It should be noted that, in the absence of conflict, the features in the embodiments of the present application may be combined with each other.

[0061] Figure 1 Schematic diagram of a fully digital delay locked loop circuit provided in an embodiment of the present application Figure 1 ,like Figure 1 As shown, the all-digital delay locked loop circuit may include: a frequency divider 10 , a phase detector 20 , a calibration logic circuit 30 and a digitally controlled delay line 40 .

[0062] The input end of the frequency divider 10 is used to receive the reference clock signal. The first output end of the frequency divider 10 is connected to the input end of the digitally controlled delay line 40, and is used to provide a reference pulse signal for the digitally controlled delay line 40. The second output end of the frequency divider 10 is connected to the first input end of the phase detector 20, and is used to provide a phase detection sampling pulse signal for the phase detector 20. The phase detection sampling pulse signal and the reference pulse signal are two frequency-divided signals of the reference clock signal. The second input end of the phase detector 20 is connected to the output end of the digitally controlled delay line 40, and is used to receive a delayed pulse signal after the digitally controlled delay line 40 delays the reference pulse signal. The output end of the phase detector 20 is connected to the input end of the calibration logic circuit 30, and is used to provide the calibration logic circuit 30 with the phase detection result of the reference pulse signal and the delayed pulse signal. The output end of the calibration logic circuit 30 is connected to the control end of the digitally controlled delay line 40, and is used to calibrate the delay step of the digitally controlled delay line 40 according to the phase detection result, so as to calibrate the delay of the delayed pulse signal. The delay step indicates the number of effective delay units in the digitally controlled delay line.

[0063] In this embodiment, the divider 10 divides the reference clock signal to generate a reference pulse signal ref_tick and a phase-locked sampling pulse signal pd_upd. The phase-locked sampling pulse signal pd_upd lags behind the reference pulse signal ref_tick by a preset delay. The preset delay is the effective delay of the digitally controlled delay line after the full digital delay locked loop is calibrated, that is, the delay length between the delayed pulse signal dll_tick obtained by delaying the reference pulse signal ref_tick through the digitally controlled delay line and the reference pulse signal ref_tick. In this embodiment, one clock cycle is taken as an example for explanation.

[0064] The digitally controlled delay line 40 includes a plurality of delay units. The enabled delay unit in the data delay line 40 is determined according to the delay step of the digitally controlled delay line 40. The effective delay unit is from the first delay unit in the digitally controlled delay line 40 to the enabled delay unit. The number of effective delay units is equal to the delay step of the digitally controlled delay line 40. The reference pulse signal ref_tick generated by the frequency divider 10 is delayed by the effective delay unit in the digitally controlled delay line 40, and the delayed pulse signal dll_tick after the reference pulse signal ref_tick is output.

[0065] The inputs of the phase detector 20 are the phase detection sampling pulse signal pd_upd and the delayed pulse signal dll_tick. The phase detection sampling pulse signal pd_upd is used as the timing control of the phase detector 20. When the phase detection sampling pulse signal pd_upd is valid, the delayed pulse signal dll_tick is sampled to obtain the synchronization signal pd_rslt about the reference pulse signal ref_tick and the delayed pulse signal dll_tick. The synchronization signal pd_rslt is used as the phase detection result obtained by the phase detector 20 for phase detection of the reference pulse signal ref_tick and the delayed pulse signal dll_tick.

[0066] The calibration logic circuit 30 calibrates the delay step of the digitally controlled delay line 40 according to the synchronization signal pd_rslt, generates a one-hot code according to the calibrated delay step, and controls a delay unit in the digitally controlled delay line 40 to turn on according to the one-hot code to select the delay path from the first delay unit to the turned-on delay unit.

[0067] In some embodiments, when the synchronization signal pd_rslt indicates that the delay between the reference pulse signal ref_tick and the delayed pulse signal dll_tick is small, the calibration logic circuit 30 needs to increase the delay step of the digitally controlled delay line 40; when the synchronization signal pd_rslt indicates that the delay between the reference pulse signal ref_tick and the delayed pulse signal dll_tick is large, the calibration logic circuit 30 needs to reduce the delay step of the digitally controlled delay line 40.

[0068] The all-digital delay phase-locked loop circuit provided in the above embodiment divides the reference clock signal based on a frequency divider to generate a reference pulse signal and a phase-locked sampling pulse signal, and uses the reference pulse signal as the input signal of the digitally controlled delay line. The phase-locked sampling pulse signal is used by the phase detector to select the phase-locked sampling moment of the delayed pulse signal. Compared with the prior art that directly performs phase-locking on the reference clock signal and the delayed pulse signal, it avoids the situation where there is an error in the delay of the reference clock signal and the delayed pulse signal reaching the phase detector, thereby ensuring the accuracy of the phase-locked loop result, thereby ensuring the calibration effect and improving the stability of the all-digital delay phase-locked loop circuit.

[0069] In one possible implementation, Figure 1As shown, the third output terminal of the frequency divider 10 is connected to the first control terminal of the calibration logic circuit 30, and is used to provide a state machine update pulse signal to the calibration logic circuit 30, so that the calibration logic circuit 30 updates the step direction and the step length based on the state machine update pulse signal, and the step direction is used to indicate an increase or decrease in the delay step, and the step length is used to indicate an increase or decrease in the length of the delay step; the fourth output terminal of the frequency divider 10 is connected to the second control terminal of the calibration logic circuit 30, and is used to provide a step length update pulse signal to the calibration logic circuit 30, so that the calibration logic circuit 30 calibrates the delay step of the numerically controlled delay line 40 according to the step direction and the step length based on the step length update pulse signal.

[0070] In the implementation of high-precision PWM, since the frequency of the digital clock cannot be increased arbitrarily, in order to improve the resolution of PWM at high frequencies, it is necessary to use a digitally controlled delay line to adjust the high-level time of the original PWM. First, use a fully digital delay phase-locked loop circuit to calibrate the digitally controlled delay line, obtain the operation code corresponding to the digitally controlled delay line in the current working environment, and then calculate the high-level time and the delay time of the digitally controlled delay line according to the duty cycle requirements of the PWM, adjust the operation code of the digitally controlled delay line, and you can achieve controllable delay of the original PWM, and then obtain high-precision PWM.

[0071] Under high frequency working conditions, if the extension of the digital controlled delay line is changed while the input signal is still propagating in the digital controlled delay line, unpredictable glitches will be generated in the output delayed signal, thus weakening the robustness of the circuit.

[0072] In this embodiment, in order to solve the problem of changing the extension of the digital control delay line when the input signal is still propagating in the digital control delay line, the reference clock signal is divided by the divider 10 to generate a state machine update pulse signal state_upd and a step update pulse signal step_upd.

[0073] The state machine of the calibration logic circuit 30 has different working states, representing different step directions and step lengths. When the state machine update pulse signal state_upd is valid, the synchronization signal pd_rslt output by the phase detector 20 is obtained to update the step direction and step length of the state machine according to the synchronization signal pd_rslt. When the step length update pulse signal step_upd is valid, the delay step length of the digital control delay line 40 is updated according to the step direction and step length.

[0074] In some embodiments, the timing relationship between the state machine update pulse signal state_upd and the step size update pulse signal step_upd can be determined according to a predetermined step direction and step size, and an update sequence of the delay step size.

[0075] If it is stipulated that after each phase detection is completed, the step direction and step length are updated first, and then the delay step length is updated according to the updated step direction and step length, then the timing of the state machine update pulse signal state_upd is before the step length update pulse signal step_upd; if it is stipulated that after each phase detection is completed, the step direction is updated first, the delay step length is updated according to the updated step direction and the original step length, and then the step length is updated, and the updated step length is updated with the delay step length after the next phase detection; then the timing of the step length update pulse signal step_upd is between the two timings of the state machine update pulse signal state_upd; if it is stipulated that after each phase detection is completed, the step direction, step length and delay step length are updated synchronously, then the state machine update pulse signal state_upd and the step length update pulse signal step_upd have the same timing.

[0076] In some embodiments, if the stepping direction indicates an increase in the step size, the step size is increased based on the current delay step size to obtain a calibrated delay step size. If the stepping direction indicates a decrease in the step size, the step size is subtracted from the current delay step size to obtain a calibrated delay step size.

[0077] In some embodiments, the divider 10 is an eight-division clock count, and of course it can also be modified to any division. The phase-locked sampling pulse signal pd_upd lags behind the reference pulse signal ref_tick by one clock cycle. The clocks of the state machine update pulse signal state_upd and the step update pulse signal step_upd can be set arbitrarily, and it only needs to be ensured that they are within the non-valid time of the phase-locked sampling pulse signal pd_upd and the reference pulse signal ref_tick.

[0078] The fully digital delay phase-locked loop circuit provided in the above embodiment controls the calibration logic circuit to update the stepping direction, stepping step and delay step by means of the state machine update pulse signal and the step length update pulse signal generated by the frequency divider, so as to calibrate the delay step of the numerically controlled delay line when there is no transmission of the reference pulse signal in the numerically controlled delay line, avoid the occurrence of glitches, and improve the robustness of the fully digital delay phase-locked loop circuit.

[0079] In one possible implementation, Figure 2 Schematic diagram of a fully digital delay locked loop circuit provided in an embodiment of the present application Figure 2 ,like Figure 2 As shown, the all-digital delay phase-locked loop circuit may further include: a result register 50 ; the digitally controlled delay line 40 includes: a reference digitally controlled delay line 411 and an application digitally controlled delay line 412 .

[0080] The output end of the calibration logic circuit 30 is connected to the reference digitally controlled delay line 411, and the input end of the result register 50 is connected to the output end of the phase detector 20, which is used to store the phase detection result, so that the preset calibration software reads the phase detection result from the result register 50, and provides a calibration step for the calibration logic circuit 30 according to the phase detection result, so as to calibrate the delay step of the reference digitally controlled delay line 411 according to the calibration step; the preset calibration software is also used to calibrate the application digitally controlled delay line 412 according to the calibration step when the phase detection result after the step calibration is correct.

[0081] In this embodiment, in order to enable the all-digital delay locked loop circuit to support the function of software calibration, a result register 50 is added to the all-digital delay locked loop circuit. The result register 50 is connected to the output end of the phase detector 20, so that when the phase detector 20 outputs the phase detection result, the phase detection result is stored in the result register 50. The phase detection result will only change when the phase detection sampling pulse signal pd_upd is valid, and is a synchronization signal with the system clock. After the calibration is completed, the synchronization signal remains unchanged. The preset calibration software can read the phase detection result from the result register 50, and directly configure the calibration step sw_step at any time. The calibration logic circuit 30 generates a one-hot code according to the calibration step sw_step at an appropriate time, and controls the delay unit in the digital control delay line according to the one-hot code to update the delay step of the digital control delay line 40, and no glitch signal is generated. Then, the preset calibration software reads the new phase detection result in the result register 50, and determines whether the delay step of the digital control delay line 40 is appropriate according to the phase detection result, thereby realizing software calibration.

[0082] Furthermore, the numerically controlled delay line 40 is set as a reference numerically controlled delay line 411 and an application numerically controlled delay line 412. After the reference numerically controlled delay line 411 is calibrated using the preset calibration software, the calibration step length of the reference numerically controlled delay line 411 is used as the ideal step length of the application numerically controlled delay line 412. There is no need to calibrate the application numerically controlled delay line 412 separately. The calibrated application numerically controlled delay line 412 can be used for clock compensation, phase adjustment and other functions.

[0083] In some embodiments, the number of applied digitally controlled delay lines 412 can be set according to actual application requirements, which is not limited in this embodiment.

[0084] The all-digital delay phase-locked loop circuit provided in the above embodiment uses a all-digital delay phase-locked loop and a plurality of digitally controlled delay lines to form a minimum system. There is no need to set up a all-digital delay phase-locked loop for each digitally controlled delay line to calibrate each digitally controlled delay line. On the one hand, the circuit area is reduced, and on the other hand, the calibration efficiency is improved.

[0085] In one possible implementation, Figure 3 Schematic diagram of the phase detector provided in the embodiment of the present application Figure 1 ,like Figure 3 As shown, the phase detector 20 includes: a first trigger 211, a second trigger 212 and a selector 213.

[0086] The input end of the first trigger 211 serves as the second input end of the phase detector 20, the output end of the first trigger 211 is connected to the first input end of the selector 213, the second input end of the selector 213 is connected to the output end of the second trigger 212, the selection input end of the selector 213 serves as the first input end of the phase detector 20, the output end of the selector 213 is connected to the input end of the second trigger 212, and the output end of the second trigger 212 serves as the output end of the phase detector 20.

[0087] For example, Figure 4 The working waveform diagram of the phase detector provided in the embodiment of the present application is as follows: Figure 3 and Figure 4 As shown, the clock end of the first trigger 211 and the clock end of the second trigger 212 are used to receive the system clock signal sys_clk, the input end of the first trigger 211 inputs the delayed pulse signal dll_tick, the first trigger 211 continuously samples the delayed pulse signal dll_tick at each rising edge of the system clock signal sys_clk to obtain the asynchronous signal pd_rslt_pre, one input end of the selector 213 is connected to the output end of the first trigger 211 to receive the asynchronous signal pd_rslt_pre, the other input end of the selector 213 is connected to the output end of the second trigger 212 to receive the output signal, the selection input end of the selector 213 receives the phase-locked sampling pulse signal pd_upd, and selects to sample the asynchronous signal pd_rslt_pre or the output signal according to the phase-locked sampling pulse signal pd_upd.

[0088] When the phase-detection sampling pulse signal pd_upd is invalid, the second trigger 212 samples the output signal of the second trigger 21, and samples the asynchronous signal pd_rslt_pre when the phase-detection sampling pulse signal pd_upd is valid. That is, the second trigger 212 samples the asynchronous signal pd_rslt_pre only when the phase-detection sampling pulse signal pd_upd is valid, and keeps the current value unchanged at other times, thereby obtaining the synchronous signal pd_rslt as the phase-detection result.

[0089] In another possible implementation, Figure 5 Schematic diagram of the phase detector provided in the embodiment of the present application Figure 2 ,like Figure 5 As shown, the phase detector 20 includes: a first trigger 211, a second trigger 212 and a selector 213.

[0090] The selection input end of the selector 213 serves as the first input end of the phase detector 20, the first input end of the selector 213 serves as the second input end of the phase detector 20, the second input end of the selector 213 is connected to the output end of the first trigger 211, the output end of the selector 213 is connected to the input end of the first trigger 211, the output end of the first trigger 211 is also connected to the input end of the second trigger 212, and the output end of the second trigger 212 serves as the output end of the phase detector 20.

[0091] In this embodiment, one input end of the selector 213 is connected to the output end of the first trigger 211 to receive the output signal of the first trigger 211, the other input end of the selector 213 receives the delayed pulse signal dll_tick, the selection input end of the selector 213 receives the phase-locked sampling pulse signal pd_upd, and the output end of the selector 213 is connected to the input end of the first trigger 211, so that the first trigger 211 samples the delayed pulse signal dll_tick only when the phase-locked sampling pulse signal pd_upd is valid, and keeps the current value unchanged at other times, and the second trigger 212 is connected to the output end of the first trigger 211, and continuously samples the output signal of the first trigger 211 at the rising edge of each system clock signal sys_clk to obtain the synchronization signal pd_rslt.

[0092] Furthermore, more triggers may be added to the phase detector according to timing requirements, which is not limited in this embodiment.

[0093] In one possible implementation, Figure 6 A schematic diagram of a digitally controlled delay line provided in an embodiment of the present application, such as Figure 6 As shown, the digitally controlled delay line 40 includes a first delay unit 401 and a plurality of second delay units 402 .

[0094] The first delay unit 401 includes a first buffer buf_1, a first NAND gate nand_1 and a second NAND gate nand_2, and each second delay unit 402 includes a second buffer buf_2, a third NAND gate nand_3 and an AND gate and; the input end of the first buffer buf_1 is used as the input end of the digital control delay line 40, and the first buffer buf_1 and the second buffers buf_2 in the plurality of second delay units 402 are connected in series in sequence; the output end of the first buffer buf_1 is connected to the first input end of the first NAND gate nand_1, the output end of the first NAND gate nand_1 is connected to the first input end of the second NAND gate nand_2, and the second NAND gate nand_3 is connected to the first input end of the second NAND gate nand_2. The output end of nd_2 serves as the output end of the digitally controlled delay line 40; the second buffer buf_2 in each second delay unit 402 is connected to the first input end of the corresponding third NAND gate nand_3, and the output end of the third NAND gate nand_3 is connected to the first input end of the corresponding AND gate and; the second input end of each AND gate and is connected to the output end of the next AND gate and, the second input end of the last AND gate and is a preset high level, and the output end of the first AND gate and is connected to the second input end of the second NAND gate nand_2; the second input end of the first NAND gate nand_1 and the second input end of the third NAND gate nand_3 serve as the control end of the digitally controlled delay line 40.

[0095] In this embodiment, the specific connection relationship between the first delay unit 401 and the second delay unit 402 is as follows: Figure 6 As shown, the second input end of the first NAND gate nand_1 in the first delay unit 401 and the second input end of the third NAND gate nand_3 in the second delay unit 402 are used to receive an enable signal to control the conduction of the corresponding delay units, and the one-hot code generated by the calibration logic circuit 30 controls the conduction of the first delay unit 401 and one of the multiple second delay units 402.

[0096] In the second delay unit 402, the third NAND gate nand_3 is a fixed delay on the delay path, the second buffer buf_2 and the gate and are effective delays on the delay path, and when the enable signal of one delay unit is 1 and the enable signals of other delay units are 0, the length of the digitally controlled delay line 40 is the delay path from the first delay unit to the delay unit whose enable signal is 1.

[0097] The delay calculation formula of the CNC delay line can be expressed as:

[0098] T = m × (t buf_2 + t and ) + t buf_1 + t nand_1 + t nand_2 (m>0)

[0099] T = t buf_1 + t nand_1 + t nand_2 (m=0)

[0100] Wherein, m is the number of effective delay units in the digitally controlled delay line.

[0101] In some embodiments, the sum of the delays of the first buffer buf_1, the first NAND gate nand_1, and the second NAND gate nand_2 can be approximately equal to the sum of the second buffer buf_2 and the AND gate and, so that the delays of each delay unit are approximately equal, thereby improving the linearity of the digital control delay line. The delay calculation formula can be expressed as: T = (m+1) × (t buf_2 +t and ).

[0102] In some embodiments, the structure of the digitally controlled delay line is not limited to the above structure, and the buffer, NAND gate and AND gate can be replaced by other devices without changing the logic, and it is only necessary to ensure that the output logic is the same. Among them, the buffer only has a delay function and no logic function, so it can be greatly changed, such as replaced by two inverters, etc., which is not limited in this embodiment.

[0103] In the all-digital delay phase-locked loop circuit provided by the above embodiment, the delays of the delay units in the digitally controlled delay line are approximately equal, which improves the linearity of the digitally controlled delay line, and adopts a hot unique code control mechanism to facilitate the calibration of the control logic and the setting of any delay time.

[0104] Based on the all-digital delay locked loop circuit provided in the above embodiment, an embodiment of the present application further provides a calibration method applied to the all-digital delay locked loop circuit. Figure 7 A schematic diagram of a calibration method for a fully digital delay locked loop circuit provided in an embodiment of the present application Figure 1 ,like Figure 7 As shown, the method may include:

[0105] S101. When the phase-comparison sampling pulse signal is valid, the delayed pulse signal is sampled to obtain the phase-comparison result of the reference pulse signal and the delayed pulse signal.

[0106] In this embodiment, the delayed pulse signal dll_tick is sampled by the phase detector when the phase detection sampling pulse signal pd_upd is valid, so as to obtain a phase detection result that can characterize the phase delay relationship between the reference pulse signal ref_tick and the delayed pulse signal dll_tick.

[0107] In some embodiments, the phase detection result is 1, indicating that the phase delay between the reference pulse signal ref_tick and the delayed pulse signal dll_tick is less than the preset delay, and the phase detection result is 0, indicating that the phase delay between the reference pulse signal ref_tick and the delayed pulse signal dll_tick is greater than the preset delay.

[0108] S102, determining the delay step of the numerically controlled delay line according to the phase detection result, the step direction and the step length, wherein the step direction is used to indicate an increase or decrease in the delay step, and the step length is used to indicate an increase or decrease in the length of the delay step.

[0109] In this embodiment, the calibration logic circuit determines the stepping direction according to the phase detection result, and adjusts the current step length of the digitally controlled delay line in the stepping direction according to the step length based on the current step length of the digitally controlled delay line to obtain the delay step length of the digitally controlled delay line.

[0110] In some embodiments, if the phase detection result is 1, the phase delay needs to be increased, the stepping direction is determined to be increasing, and the stepping length is increased based on the current step length of the numerically controlled delay line to obtain the delay step length. If the phase detection result is 0, the phase delay needs to be reduced, the stepping direction is determined to be decreasing, and the stepping length is reduced based on the current step length of the numerically controlled delay line to obtain the delay step length.

[0111] S103, calibrating the digital controlled delay line according to the delay step length to calibrate the delay of the delayed pulse signal of the digital controlled delay line, wherein the delay step length indicates the number of effective delay units in the digital controlled delay line.

[0112] In this embodiment, the calibration logic circuit generates a one-hot code according to the calculated delay step, and sends the one-hot code to the numerically controlled delay line so that a delay unit on the numerically controlled delay line is turned on. From the first delay unit of the numerically controlled delay line to the turned-on delay unit, effective delay units are used, and the number of effective delay units is equal to the delay step. The numerically controlled delay line delays the reference pulse signal ref_tick based on the effective delay unit to obtain a delayed pulse signal dll_tick after calibrated phase delay.

[0113] The calibration method of the all-digital delay phase-locked loop circuit provided in the above embodiment calibrates the delay step of the digitally controlled delay line based on the step direction and the step length, which can effectively shorten the calibration time and improve the calibration accuracy.

[0114] In one possible implementation, Figure 8 A schematic diagram of a calibration method for a fully digital delay locked loop circuit provided in an embodiment of the present application Figure 2 ,like Figure 8As shown, the process of determining the delay step length of the numerically controlled delay line according to the phase detection result, the step direction, and the step length in S102 may include:

[0115] S201, judging whether the step change direction indicated by the phase comparison result is consistent with the step direction.

[0116] S202: Update the stepping direction and stepping length according to the judgment result.

[0117] S203: Determine a delay step length according to the updated step direction and the target step length, where the target step length is the step length before the update or the step length after the update.

[0118] In some embodiments, the above-mentioned S202 process of updating the stepping direction and stepping length according to the judgment result may include: if the step length change direction is consistent with the stepping direction, determining that the stepping direction and stepping length remain unchanged; if the step length change direction is inconsistent with the stepping direction, updating the stepping direction to the opposite direction, reducing the stepping length, and determining the updated stepping length.

[0119] In this embodiment, it is determined whether the step change direction indicated by the phase comparison result is consistent with the current step direction. If they are consistent, the step direction and step length do not need to be changed. If they are inconsistent, the step direction needs to be changed and the step length is reduced. In some embodiments, each time the step length is reduced, it can be reduced according to a preset ratio.

[0120] For example, if the phase detection result is 1, that is, the delay is small, the step size changes direction to increase. If the current step direction is also increasing, the step direction and step size remain unchanged. If the current step direction is decreasing, the step direction is updated to increase, and the step size is reduced by a preset ratio.

[0121] If the phase detection result is 0, that is, the delay is large, the step length changes direction to decrease. If the current step direction is also decreasing, the step direction and step length remain unchanged. If the current step direction is increasing, the step direction is updated to decrease, and the step length is reduced by a preset ratio.

[0122] Among them, after updating the step length, the delay step length of the CNC delay line can be calibrated according to the updated step length, or the delay step length of the CNC delay line can be calibrated according to the step length before the update. The updated step length is used to calibrate the delay step length after the next phase detection result comes out.

[0123] In a possible implementation, the method may further include: repeatedly updating the step direction and the step length multiple times until the step length is equal to 1, and then ending the calibration process.

[0124] In this embodiment, if the step change direction and the step direction are inconsistent during each calibration process, the step length needs to be reduced. Therefore, during multiple repeated calibrations, when the step length is reduced to 1, the delayed step length is updated based on the last updated step direction and step length 1 until the step change direction indicated by the phase detection result is reversed, and the calibration is determined to be completed.

[0125] In this embodiment, after the step length is reduced to 1, the calibration is continued based on the step direction and the step length 1 until the phase detection result is flipped, that is, when the step length change direction indicated by the phase detection result is inconsistent with the step direction, the calibration is determined to be completed. Specifically, if the step length change direction indicated by the phase detection result is consistent with the step direction, the delay step length is continued to be calibrated based on the step direction and the step length 1 until the step length change direction indicated by the phase detection result is inconsistent with the step direction, that is, when the phase detection result is flipped, so that the delay step length of the digital control delay line reaches a critical point, and the calibration process is terminated. The calibration process can adjust the delay step length of the digital control delay line to a situation where the delay step length is one delay unit smaller than the system clock period.

[0126] The following is an exemplary description by taking the example of calibrating the delay step length of the digital controlled delay line according to the updated step length.

[0127] For example, Fig. 9 A schematic diagram of an update of a state machine provided in an embodiment of the present application, Fig.10 The working waveform diagram of the calibration logic circuit provided in the embodiment of the present application is as follows: Fig. 9 and Fig.10 As shown, the reference clock signal in this embodiment is 5ns, the digital control delay line contains 64 delay units, the delay time of each delay unit is 150ps, and after the calibration logic circuit is reset, the initial delay step length of the digital control delay line is set to 27, the step direction is set to increase, and the step length is set to 27, that is, 27 delay units are added each time. Setting a reasonable step length according to the number of delay units in the digital control delay line can avoid deadlock during the step search process.

[0128] Among them, dll_en is the enable signal of the fully digital delay phase-locked loop circuit. When this signal is 0, the state machine in the calibration logic circuit will be reset to the IDLE state; pd_rslt is the synchronization signal corresponding to the phase-locked result, state_upd is the state machine update pulse signal, cali_sts is the step state of the state machine, including the step direction and step length, step_upd is the step length update pulse signal, and cali_step is the delay step length of the CNC delay line.

[0129] Whenever the phase detection result of the phase detector is valid, the calibration logic circuit reads the phase detection result, such as Fig.10As shown, if the step change direction indicated by the first phase detection result is consistent with the step direction, the step direction and the step length will not be changed, the step direction is still increase (INC), the step length is still 27, and the step length is increased by 27 on the basis of the initial delay step length of 27, so the calibrated delay step length is 54.

[0130] If the step change direction indicated by the second phase detection result is inconsistent with the step direction, the step direction is updated to decrease (DEC), and the step length is reduced by one third, that is, the step length is updated to 9. The step length 9 is subtracted from the delay step length 54 to obtain the calibrated delay step length 45.

[0131] If the step change direction indicated by the third phase detection result is consistent with the step direction, the step direction is still decrease (DEC), the step length is still 9, and the step length 9 is subtracted from the delay step length 45 to obtain the calibrated delay step length 36.

[0132] If the step change direction indicated by the fourth phase detection result is inconsistent with the step direction, the step direction is updated to increase (INC), and the step step is reduced by one third, that is, the step step is updated to 3, and the step step 3 is added to the delay step 36 to obtain the calibrated delay step 39.

[0133] If the step change direction indicated by the fifth phase detection result is consistent with the step direction, the step direction is still increase (INC), the step length is still 3, and the step length 3 is added to the delay step length 36 to obtain the calibrated delay step length 42.

[0134] If the step change direction indicated by the sixth phase detection result is inconsistent with the step direction, the step direction is updated to decrease (DEC), and the step step is reduced by one third, that is, the step step is updated to 1, and the step step 1 is subtracted from the delay step 42 to obtain the calibrated delay step 41.

[0135] If the step change direction indicated by the seventh phase detection result is consistent with the step direction, the step direction is still decreasing (DEC), the step length is still 1, and the step length 1 is subtracted from the delay step length 41 to obtain the calibrated delay step length 40.

[0136] The step length change direction indicated by the seventh phase detection result is inconsistent with the step direction, that is, after the step length is equal to 1, the step length is reduced twice, the phase detection result is reversed, and the calibration process ends (DONE).

[0137] It can be seen that when the delay step is equal to 41, the delay time is less than the preset delay, and when the step length is equal to 40, the delay time is greater than the preset delay. It is determined that the delay step of the CNC delay line has reached the critical point and the calibration process is completed.

[0138] It should be noted that in order to avoid the increase in the step size of the state machine, which will cause the delay step size to exceed the number of delay units, it is necessary to change the step direction and step size when the delay step size adjusted based on the current step direction and step size exceeds the number of delay units.

[0139] In some embodiments, the state machine has multiple step states, each step state consists of a step direction and a step length, the step directions alternate in sequence, and the step length decreases in sequence. If the delay step length adjusted based on the current step direction and step length exceeds the number of delay units, a step state that is consistent with the current step direction and the delay step length adjusted based on the corresponding step length will not exceed the number of delay units is selected from the multiple step states, or a step state that is opposite to the current step direction and has a step length smaller than the current step length is selected from the multiple step states.

[0140] If there is no smaller step length in the current step direction, a step state opposite to the current step direction and with a step length smaller than the current step length is selected.

[0141] For example, Fig. 9 As shown, the initial step state is INC27. When the step change direction indicated by the phase detection result is consistent with the step direction, the delay step needs to be increased from 27 to 54. If the step change direction indicated by the phase detection result is still consistent with the step direction when the delay step is 54, the delay step cannot be increased from 54 to 81 (the number of delay units is 64). The step state INC27 makes the delay step of the numerical control delay line reach the maximum value of 54 (DLL_Length / 32*27), so the step state jumps to INC3. When the step state is INC3, if the step change direction indicated by the phase detection result is still consistent with the step direction when the delay step reaches 63 (DLL_Length-1), the step state jumps to DEC1.

[0142] In a possible embodiment, the method may further include:

[0143] The bias step is added to the delay step as the delay step.

[0144] In this embodiment, after the step length is equal to 1, calibration is continued to wait for the phase detection result to flip, and the final delay step length is obtained. Due to the existence of the setup time, the phase detection result of the phase detector will have deviations, and the obtained calibration result is actually smaller. Therefore, when the state machine jumps to the DONE stage, the delay step length cali_step will be corrected by using the offset dll_prd_ofst on the basis of the delay step length cali_step to compensate for the influence of the setup time of the trigger in the phase detector, and the final delay step length is obtained.

[0145] The calibration method of the all-digital delay phase-locked loop circuit provided in the above embodiment adopts a step search algorithm. Compared with the calibration method directly adopting a fixed step length, the calibration time is shortened and the calibration accuracy is guaranteed. Compared with the successive approximation algorithm such as the binary method, the step length is increased on the configurable initial step length to avoid the deadlock phenomenon. In addition, the step search is very adaptable to the digital control delay line controlled by the one-hot code, and there is no need to consider the logic conversion problem during the successive approximation. The step length of the step search algorithm can also be flexibly configured to adapt to different situations.

[0146] Furthermore, adding an offset step length to the delay step length as the final delay step length is equivalent to adding an offset to the phase detection result, thereby reducing the error of the phase detector and improving the phase detection accuracy.

[0147] The above is only a specific implementation of the present application, but the protection scope of the present application is not limited thereto. Any technician familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed in the present application, which should be included in the protection scope of the present application. Therefore, the protection scope of the present application should be based on the protection scope of the claims.

Claims

1. A fully digital delay locked loop circuit, characterized in that: The circuit comprises: a frequency divider, a phase detector, a calibration logic circuit and a digitally controlled delay line; The input end of the frequency divider is used to receive a reference clock signal, and the first output end of the frequency divider is connected to the input end of the digitally controlled delay line to provide a reference pulse signal for the digitally controlled delay line; The second output end of the frequency divider is connected to the first input end of the phase detector, and is used to provide a phase detection sampling pulse signal for the phase detector, wherein the phase detection sampling pulse signal and the reference pulse signal are two frequency division signals of the reference clock signal; The second input end of the phase detector is connected to the output end of the digitally controlled delay line, and is used to receive a delayed pulse signal after the digitally controlled delay line delays the reference pulse signal; The output end of the phase detector is connected to the input end of the calibration logic circuit, and is used to provide the calibration logic circuit with a phase detection result of the reference pulse signal and the delayed pulse signal; The output end of the calibration logic circuit is connected to the control end of the digitally controlled delay line, and is used to calibrate the delay step of the digitally controlled delay line according to the phase-locked result so as to calibrate the delay of the delayed pulse signal. The delay step indicates the number of effective delay units in the digitally controlled delay line.

2. The all-digital delay locked loop circuit according to claim 1, characterized in that: The third output terminal of the frequency divider is connected to the first control terminal of the calibration logic circuit, and is used to provide a state machine update pulse signal to the calibration logic circuit, so that the calibration logic circuit updates a step direction and a step length based on the state machine update pulse signal, wherein the step direction is used to indicate an increase or decrease in the delay step length, and the step length is used to indicate an increase or decrease in the length of the delay step length; The fourth output terminal of the frequency divider is connected to the second control terminal of the calibration logic circuit, and is used to provide a step update pulse signal to the calibration logic circuit, so that the calibration logic circuit calibrates the delay step of the digitally controlled delay line according to the step direction and the step size based on the step update pulse signal.

3. The all-digital delay locked loop circuit according to claim 1, characterized in that: The circuit further comprises: a result register, the digitally controlled delay line comprises: a reference digitally controlled delay line and an application digitally controlled delay line; The output end of the calibration logic circuit is connected to the reference digitally controlled delay line; The input end of the result register is connected to the output end of the phase detector, and is used to store the phase detection result, so that the preset calibration software reads the phase detection result from the result register, and provides a calibration step length for the calibration logic circuit according to the phase detection result, so as to calibrate the delay step length of the reference digital controlled delay line according to the calibration step length; The preset calibration software is also used to calibrate the applied digital controlled delay line according to the calibration step length when the phase discrimination result after the step length calibration is correct.

4. The all-digital delay locked loop circuit according to claim 1, characterized in that: The phase detector comprises: a first trigger, a second trigger and a selector; The input end of the first trigger serves as the second input end of the phase detector, the output end of the first trigger is connected to the first input end of the selector, the second input end of the selector is connected to the output end of the second trigger, the selection input end of the selector serves as the first input end of the phase detector, the output end of the selector is connected to the input end of the second trigger, and the output end of the second trigger serves as the output end of the phase detector.

5. The all-digital delay locked loop circuit according to claim 1, characterized in that: The phase detector comprises: a first trigger, a second trigger and a selector; The selection input end of the selector serves as the first input end of the phase detector, the first input end of the selector serves as the second input end of the phase detector, the second input end of the selector is connected to the output end of the first trigger, the output end of the selector is connected to the input end of the first trigger, the output end of the first trigger is also connected to the input end of the second trigger, and the output end of the second trigger serves as the output end of the phase detector.

6. The all-digital delay locked loop circuit according to claim 1, characterized in that: The digitally controlled delay line comprises a first delay unit and a plurality of second delay units; The first delay unit includes a first buffer, a first NAND gate and a second NAND gate, and each of the second delay units includes a second buffer, a third NAND gate and an AND gate; The input end of the first buffer is used as the input end of the digitally controlled delay line, and the first buffer and the second buffers in the plurality of second delay units are sequentially connected in series; The output end of the first buffer is connected to the first input end of the first NAND gate, the output end of the first NAND gate is connected to the first input end of the second NAND gate, and the output end of the second NAND gate serves as the output end of the digitally controlled delay line; The second buffer in each of the second delay units is connected to the first input terminal of the corresponding third NAND gate, and the output terminal of the third NAND gate is connected to the first input terminal of the corresponding AND gate; The second input terminal of each AND gate is connected to the output terminal of the next AND gate, the second input terminal of the last AND gate is a preset high level, and the output terminal of the first AND gate is connected to the second input terminal of the second NAND gate; The second input end of the first NAND gate and the second input end of the third NAND gate serve as control ends of the digitally controlled delay line.

7. A calibration method for a fully digital delay locked loop circuit, characterized in that: Applied to the all-digital delay locked loop circuit according to any one of claims 1 to 6, the method comprising: When the phase-comparison sampling pulse signal is valid, sampling the delayed pulse signal to obtain the phase-comparison result of the reference pulse signal and the delayed pulse signal; Determine the delay step of the numerically controlled delay line according to the phase detection result and the step direction and step length, wherein the step direction is used to indicate an increase or decrease in the delay step, and the step length is used to indicate an increase or decrease in the length of the delay step; The digitally controlled delay line is calibrated according to the delay step length to calibrate the delay of the delayed pulse signal of the digitally controlled delay line, and the delay step length indicates the number of effective delay units in the digitally controlled delay line.

8. The calibration method according to claim 7, characterized in that: Determining the delay step length of the numerically controlled delay line according to the phase detection result, the step direction, and the step length comprises: Determining whether the step change direction indicated by the phase detection result is consistent with the step direction; Update the step direction and the step length according to the judgment result; The delay step length is determined according to the updated step direction and the target step length, and the target step length is the step length before the update or the step length after the update.

9. The calibration method according to claim 8, characterized in that: The updating of the step direction and the step length according to the judgment result includes: If the step length change direction is consistent with the step direction, determining that the step direction and the step length remain unchanged; If the step length change direction is inconsistent with the step direction, the step direction is updated to the opposite direction, the step length is reduced, and the updated step length is determined.

10. The calibration method according to claim 9, characterized in that: The method further comprises: Repeat updating the step direction and the step length multiple times until the step length is equal to 1, and update the delay step length based on the last updated step direction and step length 1 until the step length change direction indicated by the phase detection result is reversed, thereby ending the calibration process.

11. The calibration method according to claim 8, characterized in that: The method further comprises: An offset step is added to the delay step as the delay step.

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