An active inductor for DC power carrier communication

Abstract

The present invention discloses an active inductor for DC power supply carrier communication, which is an integrated circuit and includes first, second, third and fourth level circuits. The first level circuit includes a floating end active inductor L1 and a grounded end active inductor L2. Both ends of L1 are connected to VP and VOP correspondingly to block the positive signal AC part after rectification and retain the positive DC signal Iin. Both ends of L2 are connected to VN and VON correspondingly to block the negative signal AC part after rectification and retain the negative DC signal Iin. The voltage sampling part of the second level circuit L2, the third level circuit is the carrier communication bus signal ±△V low level period detection part, and the fourth level circuit is the low level conduction part. The bus signal ±△V is compared with the reference voltage VREF to control the sampling voltage to drive the fourth level circuit to turn on or off. The present application realizes the integration inside the chip with the advantages of low conduction voltage drop and large equivalent inductance.

Description

Technical Field

[0001] The present invention relates to application fields related to direct current power supply carrier communication, and in particular to an active inductor used for direct current power supply carrier communication. Background Art

[0002] In the application field of DC power carrier communication, the host and slave communicate and power are supplied through twisted pair cables. When taking power from the bus, in order to prevent the data signal on the bus from being absorbed or filtered out, differential mode inductors are usually used to block the AC signal and realize power transmission.

[0003] In conventional two-bus DC carrier communication applications, differential mode inductors are used to block the AC signals on the bus, which usually brings the following problems: large size and cannot be applied to miniaturized usage scenarios; expensive and high cost; when the oscillation frequency falls within the frequency range that can be recognized by the human ear, there will be periodic noise; as the current increases, it will cause the inductor to be magnetically saturated, thereby reducing the inductance value.

[0004] Existing active inductors are mainly used in the radio frequency field to improve the gain flatness and signal modulation of the amplifier. Due to factors such as the large size and high price of differential mode inductors, their application is limited. There are few examples of their application in the oscillation frequency range of 1K~1M and the ability to achieve power transmission at the same time. Summary of the invention

[0005] The purpose of the present invention is to provide an active inductor for DC power carrier communication, which solves the problems of the prior art and can be integrated on-chip and has a low-cost active inductor solution with a wider range of applications and performance.

[0006] To achieve the above technical objectives, the present invention provides an active inductor for DC power carrier communication, which is an integrated circuit, wherein: the integrated circuit has a first-stage circuit STAGE1, a second-stage circuit STAGE2, a third-stage circuit STAGE3, and a fourth-stage circuit STAGE4; the first-stage circuit STAGE1 includes: a floating-end active inductor L1 and a grounded-end active inductor L2, the two ends of the floating-end active inductor L1 are correspondingly connected to a positive input voltage VP and a positive output voltage VOP to block the AC part of the rectified positive signal and retain the positive DC signal Iin, and the two ends of the grounded-end active inductor L2 are correspondingly connected to a negative input voltage VN and a negative output voltage VON. Corresponding connections are made to block the AC part of the rectified negative signal and retain the negative DC signal -Iin; the second-stage circuit STAGE2 is the voltage sampling part of the ground active inductor L2, the third-stage circuit STAGE3 is the carrier communication bus signal ±△V low-level period detection part, and the fourth-stage circuit STAGE4 is the low-level conduction part; the third-stage circuit STAGE3 samples the bus signal ±△V and compares it with the reference voltage VREF to control the sampling voltage of the second-stage circuit STAGE2 to drive the fourth-stage circuit STAGE4 to turn on or off, so as to draw a constant current from the bus during the low-level period of the bus signal ±△V.

[0007] The present invention provides an active inductor for DC power carrier communication, which solves the technical problem of twisted pair bus DC carrier communication. Instead of blocking AC signals through conventional passive differential mode inductors, an active inductor structure that can be integrated inside a chip and is tunable is adopted. The active inductor has the advantages of low on-state voltage drop, large equivalent inductance, strong current capacity, high reliability, no noise caused by mechanical vibration, low cost, small size, etc.

[0008] As a further improvement, the floating-end active inductor L1 includes: a first transistor M1, a first resistor R1, a second resistor R2 and a first capacitor C1, the drain and source of the first transistor M1 are respectively connected to the positive input voltage VP and the positive output voltage VOP, and the gate of the first transistor M1 is respectively connected to the positive input voltage VP and the positive output voltage VOP via the first resistor R1 and the second resistor R2; the grounded-end active inductor L2 includes: a second transistor M2, a third resistor R3, a fourth resistor R4 and a second capacitor C2, the source and drain of the second transistor M2 are respectively connected to the negative input voltage VN and the negative output voltage VON, and the gate of the second transistor M2 is respectively connected to the negative input voltage VN and the negative output voltage VON via the fourth resistor R4 and the third resistor R3.

[0009] As a further improvement, two ends of the first capacitor C1 are respectively connected to the source and gate of the first transistor M1 , and two ends of the second capacitor C2 are respectively connected to the source and gate of the second transistor M2 .

[0010] As a further improvement, the first stage circuit STAGE1 further includes a third capacitor C3, and two ends of the third capacitor C3 are respectively connected to the source of the first transistor M1 and the drain of the second transistor M2.

[0011] As a further improvement, the second-stage circuit STAGE2 includes an operational amplifier OP, the non-inverting input terminal of the operational amplifier OP is connected to the gate of the second transistor M2, and the fourth-stage circuit STAGE4 includes a third transistor M3 and an impedance Z1; the inverting input terminal of the operational amplifier OP is connected to the signal output terminal and to the gate of the third transistor M3, the source of the third transistor M3 is connected to the negative input voltage VN, and the drain of the third transistor M3 is connected to the positive input voltage VP via the impedance Z1.

[0012] As a further improvement, the second stage circuit STAGE2 samples the gate-source voltage VGS of the second transistor M2 in the first stage circuit STAGE1 to drive the third transistor M3 in the fourth stage circuit STAGE4 to be turned on or off.

[0013] As a further improvement, the third-stage circuit STAGE3 includes: a comparator COMP, a fifth resistor R5, a sixth resistor R6 and a switch K1, the positive input terminal of the comparator COMP is connected to the reference voltage VREF, and the negative input terminal of the comparator COMP is correspondingly connected to the positive input voltage VP and the negative input voltage VN via the fifth resistor R5 and the sixth resistor R6 respectively; the signal output terminal of the operational amplifier OP is connected to the gate of the third transistor M3 via the switch K1, and the switch K1 includes: an input terminal connected to the signal output terminal of the operational amplifier OP, an output terminal connected to the gate of the third transistor M3, and a control terminal connected to the output terminal of the comparator COMP.

[0014] As a further improvement, the bus signal ±△V is compared with the reference voltage VREF. If the bus signal ±△V is lower than the reference voltage VREF, the switch K1 is controlled to be closed; if the bus signal ±△V is higher than the reference voltage VREF, the switch K1 is controlled to be opened.

[0015] Correspondingly, the present invention also provides a DC power carrier communication circuit, which adopts an active inductor for DC power carrier communication provided by the present invention, the negative output voltage VON is set as the reference ground of the slave, and the positive output voltage VOP is used to power the slave through the DC-DC module output voltage VCC.

[0016] As a further improvement, the output voltage VCC is equal to 5V, and output capacitors COUT are arranged at both ends of the output end of the DC-DC module, one end of the output capacitor COUT is connected to the output voltage VCC, and the other end is connected to the negative output voltage VON, the host includes: a first input end IN1, a second input end IN2, a first output end OUTA, and a second output end OUTB respectively connected to the twisted pair, and the slave includes: a first input end IN1', a second input end IN2', a first output end OUTA', and a second output end OUTB' respectively connected to the twisted pair. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figure 1 It is a schematic diagram of the basic principle of the present invention;

[0018] Figure 2 This is a connection diagram of the internal circuit of the active inductor of the present invention;

[0019] Figure 3 It is a frequency response simulation diagram of the input impedance of the present invention;

[0020] Figure 4 This is the working waveform diagram of the present invention;

[0021] Figure 5 This is a diagram showing an application example of the carrier communication circuit of the present invention. DETAILED DESCRIPTION

[0022] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0023] like Figures 1 to 4As shown, the present invention provides an active inductor for DC power carrier communication. In the carrier communication, the host and the slave communicate and are connected for power supply through a twisted pair bus, wherein: the power supply connection circuit also includes: a rectifier bridge and an active inductor. The bus DC voltage VDC on the bus is output through the rectifier bridge and forms a positive input voltage VP and a negative input voltage VN of the main circuit of the active inductor. The positive output voltage VOP and the negative output voltage VON of the main circuit of the active inductor form an output DC power supply voltage Vout and power the slave.

[0024] The main circuit of the active inductor is an integrated circuit, which has a first-stage circuit STAGE1, a second-stage circuit STAGE2, a third-stage circuit STAGE3, and a fourth-stage circuit STAGE4; the first-stage circuit STAGE1 includes: a floating-end active inductor L1 and a grounded-end active inductor L2, wherein both ends of the floating-end active inductor L1 are correspondingly connected to a positive input voltage VP and a positive output voltage VOP to block the positive signal AC part after rectification and retain the positive DC signal Iin, and both ends of the grounded-end active inductor L2 are correspondingly connected to a negative input voltage VN and a negative output voltage VON to block the negative signal AC part after rectification. The AC part of the signal is blocked, and the negative DC signal -Iin is retained; the second-stage circuit STAGE2 is the voltage sampling part of the ground active inductor L2, the third-stage circuit STAGE3 is the carrier communication bus signal ±△V low-level period detection part, and the fourth-stage circuit STAGE4 is the low-level conduction part; the third-stage circuit STAGE3 samples the bus signal ±△V and compares it with the reference voltage VREF to control the sampling voltage of the second-stage circuit STAGE2 to drive the fourth-stage circuit STAGE4 to be turned on or off, so as to draw a constant current from the bus during the low-level period of the bus signal ±△V.

[0025] The present invention provides an active inductor for DC power carrier communication, which solves the technical problem of twisted pair bus DC carrier communication. Instead of blocking AC signals through conventional passive differential mode inductors, an active inductor structure that can be integrated inside a chip and is tunable is adopted. The active inductor has the advantages of low on-state voltage drop, large equivalent inductance, strong current capacity, high reliability, no noise caused by mechanical vibration, low cost, small size, etc.

[0026] As a further improvement, the floating-end active inductor L1 includes: a first transistor M1, a first resistor R1, a second resistor R2 and a first capacitor C1, the drain and source of the first transistor M1 are respectively connected to the positive input voltage VP and the positive output voltage VOP, and the gate of the first transistor M1 is respectively connected to the positive input voltage VP and the positive output voltage VOP via the first resistor R1 and the second resistor R2; the grounded-end active inductor L2 includes: a second transistor M2, a third resistor R3, a fourth resistor R4 and a second capacitor C2, the source and drain of the second transistor M2 are respectively connected to the negative input voltage VN and the negative output voltage VON, and the gate of the second transistor M2 is respectively connected to the negative input voltage VN and the negative output voltage VON via the fourth resistor R4 and the third resistor R3.

[0027] As a further improvement, two ends of the first capacitor C1 are respectively connected to the source and gate of the first transistor M1 , and two ends of the second capacitor C2 are respectively connected to the source and gate of the second transistor M2 .

[0028] As a further improvement, the first stage circuit STAGE1 further includes a third capacitor C3, and two ends of the third capacitor C3 are respectively connected to the source of the first transistor M1 and the drain of the second transistor M2.

[0029] As a further improvement, the integrated circuit also has a second-stage circuit STAGE2 and a fourth-stage circuit STAGE4, ​​the second-stage circuit STAGE2 includes an operational amplifier OP, the non-inverting input terminal of the operational amplifier OP is connected to the gate of the second transistor M2, and the fourth-stage circuit STAGE4 includes a third transistor M3 and an impedance Z1; the inverting input terminal of the operational amplifier OP is connected to the signal output terminal and to the gate of the third transistor M3, the source of the third transistor M3 is connected to the negative input voltage VN, and the drain of the third transistor M3 is connected to the positive input voltage VP via the impedance Z1.

[0030] As a further improvement, the second stage circuit STAGE2 samples the gate-source voltage VGS of the second transistor M2 in the first stage circuit STAGE1 to drive the third transistor M3 in the fourth stage circuit STAGE4 to be turned on or off.

[0031] As a further improvement, a third-stage circuit STAGE3 is further provided between the second-stage circuit STAGE2 and the fourth-stage circuit STAGE4, ​​and the third-stage circuit STAGE3 includes: a comparator COMP, a fifth resistor R5, a sixth resistor R6 and a switch K1, the positive input terminal of the comparator COMP is connected to the reference voltage VREF, and the negative input terminal of the comparator COMP is correspondingly connected to the positive input voltage VP and the negative input voltage VN via the fifth resistor R5 and the sixth resistor R6 respectively; the signal output terminal of the operational amplifier OP is connected to the gate of the third transistor M3 via the switch K1, and the switch K1 includes: an input terminal connected to the signal output terminal of the operational amplifier OP, an output terminal connected to the gate of the third transistor M3, and a control terminal connected to the output terminal of the comparator COMP.

[0032] As a further improvement, the bus signal ±△V is compared with the reference voltage VREF (the signal after voltage division and sampling by the fifth and sixth resistors R5 and R6 is compared with VREF). If the bus signal ±△V is lower than the reference voltage VREF, the switch K1 is controlled to be closed; if the bus signal ±△V is higher than the reference voltage VREF, the switch K1 is controlled to be opened.

[0033] When the host and slave communicate and power the device through twisted pair cables, the bus power supply must not affect the communication quality. The "DC isolation" characteristic of the inductor must be used to block the AC signal, and the DC component must be used to power the slave. In view of the large size and high cost of passive inductors, and the complex structure and low output power of other active inductors, the patent of this invention provides a bus power supply method, using a rectifier bridge and a new active inductor structure, which can be integrated into the chip. While the bus is powering the slave, it does not affect the communication quality of the signal.

[0034] It can be understood by those skilled in the art that the technical solution provided by the present invention is only a principle circuit and its application, and any circuit, device, apparatus or structure based on or equivalent to the principle and its corresponding transformations belong to the scope disclosed by the present invention. Similarly, those skilled in the art can make equivalent or corresponding replacements for the electronic devices in the principle circuit of the present invention according to the principles disclosed by the present invention. For example, if the transistor in the present invention is an NMOS tube, those skilled in the art can replace it with a PMOS tube and directly adjust the connection relationship of its poles. These equivalent transformations all belong to the content and scope disclosed by the present invention, and also belong to the embodiments covered by the claims of the present invention and are protected by the present invention.

[0035] In a preferred embodiment of the present invention, Figure 1In the figure shown, ±△v is the AC signal on the bus, VDC is the DC voltage of the bus, VN is the input voltage signal of the active inductor L2 at the ground end, VON is the output voltage signal of the active inductor L1 at the ground end, VOP is the output voltage signal of the active inductor at the floating end, and Vout is the output DC power supply for the subsequent stage. There is also an AC coupling capacitor in front of the slave, and the signal is received by the slave through the AC coupling capacitor.

[0036] Can Figure 1 The active inductor is regarded as a 4-port network, VP and VN are input ports, and VOP and VON are output ports. This patent realizes that the AC signal of a certain frequency range passing through the VP and VN ports is isolated by the active inductor, which is manifested as the DC bias power supply Vout = VOP-VON measured at the output ports VOP and VON, and the AC component of the loop current is very small.

[0037] Figure 2 for Figure 1 The schematic diagram of the active inductor part, and the following are the explanations of each level in the figure:

[0038] The first stage circuit STAGE1 is composed of the floating active inductor L1 and the grounded active inductor L2. The floating active inductor L1 includes the first transistor M1, the first and second resistors R1, R2 and the first capacitor C1, which are used to block the positive AC part of the rectified signal and retain the positive DC signal; the grounded active inductor L2 includes the second transistor M2, the third and fourth resistors R3, R4 and the second capacitor C2, which are used to block the negative AC part of the rectified signal and retain the negative DC signal.

[0039] The second stage circuit STAGE2 is the VGS voltage sampling part of the second transistor M2, samples the voltage of the second capacitor C2, namely the VGS voltage of the second transistor M2, through the source follower, and drives the subsequent third transistor M3 to turn on or off.

[0040] The third stage circuit STAGE3 is the bus signal low level period detection part. It samples the bus signal through the voltage divider resistor and compares it with the reference voltage VREF. If the signal is lower than the reference voltage VREF, the control switch K1 is closed; if the signal is higher than the reference voltage VREF, the control switch K1 is opened.

[0041] The third stage circuit STAGE4 is a low level period conduction part, which includes a third transistor M3 and an impedance Z1, and functions to draw a constant current from the bus during the low level period of the signal.

[0042] The first stage circuit STAGE1 is an active inductor, and its principle is as follows:

[0043] VP to VOP is an active inductor at the floating end. By reasonably setting the values ​​of resistors R1 and R2, Vgs of M1 is greater than Vth and works in the saturation region. The filter capacitor C1 makes the Vgs voltage of M1 change smoothly. Therefore, when the VP end is alternating, Ids of M1 remains unchanged as its Vds changes. At this time, Id and Vds are relatively independent, that is, an ac signal is input but the drain current does not change significantly.

[0044] At this time, the input impedance of the STAGE1 circuit is high impedance within the AC range, and its input impedance Zin formula is as follows:

[0045]

[0046] Zp is its open-loop impedance, R2 and its symbol represent a parallel relationship, and the expression is as follows:

[0047]

[0048] KH (s) is its loop function, R2 and its symbol represent a parallel relationship, and the expression is as follows:

[0049]

[0050] It can be seen that the input impedance of the circuit is related to the frequency, and the circuit can be made high-impedance to the ac signal at a specific frequency by adjusting the resistance and capacitance parameters. Figure 3 As shown, when the circuit input signal is in the range of 1KHz~1MHz, the input impedance is 90dBΩ (dBΩ=20 log10(R / 1), R is the impedance value).

[0051] Similarly, VN to VON is a grounded active inductor, the principle is similar to the above, but it is a source input. Its output terminal VON is used as the reference ground potential of the load. At this time (VOP-VON) can be used as a stable DC voltage source to power the subsequent stage.

[0052] Since there will be a certain Dropout voltage passing through this active inductor, and Vout (Vout=VOP-VON) will decrease linearly with the increase of load current Iload. Since the slave requires Vout to be greater than a certain voltage value, it is necessary to reduce the Dropout voltage of the bus passing through this circuit as much as possible. The second stage circuit STAGE2 to the fourth stage circuit STAGE4 are used to solve this problem.

[0053] STAGE2 is the Vgs voltage sampling part of transistor M2. The principle is: through the voltage follower, the gate-source voltage of transistor M2 is output and the transistor is controlled to draw the same current without releasing the charge of C2.

[0054] STAGE3 is the bus signal low level cycle detection part, which is composed of resistors R5, R6, comparator COMP and reference voltage VREF. The bus signal is sampled by R5 and R6 and compared with the reference voltage VREF. When the bus is in a low level cycle, the output signal controls the switch K1 to close, and the output of STAGE2 is connected to the gate of transistor M3.

[0055] STAGE4 is the signal low level period constant current conduction part, which is composed of transistor M3 (parameters are consistent with M2) and impedance Z1. Z1 provides an impedance or clamping voltage to keep the source-drain voltage of M3 equal to the source-drain voltage of M2 when it is normally turned on in the same cycle. At this time, the Vgs and Vds voltages of transistor M3 are equal to those of transistor M2, so it can ensure that the current is drawn from the bus constant current during the low level period.

[0056] Figure 4 The relative relationship between related signals is shown. Its active inductor characteristics are reflected in the input VP and VN as AC signals of a certain frequency (the frequency must be greater than the lower limit of the frequency response of the module), and the output DC bias power supply Vout. It can be seen that the AC part has been blocked.

[0057] When |VP-VN|—|VOP-VON|> transistor turn-on voltage, transistors M1 and M2 are normally turned on, and the gate-source voltage is Vgs, and the current drawn is Iin; when |VP-VN|—|VOP-VON|< transistor turn-on voltage, the transistor is cut off, IM1=IM2=0, switch K1 is turned on to turn on transistor M3, and the current is drawn from transistor M3, and its Vgs and Vds voltages are the same as when M1 and M2 are normally turned on in the same cycle, so IM1+IM3 is equal to the input current Iin; load capacitor C3 continues to supply power to the load, and at this time the load current Iload is the average current of IM1 or IM2. The bus input current Iin is continuous and the AC ripple of the current is very small, realizing the active inductor function with low voltage difference.

[0058] Accordingly, the present invention can be applied to the scenario where an inductor is required to isolate the AC signal when two buses are powered. Figure 5 As shown, the present invention also provides a DC power carrier communication circuit, which adopts an active inductor for DC power carrier communication provided by the present invention, the negative output voltage VON is set as the reference ground of the slave, and the positive output voltage VOP is used to power the slave through the DC-DC module output voltage VCC.

[0059] As a further improvement, the output voltage VCC is equal to 5V, and output capacitors COUT are arranged at both ends of the output end of the DC-DC module, one end of the output capacitor COUT is connected to the output voltage VCC, and the other end is connected to the negative output voltage VON, the host includes: a first input end IN1, a second input end IN2, a first output end OUTA, and a second output end OUTB respectively connected to the twisted pair, and the slave includes: a first input end IN1', a second input end IN2', a first output end OUTA', and a second output end OUTB' respectively connected to the twisted pair.

[0060] like Figure 5 , this is an application example diagram of the patent of this invention. U1 is the main circuit of the active inductor introduced earlier. The bus signal passes through the rectifier bridge to obtain VP and VN, which are input to U1 and output VOP and VON, where VON is used as the reference ground of the slave. VOP is the output voltage of the power chip, and the DC-DC module outputs VCC=5V power to power the slave. The host and the slave communicate through the bus, and the bus signal cannot be absorbed by capacitor C3, so U1 needs to isolate the bus AC component, and the DC impedance cannot be too large. The AC impedance of U1 is related to the internal resistance and capacitance values, so the input impedance of the active inductor can be changed by increasing or decreasing the capacitor.

[0061] The patent of the present invention can be applied to the scenario where an inductor is needed to isolate the AC signal when two-bus power is taken (DC power carrier communication solution). It solves the previous practice of blocking the AC signal by conventional passive differential mode inductors during two-bus DC carrier communication. Instead, it adopts an active inductor structure that can be integrated inside the chip and is tunable. It has the advantages of low on-state voltage drop, large equivalent inductance, strong current capacity, high reliability, no noise caused by mechanical vibration, low cost, and small size.

[0062] It should be understood that the scope of the present invention is not limited to the non-limiting embodiments, and it should be understood that the non-limiting embodiments are only described as examples. The substantial protection scope required by this application is more embodied in the scope provided by the independent claims, as well as its dependent claims.

Claims

1. An active inductor for DC power carrier communication, which is an integrated circuit, characterized in that: The integrated circuit comprises a first-level circuit STAGE1, a second-level circuit STAGE2, a third-level circuit STAGE3, and a fourth-level circuit STAGE4; The first stage circuit STAGE1 comprises: a floating end active inductor L1 and a grounded end active inductor L2, wherein two ends of the floating end active inductor L1 are correspondingly connected to a positive input voltage VP and a positive output voltage VOP to block the positive signal AC part after rectification and retain the positive DC signal Iin, and two ends of the grounded end active inductor L2 are correspondingly connected to a negative input voltage VN and a negative output voltage VON to block the negative signal AC part after rectification and retain the negative DC signal -Iin; The second stage circuit STAGE2 is the voltage sampling part of the ground active inductor L2, the third stage circuit STAGE3 is the carrier communication bus signal ±△V low level period detection part, and the fourth stage circuit STAGE4 is the low level conduction part; The third stage circuit STAGE3 samples the bus signal ±△V and compares it with the reference voltage VREF to control the sampling voltage of the second stage circuit STAGE2 to drive the fourth stage circuit STAGE4 to turn on or off, so as to draw a constant current from the bus during the low level period of the bus signal ±△V; The floating-end active inductor L1 comprises: a first transistor M1, a first resistor R1, a second resistor R2 and a first capacitor C1, wherein the drain and source of the first transistor M1 are respectively connected to the forward input voltage VP and the forward output voltage VOP, and the gate of the first transistor M1 is respectively connected to the forward input voltage VP and the forward output voltage VOP via the first resistor R1 and the second resistor R2; The ground-end active inductor L2 includes: a second transistor M2, a third resistor R4, a fourth resistor R5 and a second capacitor C2, the source and drain of the second transistor M2 are respectively connected to the negative input voltage VN and the negative output voltage VON, and the gate of the second transistor M2 is correspondingly connected to the negative input voltage VN and the negative output voltage VON via the fourth resistor R4 and the third resistor R3.

2. The active inductor for DC power carrier communication according to claim 1, characterized in that: Two ends of the first capacitor C1 are connected to the source and gate of the first transistor M1 respectively, and two ends of the second capacitor C2 are connected to the source and gate of the second transistor M2 respectively.

3. The active inductor for DC power carrier communication according to claim 2, characterized in that: The first stage circuit STAGE1 further includes a third capacitor C3 , and two ends of the third capacitor C3 are respectively connected to the source of the first transistor M1 and the drain of the second transistor M2 .

4. The active inductor for DC power carrier communication according to claim 3, characterized in that: The second stage circuit STAGE2 includes an operational amplifier OP, a non-inverting input terminal of the operational amplifier OP is connected to the gate of the second transistor M2, and the fourth stage circuit STAGE4 includes a third transistor M3 and an impedance Z1; The inverting input terminal of the operational amplifier OP is connected to the signal output terminal and to the gate of the third transistor M3. The source of the third transistor M3 is connected to the negative input voltage VN. The drain of the third transistor M3 is connected to the positive input voltage VP via the impedance Z1.

5. The active inductor for DC power carrier communication according to claim 4, characterized in that: The second stage circuit STAGE2 samples the gate-source voltage VGS of the second transistor M2 in the first stage circuit STAGE1 to drive the third transistor M3 in the fourth stage circuit STAGE4 to be turned on or off.

6. The active inductor for DC power carrier communication according to claim 5, characterized in that: The third stage circuit STAGE3 comprises: a comparator COMP, a fifth resistor R5, a sixth resistor R6 and a switch K1, wherein the positive input terminal of the comparator COMP is connected to a reference voltage VREF, and the negative input terminal of the comparator COMP is connected to the positive input voltage VP and the negative input voltage VN via the fifth resistor R5 and the sixth resistor R6 respectively; The signal output terminal of the operational amplifier OP is connected to the gate of the third transistor M3 via the switch K1. The switch K1 includes: an input terminal connected to the signal output terminal of the operational amplifier OP, an output terminal connected to the gate of the third transistor M3, and a control terminal connected to the output terminal of the comparator COMP.

7. An active inductor for DC power carrier communication according to claim 6, characterized in that: The bus signal ±△V is compared with the reference voltage VREF. If the bus signal ±△V is lower than the reference voltage VREF, the switch K1 is controlled to be closed; if the bus signal ±△V is higher than the reference voltage VREF, the switch K1 is controlled to be opened.

8. A DC power supply carrier communication circuit, in which a host and a slave communicate via a bus, characterized in that: According to claim 1, an active inductor for direct current power carrier communication is used, the negative output voltage VON is set as the reference ground of the slave, and the positive output voltage VOP is used to power the slave through the DC-DC module output voltage VCC.

9. A DC power carrier communication circuit according to claim 8, characterized in that: The output voltage VCC is equal to 5V, and output capacitors COUT are arranged at both ends of the output end of the DC-DC module, one end of the output capacitor COUT is connected to the output voltage VCC, and the other end is connected to the negative output voltage VON, the host includes: a first input end IN1, a second input end IN2, a first output end OUTA, and a second output end OUTB respectively connected to the twisted pair, and the slave includes: a first input end IN1', a second input end IN2', a first output end OUTA', and a second output end OUTB' respectively connected to the twisted pair.

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