Data frame detection circuit and data frame detection method for communication system

Abstract

The invention discloses a data frame detection circuit and a data frame detection method for a communication system. The circuit comprises a preorder code detection unit and a shielding unit. The preamble code detection unit is used for detecting a preamble sequence code in a data frame and generating a first enable signal based on the preamble sequence code; the shielding unit generates a shielding control signal with a shielding window based on a first enable signal and a reference clock signal, closes the preorder code detection circuit based on the shielding window of the shielding control signal, and opens the preorder code detection circuit after the shielding window ends. According to the data frame detection circuit and the data frame detection method for the communication system, shielding window protection is provided after system initialization is finished, and the preorder code detection unit stops receiving the data frame during the effective period of the shielding window, so that the situation that error data caused by any reason triggers preorder code identification and interferes normal work of a link is prevented; the problem of sensitivity to EMC in the link establishment process is solved.

Description

Technical Field

[0001] The present invention belongs to the technical field of integrated circuits, and in particular relates to a data frame detection circuit and a data frame detection method for a communication system. Background Art

[0002] In today's information age, computer networks have become an indispensable part of people's daily life and work. As an important communication method in computer networks, synchronous communication is of great significance for ensuring reliable data transmission and coordinating operations between multiple devices. The key to synchronous communication is to achieve clock signal synchronization between the sender and the receiver. In order to reduce costs and circuit complexity, the most widely used clock synchronization mechanism is that one device is used as the main clock source, usually called the master. Other devices (i.e. slaves) use the clock signal provided by the master as a reference for clock signal synchronization and control the timing of data transmission in the link. This clock synchronization method does not require a high-precision clock source to be implemented locally. Figure 1 As shown, in a communication network such as a daisy chain topology or a star topology, the host master first generates a synchronous clock for the entire communication network and transmits it in the communication link, completing the clock synchronization and link establishment between the host master and multiple slaves slave1, slave2, slave3, slave4~.

[0003] Take daisy chain topology communication as an example, Figure 2 As shown, each device includes a transmitter TX, a receiver RX and a clock data recovery circuit CDR. The data frame DATA sent by the host master through the transmitter TX contains a preamble sequence code Preamble in a special format and data information. The slave slave1 detects and identifies the special preamble sequence code Preamble in the data frame DATA through the corresponding preamble code detection unit PreambleDetect, and recovers the system clock signal SCLK by the clock data recovery circuit CDR to correctly sample the data. The first function of the preamble sequence code Preamble is to provide frame header information. The high-speed serial data stream in the synchronous communication system needs to be converted into multi-byte parallel data at the receiving end RX. This special preamble sequence code Preamble can be used as a mark of the beginning of the data frame, identify the boundary of the data, or as a control character for correction and alignment of the data stream. The second function of the preamble sequence code Preamble is to provide synchronization information so that the clock received by the slave is synchronized with the clock sent by the source host, which is used for initial clock synchronization and fast locking of the clock data recovery circuit CDR. In addition, the preamble code Preamble can also provide data type information of this frame, such as data speed and data direction.

[0004] The method of clock synchronization through the preamble sequence code greatly reduces the cost because it does not require an additional local high-precision clock source, but it may cause system failures because it does not have anti-interference capabilities during the link establishment process. When subject to EMC (electromagnetic compatibility) interference or other unpredictable interference, the preamble sequence code Preamble will be wrong, or the receiving end RX will identify normal data as the preamble sequence code Preamble, thereby recovering incorrect synchronization information or frame header information. The wrong synchronization clock causes the clock data recovery circuit CDR to work incorrectly and generate a large number of bit errors, or directly causes the link establishment to fail, requiring reinitialization.

[0005] The information disclosed in this background technology section is only intended to enhance the understanding of the overall background of the invention and should not be regarded as an acknowledgment or any form of suggestion that the information constitutes the prior art already known to a person skilled in the art. Summary of the invention

[0006] The object of the present invention is to provide a data frame detection circuit and a data frame detection method for a communication system, which can shield EMC interference or other unpredictable interference during the communication system link establishment process to ensure the normal operation of a clock data recovery circuit CDR.

[0007] In order to achieve the above objective, a specific embodiment of the present invention provides a data frame detection circuit for a communication system, comprising: a preamble detection unit and a shielding unit.

[0008] The preamble detection unit is used to detect the preamble sequence code in the data frame and generate a first enable signal based on the preamble sequence code; the shielding unit generates a shielding control signal with a shielding window based on the first enable signal and the reference clock signal, and turns off the preamble detection circuit based on the shielding window of the shielding control signal and turns on the preamble detection circuit after the shielding window ends.

[0009] The controller includes a clock generating unit and an encoding control unit. The clock generating unit is used to generate one or more groups of clock signals with different rates. The encoding control unit is used to encode the input data based on the control of the corresponding clock signal to generate a group of control signals, and control the first switch unit and the second switch unit through the control signal to generate a data signal at the output end.

[0010] In one or more embodiments of the present invention, the masking window duration of the masking control signal is shorter than the cycle time of the data frame.

[0011] In one or more embodiments of the present invention, the shielding unit includes a first counting unit and a first logic unit, wherein the first counting unit counts the reference clock signal based on the first enable signal and generates a counting value when the count reaches the target value, and the first logic unit generates a shielding control signal with a shielding window based on the first enable signal and the counting value.

[0012] In one or more embodiments of the present invention, the shielding unit further comprises a trigger, which generates a synchronization signal based on a reference clock signal and a first enable signal, and the first logic unit generates a shielding control signal having a shielding window based on the synchronization signal and a count value.

[0013] In one or more embodiments of the present invention, the shielding unit further includes a calibration unit connected to the first counting unit, and the calibration unit is used to generate a target value to calibrate the duration of the shielding window.

[0014] In one or more embodiments of the present invention, the preamble detection unit is used to generate a characterization signal characterizing a data frame period, and the calibration unit generates a target value based on the characterization signal.

[0015] In one or more embodiments of the present invention, the calibration unit includes a second counting unit and a second logic unit, the second counting unit counts the reference clock signal based on the characterization signal to generate a reference value, and the second logic unit adjusts the reference value based on the time margin to generate a target value.

[0016] The present invention also discloses a data frame detection method, comprising:

[0017] Detecting a leading sequence code in a data frame, and generating a first enabling signal based on the leading sequence code;

[0018] generating a shielding control signal having a shielding window based on the first enable signal and the reference clock signal;

[0019] The preamble detection circuit is turned off based on the shielding window of the shielding control signal and is turned on after the shielding window ends.

[0020] In one or more embodiments of the present invention, generating a shielding control signal having a shielding window based on the first enable signal includes:

[0021] Counting the reference clock signal based on the first enable signal, and generating a count value when the count reaches a target value;

[0022] A mask control signal having a mask window is generated based on the first enable signal and the count value.

[0023] In one or more embodiments of the present invention, the data frame detection method further includes:

[0024] providing a reference value;

[0025] The reference value is adjusted based on the time margin to produce a target value to calibrate the duration of the masking window.

[0026] Compared with the prior art, the data frame detection circuit and data frame detection method for a communication system of the present invention provide shielding window protection after the system initialization is completed, and the preamble detection unit stops receiving data frames during the effective period of the shielding window, so as to prevent the triggering of preamble recognition by erroneous data caused by any reason, and interfere with the normal operation of the link, thereby solving the problem of sensitivity to EMC during the link establishment process. At the same time, the present invention proposes a calibration mechanism, which monitors and adjusts the shielding window based on the data frame period, and prevents the problem of data loss caused by the change of the shielding window. The present invention improves the anti-interference ability of the clock synchronization process in the synchronous communication system and the reliability of single-channel communication by adopting a low-cost implementation method. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the prior art descriptions are briefly introduced below. Obviously, the drawings described below are only some embodiments recorded in the present invention, and for ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0028] Figure 1 This is the topological structure of the communication system in the prior art.

[0029] Figure 2 The figure is a communication principle diagram of a communication system in the prior art.

[0030] Figure 3 FIG. 4 is a system diagram of a data frame detection circuit in one embodiment.

[0031] Figure 4 FIG. 4 is a waveform diagram of data frame detection in an embodiment.

[0032] Figure 5 FIG. 4 is a circuit schematic diagram of a data frame detection circuit in an embodiment.

[0033] Figure 6 Detailed waveform diagram of each signal of a data frame detection circuit in one embodiment. DETAILED DESCRIPTION

[0034] In order to enable those skilled in the art to better understand the technical solutions in the present invention, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the present invention.

[0035] "Coupled" or "connected" or "connected" in the specification includes both direct connection and indirect connection. Indirect connection is a connection through an intermediate medium, such as a connection through an electrically conductive medium, which may have parasitic inductance or parasitic capacitance; indirect connection may also include connection through other active or passive devices on the basis of achieving the same or similar functional purposes, such as connection through circuits or components such as switches and follower circuits. In addition, in the invention, words such as "first" and "second" are mainly used to distinguish one technical feature from another technical feature, and do not necessarily require or imply that there is a certain actual relationship, quantity or order between these technical features.

[0036] In the detailed description of the specification, reference is made to the accompanying drawings forming a part thereof, wherein like reference numerals refer to like parts throughout, and wherein are shown by way of exemplary embodiments that may be implemented. It should be understood that other embodiments may be utilized and structural or logical changes may be made without departing from the scope of the present disclosure. Therefore, the following detailed description should not be considered in a limiting sense.

[0037] The various operations in the specification may be described in turn as multiple discrete actions or operations in a manner that is most helpful in understanding the claimed subject matter. However, the order of description should not be interpreted as implying that these operations must be order-dependent. Specifically, these operations may not be performed in the order presented. The described operations may be performed in an order different from the described embodiments. Various additional operations may be performed and / or the described operations may be omitted in additional embodiments.

[0038] For purposes of this disclosure, the phrase "A and / or B" means (A), (B), or (A and B). For purposes of this disclosure, the phrase "A, B and / or C" means (A), (B), (C), (A and B), (A and C), (B and C), or (A, B and C).

[0039] Various components and devices may be referred to or shown in the singular form herein (e.g., "transistor," "transistor," "switch," etc.), but this is merely for ease of discussion, and any element referred to in the singular form may include multiple such elements in accordance with the teachings herein.

[0040] The specification describes the use of the phrases "in one embodiment" or "in other embodiments" or "in some embodiments", which may each refer to one or more of the same or different embodiments. In addition, the terms "including", "comprising", "having", etc. used in relation to the embodiments of the present disclosure are synonymous.

[0041] A data frame detection circuit for a communication system in an embodiment of the present invention, wherein the communication system may be as follows Figure 1 The daisy chain topology or star topology shown. One or more devices (master Madter or slave Slave) of the communication system have a clock data recovery circuit CDR for clock recovery and a data frame detection circuit.

[0042] like Figure 3 As shown, the data frame detection circuit includes: a preamble detection unit Preamble Detect and a shielding unit EMC Window Generator.

[0043] In one embodiment, the preamble detection unit Preamble Detect is used to detect the preamble sequence code Preamble in the data frame DATA received by the receiving end RX. After detecting the preamble sequence code Preamble, the preamble detection unit Preamble Detect cooperates with the clock data recovery circuit CDR to perform clock recovery to generate a system clock signal SCLK. The preamble detection unit Preamble Detect generates a first enable signal EN based on the detected preamble sequence code Preamble.

[0044] The data frame DATA contains a preamble with a special data format. The preamble can be composed of "1010...+k-code" or "special data pattern + Hamming distance". The slave uses the preamble detection unit PreambleDetect corresponding to the special format preamble to detect the preamble. This detection method has the advantage of low cost because it does not require an additional low-frequency difference clock source (usually a crystal oscillator, an external clock or a separate clock channel).

[0045] The shielding unit EMC Window Generator generates a shielding control signal RESET having a shielding window shielding window based on the first enable signal EN and the reference clock signal clk_osc, turns off the preamble detection circuit PreambleDetect based on the shielding window shielding window of the shielding control signal RESET, and turns on the preamble detection circuit PreambleDetect after the shielding window shieldingwindow ends.

[0046] In one embodiment, it is necessary to control the duration of the shielding window of the shielding control signal RESET to be shorter than the cycle time of the data frame DATA.

[0047] like Figure 4 As shown, due to interference or because a segment of data between two preambles may be the same as the preamble, an error will occur if detected by the preamble detection unit. A corresponding pulse will appear in the synchronous system clock signal SCLK, but due to the shielding window generated by the present invention, during this period, the input end of the preamble detection unit Preamble Detect does not receive a signal, so the preamble will not be misidentified.

[0048] like Figure 5 As shown, the shielding unit EMC Window Generator includes: a trigger DFF, a first counting unit Counter1 and a first logic unit Digital Logic1.

[0049] The trigger DFF generates a synchronization signal Q1 based on the reference clock signal clk_osc and the first enable signal EN. By setting the trigger DFF, the first enable signal EN can be synchronized to the reference clock signal clk_osc, that is, the first enable signal EN is resampled based on the reference clock signal clk_osc to generate the synchronization signal Q1, thereby ensuring that the subsequent circuits work normally and stably.

[0050] The first counting unit Counter1 counts the reference clock signal clk_osc based on the first enable signal EN and generates a count value Q2 when counting to a target value num1. The first logic unit Digital Logic1 generates a shielding control signal RESET having a shielding window based on the synchronization signal Q1 and the count value Q2.

[0051] In other embodiments, the trigger DFF may not be set, and the first logic unit Digital Logic1 may generate a shielding control signal RESET having a shielding window based on the first enable signal EN and the count value Q2.

[0052] In addition, the shielding unit EMC Window Generator further includes a calibration unit, which is connected to the first counting unit Counter1 and the preamble detection unit Preamble Detect. At this time, the preamble detection unit PreambleDetect is used to generate a characterization signal Calibration that characterizes the period of the data frame DATA. In one embodiment, the period of the data frame DATA is equal to the period of the system clock signal SCLK, and the calibration unit generates a target value num1 based on the characterization signal Calibration.

[0053] Furthermore, the calibration unit includes a second counting unit Counter2 and a second logic unit DigitalLogic2. The second counting unit Counter2 is an adding counter Adder Counter2. The second counting unit Counter2 counts the reference clock signal clk_osc based on the characterization signal Calibration to generate a reference value num2. The second logic unit DigitalLogic2 adjusts the reference value num2 based on the time margin num_marg to generate a target value num1 to calibrate the duration of the shielding window.

[0054] In one embodiment, the first counting unit Counter1 is a modulo N counter Module N Counter1, and the target value num1 is the modulo value. The first counting unit Counter1 outputs a count value Q2 when counting the reference clock signal clk_osc to the target value num1 based on the first enable signal EN, and the first logic unit DigitalLogic1 generates a shielding control signal RESET based on the synchronization signal Q1 and the count value Q2.

[0055] In other embodiments, the calibration unit may be other circuits that can be set to provide the reference value num2.

[0056] The detection principle of the data frame detection circuit is further described in detail below.

[0057] like Figure 6 Combination Figure 5 and Figure 4As shown, after the slave initialization is completed, the preamble detection unit PreambleDetect detects the data frame DATA sent by the host. When the preamble detection unit Preamble Detect detects the frame header Preamble of the data frame DATA, it generates the rising edge of the system clock signal SCLK, the rising edge of the first enable signal EN and the rising edge of the characterization signal Calibration, and the high level duration of the characterization signal Calibration is equal to the cycle time of the data frame DATA and the cycle time of the system clock signal SCLK.

[0058] The first enable signal EN is transmitted to the first counting unit Counter1 and the trigger DFF, the characterization signal Calibration is transmitted to the second counting unit Counter2, the first counting unit Counter1, the trigger DFF and the second counting unit Counter2 simultaneously receive the reference clock signal clk_osc, the trigger DFF outputs the synchronization signal Q1, the first counting unit Counter1 outputs the count value Q2, the count value Q2 and the synchronization signal Q1 are transmitted to the first logic unit Digital Logic1, and the first logic unit Digital Logic1 outputs the shielding control signal RESET based on the synchronization signal Q1 and the count value Q2. In one embodiment, under the control of the reference clock signal clk_osc, the rising edge of the first enable signal EN triggers the rising edge of the synchronization signal Q1, and the rising edge of the synchronization signal Q1 triggers the rising edge of the shielding control signal RESET (the shielding control signal RESET jumps to a high level).

[0059] After the rising edge of the first enable signal EN is generated, the second counting unit Counter2 with the modulus value of the target value num1 counts the reference clock signal clk_osc, and outputs a pulse signal after the target value num1 is counted: the count value Q2. At this time, the first logic unit Digital Logic1 performs a logic operation on the count value Q2 and the synchronization signal Q1 to obtain the shielding control signal RESET=Q1&&(~Q2), that is, the count value Q2 is first inverted, and then a logic AND operation is performed with the synchronization signal Q1. The count value Q2 after the shielding control signal RESET is inverted is pulled down to a low level. Therefore, the high level period of the shielding control signal RESET constitutes a shielding window. During the period when the shielding control signal RESET is at a high level (valid), the preamble detection unit Preamble Detect does not receive data information and does not detect the data output by the receiving end RX. When the shielding control signal RESET jumps to a low level, the preamble detection unit Preamble Detect controls the first enable signal EN to also jump to a low level, thereby turning off the shielding unit EMC WindowGenerator. The preamble detection unit Preamble Detect continues to receive the data frame DATA normally, which does not affect the detection of the next frame header Preamble. The host and the slave complete the transmission of the system clock.

[0060] When the preamble detection unit Preamble Detect detects the first frame header Preamble of the data frame DATA, the rising edge of the characterization signal Calibration is generated. When the preamble detection unit Preamble Detect detects the next frame header Preamble of the data frame DATA, the falling edge of the characterization signal Calibration and the falling edge of the system clock signal SCLK are generated. The corresponding characterization signal Calibration has a period of Ts. During Ts, the communication system link is established. The second counting unit Counter2 simultaneously counts the reference clock signal clk_osc within Ts and outputs the reference value num2 (the reference value num2 represents the length of Ts) to the second logic unit Digital Logic2. After receiving the reference value num2, the second logic unit Digital Logic2 adjusts the reference value num2 based on the time margin num_marg to generate a target value num1=num1-num_marg. In one embodiment, the second logic unit Digital Logic2 can be a subtraction circuit, thereby updating the target value num1 and loading it to the first counting unit Counter1 to calibrate the length of the shielding window shieldingwindow in the next period.

[0061] In one embodiment, the time margin num_marg represents the time interval from the end of the shielding window to the arrival of the next cycle of the data frame DATA. If the condition of ending the shielding window before the arrival of the next cycle of the data frame DATA needs to be met, that is, the length of the shielding window is less than Ts, a certain time margin num_marg needs to be set to ensure that after the communication system link is established, the shielding window will not affect the subsequent normal operation of the link.

[0062] In addition, the shielding window is determined by the low-cost on-chip reference clock signal clk_osc and the system clock signal SCLK. The poor frequency accuracy of the on-chip reference clock signal clk_osc will affect the duration of the shielding window, which may cause data loss or reduce its anti-interference ability due to a short duration. A calibration mechanism based on the system clock signal SCLK is proposed here. Because the period of the system clock signal SCLK generated by the host is accurate, based on the system clock signal SCLK, the FLL (Frequency Locked Loop) is used to calibrate the on-chip clock, monitor and adjust the duration of the shielding window, and ensure the stability of the shielding window. When the shielding window increases, the calibration unit adjusts it to decrease, ensuring that the duration of the shielding window is less than the period Ts of the data frame DATA, avoiding problems such as data loss caused by frequency difference. When the shielding window decreases, the calibration unit adjusts it to increase, so that the shielding window can shield EMC interference to the maximum extent and improve anti-interference ability.

[0063] The present invention also discloses a data frame detection method, comprising:

[0064] A preamble sequence code Preamble in the data frame DATA is detected, and a first enable signal EN is generated based on the preamble sequence code Preamble.

[0065] A shielding control signal RESET having a shielding window shieldingwindow is generated based on the first enable signal EN and the reference clock signal clk_osc. Further, the reference clock signal clk_osc is counted based on the first enable signal EN, and a count value Q2 is generated when the count reaches a target value; a shielding control signal RESET having a shielding window shieldingwindow is generated based on the first enable signal EN and the count value Q2.

[0066] The shielding window based on the shielding control signal RESET turns off the preamble detection circuit Preamble Detect and turns on the preamble detection circuit Preamble Detect after the shielding window ends.

[0067] In addition, a reference value may be provided; and a target value may be generated by adjusting the reference value based on the time margin to calibrate the duration of the shielding window.

[0068] The specific implementation of the data frame detection method can refer to the above circuit description part.

[0069] It will be apparent to those skilled in the art that the invention is not limited to the details of the exemplary embodiments described above and that the invention can be implemented in other specific forms without departing from the spirit or essential features of the invention. Therefore, the embodiments should be considered exemplary and non-limiting in all respects, and the scope of the invention is defined by the appended claims rather than the foregoing description, and it is intended that all variations falling within the meaning and scope of the equivalent elements of the claims be included in the invention. Any reference numeral in a claim should not be considered as limiting the claim to which it relates.

[0070] In addition, it should be understood that although the present specification is described according to implementation modes, not every implementation mode contains only one independent technical solution. This description of the specification is only for the sake of clarity. Those skilled in the art should regard the specification as a whole. The technical solutions in each embodiment may also be appropriately combined to form other implementation modes that can be understood by those skilled in the art.

Claims

1. A data frame detection circuit for a communication system, characterized in that: include: A preamble detection unit, configured to detect a preamble sequence code in a data frame and generate a first enable signal based on the preamble sequence code; The shielding unit generates a shielding control signal with a shielding window based on the first enable signal and the reference clock signal, closes the preamble detection circuit based on the shielding window of the shielding control signal, and opens the preamble detection circuit after the shielding window ends.

2. The data frame detection circuit for a communication system according to claim 1, characterized in that: The shielding window duration of the shielding control signal is shorter than the cycle time of the data frame.

3. The data frame detection circuit for a communication system according to claim 1, characterized in that: The shielding unit includes a first counting unit and a first logic unit, wherein the first counting unit counts the reference clock signal based on the first enable signal and generates a count value when the count reaches a target value, and the first logic unit generates a shielding control signal with a shielding window based on the first enable signal and the count value.

4. The data frame detection circuit for a communication system according to claim 3, characterized in that: The shielding unit further includes a trigger, which generates a synchronization signal based on a reference clock signal and a first enable signal, and the first logic unit generates a shielding control signal having a shielding window based on the synchronization signal and a count value.

5. The data frame detection circuit for a communication system according to claim 3, characterized in that: The shielding unit further includes a calibration unit connected to the first counting unit, and the calibration unit is used to generate a target value to calibrate the duration of the shielding window.

6. The data frame detection circuit for a communication system according to claim 5, characterized in that: The preamble detection unit is used to generate a characterization signal that characterizes a data frame period, and the calibration unit generates a target value based on the characterization signal.

7. The data frame detection circuit for a communication system according to claim 6, characterized in that: The calibration unit includes a second counting unit and a second logic unit, wherein the second counting unit counts a reference clock signal based on a characterization signal to generate a reference value, and the second logic unit adjusts the reference value based on a time margin to generate a target value.

8. A data frame detection method, characterized in that: include: Detecting a leading sequence code in a data frame, and generating a first enabling signal based on the leading sequence code; generating a shielding control signal having a shielding window based on the first enable signal and the reference clock signal; The preamble detection circuit is turned off based on the shielding window of the shielding control signal and is turned on after the shielding window ends.

9. The data frame detection method according to claim 8, characterized in that: The step of generating a shielding control signal having a shielding window based on the first enable signal comprises: Counting the reference clock signal based on the first enable signal, and generating a count value when the count reaches a target value; A mask control signal having a mask window is generated based on the first enable signal and the count value.

10. The data frame detection method according to claim 9, characterized in that: The data frame detection method also includes: providing a reference value; The reference value is adjusted based on the time margin to produce a target value to calibrate the duration of the masking window.

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