Method for transmitting video and protocol through USB interface of infrared system and infrared system

Abstract

The invention belongs to the technical field of infrared image transmission, and discloses a method for transmitting videos and protocols through a USB interface of an infrared system and the infrared system. The infrared system is based on an FPGA (Field Programmable Gate Array), and the method comprises the following steps of: controlling a USB (Universal Serial Bus) interface by utilizing a state machine through the FPGA, transmitting infrared image data from an FPGA end to an upper computer through the USB interface, and transmitting an instruction from the upper computer to the FPGA end through the USB interface. The USB interface is used for transmitting infrared images, wiring is simple, the anti-interference capacity is high, and the transmission distance is long; image preprocessing and USB protocol coding are realized by utilizing the FPGA, so that the real-time performance and stability of data transmission are improved; the method has good compatibility and expandability, and is suitable for various infrared systems; protocol and video transmission share a differential cable, and the system structure is further simplified.

Description

Technical Field

[0001] The invention belongs to the technical field of infrared image transmission, and in particular relates to a method for transmitting video and protocol via a USB interface of an infrared system, and an infrared system. Background Art

[0002] With the rapid development of science and technology, infrared imaging technology has been widely used in many fields, such as security monitoring, military reconnaissance, medical diagnosis, etc. Infrared systems are usually composed of infrared cameras, image processors, displays and other devices to capture, process and display infrared images.

[0003] However, traditional infrared systems usually use transmission media such as coaxial cables and optical fibers to transmit instructions and image data, which leads to certain limitations in data transmission, which are mainly manifested in the following aspects: 1. Although transmission media such as coaxial cables and optical fibers can meet the needs of data transmission to a certain extent, they have problems such as complex wiring, poor anti-interference ability, and limited transmission distance. These problems limit the application scope and performance of infrared systems; 2. Due to the large amount of infrared image data, there is a high requirement for transmission speed. However, the existing data transmission methods often cannot meet the needs of high-speed transmission, resulting in delays and packet loss during the transmission of infrared images, affecting the real-time performance and stability of the system. 3. With the development of technology, infrared systems need to interact with other devices (such as computers, mobile devices, etc.) for data; however, existing data transmission methods often lack good compatibility and scalability, which limits the interconnection between infrared systems and other devices.

[0004] In order to solve the above problems, researchers have begun to pay attention to infrared image transmission technology based on USB interface in recent years. As a common computer peripheral device connection interface, USB (Universal Serial Bus) interface has the advantages of simple wiring, strong anti-interference ability, long transmission distance, good compatibility and scalability. For example, in the existing method, the USB interface is used to transmit video data from the infrared system to the host computer in a one-way manner. However, it is difficult to develop the simultaneous transmission of video and protocol through the USB interface. It is necessary to transmit video and protocol at the same time. Therefore, the command control still needs to use the serial port, which results in the need for two interfaces (USB interface, serial port) to complete the integration of the infrared module into other systems. Although the existing method can realize data interaction between the infrared system and other systems, it also leads to the corresponding circuit board and hardware structure being complicated, and more interface lines, which is not conducive to the miniaturization of the infrared module, especially cannot meet the application requirements of small scenes such as drone pods. Summary of the invention

[0005] In order to solve the above problems, one object of the present invention is to provide a method for transmitting video and protocol via a USB interface of an infrared system. The method can realize bidirectional transmission of infrared image data and instructions via a USB interface.

[0006] The specific technical solutions are as follows: A method for transmitting video and protocol via a USB interface of an infrared system. The infrared system is based on FPGA. The method comprises controlling the USB interface by using a state machine through the FPGA, transmitting infrared image data from the FPGA end to a host computer through the USB interface, and transmitting instructions from the host computer to the FPGA end through the USB interface.

[0007] Furthermore, the USB interface uses a USB chip with an embedded processing hard core, and the steps of the FPGA controlling the USB interface using a state machine include: The signal for selecting the FIFO to be connected to the data bit in the interface signal of the USB chip is the first interface signal, the output enable signal for enabling control connected to the FIFO data bit is the second interface signal, the write strobe pulse signal connected to the FIFO data bit is the third interface signal, and the read strobe pulse signal connected to the FIFO data bit is the fourth interface signal; The set initial state is used as the main state machine 0 state. When the main state machine is in the 0 state, the first interface signal of the USB chip is set to 1, the second interface signal is set to 0, and the third interface signal is set to 1, and then the secondary state machine enters the 0 state; In the state of the secondary state machine 0, the protocol parameters are initialized to 255; then the state of the secondary state machine 1 is entered; In the state of the secondary state machine 1, the fourth interface signal of the USB chip is set to 0; then the secondary state machine 2 state is entered; In the state of the secondary state machine 2, it is determined whether the 16-bit data signal value input by the USB chip is the target value. If not, it jumps to the state of the secondary state machine 0; if yes, it jumps to the state of the secondary state machine 3; In the state 3 of the secondary state machine, the value of the 8th signal input by the USB chip is assigned to the signal Write_SDRAM, where Write_SDRAM is a signal for writing the dual-port RAM in the FPGA, and then the state machine jumps to the state 4; In the state of the secondary state machine 4, the signal values ​​of the 1st to 8th roots or the 1st to 16th roots input by the USB chip are assigned to the protocol parameters, and the signal values ​​are read by the FPGA; then jump to the state of the secondary state machine 5; In the state of the secondary state machine 5, the fourth interface signal is set to 1, and then jumps to the state of the main state machine 1; In the main state machine 1 state, the fourth interface signal is set to 1, and then the value of Write_SDRAM is determined; when Write_SDRAM=1, it is in the waiting state; when Write_SDRAM=0, it jumps to the main state machine 2 state, and then enters the main state machine 3 state; In the main state machine 3 state, the first interface signal is set to 1, the second interface signal is set to 0, and the fourth interface signal is set to 1; the image address is initialized, and the FPGA starts to read the first row of data from the DDR, and then transmits it to the host computer through the USB chip; the remaining rows of data are transmitted in sequence; after a frame of image is transmitted, the control signal of the USB chip is reset to the initial state; Return to the state of main state machine 0 and repeat all the above operations.

[0008] This solution uses a state machine to control the USB chip. Through signal and timing control design, the USB interface can transmit image data while also transmitting command protocols.

[0009] Furthermore, the infrared image data and instructions are transmitted using a pair of differential cables.

[0010] Another object of the present invention is to provide an infrared system, wherein the system applies the above-mentioned infrared system USB interface video and protocol transmission method; the system comprises: Infrared lens, collecting infrared image signals; Infrared detector, converting infrared image signal into electrical signal; Infrared detector driving circuit converts electrical signals into parallel digital signals; The FPGA processing system processes the parallel digital signals input by the infrared detector driving circuit in real time, pre-processes the infrared image, and outputs a digital video stream; The USB interface circuit converts the digital video stream into a USB interface signal.

[0011] Furthermore, the USB interface circuit includes a power supply module, a USB chip and a memory.

[0012] Furthermore, the USB chip adopts one of the models CY7C68014, CY7C68013 and CBM9002A.

[0013] Furthermore, the reset circuit of the USB chip is an RC reset circuit, and diodes are arranged in parallel at both ends of a charging resistor of the RC reset circuit.

[0014] Furthermore, the memory adopts MICROCHIP serial EEPROM memory.

[0015] Compared with the prior art, one or more of the above technical solutions can achieve at least one of the following beneficial effects: The present invention adopts a USB interface to transmit infrared images, which has simple wiring, strong anti-interference ability and long transmission distance; uses FPGA to implement image preprocessing and USB protocol encoding, thereby improving the real-time performance and stability of data transmission; has good compatibility and scalability, and is suitable for various infrared systems; the transmission of the protocol and video shares a differential cable, further simplifying the system structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other accompanying drawings can be obtained based on these accompanying drawings without paying creative work.

[0017] Figure 1 It is a structural block diagram of the infrared system of Example 1; Figure 2 This is the block diagram of the USB interface circuit hardware; Figure 3 This is a partial schematic diagram of the USB interface circuit; Figure 4 This is a block diagram of the data transmission channel between the FPGA end, USB end, and PC end; Figure 5 This is the data transmission flow chart between FPGA end, USB end and PC end; Figure 6 Design diagrams for command sequences; Figure 7 An example of the change in the value of the state machine command sequence when online data capture is performed on the FPGA side; Figure 8 This is the main state machine flow control diagram for the interaction timing between FPGA and USB chip. DETAILED DESCRIPTION

[0018] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0019] Example 1 This embodiment provides a method for transmitting video and protocol via a USB interface of an infrared system. The infrared system is based on an FPGA; the method of this embodiment includes controlling the USB interface by using a state machine through the FPGA, transmitting infrared image data from the FPGA end to a host computer via the USB interface, and transmitting instructions from the host computer to the FPGA end via the USB interface.

[0020] This embodiment further provides an infrared system, and the method for transmitting video and protocol via a USB interface of the infrared system is described in detail by taking the application of the infrared system as an example.

[0021] like Figure 1 As shown, the infrared system includes an infrared lens, an infrared detector, an infrared detector driving circuit, an FPGA processing system, and a USB interface circuit. Among them, the infrared lens collects infrared image signals; the infrared detector converts the infrared image signals into electrical signals; the infrared detector driving circuit converts the electrical signals into parallel digital signals; the FPGA processing system processes the parallel digital signals input by the infrared detector driving circuit in real time, pre-processes the infrared image signals, including image noise reduction, contrast enhancement, etc., and encodes the pre-processed image signals into a data format compatible with the USB chip protocol: digital video stream; the USB interface circuit converts the digital video stream into a USB interface signal, and transmits the encoded data to the host computer through the USB interface circuit; the host computer receives and decodes the data and displays the infrared image.

[0022] The USB data cable can be used to transmit infrared video to the PC, and the PC can transmit commands to the infrared module via the USB data cable, thus making the product more miniaturized.

[0023] As a specific implementation method, the infrared detector selected is Anhui Guangzhi's metal package infrared detector, model VL0617VM. It is an uncooled long-wave infrared detector that uses metal packaging technology, has a pixel size of 640×512, and a pixel pitch of 17μm. The FPGA used in the FPGA processing system is the SmartFusion2 series of Microsemi, model M2S060-FCS325. SmartFusion2 is Microsemi's fourth-generation 65nm process system-on-chip product, and is one of the choices for SoC systems that meet the high security, high reliability, and extremely low power consumption required by the industrial, military, aviation, communications, and medical fields. like Figure 2 , Figure 3 As shown, the USB interface circuit includes a power supply module, a USB chip and a memory.

[0024] The power supply module uses a DC-DC power chip from Texas Instruments, which is a synchronous step-down DC-DC converter with overcurrent protection, internal soft start, thermal shutdown protection, etc., and is optimized for high-efficiency and compact solutions. The switch integrated in the device can provide an output current of up to 2A. Under medium or heavy load conditions, the device operates in pulse width modulation (PWM) mode with a switching frequency of 1.5MHz. Under light load conditions, the device automatically enters power saving mode (PSM), thereby maintaining high efficiency over the entire load current range. When turned off, the current consumption is reduced to less than 2μA. The input voltage Vin is filtered by a large capacitor and a small capacitor in parallel with a C-type filter, making the power entering the power chip cleaner. The same output voltage Vout is filtered by a large capacitor and a small capacitor in parallel with a C-type filter to ensure that the voltage ripple to the chip is small enough. At the same time, in order to make the output voltage more accurate, the feedback resistor should use a precision resistor with an accuracy of 1%.

[0025] The USB chip may be a USB chip with a built-in processing hard core; the USB chip may be one of CY7C68014, CY7C68013, and CBM9002A. It is understood that other USB chips of the same type may also be used. This embodiment takes the USB chip as an example, which is a USB2.0 chip CY7C68014 from CYPRESS.

[0026] like Figure 3 As shown, the reset circuit design adopts RC to improve the reset circuit. The RC reset circuit has certain defects and can only be used in occasions where the timing and reliability are not high. When the circuit is powered off, the voltage across the capacitor C is close to 3.3V, and the power supply starts to drop from 3.3V to 0V. Since the RST pin of the chip is usually in a high-impedance state, the capacitor can only be discharged through the resistor, and the capacitor discharge process is relatively slow. If the circuit is powered off in a short time and powered on immediately, then there may be a situation where the electricity at both ends of the capacitor is not fully discharged, resulting in that although the power supply has been powered on again at this time, the reset level is not low enough, and the reset does not work reliably, causing the system state to be disordered. The charging resistor at both ends of the RC reset circuit in this embodiment is provided with a diode in parallel, which solves the above problem. Since the charging resistor limits the discharge speed at this time, only a diode needs to be reversely connected in parallel at both ends of the resistor. This diode is reverse biased when the circuit is powered on, and does not affect the charging of the capacitor. When the power supply is powered off, the diode is forward biased and conducts, shorting the two ends of the resistor to form a fast discharge path for the capacitor.

[0027] The memory uses MICROCHIP serial EEPROM memory. This memory is powered by a single power supply, the input power supply 3.3V is filtered by a small capacitor, and the I2C is pulled up by a 2.2K resistor. The operating voltage can be as low as 2.5 V, low-power CMOS technology, maximum read current of 400μA, maximum standby current of 1μA (industrial temperature), 2-wire serial interface, compatible with I2C, package with 3 address pins, can cascade up to 8 devices Schmitt trigger input, easy to achieve noise suppression, output slope control to eliminate ground bounce; compatible with 100kHz and 400kHz clocks, typical page write time is 5 ms, self-timed erase / write cycle 32 bytes, with hardware write protection function, ESD protection voltage greater than 4000 V, more than one million erase / write cycles, data retention period greater than 200 years, factory programmable.

[0028] like Figure 4 As shown, a USB chip is used to realize bidirectional transmission of video and instructions. This embodiment takes the PC as an example: on the one hand, infrared image data is transmitted from the FPGA end to the PC end, and on the other hand, instructions are transmitted from the PC end to the FPGA end. Among them, a data channel and a command channel are set between the PC end and the USB chip. The command channel is used to transmit the protocol, and the data channel is used to transmit infrared image data. The PC end sends read and write instructions and ends read and write instructions through the command channel, which are transmitted to the FPGA end through the USB chip; the FPGA end sends image data through the USB chip, which is read by the PC end through the data channel. The transmission of image data and instructions shares a pair of differential cables.

[0029] like Figure 5 As shown, the FPGA processing system uses a state machine for the USB program, which is designed as follows: The clock of USBIFCLK is 20MHz, which is the clock paired with the PC software.

[0030] The infrared image data is transmitted from the FPGA to the host computer through the USB interface, and the instructions are transmitted from the host computer to the FPGA through the USB interface. The data transmission between the FPGA, USB interface (USB chip), and host computer (PC) is divided into four processes, which are: Step 1: The PC sends data command 0x55, 0xaa, through the USB chip, to the FPGA (using channel 0, maximum 64 bytes); Step 2: FPGA sends image data, which is read by PC via USB chip (using channel 1, minimum 2KB, maximum 3MB); Step 3: The PC sends an end command (starting with 0x5e, Oxaa, using channel 0, maximum 64 bytes) to the FPGA via the USB chip; Step 4: Read status (using channel 1, size is 64 bytes), the FPGA side waits for instructions from the PC side.

[0031] The command sequence is as follows Figure 6 The design shown can be increased according to the project: Among them, the value of USBComd can be set according to Table 1.

[0032] Table 1 USBComd value design As a specific implementation, for infrared images, each line has 512 dots, but the computer software can cut them automatically when displaying as needed. For visible light images, each line has 1024 dots, but the computer software can cut them automatically when displaying as needed.

[0033] The data storage format is: YCrYCb format. The sending format of the PC command is to spell a string of characters. Figure 7 As shown, when the FPGA end performs online data capture, the value changes of the command sequence under the state machine can be seen.

[0034] Specifically, the main state machine flow of the interaction timing design between FPGA and USB chip is as follows: Figure 8 shown.

[0035] The signal for selecting the FIFO connected to the data bit in the interface signal of the USB chip is the first interface signal (USBIFA), the output enable signal for the enable control connected to the FIFO data bit is the second interface signal (SLOE), the write strobe pulse signal connected to the FIFO data bit is the third interface signal (SLWE), and the read strobe pulse signal connected to the FIFO data bit is the fourth interface signal (SLRD); The set initial state is used as the main state machine 0 state. When in the main state machine 0 state, the first interface signal of the USB chip is 1, the second interface signal is 0, and the third interface signal is 1, that is, USBIFA=1, SLOE=0, SLWE=1; then enter the secondary state machine 0 state.

[0036] In the state of the sub-state machine 0, the protocol parameters are initialized to 255, and then the state of the sub-state machine 1 is entered. The protocol parameters can be the key parameter KeyComd, and the key value is transmitted from the PC to the FPGA through the USB interface, that is, the infrared module is controlled through the PC interface. Physical keys can also be used, corresponding to 8 or 16, connected to the PC, and after the physical key is pressed, it is converted into an 8bti data with a data value range of 0-255; the value is sent to the FPGA as part of the protocol; the initialization value is 255, and the key is not pressed at this time.

[0037] In the state of the secondary state machine 1, the fourth interface signal SLRD of the USB chip is set to 0; then the secondary state machine 2 state is entered.

[0038] In the state of sub-state machine 2, the FPGA determines whether the 16-bit data signal value input by the USB chip is the target value. In this embodiment, the target value is 43605; if not, it jumps to the state of sub-state machine 0; if so, it jumps to the state of sub-state machine 3.

[0039] In the state of the secondary state machine 3, the value of the 8th signal input by the USB chip is assigned to the signal Write_SDRAM, and then jumps to the state of the secondary state machine 4. Wherein Write_SDRAM is a signal used to write the dual-port RAM in the FPGA.

[0040] In the state of the secondary state machine 4, the signal values ​​of the 1st to 8th roots or the 1st to 16th roots input by the USB chip are assigned to the protocol parameters (key parameters KeyComd), and the signal values ​​are read by the FPGA. Then jump to the state of the secondary state machine 5.

[0041] In the secondary state machine 5 state, the fourth interface signal SLRD is set to 1, and then the process jumps to the primary state machine 1 state.

[0042] In the main state machine 1 state, set the fourth interface signal SLRD = 1 (SLRD = 1 again to avoid the situation where SLRD is not 1 when jumping from other states to the main state machine 1 state), and then judge the value of Write_SDRAM. When Write_SDRAM = 1, it is in the waiting state; when Write_SDRAM = 0, it jumps to the main state machine 2 state, and then enters the main state machine 3 state.

[0043] In the main state machine 3 state, set the first interface signal USBIFA=1, the second interface signal SLOE=0, and the fourth interface signal SLRD=1. Then initialize the image address, FPGA starts to read the first row of data from DDR, and then transmits it to PC through USB chip; and transmits the remaining row data in sequence, a total of 512 rows. Specifically, in the sub-state machine a state in the main state machine 3 state, the image address is initialized, the first row of data is read out, and then jumps to the sub-state machine b state; in the sub-state machine b state, the image y address is changed, and the y address data is processed in sequence, and then jumps to the sub-state machine c state; in the sub-state machine c state, the image y address remains unchanged, the x address changes, and the x address data is processed in sequence; cycle the sub-state machine a state, the sub-state machine b state, and the sub-state machine c state until the transmission of a frame of image is completed. After a frame of image is transmitted, the control signal of the USB chip is reset to the initial state.

[0044] Return to the main state machine state 0 and repeat all the above operations.

[0045] This embodiment realizes the bidirectional transmission of video and instructions using a 4-wire USB interface (power supply, ground, two USB lines). On the one hand, infrared data is transmitted from the FPGA chip to the PC, and on the other hand, instructions are transmitted from the PC to the FPGA. It overcomes the defect that the FPGA chip in the prior art transmits video to the PC via USB, and the serial port (ground, serial port receiving, serial port sending) is used for instruction control, which requires two interfaces (USB interface, serial port) to complete the integration of the infrared module into other systems. This embodiment only needs to use a 4-wire USB interface to realize the integration of the infrared module into other systems. This method has the advantages of simple wiring, strong anti-interference ability, and long transmission distance. It can be widely used in various infrared systems to improve the application performance of infrared imaging technology in various fields.

[0046] Obviously, the above embodiments are merely examples for clearly explaining the technical solutions of the present invention, and are not intended to limit the implementation methods of the present invention. For those skilled in the art, other different forms of changes or modifications can be made based on the above description. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of the present invention should be included in the protection of the claims of the present invention.

Claims

1. A method for transmitting video and protocol via USB interface of infrared system, wherein the infrared system is based on FPGA and is characterized in that: The method comprises controlling the USB interface by using a state machine through an FPGA, transmitting infrared image data from the FPGA end to a host computer through the USB interface, and transmitting instructions from the host computer to the FPGA end through the USB interface.

2. The method for transmitting video and protocol via USB interface of infrared system according to claim 1, characterized in that: The USB interface uses a USB chip with an embedded processing hard core, and the steps of FPGA controlling the USB interface using a state machine include: The signal for selecting the FIFO connected to the data bit in the interface signal of the USB chip is the first interface signal, the output enable signal of the enable control connected to the FIFO data bit is the second interface signal, the write strobe pulse signal connected to the FIFO data bit is the third interface signal, and the read strobe pulse signal connected to the FIFO data bit is the fourth interface signal; The set initial state is used as the main state machine 0 state. When the main state machine is in the 0 state, the first interface signal of the USB chip is set to 1, the second interface signal is set to 0, and the third interface signal is set to 1; then the secondary state machine enters the 0 state; In the state of the secondary state machine 0, the protocol parameters are initialized to 255; then the state of the secondary state machine 1 is entered; In the state of the secondary state machine 1, the fourth interface signal of the USB chip is set to 0; then the secondary state machine 2 state is entered; In the state of the secondary state machine 2, it is determined whether the 16-bit data signal value input by the USB chip is the target value. If not, it jumps to the state of the secondary state machine 0; if yes, it jumps to the state of the secondary state machine 3; In the state 3 of the secondary state machine, the value of the 8th signal input by the USB chip is assigned to the signal Write_SDRAM, where Write_SDRAM is a signal for writing the dual-port RAM in the FPGA, and then the state machine jumps to the state 4; In the state of the secondary state machine 4, the signal values ​​of the 1st to 8th roots or the 1st to 16th roots input by the USB chip are assigned to the protocol parameters, and the signal values ​​are read by the FPGA; then jump to the state of the secondary state machine 5; In the state of the secondary state machine 5, the fourth interface signal is set to 1, and then jumps to the state of the main state machine 1; In the main state machine 1 state, the fourth interface signal is set to 1, and then the value of Write_SDRAM is determined; when Write_SDRAM=1, it is in the waiting state; when Write_SDRAM=0, it jumps to the main state machine 2 state, and then enters the main state machine 3 state; In the main state machine 3 state, the first interface signal is set to 1, the second interface signal is set to 0, and the fourth interface signal is set to 1; the image address is initialized, the first line of data is read from the DDR, and then transmitted to the host computer through the USB chip; the remaining lines of data are transmitted in sequence; after a frame of image is transmitted, the control signal of the USB chip is reset to the initial state; Return to the main state machine state 0 and repeat all the above operations.

3. The method for transmitting video and protocol via USB interface of infrared system according to claim 1, characterized in that: The infrared image data and instructions are transmitted by sharing a pair of differential cables.

4. Infrared system, characterized in that, The method for transmitting video and protocol via USB interface of infrared system as described in any one of claims 1 to 3 is applied; the system comprises: Infrared lens, collecting infrared image signals; Infrared detector, converting infrared image signal into electrical signal; Infrared detector driving circuit, converting electrical signals into parallel digital signals; The FPGA processing system processes the parallel digital signals input by the infrared detector driving circuit in real time, pre-processes the infrared image, and outputs a digital video stream; The USB interface circuit converts the digital video stream into a USB interface signal.

5. The infrared system according to claim 4, characterized in that: The USB interface circuit includes a power supply module, a USB chip and a memory.

6. The infrared system according to claim 5, characterized in that The USB chip is one of the USB chips with models of CY7C68014, CY7C68013 and CBM9002A.

7. The infrared system according to claim 6, characterized in that The reset circuit of the USB chip is an RC reset circuit, and diodes are arranged in parallel at both ends of a charging resistor of the RC reset circuit.

8. The infrared system according to any one of claims 5 to 7, characterized in that: The memory adopts MICROCHIP serial EEPROM memory.

Images