Semiconductor structure and manufacturing method thereof

Abstract

The invention belongs to the field of storage, and particularly relates to a semiconductor structure and a manufacturing method thereof. The semiconductor structure comprises a substrate and at least one memory device layer, the at least one memory device layer is stacked on the same side of the substrate in the vertical direction, the memory device layer at least comprises a first signal line, a transistor, a second signal line and a gate line, one of the first signal line and the second signal line is a reference voltage line, and the other of the first signal line and the second signal line is a gate line. One of the gate lines is a gate line, and the other one is a read-write line, and the gate layer of the transistor is connected with the gate line; an active layer of the transistor extends in the vertical direction and is independently arranged relative to the substrate, and the bottom end of the active layer is connected with the first signal line; and the top end of the active layer is connected with the second signal line. According to the scheme, the process difficulty and the technical cost can be reduced while the storage density is improved.

Description

Technical Field

[0001] The present disclosure belongs to the field of storage, and in particular relates to a semiconductor structure and a manufacturing method thereof. Background Art

[0002] With the miniaturization of technology nodes, 1T0C (T stands for transistor, C stands for capacitor) DRAM (Dynamic Random Access Memory) has become a research hotspot. However, traditional 1T0C DRAM uses the substrate as the active layer, and the active layer is arranged in a planar manner, that is, the active layer as a whole extends in the horizontal direction. Increasing the storage density of 1T0C DRAM by miniaturizing the size of transistors will increase process difficulty and technical cost. Summary of the invention

[0003] The embodiments of the present disclosure provide a semiconductor structure and a method for manufacturing the same, which can improve storage density while reducing process difficulty and technical cost.

[0004] A first aspect of the present disclosure provides a semiconductor structure, comprising:

[0005] substrate; and

[0006] At least one memory device layer is stacked on the same side of the substrate in a vertical direction, the memory device layer at least includes a first signal line, a transistor, a second signal line and a gate line, one of the first signal line and the second signal line is a reference voltage line, and the other is a read-write line, wherein:

[0007] The gate layer of the transistor is connected to the gate line;

[0008] The active layer of the transistor extends in a vertical direction and is independently arranged relative to the substrate, and the bottom end of the active layer is connected to the first signal line;

[0009] A top end of the active layer is connected to the second signal line.

[0010] A second aspect of the present disclosure provides a method for manufacturing a semiconductor structure, comprising:

[0011] providing a substrate;

[0012] At least one memory device layer stacked in a vertical direction is formed on the substrate, wherein the method for forming the memory device layer comprises:

[0013] A first signal line, a transistor, a second signal line and a selection line are formed on the substrate, one of the first signal line and the second signal line is a reference voltage line, and the other is a read / write line, a gate layer of the transistor is connected to the selection line, an active layer of the transistor extends in a vertical direction and is independently arranged relative to the substrate, a bottom end of the active layer is connected to the first signal line, and a top end of the active layer is connected to the second signal line.

[0014] The technical solution provided by the embodiments of the present disclosure has at least the following advantages:

[0015] The present disclosure enables the active layer of the transistor to be independently arranged relative to the substrate of the semiconductor structure. Compared with the solution of using part of the substrate as the active layer, it can reduce the design difficulty and technical cost of the three-dimensional transistor (that is, the active layer of the present disclosure extends in the vertical direction as a whole), and can also increase the number of transistors per unit area in the storage device layer, thereby improving the storage density. In addition, it is also convenient to arrange multiple layers of the storage device layer and stack them in the vertical direction to further improve the storage density. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] The accompanying drawings herein are incorporated into the specification and constitute a part of the specification, illustrate embodiments consistent with the present disclosure, and together with the specification are used to explain the principles of the present disclosure. Obviously, the accompanying drawings described below are only some embodiments of the present disclosure, and for ordinary technicians in this field, other accompanying drawings can be obtained based on these accompanying drawings without creative work.

[0017] Figures 1 to 3 Structural schematic diagrams of semiconductor structures shown in different technical solutions of the present disclosure are respectively shown.

[0018] Figure 4 Shows Figure 1 Schematic diagram of the cross-sectional structure of the semiconductor structure shown in FIG.

[0019] Figure 5 Shows Figure 3 Schematic diagram of the cross-sectional structure of the semiconductor structure shown in FIG. 1 along the BB direction.

[0020] Figures 6 to 8 Structural schematic diagrams showing that the semiconductor structure shown in different technical solutions of the present disclosure includes multiple shared units are respectively shown.

[0021] Fig. 9 A schematic structural diagram of a substrate in a semiconductor structure shown in the technical solution of the present disclosure is shown.

[0022] Fig.10 It shows a schematic diagram of the structure after step S2003 is performed in the process of manufacturing the semiconductor structure.

[0023] Fig.11 It shows a schematic diagram of the structure after step S2100 is performed in the process of manufacturing the semiconductor structure.

[0024] Fig.12 Shows Fig.10 The structure shown is a schematic cross-sectional structure diagram along the CC direction or a schematic cross-sectional structure diagram along the DD direction.

[0025] Figures 13 to 21 The structural schematic diagrams of the third solution of the present disclosure after executing different steps are respectively shown.

[0026] Figures 22 to 32 The structural schematic diagrams of the fourth scheme of the present disclosure after executing different steps are respectively shown. DETAILED DESCRIPTION

[0027] Example embodiments will now be described more fully with reference to the accompanying drawings. However, example embodiments can be implemented in a variety of forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided so that this application will be more comprehensive and complete and fully convey the concept of the example embodiments to those skilled in the art.

[0028] In addition, described feature, structure or characteristic can be combined in one or more embodiments in any suitable manner. In the following description, many specific details are provided to provide a full understanding of the embodiments of the present application. However, those skilled in the art will appreciate that the technical scheme of the present application can be put into practice without one or more of the specific details, or other methods, components, devices, steps, etc. can be adopted. In other cases, known methods, devices, realizations or operations are not shown or described in detail to avoid blurring the various aspects of the application.

[0029] The present application is further described in detail below in conjunction with the accompanying drawings and specific embodiments. It should be noted that the technical features involved in the various embodiments of the present application described below can be combined with each other as long as they do not conflict with each other. The embodiments described below with reference to the accompanying drawings are exemplary and are intended to be used to explain the present application, and should not be understood as limiting the present application.

[0030] The present disclosure provides a semiconductor structure, which may include a DRAM, but is not limited thereto and will not be further limited herein.

[0031] The semiconductor structure disclosed in the present invention is described in detail below with reference to the accompanying drawings.

[0032] refer to Figures 1 to 3 As shown, the semiconductor structure may include a substrate 10 and a memory device layer 20 formed on the substrate 10 .

[0033] For example, the substrate 10 may include at least a single crystal semiconductor material layer 101 and an insulating isolation layer 102 formed between the memory device layer 20 and the single crystal semiconductor material layer 101. In this embodiment, the material of the single crystal semiconductor material layer 101 may include single crystal silicon, but is not limited thereto, and may also include single crystal semiconductor materials such as germanium (Ge). The material of the insulating isolation layer 102 may be silicon oxide, such as silicon dioxide (SiO2), but is not limited thereto, and the insulating isolation layer 102 may also be made of other materials with insulating properties, depending on the actual situation.

[0034] In the process of preparing silicon dioxide as the insulating isolation layer 102, TEOS (Tetraethoxysilane) can be used as a silicon source in the chemical vapor deposition (CVD) process. In the chemical vapor deposition process, TEOS and oxygen react on the surface of the single crystal semiconductor material layer 101 at a certain temperature and pressure to generate silicon dioxide and ethanol. In this process, the silicon atoms in the TEOS molecules react with oxygen to generate silicon dioxide and release ethanol. Silicon dioxide is formed as a deposit on the surface of the single crystal semiconductor material layer 101, forming a silicon dioxide film as the insulating isolation layer 102.

[0035] It can be understood that the substrate 10 can be a peripheral substrate, a supporting substrate, or a bonding substrate.

[0036] The present application is mainly described below by taking the case where the storage device layer 20 is formed on the substrate 10 , that is, the substrate 10 is a supporting substrate as an example.

[0037] The memory device layer 20 may include a first signal line 20 a , a transistor 20 b , a second signal line 20 c , and a gate line 20 d .

[0038] refer to Figures 1 to 3 As shown, the transistor 20b at least includes an active layer 201, a gate layer 202, and a gate insulating layer 203 filled between the gate layer 202 and the active layer 201. The active layer 201 of this embodiment may extend along a vertical direction Z, and the vertical direction Z may be a direction perpendicular or approximately perpendicular to the substrate 10, that is, the active layer 201 may be perpendicular or approximately perpendicular to the substrate 10.

[0039] For example, the transistor 20b mentioned in this embodiment can be a three-dimensional structure as a whole to improve the storage density per unit area, increase the channel width, increase the read and write current of the transistor 20b in the storage device layer 20, and improve the gate control capability by increasing the channel length in the vertical direction. Specifically, the transistor 20b includes a core layer and a sleeve layer, the sleeve layer at least surrounds the outer peripheral side of the core layer, and the core layer and the sleeve layer as a whole extend in the vertical direction Z. One of the core layer and the sleeve layer is the active layer 201 of the transistor 20b, and the other is the gate layer 202 of the transistor 20b. When the sleeve layer is the gate layer 202 and the core layer is the active layer 201, refer to Figure 1 and Figure 2 As shown, the transistor 20b is understood as a gate-surround structure; when the sleeve layer is the active layer 201 and the core layer is the gate layer 202, refer to Figure 3 As shown, transistor 20b is understood to be a channel-around structure.

[0040] In the present disclosure, the material of the active layer 201 is a semiconductor material, specifically a polycrystalline semiconductor material, such as polycrystalline (abbreviated as: Poly) silicon and other materials. It should be understood that the active layer 201 is not limited to the aforementioned semiconductor materials, as long as the semiconductor material can achieve full depletion, illustratively, the active layer 201 can also be IGZO. The material of the gate layer 202 can be a metal material, such as copper, tungsten and other metal materials, to improve the conductivity, but is not limited thereto, and other materials with good conductivity can also be used, depending on specific needs.

[0041] In an alternative embodiment, if Figure 1 As shown, the active layer 201 may be a junction active layer, so that the transistor 20b is a junction transistor. A junction transistor refers to a semiconductor device in which semiconductor materials of different conductivity types (i.e., doping types) are used to form a channel region and a source-drain region, thereby forming a transistor with a junction structure. Specifically, the active layer 201 of this embodiment may include a channel region 2011 and a first electrode region 2012 and a second electrode region 2013 located on opposite sides of the channel region 2011 in the vertical direction Z. It should be noted that one of the first electrode region 2012 and the second electrode region 2013 is a source region, and the other is a drain region.

[0042] Among them, the first electrode region 2012 can be formed between the first signal line 20a and the channel region 2011, that is: the top of the first electrode region 2012 contacts the bottom of the channel region 2011, and the bottom of the first electrode region 2012 contacts the top of the first signal line 20a; and the second electrode region 2013 can be formed between the second signal line 20c and the channel region 2011, that is: the bottom of the second electrode region 2013 contacts the top of the channel region 2011, and the top of the second electrode region 2013 contacts the top of the second signal line 20c.

[0043] In this embodiment, the first electrode region 2012 and the second electrode region 2013 have the same conductivity type, for example, both are N-type semiconductors or both are P-type semiconductors; and the conductivity types of the first electrode region 2012 and the second electrode region 2013 are different from the conductivity type of the channel region 2011, thereby forming a junction active layer 201. For example, when the conductivity types of the first electrode region 2012 and the second electrode region 2013 are N-type semiconductors, the channel region 2011 is a P-type semiconductor. At this time, the transistor 20b can be an NMOS (N-Metal-Oxide-Se miconductor, N-type metal-oxide-semiconductor) transistor; when the conductivity type of the first electrode region 2012 and the second electrode region 2013 is a P-type semiconductor, the channel region 2011 is an N-type semiconductor. At this time, the transistor 20b can be a PMOS (P-Metal-Oxide-Semiconductor) transistor, so that a PN junction is formed between the channel region 2011 and the first electrode region 2012, and between the channel region 2011 and the second electrode region 2013, respectively.

[0044] When the active layer 201 of the transistor 20b is the aforementioned junction type active layer, in order to realize the charge storage function of the transistor in the memory device layer 20, the gate layer 202 can be made to correspond to the channel region 2011 of the active layer 201. Specifically, Figure 1 As shown, the top surface of the first electrode region 2012 in the active layer 201 is higher than the bottom surface of the gate layer 202, and the bottom surface of the second electrode region 2013 is lower than the top surface of the gate layer 202, so that the junction formed between the channel region 2011 and the first electrode region 2012 (i.e., the position where the channel region 2011 and the first electrode region 2012 are in contact) and the junction formed between the channel region 2011 and the second electrode region 2013 (i.e., the position where the channel region 2011 and the second electrode region 2013 are in contact) both correspond to the gate layer 202. Therefore, during the manufacturing process of the transistor 20b, the design and position of the gate layer 202 need to correspond to the junction of the active layer 201 to ensure the normal operation of the device.

[0045] In another optional embodiment, the active layer 201 may also be a junction-free active layer, such as Figure 2As shown, the junctionless active layer refers to a semiconductor active layer without a PN junction, which is usually composed of a continuous semiconductor film. When the active layer 201 is a junctionless active layer, the transistor 20b formed can be a junctionless transistor or a junction transistor. Compared with the junction active layer, the junctionless active layer does not need to pattern the doped source and drain regions or the channel regions, so the manufacturing process is relatively simple, which can reduce the manufacturing cost and improve the production efficiency. When the active layer 201 is a junctionless active layer and the material is doped polysilicon, the signal line in contact with the active layer 201 can include a semiconductor layer of the opposite doping type to the active layer 201, so that the formed transistor 20b is a junction transistor.

[0046] It should be noted that the performance of junction-less transistors is affected by many factors, such as material quality, film thickness, and doping concentration. Therefore, in practical applications, it is necessary to optimize the design according to specific application scenarios and requirements to achieve the best performance.

[0047] refer to Figure 1 or Figure 2 As shown, in the present disclosure, the active layer 201 can be formed at the top of the first signal line 20a, and the second signal line 20c can be formed at the top of the active layer 201, that is, the active layer 201 can be arranged between the first signal line 20a and the second signal line 20c, the top of the active layer 201 is connected to the second signal line 20c, and the bottom of the active layer 201 is connected to the first signal line 20a.

[0048] It should be noted that the top end and top surface of a structure mentioned in the present disclosure refer to its end away from the substrate 10 or the surface away from the substrate 10, and the bottom end and bottom surface refer to its end close to the substrate 10 or the surface close to the substrate 10.

[0049] Among them, one of the first signal line 20a and the second signal line 20c is a reference voltage line, and the other is a read-write line; the read-write line is connected to the peripheral circuit to input or output the storage signal, and the selection line 20d is connected to the gate layer 202 of the transistor 20b. Different voltages are applied between the read-write line and the selection line 20d, which can realize the reading and writing of data in the transistor 20b.

[0050] Exemplarily, the reference voltage line may be a ground line whose reference voltage is 0V, and the subsequent embodiments of the present invention are also described by taking the reference voltage of 0V as an example.

[0051] By way of example, taking the transistor 20b as an NMOS transistor as an example, the read and write operations of the transistor 20b are described as follows:

[0052] The process of writing "1": negative voltage is applied to the gate layer 202 of the transistor 20b through the selection line 20d, and positive voltage is applied to the drain region of the transistor 20b through the read-write line. The holes generated by GIDL (Gate Induced Drain Leakage) in the depletion region where the drain region overlaps the gate layer accumulate in the floating area.

[0053] The process of reading "0" or "1": applying a positive voltage to the gate layer 202 of the transistor 20b through the selection line 20d, and applying a suitable positive voltage to the drain region of the transistor 20b through the read-write line. This suitable positive voltage is a relatively small voltage so that the NMOS transistor can work in the linear region to prevent the generation of HCI (Hot Carrier Injection effect), thereby causing the problem of ionization. If holes accumulate in the floating body, the threshold voltage of this transistor 20b is low and the drain current is large, and it is "1" at this time; if there are no holes accumulated in the floating body, the threshold voltage of this transistor 20b is large and the drain current is small, and it is "0" at this time; wherein, the difference between the drain current when reading "1" and the drain current when reading "0" is the sense margin.

[0054] The process of writing "0": add positive voltage to the gate layer 202 of transistor 20b through the selection line 20d, and add negative voltage to the drain area of ​​transistor 20b through the read-write line, so that the PN junction from the drain area to the channel area is forward-biased and turned on, and electrons and holes recombine to eliminate holes.

[0055] In the process of selectively writing "0": a small positive voltage is applied to the selection line 20d connected to the selected transistor 20b at "1" to increase the floating body potential of this transistor 20b. Assuming that the PN junction turn-on voltage from the drain region to the channel region of the transistor with hole accumulation is 0.7V, a small voltage is applied to the gate layer 202 of the selected transistor 20b to make the PN junction turn-on voltage from the drain region to the channel region 0.5V. Then a negative voltage is applied to the read-write line connected to the selected transistor 20b. This negative voltage ensures that the drain terminal of the selected transistor is opened, and also ensures that the transistor without voltage on the gate layer is turned off, thereby completing the write "0" operation.

[0056] "Hold" process: the drain region of the transistor is connected to 0V through the read and write lines.

[0057] It should be noted that in the above process, the source region of each transistor 20b is connected to a reference voltage through a reference voltage line. The reference voltage can be a fixed voltage or ground. In addition, the "hold" mentioned above is an operation to keep the state of the transistor unchanged so that the stored data can be correctly obtained in the subsequent reading process.

[0058] Based on the foregoing, in the present disclosure, each transistor 20b itself can be used as a storage unit without providing an additional storage capacitor, that is, the storage unit of the storage device layer 20 in the present disclosure can be a 1T0C type storage unit.

[0059] For example, combined with Figure 1 and Figure 2 As shown, if the transistor 20b is a gate-surrounding structure, the gate line 20d can be formed on the side of the second signal line 20c close to the substrate 10, that is, the gate line 20d can be formed between the first signal line 20a and the second signal line 20c. This design can use part of the gate line 20d as the gate layer 202 of the transistor 20b. That is, when the gate line 20d is made, the gate layer 202 in the transistor 20b can be made, so as to save manufacturing steps and reduce manufacturing difficulty and cost. It should be understood that, with reference to Figure 1 and Figure 2 As shown, the gate line 20d needs to be insulated from the first signal line 20a and the second signal line 20c. Therefore, a first insulating dielectric layer 204 can be formed between the gate line 20d and the first signal line 20a, and a second insulating dielectric layer 205 can be formed between the gate line 20d and the second signal line 20c.

[0060] For example, Figure 3 As shown, if the transistor 20b is a channel-surround structure, since the gate layer 202 of the transistor 20b is surrounded by the active layer 201, in order to facilitate the connection of the gate line 20d to the gate layer 202 of the corresponding transistor 20b, the gate line 20d can be formed on the top or bottom side of the gate layer 202, wherein, if the gate line 20d is formed on the top side of the gate layer 202, the gate line 20d can be located on the side of the second signal line 20c away from the substrate 10, and if the gate line 20d is formed on the bottom side of the gate layer 202, the gate line 20d can be located on the side of the first signal line 20a close to and away from the substrate 10.

[0061] In the present disclosure, since the material of the active layer 201 is a semiconductor material, when designing the first signal line 20a and the second signal line 20c, reference is made to Figure 1 and Figure 2As shown, the first signal line 20a and the second signal line 20c can be designed to include at least a semiconductor material layer 206, wherein the bottom end of the active layer 201 is in direct contact with the semiconductor material layer 206 of the first signal line 20a, and the top end of the active layer 201 is in direct contact with the semiconductor material layer 206 of the second signal line 20c. Taking polysilicon as an example of the semiconductor material, the contact area between the polysilicon and the metal silicide in the first signal line 20a and the second signal line 20c can be increased to reduce the impedance. The arrangement of the metal silicide in the first signal line 20a and the second signal line 20c will be described later.

[0062] Among them, when the active layer 201 is the junction-free active layer mentioned above, the conductivity type of this active layer 201 can be the same as the conductivity type of the semiconductor material layer 206 in the first signal line 20a and the second signal line 20c to form a junction-free storage unit. For example: the active layer 201 and the semiconductor material layer 206 in the first signal line 20a and the second signal line 20c are all N-type semiconductors, or the active layer 201 and the semiconductor material layer 206 in the first signal line 20a and the second signal line 20c are all P-type semiconductors, which can reduce manufacturing costs and improve production efficiency.

[0063] However, it is not limited thereto. When the active layer 201 is the aforementioned junction-free active layer, the conductivity type of the active layer 201 may be different from the conductivity type of the semiconductor material layer 206 in the first signal line 20a and the second signal line 20c to form a junction transistor as a storage unit. Figure 3In the embodiment of the transistor 20b shown as a gate-surrounding structure, when the active layer 201 is an N-type semiconductor, the conductivity type of the semiconductor material layer 206 in the first signal line 20a and the second signal line 20c can be a P-type semiconductor, or when the active layer 201 is a P-type semiconductor, the conductivity type of the semiconductor material layer 206 in the first signal line 20a and the second signal line 20c can be an N-type semiconductor, so that a PN junction structure is formed between the semiconductor material layer 206 of the first signal line 20a and the active layer 201, and between the semiconductor material layer 206 of the second signal line 20c and the active layer 201. However, in this case, it is necessary to make the gate layer 202 opposite to the PN junction structure, wherein, when the selection line 20d is formed on the top side of the gate layer 202: the bottom surface of the active layer 201 higher than the bottom surface of the gate layer 202, that is, the bottom end of the gate layer 202 in the transistor 20b is closer to the substrate 10 than the bottom end of the active layer 201; when the selection line 20d is formed on the bottom side of the gate layer 202: the top surface of the active layer 201 is lower than the top surface of the gate layer 202, that is, the top of the gate layer 202 in the transistor 20b is farther away from the substrate 10 than the top of the active layer 201; in the orthographic projection on the substrate 10: the selection line 20d covers at least part of the outer boundary of the active layer 201, preferably, the selection line 20d completely covers the outer boundary of the active layer 201, and this outer boundary refers to the boundary between the active layer 201 and the second signal line 20c, or it can be understood that when the second signal line 20c is used as a read-write line, the channel and the drain of the transistor 20b form a PN junction.

[0064] In addition, when the active layer 201 is the aforementioned junction active layer, the semiconductor material layer 206 of the first signal line 20a can be of the same conductivity type as the first electrode region 2012 in the active layer 201, and the semiconductor material layer 206 of the first signal line 20a can be in contact with the first electrode region 2012 of the active layer 201; the semiconductor material layer 206 of the second signal line 20c is of the same conductivity type as the second electrode region 2013 in the active layer 201, and the semiconductor material layer 206 of the second signal line 20c is in contact with the second electrode region 2013 of the active layer 201. Taking the semiconductor material as polysilicon as an example, the contact area between the polysilicon and the metal silicide in the first signal line 20a and the second signal line 20c can be increased to reduce the impedance. It can be understood that in other embodiments, the semiconductor material layer 206 may not be formed between the metal silicide in the first signal line 20a and the second signal line 20c and the first electrode region 2012 and the second electrode region 2013 to simplify the process. It depends on the specific situation.

[0065] It should be noted that the junction formed at the source region, that is, the junction on the ground line side, may be covered by the gate layer 202 or not, but the junction formed at the drain region, that is, the junction on the read / write line side, must be covered by the gate layer 202 .

[0066] In the present disclosure, when the material of the active layer 201 is polycrystalline semiconductor material, the material of the semiconductor material layer 206 in the first signal line 20a and the second signal line 20c may also be polycrystalline semiconductor material. For example, when the material of the active layer 201 is polycrystalline silicon, the material of the semiconductor material layer 206 is also polycrystalline silicon.

[0067] For example, in order to improve the conductivity of the first signal line 20a and the second signal line 20c, refer to Figure 1 and Figure 2 As shown, the first signal line 20a and the second signal line 20c may further include a metal conductive material layer 207, and the metal conductive material layer 207 is disposed on a side of the semiconductor material layer 206 away from the active layer 201. Further, in order to reduce the contact resistance between the metal conductive material layer 207 and the semiconductor material layer 206, the reference Figure 1 and Figure 2 As shown, the first signal line 20a and the second signal line 20c may further include a transition conductive material layer 208 formed between the semiconductor material layer 206 and the metal conductive material layer 207 , and the material of the transition conductive material layer 208 includes the metal element in the metal conductive material layer 207 and the semiconductor element in the semiconductor material layer 206 .

[0068] For example, when the semiconductor material of the semiconductor material layer 206 is polycrystalline silicon, the material of the transition conductive material layer 208 may be the metal silicide mentioned above. For example, when the metal material of the metal conductive material layer 207 is tungsten, the material of the transition conductive material layer 208 may be tungsten silicide (WSi2) to reduce the contact resistance between the semiconductor material layer 206 of polycrystalline silicon material and the metal conductive material layer 207.

[0069] It should be understood that when the material of the active layer 201 is not polysilicon, the transition conductive material layer 208 made of metal silicide may not be provided according to actual conditions. For example, when the material of the active layer 201 is an oxide semiconductor such as IGZO, the material of the first signal line 20a and the second signal line 20c may only include the metal conductive material layer 207, but not the transition conductive material layer 208, and the active layer 201 is directly in contact with the metal conductive material layer 207.

[0070] In addition, it should be noted that if the resistivity of the semiconductor material layer 206 in the first signal line 20a and the second signal line 20c meets the requirements, the first signal line 20a and the second signal line 20c can be made of only semiconductor materials. Figure 3 shown.

[0071] For example, the gate line 20d can be made of metal materials, such as copper, tungsten and other metal materials, to improve the conductivity, but is not limited thereto, and other materials with good conductivity can also be used, depending on specific needs.

[0072] In the present disclosure, in order to improve the storage density of the memory device layer 20, the present embodiment may set a plurality of transistors 20b in the memory device layer 20, and the plurality of transistors 20b may be arranged in an array in the first horizontal direction X and the second horizontal direction Y, referring to Figure 4 and Figure 5 As shown. The read / write line (ie, the first signal line 20a or the second signal line 20c) and the gate line 20d may also be provided in plurality, Figure 1 and Figure 4 As shown, the gate line 20d can extend in the first horizontal direction X, the read / write line can extend in the second horizontal direction Y, and a plurality of read / write lines can be arranged at intervals in the first horizontal direction X, and a plurality of gate lines 20d can be arranged at intervals in the second horizontal direction Y.

[0073] Among them, Figures 1 to 3 As shown, the active layers 201 of the plurality of transistors 20b arranged in the second horizontal direction Y can be connected to the same read-write line, and ... can be connected to the same read-write line, and the active layers 201 of the plurality of transistors 20b can be connected to the same Figure 1 and Figure 4 As shown, the gate layer 202 of each transistor 20b arranged in the first horizontal direction X can be connected to the same gate line 20d. This design can reduce the number of read-write lines and gate lines 20d while independently controlling the storage unit to perform read and write operations, thereby reducing the plane space they occupy, and then increase the number of transistors 20b within the limited plane space to further improve the storage density.

[0074] It should be noted that the first horizontal direction X and the second horizontal direction Y are parallel or approximately parallel to the substrate 10. The first horizontal direction X and the second horizontal direction Y intersect, for example, the first horizontal direction X and the second horizontal direction Y are perpendicular or approximately perpendicular to each other, and in other embodiments, the angle between the first horizontal direction X and the second horizontal direction Y may be an acute angle or an obtuse angle.

[0075] Furthermore, since the active layer 201 of the transistor 20b in the memory device layer 20 is independently arranged relative to the substrate 10, that is, the active layer 201 of the transistor 20b in the memory device layer 20 in the present disclosure does not need to be formed using part of the substrate 10, the entire memory device layer 20 can be independently arranged relative to the substrate 10, so that the memory device layer 20 can be arranged to have multiple layers on the same substrate 10, refer to Figures 1 to 3 As shown, the multi-layer memory device layers 20 may be stacked on the same side of the substrate 10 along the vertical direction Z to improve the storage density of the entire semiconductor structure.

[0076] In addition, for transistors 20 b of different structures, the design relationship between the multi-layer memory device layers 20 may also be different, such as the contents described in the following schemes 1 and 2.

[0077] Solution 1

[0078] In this plan, refer to Figure 1 , Figure 2 and Figure 4 As shown, the transistor 20b is the gate surround structure mentioned above, and the selection line 20d is located between the first signal line 20a and the second signal line 20c. Therefore, in order to reduce the difficulty of manufacturing, when manufacturing a multi-layer storage device layer 20, the selection lines 20d of any two storage device layers 20 can be set independently of each other, so that any two storage device layers 20 can be controlled independently of each other.

[0079] Based on this, in order to simplify the manufacturing process, when manufacturing a multi-layer memory device layer 20, at least two adjacent memory device layers 20 can share a signal line. Specifically, in two adjacent memory device layers 20: the memory device layer 20 away from the substrate 10 is defined as the top memory device layer, and the memory device layer 20 close to the substrate 10 is defined as the bottom memory device layer. Figure 1 and Figure 2 As shown, at least part of the second signal line 20c in the bottom storage device layer is shared as at least part of the first signal line 20a in the top storage device layer, that is, the first signal line 20a of the top storage device layer and the second signal line 20c of the bottom storage device layer can be used as the same signal line, such as the same reference voltage line or the same read / write line. It can be understood that in other embodiments, the read / write signal lines and / or reference voltage lines have no shared parts.

[0080] For example, if in any two adjacent storage device layers 20 the first signal line 20a of the top storage device layer and the second signal line 20c of the bottom storage device layer share a reference voltage line, then the second signal line 20c of the top storage device layer and the first signal line 20a of the bottom storage device layer are both read-write lines; if in any two adjacent storage device layers 20 the first signal line 20a of the top storage device layer and the second signal line 20c of the bottom storage device layer share a read-write line, then the second signal line 20c of the top storage device layer and the first signal line 20a of the bottom storage device layer are both reference voltage lines.

[0081] Wherein, when the first signal line 20a and the second signal line 20c include the aforementioned semiconductor material layer 206, transition conductive material layer 208 and metal conductive material layer 207, refer to Figure 1 and Figure 2As shown, the metal conductive material layer 207 of the first signal line 20a in the top memory device layer can be shared as the metal conductive material layer 207 of the second signal line 20c in the bottom memory device layer, and after forming the shared metal conductive material layer 207, the transition conductive material layer 208 and the semiconductor material layer 206 of the first signal line 20a in the top memory device layer are formed. When the first signal line 20a and the second signal line 20c only include the semiconductor material layer 206, the first signal line 20a in the top memory device layer can be completely shared as the second signal line 20c in the bottom memory device layer.

[0082] In this solution, in order to further simplify the manufacturing process, when manufacturing multiple memory device layers 20, the first signal line 20a of the top memory device layer and the second signal line 20c of the bottom memory device layer in any two adjacent memory device layers 20 can be used as the same signal line.

[0083] Solution 2

[0084] In this second solution, refer to Figure 3 and Figure 5 As shown, the transistor 20b is the aforementioned channel-surrounding structure, and the gate line 20d is formed on the top or bottom side of the gate layer 202 in the transistor 20b. In order to simplify the manufacturing process, when manufacturing the multi-layer memory device layer 20, as shown in FIG. Figure 3 As shown, the transistors 20b of at least two adjacent storage device layers 20 are arranged correspondingly in the vertical direction Z. In other words, the positive projections of the adjacent transistors 20b on the substrate 10 in the vertical direction Z overlap or approximately overlap, so that the gate layers 202 of at least some of the adjacent transistors 20b in the vertical direction Z can share the same selection line 20d, thereby reducing the total number of signal lines, thereby simplifying the manufacturing process and reducing the manufacturing cost.

[0085] refer to Figure 3As shown, the multi-layer memory device layer 20 can be divided into at least one common unit GG along the vertical direction Z. The common unit GG includes two adjacent memory device layers 20. For the convenience of the following description, the memory device layer 20 on the side away from the substrate 10 in the common unit GG can be defined as the top memory device layer, and the memory device layer 20 on the side close to the substrate 10 can be defined as the bottom memory device layer. In the common unit GG: the gate layers 202 of the two transistors 20b arranged in the vertical direction Z share the same selection line 20d, and the second signal line 20c of the top memory device layer and the first signal line 20a of the bottom memory device layer are both read-write lines and are independently set. In this way, the read-write states of the two memory device layers 20 in the common unit GG can be independently controlled. It should be understood that if the second signal line 20c of the top memory device layer and the first signal line 20a of the bottom memory device layer are both read-write lines, then the first signal line 20a of the top memory device layer and the second signal line 20c of the bottom memory device layer are both reference voltage lines.

[0086] Further references Figure 3 As shown, in the common unit GG: the gate layers 202 of the two transistors 20b arranged in the vertical direction Z are directly connected to form a common gate layer, and the common gate line 20d is located at the top side of the common gate layer, but is not limited to this, and can also be located at the bottom side of the common gate layer. In other embodiments, in the shared unit GG: the shared gate line 20d may also be located between the top memory device layer and the bottom memory device layer, then the gate layers 202 of the two transistors 20b arranged in the vertical direction Z are indirectly connected via the shared gate line 20d, specifically: in the shared unit GG: the gate line 20d of the top memory device layer is formed on the bottom side of the gate layer 202 of the top memory device layer, the gate line 20d of the bottom memory device layer is formed on the top side of the gate layer 202 of the bottom memory device layer, and the gate line 20d of the bottom memory device layer and the gate line 20d of the top memory device layer are at least partially shared to form a shared gate line; for example, the gate line 20d of the bottom memory device layer and the gate line 20d of the top memory device layer may be completely shared to reduce costs.

[0087] In some embodiments, in the shared unit GG, at least a portion of the second signal line 20c in the bottom storage device layer is shared with at least a portion of the first signal line 20a in the top storage device layer, so that the first signal line 20a of the top storage device layer and the second signal line 20c of the bottom storage device are used together as the reference voltage line of the shared unit GG, which can simplify the process flow and reduce costs, but is not limited to this. The first signal line 20a of the top storage device layer and the second signal line 20c of the bottom storage device layer can also be set independently of each other to be used as the reference voltage line or read-write line of the shared unit GG respectively.

[0088] In an optional example, if Figure 6 As shown, a plurality of common units GG may be provided, wherein, in two adjacent common units GG: the read and write lines of one are independently provided with the read and write lines of the other, so that the read and write lines of any two storage device layers 20 are independently provided with each other, so as to realize independent control of the read and write states of each storage device layer 20.

[0089] In an alternative example, reference Figure 6 As shown, in two adjacent shared units GG: the gate layer 202 of the transistor 20b of one shared unit GG is insulated from the gate layer 202 of the transistor 20b of the other shared unit GG by an isolation insulating layer 218, and the gate line 20d of one of the two adjacent shared units GG is independently set from the gate line 20d of the other, so that independent control between adjacent shared units GG can be achieved, reducing the difficulty of control.

[0090] It can be understood that at least one of the read / write line and the gate line can be independently set between different common cells GG to achieve independent operation between different common cells GG. Therefore, when the gate line 20d connected to the gate layer 202 between two adjacent common cells GG is independently set, for example, the gate line 20d of the common cell GG close to the substrate 10 in the two adjacent common cells GG is located between it and the substrate 10, and the gate line 20d of the common cell GG far from the substrate 10 is located on the side away from the substrate 10, or the gate line 20d shared in the common cells GG is located between the top storage device layer and the bottom storage device layer, the read / write line can be partially shared between the two, for example, the top read / write line of the common cell GG close to the substrate 10 and the bottom read / write line of the common cell GG far from the substrate 10 can be at least partially shared. In other words, the read / write lines adjacent to each other in two adjacent common cells GG at least share a portion.

[0091] In another alternative example, if Figure 7 As shown, the multi-layer memory device layer 20 can be divided into at least one shared group G along the vertical direction Z, and the shared group G can include two adjacent shared cells GG. For the convenience of the following description, the shared cells GG in the shared group G far away from the substrate 10 side can be defined as top shared cells, and the shared cells GG close to the substrate 10 side can be defined as bottom shared cells. In the shared group G: two layers of shared cells GG share the same gate line 20d, and the gate line 20d is formed on the bottom side of the shared gate layer in the top shared cell and the top side of the shared gate layer in the bottom shared cell, and the read and write lines of the top shared cell and the read and write lines of the bottom shared cell are independently set. In this way, while realizing independent control of each layer of the memory device layer 20 in the shared group G, the production of the gate line 20d can be further saved, thereby reducing the production cost.

[0092] Alternatively, if Figure 8 As shown, multiple sharing groups G can be set. In two adjacent sharing groups G: the bottom read / write line in the sharing group G away from the substrate 10 side and the top read / write line in the sharing group G close to the substrate 10 side are at least partially shared, and the gate line 20d of the sharing group G away from the substrate 10 side and the gate line 20d of the sharing group G close to the substrate 10 side are independently set. While realizing independent control of each storage device layer 20, it can also further save the production of read / write lines and reduce the production cost.

[0093] Among them, based on any of the embodiments mentioned above in the present disclosure, by making the active layer 201 of the transistor 20b independently arranged relative to the substrate 10 of the semiconductor structure, compared with the solution of using part of the substrate 10 as the active layer 201, the storage device layer 20 can be arranged in multiple layers and stacked along the vertical direction Z to improve the storage density. At the same time, the design difficulty and technical cost of the transistor 20b can also be reduced.

[0094] In addition, the present disclosure also provides a method for manufacturing a semiconductor structure, which is used to manufacture the semiconductor structure described in any of the aforementioned embodiments, wherein the structure, shape, positional relationship with other layers, connection relationship, etc. of each layer in the semiconductor structure can all refer to the aforementioned contents and will not be repeated here.

[0095] The method for manufacturing the semiconductor structure disclosed herein may include:

[0096] Step S100, providing a substrate 10, for example, the substrate 10 may be a stacked structure, such as Fig. 9 As shown, the substrate 10 may include a single crystal semiconductor material layer 101 and an insulating isolation layer 102 formed on the single crystal semiconductor material layer 101;

[0097] Step S200, forming at least one memory device layer 20 stacked along a vertical direction Z on the substrate 10, referring to Figures 1 to 3 as well as Figures 6 to 8 As shown, the method for forming the memory device layer 20 includes:

[0098] A first signal line 20a, a transistor 20b, a second signal line 20c and a selection line 20d are formed on the substrate 10. One of the first signal line 20a and the second signal line 20c is a reference voltage line, and the other is a read-write line. The gate layer 202 of the transistor 20b is connected to the selection line 20d. The active layer 201 of the transistor 20b extends along the vertical direction Z and is independently arranged relative to the substrate 10. The bottom end of the active layer 201 is connected to the first signal line 20a; the top end of the active layer 201 is connected to the second signal line 20c.

[0099] In the present disclosure, the step of forming the first signal line 20a in the bottommost memory device layer 20 on the substrate 10 may include:

[0100] In step S2001, a metal conductive material film and a semiconductor material film are sequentially formed on the substrate 10 to cover the entire surface, so as to form a composite conductive film; wherein, in step S2001, a transition conductive material film may also be formed between the metal conductive material film and the semiconductor material film, and the transition conductive material film may be prepared by deposition, or may be formed by a silicidation reaction between the metal conductive material film and the semiconductor material film. It is understandable that the composite conductive film may include a metal conductive material film, a semiconductor material film, and a transition conductive material film formed between the metal conductive material film and the semiconductor material film.

[0101] In step S2002, the composite conductive film is patterned to form a plurality of fractures penetrating the composite conductive film, wherein the composite conductive film is divided into a plurality of first signal lines 20a arranged at intervals under the fractures, and the first signal line 20a may include a metal conductive material layer 207, a transition conductive material layer 208 and a semiconductor material layer 206 stacked in sequence.

[0102] In other embodiments, the step of forming the first signal line 20a in the bottommost storage device layer 20 on the substrate 10 may include: after sequentially forming a semiconductor material film covering the entire surface on the substrate 10, patterning the semiconductor material film to form a plurality of fractures penetrating the semiconductor material film, wherein the semiconductor material film is divided into a plurality of first signal lines 20a arranged at intervals under the fractures, and the first signal line 20a may include a semiconductor material layer 206.

[0103] In other embodiments, when the material layer of the first signal line 20 a is formed in step S2001 , a semiconductor material film or a transition conductive material film may not be formed, depending on the specific situation.

[0104] It should be noted that the first signal line 20a produced in the present invention can be used as a read-write line, but is not limited to this. It can also be used as a reference voltage line. When the first signal line 20a is used as a reference voltage line, it is not limited to the above-mentioned production method to form a plurality of spaced reference voltage lines, and the composite conductive film does not need to be patterned, and the composite conductive film can be directly used as the reference voltage line for the entire surface.

[0105] In addition, it should be understood that, except for the first signal line 20a in the bottom storage device layer 20, the first signal line 20a in other storage device layers 20 can also be manufactured according to the above steps, or manufactured in other ways, which can be selected according to actual conditions.

[0106] In the present disclosure, for transistors 20 b of different structures, the manufacturing methods of the present disclosure are different, such as the descriptions of the following schemes three and four.

[0107] Option 3

[0108] In the third solution, after forming the first signal line 20a, a GAA type transistor 20b may be formed on the substrate 10, wherein the step of forming the GAA type transistor 20b may include:

[0109] Step S2003, forming a first insulating dielectric layer 204 on the substrate 10, the first insulating dielectric layer 204 at least covering the top surface of the first signal line 20a, such as Fig.10 As shown; it should be noted that, combined with Fig.10 and Fig.12 As shown, when a plurality of first signal lines 20a are provided and arranged at intervals, the first insulating dielectric layer 204 may also be formed in the gaps between adjacent first signal lines 20a. In this embodiment, the surface of the first insulating dielectric layer 204 away from the substrate 10 may be polished by a CMP (Chemical Mechanical Polishing) device to form a plane parallel to the substrate 10. The flat surface is conducive to the preparation of subsequent film layers.

[0110] Step S2004, forming a conductive film layer 211 and a second insulating dielectric layer 205 stacked in sequence along a vertical direction Z on the top surface of the first insulating dielectric layer 204, referring to Fig.13 As shown, it should be understood that, in this embodiment, the conductive film layer 211 and the second insulating dielectric layer 205 are film structures that cover the entire surface of the first insulating dielectric layer 204, and the conductive film layer 211 is patterned in the subsequent step S2008. In other embodiments, the conductive film layer 211 may be formed and then patterned into a gate line, and then the entire second insulating dielectric layer 205 is prepared;

[0111] Step S2005, forming a filling hole S1 penetrating the second insulating dielectric layer 205, the conductive film layer 211 and the first insulating dielectric layer 204 along the vertical direction Z, wherein the filling hole S1 exposes a portion of the first signal line 20a, as shown in FIG. Fig.14 As shown, it should be understood that a plurality of filling holes S1 may be provided and arranged at intervals in the first horizontal direction X and the second horizontal direction Y;

[0112] Step S2006, forming a gate insulating layer 203 on the inner wall of the filling hole S1, the inner wall of the gate insulating layer 203 is formed into a through hole S2 penetrating along the vertical direction Z, and the through hole S2 exposes a portion of the first signal line 20a, referring to Fig.15 As shown;

[0113] Step S2007, forming an active layer 201 in the through hole S2 of the gate insulating layer 203;

[0114] Step S2008, patterning the conductive film layer 211 to form a plurality of gate lines 20d arranged at intervals, wherein the gate lines 20d intersect with the extending direction of the read / write lines, for example, the gate lines 20d may extend along a first horizontal direction X, and the read / write lines may extend along a second horizontal direction Y; wherein the gate lines 20d include at least one gate layer 202, each gate layer 202 at least partially surrounds an active layer 201, and specifically, each gate layer 202 may completely surround an active layer 201, refer to Figure 4 and 16 shown.

[0115] For example, in step S2005, the filling hole S1 not only penetrates the second insulating dielectric layer 205, the conductive film layer 211 and the first insulating dielectric layer 204, but can also be overetched into the first signal line 20a. For example, the bottom end of the filling hole S1 can be embedded in the semiconductor material layer 206 of the first signal line 20a. Fig.14 That is, in some embodiments, the filling hole S1 is recessed into the surface of the first signal line 20a; in other embodiments, when the first signal line 20a includes a metal conductive material layer 207, a transition conductive material layer 208, and a semiconductor material layer 206 stacked in sequence, or the first signal line 20a includes a semiconductor material layer 206, the filling hole S1 is recessed into the surface of the semiconductor material layer 206 without passing through the semiconductor material layer 206.

[0116] For example, in step S2006, specific steps may include:

[0117] Step S20061, forming a silicon oxide film and a silicon nitride film in sequence, wherein a portion of the silicon oxide film and the silicon nitride film are sequentially stacked to cover the surface of the second insulating dielectric layer 205 away from the substrate 10, and another portion of the silicon oxide film and the silicon nitride film are located in each filling hole S1, wherein the silicon oxide film and the silicon nitride film located in the filling hole S1 may be a groove-shaped structure, and the groove-shaped structure of the silicon nitride film is located in the groove-shaped structure of the silicon oxide film;

[0118] Step S20062, removing the bottom of the groove structure in the silicon nitride film and the silicon oxide film to expose the first signal line 20a;

[0119] Step S20063, removing the remaining portion of the groove structure in the silicon nitride film located in the filling hole S1, that is, removing the groove sidewall of the groove structure in the silicon nitride film, so that the portion of the silicon oxide film remaining in the filling hole S1 forms a gate insulating layer 203.

[0120] In the third embodiment, during the process of manufacturing the gate insulating layer 203, the gate insulating layer 203 formed by the silicon oxide film can be protected by forming a silicon nitride film, thereby improving the quality of the gate insulating layer and reducing current leakage. In this embodiment, the gate insulating layer 203 is formed by using a silicon oxide film, but it can be understood that the material in the actual gate insulating layer 203 can be set according to specific needs, and the silicon nitride film can also be replaced as its material layer according to specific needs.

[0121] It should be noted that, in the process of forming the gate insulating layer 203, step S20063 may be omitted, that is, the groove sidewalls of the groove structure in the silicon nitride film may be retained in the filling hole S1, so as to form the gate insulating layer 203 together with the portion of the silicon oxide film retained in the filling hole S1. In step S2006, the gate insulating layer 203 may also be prepared by other methods known in the art, which are not specifically limited in the present invention.

[0122] For example, in step S2007, the specific steps may include: sequentially forming a first electrode region 2012, a channel region 2011, and a second electrode region 2013 in the through hole S2 of the gate insulating layer 203, wherein the top surface of the first electrode region 2012 is higher than the bottom surface of the gate layer 202, the bottom surface of the second electrode region 2013 is lower than the top surface of the gate layer 202, and the first electrode region 2012 and the second electrode region 2013 have the same conductivity type, and are different from the conductivity type of the channel region 2011, with reference to Fig.16 As shown, that is, the active layer 201 formed in step S2007 is a junction type active layer.

[0123] In the third embodiment, it is mentioned above that the first signal line 20a may include a semiconductor material layer 206, and the semiconductor material layer 206 of the first signal line 20a may be exposed at the through hole S2; based on this, the step of forming the first electrode region 2012 in the through hole S2 of the gate insulation layer 203 includes: epitaxially growing the semiconductor material layer 206 of the first signal line 20a exposed at the through hole S2 to form the first electrode region 2012. In this embodiment, the epitaxial growth of the semiconductor material layer 206 of the first signal line 20a exposed at the through hole S2 to form the first electrode region 2012 is also regarded as constituting an integrated structure with the semiconductor material layer 206 of the first signal line 20a. However, it is not limited thereto, and a semiconductor material having the same conductivity type as the semiconductor material layer 206 of the first signal line 20a may be directly deposited in the through hole S2. It should be understood that after the semiconductor material having the same conductivity type as the semiconductor material layer 206 of the first signal line 20a is deposited, the semiconductor material portion on the inner wall of the through hole S2 and the top of the second insulating dielectric layer 205 needs to be removed to form the first electrode region 2012. Fig.17 shown.

[0124] For example, in the third embodiment, the step of forming the channel region 2011 in the through hole S2 of the gate insulating layer 203 may include: after forming the first electrode region 2012, depositing a semiconductor film of a conductivity type different from that of the first electrode region 2012, and then etching back the semiconductor film to form the channel region 2011 in the through hole S2, wherein the top surface of the channel region 2011 is lower than the top surface of the gate layer 202, referring to Fig.18 shown.

[0125] In the third embodiment, when the second signal line 20c includes a semiconductor material layer 206, the semiconductor material layer 206 of the second signal line 20c can be formed into an integrated structure with the second electrode region 2013 of the active layer 201; specifically, after forming the channel region 2011 of the active layer 201, a semiconductor thin film layer 212 of the same conductivity type as the semiconductor material layer 206 of the first signal line 20a can be formed on the substrate 10, and the semiconductor thin film layer 212 covers the channel region 2011, the gate insulating layer 203 and the second insulating dielectric layer 205, referring to Fig.19 As shown; then, the semiconductor thin film layer 212 can be patterned to form a plurality of semiconductor portions arranged at intervals, wherein the semiconductor portion includes the second electrode region 2013 of the active layer 201 and the semiconductor material layer 206 of the second signal line 20c, the second electrode region 2013 of the active layer 201 is filled in the through hole S2, and the semiconductor material layer 206 of the second signal line 20c covers the second electrode region 2013, the gate insulation layer 203 and the second insulating medium layer 205.

[0126] In other embodiments, the semiconductor material layer 206 of the second signal line 20c and the second electrode region 2013 of the active layer 201 may also be fabricated separately so that the two have different doping concentrations, or the semiconductor material layer 206 of the second signal line 20c and the second electrode region 2013 of the active layer 201 may be fabricated integrally and then further doped. It is understood that making the semiconductor material layer 206 have a higher doping concentration can reduce impedance.

[0127] In other embodiments, when the transistor 20b is a junction-less transistor, the active layer 201 and the semiconductor material layer 206 of the second signal line 20c can be formed by epitaxial growth on the upper surface of the semiconductor material layer 206 of the first signal line 20a, depending on the specific situation.

[0128] In the present disclosure, the second signal line 20c can be a reference voltage line or a read / write line; if the second signal line 20c manufactured in the present disclosure is used as a reference voltage line, the semiconductor film layer 212 can be patterned in the aforementioned manner, and the patterned reference voltage line can have the same extension direction as the gate line 20d, or can be different from the extension direction of the gate line 20d, depending on the specific situation. In addition, the semiconductor film layer 212 can be directly connected to the electrode areas used for grounding of all transistors 20b in the entire storage device layer 20 without patterning the semiconductor film layer 212, so as to reduce the steps of patterning and reduce the manufacturing cost; if the second signal line 20c manufactured in the present disclosure is used as a read / write line, it is necessary not only to pattern the semiconductor film layer 212, but also to make the overall extension direction of the patterned second signal line 20c different from the extension direction of the gate line 20d, for example: when the gate line extends in the first horizontal direction X, the read / write line as a whole can extend in the second horizontal direction Y.

[0129] For example, in the third solution, when the second signal line 20c is used as a read / write line, the step of forming the second signal line 20c may specifically include step S2009, step S2010, step S2011, and step S2012.

[0130] In step S2009, a semiconductor thin film layer 212 having the same conductivity type as the semiconductor material layer 206 of the first signal line 20a is formed, and the semiconductor thin film layer 212 covers the channel region 2011, the gate insulating layer 203 and the second insulating dielectric layer 205. Fig.19 As shown; in other embodiments, the semiconductor film layer 212 may only fill the through hole S2, and its upper surface is flush with the upper surface of the second insulating medium layer 205, and the semiconductor material layer 206 of the second signal line 20c is prepared in the subsequent step S2012.

[0131] In step S2010, a first break extending in the first horizontal direction X and a second break extending in the second horizontal direction Y are formed, the first break sequentially penetrates the semiconductor film layer 212, the second insulating medium layer 205 and the conductive film layer 211 along the vertical direction Z, and is located between adjacent filling holes S1 in the second horizontal direction Y, the second break penetrates the semiconductor film layer 212, and is located between adjacent filling holes S1 in the first horizontal direction X, the conductive film layer 211 forms a plurality of gate lines 20d extending in the first horizontal direction X under the action of the first break, and the semiconductor film layer 212 forms a plurality of semiconductor portions arranged at intervals in the first horizontal direction X and the second horizontal direction Y under the action of the first break and the second break, the semiconductor portion including the second electrode region 2013 and the second The semiconductor material layer 206 of the signal line 20c and the second electrode region 2013 are filled in the through hole S2, and the semiconductor material layer 206 of the second signal line 20c covers the second electrode region 2013, the gate insulation layer and the second insulating medium layer 205. That is to say, step S2010 may include the aforementioned step S2008. Specifically, in the process of forming the first break, a patterning process of the semiconductor film layer 212 is realized, and the patterning process of the conductive film layer 211 is completed, so as to reduce the process steps and reduce the cost. It should be noted that in this scheme, no special explanation is given for the order of forming the first break and the second break. The first break can be formed before or after the second break. Within the range allowed by the etching process, the first break and the second break can also be carried out simultaneously.

[0132] In other embodiments, when the semiconductor film layer 212 only fills the through hole S2, the step of forming the second break in step S2010 can be omitted, and other steps involving the second break in the subsequent step S2011 can be deleted.

[0133] In other embodiments, the conductive film layer 211 has been patterned into a gate line before preparing the second insulating dielectric layer 205 , and the semiconductor material layer 206 can be patterned simultaneously with the transition conductive material layer 208 and the metal conductive material layer 207 in the second signal line 20 c .

[0134] In step S2011, an insulating filling portion 209 is formed in the first fracture and the second fracture, and the top surface of the insulating filling portion 209 is flush with the top surface of the semiconductor portion. Fig.16As shown, it should be noted that the insulating filling part 209 in the first break and the second break can be filled at the same time or in sequence. For example, after the second break is formed and before the first break is formed, the second break can be filled with the insulating filling part 209 first, and then, after the first break is formed, the insulating filling part 209 can be filled in the first break. However, it is not limited to this. The first break can be formed first, and then the insulating filling part 209 can be filled in the first break, and then the second break can be formed, and then the insulating filling part 209 can be filled in the second break, or, after the first break and the second break are formed, the insulating filling part 209 can be formed in the first break and the second break at the same time.

[0135] In step S2012, a plurality of transition conductive material layers 208 of second signal lines 20c arranged at intervals in the first horizontal direction X and extending in the second horizontal direction Y and a plurality of metal conductive material layers 207 of second signal lines 20c arranged at intervals in the first horizontal direction X and extending in the second horizontal direction Y are formed. In the second signal lines 20c, the metal conductive material layers 207 and the transition conductive material layers 208 correspond one to one in the vertical direction Z, and each transition conductive material layer 208 is connected to the top surface of the plurality of semiconductor portions arranged in the second horizontal direction Y. Fig. 20As shown, for example, the transition conductive material layer 208 and the metal conductive material layer 207 in the second signal line 20c can be patterned at the same time to form a long strip structure extending along the second horizontal direction Y, for example: a transition conductive material film and a metal conductive material film covering the entire surface can be formed on the substrate 10 first, and then the transition conductive material film and the metal conductive material film are patterned to simultaneously cut out the transition conductive material layer 208 and the metal conductive material layer 207 in the second signal line 20c, which can reduce the manufacturing cost. In other embodiments, when the semiconductor film layer 212 only fills the through hole S2, the semiconductor material layer 206 can be prepared as the second signal line 20c in step S2012, or the semiconductor material layer 206, the transition conductive material film and the metal conductive material film can be deposited and prepared in sequence to prepare the second signal line 20c, or the semiconductor material layer 206 and the metal conductive material film can be deposited and prepared in sequence and then the two are subjected to silicide reaction to form a transition conductive material film, thereby obtaining the second signal line 20c, which can be determined according to the specific situation and will not be given too many examples. In this solution, in any two adjacent memory device layers 20: at least part of the second signal line 20c in the bottom memory device layer is shared as at least part of the first signal line 20a in the top memory device layer, for example: the metal conductive material layer 207 of the second signal line 20c in the bottom memory device layer can be shared by the first signal line 20a in the top memory device layer. The first signal line 20a in the top memory device layer can be formed simultaneously with the transition conductive material layer 208 and the metal conductive material layer 207 in the second signal line 20c, and the specific steps may include:

[0136] First, a first transition conductive material film, a metal conductive material film, a second transition conductive material film and a semiconductor material film are formed on the substrate 10, which are covered on the entire surface and stacked in sequence. It should be noted that the first transition conductive material film is used to form a transition conductive material layer 208 of the second signal line 20c in the bottom storage device layer after subsequent patterning, and the metal conductive material film is used to form a metal conductive material layer 207 shared by the second signal line 20c in the bottom storage device layer and the first signal line 20a in the top storage device layer after subsequent patterning. The second transition conductive material film and the semiconductor material film are used to form a transition conductive material layer 208 and a semiconductor material layer 206 of the first signal line 20a in the top storage device layer after subsequent patterning;

[0137] Then, the first transition conductive material film, the metal conductive material film, the second transition conductive material film and the semiconductor material film are patterned at the same time to form a composite linear structure, such as Fig.21As shown, the composite linear structure includes a metal conductive material layer 207 and a transition conductive material layer 208 of the second signal line 20c in the bottom storage device layer and a metal conductive material layer 207, a transition conductive material layer 208 and a semiconductor material layer 206 of the first signal line 20a in the top storage device layer, wherein the metal conductive material layer 207 of the second signal line 20c in the bottom storage device layer and the metal conductive material layer 207 of the first signal line 20a in the top storage device layer are a common layer.

[0138] In other embodiments, the composite line structure may include only the semiconductor material layer 206; or the semiconductor material layer 206, the metal conductive material layer 207 and the transition conductive material layer 208 of the second signal line 20c and the metal conductive material layer 207, the transition conductive material layer 208 and the semiconductor material layer 206 of the first signal line 20a in the top storage device layer; or the metal conductive material layer 207 of the second signal line 20c in the bottom storage device layer and the metal conductive material layer 207 of the first signal line 20a in the top storage device layer are different layers that are electrically connected to each other or insulated from each other, depending on actual needs.

[0139] In other embodiments, after forming the conductive film layer 211, the conductive film layer 211 may be directly patterned to form a plurality of spaced-apart gate lines 20d; then, an insulating dielectric layer is deposited to cover the top surface of the gate line 20d and fill the gaps between adjacent gate lines 20d; then, the insulating dielectric layer is planarized and stops at the top surface of the gate line 20d, that is, the portion of the insulating dielectric layer covering the top surface of the gate line 20d is removed, and only the portion filling between adjacent gate lines 20d is retained, and this portion is defined as an isolation portion; then, a second insulating dielectric layer 205 is formed to cover the isolation portion and the gate line 20d on the entire surface. It can be understood that the second insulating dielectric layer 205 and the isolation portion can be prepared as a whole; then, the aforementioned steps S2005 are performed in sequence. , step S2006 and step S2007, the filling hole S1 formed in step S2005 penetrates the second insulating dielectric layer 205, the gate line 20d and the first insulating dielectric layer 204 along the vertical direction Z; after executing step S2007, a semiconductor film layer, a transition conductive material film, and a metal conductive material film covering the entire surface can be formed in sequence, and then the whole is patterned to form a second signal line 20c intersecting with the extension direction of the gate line 20d. At the same time, a second electrode region 2013 of a row of transistors 20b is also formed. The row mentioned here refers to a plurality of transistors 20b arranged along the extension direction of the second signal line 20c, that is, the second electrode region 2013 of a row of transistors 20b can be integrally formed with the semiconductor material layer 206 of the second signal line 20c.

[0140] In this scheme, in any two adjacent storage device layers 20: the second signal line 20c of the bottom storage device layer and the first signal line 20a of the top storage device layer are shared, and the shared signal lines as a whole are defined as shared composite signal lines. If the storage device layer 20 of the semiconductor structure in this scheme is set to three or more layers, there may be multiple shared composite signal lines, and one of the adjacent shared composite signal lines in the vertical direction Z is a reference voltage line, and the other is a read-write line.

[0141] In addition, after the last memory device layer 20 (ie, the memory device layer 20 farthest from the substrate 10) is formed, an insulating capping layer 210 may be formed. Figure 1 As shown, the second signal line 20c of the last storage device layer 20 is covered. After the insulating capping layer 210 is formed, a via structure (not shown in the figure) can be designed to facilitate the lead-out of the signal lines of each storage device layer 20, which will not be explained in detail here.

[0142] Option 4

[0143] In the fourth embodiment, after forming the first signal line 20a, a CAA transistor 20b may be formed on the substrate 10, wherein the step of forming the CAA transistor 20b may include:

[0144] Step S2100, forming a first insulating dielectric layer 204 on the substrate 10, wherein the first insulating dielectric layer 204 at least covers the top surface of the first signal line 20a. Fig.11 It should be noted that when the first signal line 20a is provided with multiple and spaced apart arrangements, Fig.11 and Fig.12 As shown, the first insulating dielectric layer 204 may also be formed in the gap between adjacent first signal lines 20a. In this embodiment, the surface of the first insulating dielectric layer 204 away from the substrate 10 may be planarized by a CMP (Chemical Mechanical Polishing) device to form a plane parallel to the substrate 10, which is beneficial to the preparation of subsequent film layers.

[0145] Step S2101, forming a filling hole S1 penetrating the first insulating dielectric layer 204 in the vertical direction Z, wherein the filling hole S1 exposes a portion of the first signal line 20a, referring to Fig. 22 As shown;

[0146] Step S2102, forming an annular active layer 201 on the inner wall of the filling hole S1, forming a through hole S2 penetrating along the vertical direction Z on the inner wall of the annular active layer 201, and exposing a portion of the first signal line 20a through the through hole S2, Fig.23 As shown;

[0147] Step S2103, forming a groove-shaped gate insulating layer 203 in the through hole S2, the groove-shaped gate insulating layer 203 covers the inner wall of the ring-shaped active layer 201 and the area of ​​the first signal line 20a exposed by the through hole S2, such as Fig.24 As shown;

[0148] Step S2104, forming a gate layer 202 in the groove of the groove-shaped gate insulating layer 203, referring to Fig.25 shown.

[0149] It should be noted that step S2103 and step S2104 can be performed sequentially, but are not limited thereto. After step S2102, a gate insulating film material layer 214 and a gate film material layer 215 can be formed sequentially. The gate insulating film material layer 214 includes a planar portion located on the top surface of the first insulating dielectric layer 204 and a groove-shaped portion located in the filling hole S1. The gate film material layer 215 includes a planar portion located on the top surface of the gate insulating film material layer 214 and a columnar portion filled in the filling hole S1. Fig.26 As shown, then, the gate insulating film material layer 214 and the gate film material layer 215 are removed from the top surface of the first insulating dielectric layer 204 to simultaneously form the gate layer 202 and the gate insulating layer 203, as shown in FIG. Fig.25 As shown, the top of the gate layer 202 can be protruded, so that the second signal line 20c formed subsequently includes a semiconductor material layer, and when the semiconductor material layer is in contact with the top surface of the active layer 201 and the conductivity type is different, the junction formed by the active layer 201 and the semiconductor material layer of the second signal line 20c can be covered by the gate layer 202. In some embodiments, when the active layer 201 is a junction-free active layer, and the conductivity type of the semiconductor material layer 206 in contact with the active layer 201 in the first signal line 20a and the second signal line 20c is different from the conductivity type of the active layer 201, when designing the gate layer 202, it is necessary to make the bottom end of the gate layer 202 lower than the bottom end of the active layer 201, that is, the bottom end of the through hole S2 mentioned in step S2102 needs to be embedded in the semiconductor material layer 206 of the first signal line 20a, and the bottom end of the groove of the gate insulating layer 203 in step S2103 also needs to be lower than the bottom end of the active layer 201, so that the gate layer 202 can be formed in the following manner. The bottom end of the gate layer 202 formed in the subsequent step S2104 is lower than the bottom end of the active layer 201, and the top end of the gate layer 202 is also required to be higher than the top end of the active layer 201, so that the junction formed by the active layer 201 and the semiconductor material layer 206 of the first signal line 20a, and the junction formed by the active layer 201 and the semiconductor material layer 206 of the second signal line 20c are both covered by the gate layer 202, wherein one of the semiconductor material layer 206 of the first signal line 20a and the semiconductor material layer 206 of the second signal line 20c can be regarded as the source region of the transistor 20b, and the other can be regarded as the drain region of the transistor 20b.

[0150] It should be noted that the junction formed at the source region may be covered by the gate layer 202 or may not be covered, but the junction formed at the drain region must be covered by the gate layer 202 .

[0151] In some embodiments, the gate insulating layer 203 is prepared by deposition. In some embodiments, the gate insulating layer 203 is formed by oxidizing a portion of the inner wall of the active layer 201 and the surface of the semiconductor material layer 206 (not shown in the figure) in the first signal line 20a. The oxidation method is, for example, ISSG (In Situ Steam Generation) or thermal oxidation.

[0152] After forming the gate layer 202 and before forming the second signal line 20c, the manufacturing method further includes:

[0153] Step S2105, forming an isolation insulating portion 216, such as Fig. 27 As shown, the isolation insulating portion 216 completely covers the top of the gate layer 202 and exposes at least part of the top surface of the annular active layer 201, so that the subsequently formed second signal line 20c can be insulated from the gate layer 202 while contacting the top surface of the annular active layer 201.

[0154] It should be noted that the manufacturing process of the CAA transistor is simple and the manufacturing cost is low.

[0155] In the fourth embodiment of the present invention, the multi-layer memory device layer 20 can be divided into at least one common unit GG, and the common unit GG includes two adjacent memory device layers 20, and the memory device layer 20 on the side away from the substrate 10 in the common unit GG is defined as the top memory device layer, and the memory device layer 20 on the side close to the substrate 10 is defined as the bottom memory device layer, wherein the specific relationship between the layers in the common unit GG can be referred to the aforementioned content, and will not be repeated here.

[0156] Wherein, when manufacturing the common unit GG, the manufacturing method further comprises:

[0157] Step S2106, after forming the reference voltage line of the common unit GG (i.e., the first signal line 20a of the top storage device layer and the second signal line 20c of the bottom storage device layer), a third insulating dielectric layer and a top read / write line are sequentially formed. Fig.28 As shown, the third insulating dielectric layer refers to the first insulating dielectric layer 204 of the top storage device layer in the common unit GG, and the top read / write line refers to the second signal line 20c of the top storage device layer in the common unit GG;

[0158] Step S2107, forming a first alignment hole penetrating the top read / write line and the third insulating dielectric layer, the first alignment hole corresponds to the filling hole S1 one by one, and exposes a portion of the reference voltage line. It should be noted that the size and manufacturing method of the first alignment hole can refer to Fig. 22 In the method for making the filling hole S1, in this solution, the orthographic projection of the first alignment hole on the substrate 10 and the orthographic projection of the filling hole S1 on the substrate 10 at least partially overlap;

[0159] Step S2108, forming a groove-shaped active layer on the inner wall of the first alignment hole, the groove-shaped active layer covers the top read / write line and the hole surface of the third insulating dielectric layer, and covers the area of ​​the reference voltage line corresponding to the first alignment hole;

[0160] Step S2109, forming a second alignment hole S3, referring to Fig.29 As shown, the second alignment hole S3 penetrates the groove bottom of the groove active layer, the reference voltage line and the isolation insulating portion 216 from the inner side wall of the groove active layer, and the second alignment hole S3 exposes the top surface of the bottom gate layer, which refers to the gate layer 202 of the transistor 20b of the bottom memory device layer in the common unit GG;

[0161] Step S2110, forming an annular gate insulating layer 203 on the inner wall of the second alignment hole S3, the inner wall of the annular gate insulating layer 203 is formed into a third alignment hole, the third alignment hole exposes the top surface of the bottom gate layer, and a top gate layer is formed in the third alignment hole, the top gate layer is filled in the third alignment hole and contacts with the top surface of the bottom gate layer, refer to Fig.30 As shown, this top gate layer refers to the gate layer 202 of the transistor 20b of the top memory device layer in the shared cell GG;

[0162] In other embodiments, the second alignment hole S3 at least extends through the reference voltage line but does not extend to the isolation insulating portion 216, or extends to but does not penetrate the isolation insulating portion 216, and then penetrates the isolation insulating portion 216 to expose the top surface of the underlying gate layer when the third alignment hole is formed in step S2110.

[0163] Step S2111, forming a fourth insulating dielectric layer 217 covering the grooved active layer and the top read / write line, referring to Fig.31 As shown; the fourth insulating dielectric layer 217 exposes the top surface of the top gate layer;

[0164] Step S2112, forming a gate line 20d on the top surface of the fourth insulating dielectric layer 217 so as to contact the top surface of the top gate layer, referring to Fig.32 As shown, the gate line 20d contacts the top surface of the top gate layer and is insulated from the top active layer (ie, the active layer 201 of the top memory device layer) and the top read / write line by the fourth insulating dielectric layer 217 .

[0165] For example, in the common unit GG: the active layer 201 is one of an N-type semiconductor and a P-type semiconductor, the top read-write line (i.e., the second signal line 20c of the top storage device layer) and the bottom read-write line (i.e., the first signal line 20a of the bottom storage device layer) both include semiconductor material layers, and the semiconductor material layers of the top read-write line and the bottom read-write line are both the other of an N-type semiconductor and a P-type semiconductor; wherein the bottom of the groove of the groove-shaped gate insulating layer in the bottom storage device layer is embedded in the semiconductor material layer of the bottom read-write line, and the top surface of the bottom of the groove in the groove-shaped gate insulating layer is lower than the bottom surface of the active layer 201 in the bottom storage device layer, so that the bottom surface of the common gate layer is lower than the bottom surface of the active layer 201 in the bottom storage device layer, thereby making the PN junction formed by the bottom active layer (i.e., the active layer 201 of the bottom storage device layer) and the semiconductor material layer of the bottom read-write line covered by the common gate layer.

[0166] Among them, in the orthographic projection of the substrate 10: the gate line 20d covers the boundary of the first alignment hole, so that the bottom active layer (i.e.: the active layer 201 of the top storage device layer) and the semiconductor material layer of the top read-write line form a PN junction covered by the gate line 20d; in this embodiment, the fourth insulating dielectric layer 217 can be located between the gate line 20d and the semiconductor material layer of the top read-write line, step S2111 is performed during step S2110, the fourth insulating dielectric layer 217 is prepared on the same layer as the annular gate insulating layer to form a continuous film layer with equal thickness, and then the step of preparing the top gate layer in step S2110 is performed.

[0167] In other embodiments, the fourth insulating dielectric layer 217 may not be prepared on the same layer as the annular gate insulation layer. For example, after the annular gate insulation layer and the top gate layer are formed in sequence, the fourth insulating dielectric layer 217 covering the top gate layer, the annular gate insulation layer 203, the groove-shaped active layer and the top read / write line is first formed, and then the fourth insulating dielectric layer 217 is patterned to expose the top surface of the top gate layer; thereafter, step S2112 is executed.

[0168] In other embodiments, after step S2112, the method for manufacturing the common unit GG may further include:

[0169] Step S2113, forming an isolation insulating layer 218 covering at least the fourth insulating dielectric layer 217 and filling between adjacent gate lines 20d, referring to Fig.32 shown.

[0170] In other embodiments, when the first signal line 20a of the bottom storage device layer and the second signal line 20c of the top storage device layer are read-write lines, and are a composite line layer formed by a semiconductor material layer, a metal material layer, and a transition metal material layer having a conductivity type different from that of the active layer 201, the semiconductor material layer contacts the active layer 201 to form a PN junction.

[0171] Among them, the common unit GG of this scheme four can be set in multiples, and two adjacent common units GG can be formed completely independently. That is to say, after forming step S2114, steps S2106 to S2114 can be repeated multiple times to produce more layers of common units GG.

[0172] It should be understood that the multi-layer shared unit GG is not limited to the independent formation mentioned above, and can also form at least one shared group G mentioned above, wherein the manufacturing method of the shared group G may include the steps S2106 to S2114 mentioned above, and the steps S2106 to S2114 mentioned above are used to form the bottom shared unit of the shared group G. After the step S2114 is formed, the top shared unit is formed. It should be noted that the first signal line 20a of the bottom storage device layer in the top shared unit needs to be insulated from the gate line 20d. Therefore, the isolation insulating layer 218 produced in step S2114 not only covers the fourth insulating dielectric layer 217 and fills between adjacent gate lines 20d, but also covers the top surface of the gate line 20d.

[0173] In this embodiment, the overall formation steps of the top-layer common unit and the bottom-layer common unit in the common group G may be similar, but because the top-layer common unit needs to share the gate line 20d with the bottom-layer common unit, when forming the filling hole S1 of the bottom-layer storage device layer in the top-layer common unit, the filling hole S1 needs to penetrate the first signal line 20a of the bottom-layer storage device layer in the top-layer common unit and the isolation insulating layer 218 in the bottom-layer common unit to expose the gate line 20d of the bottom-layer common unit, so as to facilitate the subsequent manufacture of the gate layer 202 of the top-layer common unit, so that the gate layer 202 of the top-layer common unit is in contact with and connected to the gate line 20d, thereby realizing the scheme that the two layers of common units GG in the common group G share the same gate line 20d. In addition, the remaining steps of the top-layer common unit can refer to the manufacturing method of each layer in the bottom-layer common unit in scheme 4, and will not be described in detail here.

[0174] Among them, when there is no common structure between adjacent storage device layers 20, the manufacturing method of the single-layer storage device layer 20 may include: forming a first signal line 20a, a first insulating dielectric layer 204, and a second signal line 20c in sequence, and then making a through hole that penetrates the second signal line 20c, the first insulating dielectric layer 204 and the first signal line 20a, and forming an active layer 201 and a gate insulating layer 203 in the through hole in sequence, and then forming a gate layer 202 and a gate line 20d. The gate layer 202 and the gate line 20d can be formed as a whole or can be made separately. It should be understood that the manufacturing method of the single-layer storage device layer 20 is not limited to this, as long as the CAA structure of this embodiment can be produced.

[0175] In the present disclosure, the terms "first", "second", "third", "fourth", etc. are used for descriptive purposes only and are not to be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Thus, a feature defined as "first", "second", "third", "fourth" may explicitly or implicitly include one or more of the feature. In the description of the present application, the meaning of "plurality" is two or more, unless otherwise clearly and specifically defined.

[0176] In the description of this specification, the description with reference to the terms "some embodiments", "exemplarily", etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present application. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described may be combined in any one or more embodiments or examples in a suitable manner. In addition, those skilled in the art may combine and combine the different embodiments or examples described in this specification and the features of the different embodiments or examples, without contradiction.

[0177] Although the embodiments of the present application have been shown and described above, it can be understood that the above embodiments are exemplary and cannot be understood as limitations on the present application. Ordinary technicians in this field can change, modify, replace and modify the above embodiments within the scope of the present application. Therefore, any changes or modifications made in accordance with the claims and description of the present application should fall within the scope of the patent of this application.

Claims

1. A semiconductor structure, characterized in that: include: substrate; as well as At least one memory device layer is stacked on the same side of the substrate in a vertical direction, the memory device layer at least includes a first signal line, a transistor, a second signal line and a gate line, one of the first signal line and the second signal line is a reference voltage line, and the other is a read-write line, wherein: The gate layer of the transistor is connected to the gate line; The active layer of the transistor extends in a vertical direction and is independently arranged relative to the substrate, and the bottom end of the active layer is connected to the first signal line; A top end of the active layer is connected to the second signal line.

2. The semiconductor structure according to claim 1, characterized in that: In the memory device layer: The transistors are provided in plurality and arranged in an array in a first horizontal direction and a second horizontal direction, and the first horizontal direction and the second horizontal direction intersect; A plurality of read / write lines are provided and arranged at intervals in a first horizontal direction, and the read / write lines extend in a second horizontal direction and are connected to active layers of a plurality of transistors arranged in the second horizontal direction; A plurality of the gate lines are provided and arranged at intervals in the second horizontal direction. The gate lines extend in the first horizontal direction and are connected to the gate layers of the transistors arranged in the first horizontal direction.

3. The semiconductor structure according to claim 1, characterized in that: The transistor comprises: a core layer extending in the vertical direction; A sheath layer, at least surrounding the outer peripheral side of the core layer, wherein one of the core layer and the sheath layer is an active layer of the transistor, and the other is a gate layer of the transistor; A gate insulating layer is filled between the gate layer and the active layer.

4. The semiconductor structure according to claim 3, characterized in that: The core layer is the active layer, and the jacket layer is the gate layer; The gate line is formed on a side of the second signal line close to the substrate, a first insulating dielectric layer is formed between the gate line and the first signal line, and a second insulating dielectric layer is formed between the gate line and the second signal line, and the gate layer of the transistor is part of the gate line.

5. The semiconductor structure according to claim 4, characterized in that: The active layer comprises: Channel area; A first electrode region is formed between the first signal line and the channel region, and a top surface of the first electrode region is higher than a bottom surface of the gate layer, and one of the first electrode region and the channel region is an N-type semiconductor, and the other is a P-type semiconductor; The second electrode region is formed between the second signal line and the channel region, and the bottom surface of the second electrode region is lower than the top surface of the gate layer. The second electrode region has the same conductivity type as the first electrode region.

6. The semiconductor structure according to claim 5, characterized in that: The first signal line and the second signal line include semiconductor material layers, wherein: The semiconductor material layer of the first signal line has the same conductivity type as the first electrode region, and the semiconductor material layer of the first signal line is in contact with the first electrode region or forms an integrated structure; The semiconductor material layer of the second signal line has the same conductivity type as that of the second electrode region, and the semiconductor material layer of the second signal line is in contact with the second electrode region or forms an integrated structure.

7. The semiconductor structure according to claim 4, characterized in that: The memory device layer is a multi-layer layer, the gate lines of any two memory device layers are independently arranged, and in at least two adjacent memory device layers: The memory device layer away from the substrate side is defined as a top memory device layer, and the memory device layer close to the substrate side is defined as a bottom memory device layer, wherein at least part of the second signal line in the bottom memory device layer is shared as at least part of the first signal line in the top memory device layer.

8. The semiconductor structure according to claim 3, characterized in that: The core layer is the gate layer, and the sleeve layer is the active layer; Wherein, the gate line is formed on the top or bottom side of the gate layer.

9. The semiconductor structure according to claim 8, characterized in that: The memory device layer is a multi-layer layer, and the multi-layer memory device layer is divided into at least one common unit along the vertical direction, and the common unit includes two adjacent memory device layers, and the memory device layer far from the substrate side in the common unit is defined as the top memory device layer, and the memory device layer close to the substrate side is defined as the bottom memory device layer, wherein in the common unit: The gate layers of two transistors arranged in the vertical direction share the same selection line, and the second signal line of the top storage device layer and the first signal line of the bottom storage device layer are both the read-write lines and are independently arranged.

10. The semiconductor structure according to claim 9, characterized in that: In the common unit: At least part of the second signal line in the bottom memory device layer is shared as at least part of the first signal line in the top memory device layer, so that the first signal line of the top memory device layer and the second signal line of the bottom memory device layer are used together as the reference voltage line of the shared unit; or The first signal line of the top memory device layer and the second signal line of the bottom memory device layer are independently arranged to be used as reference voltage lines of the common unit respectively.

11. The semiconductor structure according to claim 9, characterized in that: In the common unit: the gate layers of two transistors arranged in the vertical direction are directly connected to form a common gate layer, and the gate line is located at the top or bottom side of the common gate layer; or In the shared unit: the gate line of the top storage device layer is formed on the bottom side of the gate layer of the top storage device layer, the gate line of the bottom storage device layer is formed on the top side of the gate layer of the bottom storage device layer, and the gate line of the bottom storage device layer is at least partially shared with the gate line of the top storage device layer.

12. The semiconductor structure according to claim 11, characterized in that: There are multiple shared units, among which: In two adjacent common units, the read / write line of one is independently arranged from the read / write line of the other common unit.

13. The semiconductor structure according to claim 11, characterized in that: In two adjacent shared units: the gate layer of the transistor of one is insulated from the gate layer of the transistor of the other; and the selection line of one is independently arranged from the selection line of the other in the two adjacent shared units, and the read-write lines adjacent to each other in the two adjacent shared units at least share a common part.

14. The semiconductor structure according to claim 11, characterized in that: In the common unit: the gate layers of two transistors arranged in the vertical direction are directly connected to form a common gate layer, and the gate line is located at the top or bottom side of the common gate layer; wherein, The multiple layers of the memory device layers are divided into at least one common group along the vertical direction, and the common group includes two adjacent layers of the common units, and the common units in the common group far away from the substrate side are defined as top common units, and the common units close to the substrate side are defined as bottom common units, wherein in the common group: two layers of the common units share the same gate line, and the gate line is formed on the bottom side of the common gate layer in the top common unit and the top side of the common gate layer in the bottom common unit, and the read and write lines of the top common unit and the read and write lines of the bottom common unit are set independently of each other.

15. The semiconductor structure according to claim 14, characterized in that: The shared groups are arranged in multiple groups, and in two adjacent shared groups: the bottom read / write line in the shared group away from the substrate side and the top read / write line in the shared group close to the substrate side are at least partially shared, and the gate line of the shared group away from the substrate side and the gate line of the shared group close to the substrate side are independently arranged.

16. The semiconductor structure according to claim 8, characterized in that The first signal line and the second signal line include semiconductor material layers, the bottom end of the active layer is in direct contact with the semiconductor material layer of the first signal line, and the top end of the active layer is in direct contact with the semiconductor material layer of the second signal line, wherein: The active layer is one of an N-type semiconductor and a P-type semiconductor, the conductivity type of the semiconductor material layer in the first signal line and the second signal line is the same and is the other of the N-type semiconductor and the P-type semiconductor, and in the orthographic projection of the substrate: the gate line covers at least part of the outer boundary of the active layer, wherein, When the gate line is formed on the top side of the gate layer: the bottom surface of the active layer is higher than the bottom surface of the gate layer; When the gate line is formed on the bottom end side of the gate layer: the top surface of the active layer is lower than the top surface of the gate layer.

17. The semiconductor structure according to claim 16, characterized in that: The materials of the semiconductor material layer and the active layer in the first signal line and the second signal line are polycrystalline semiconductor materials; and / or The first signal line and the second signal line further include a metal conductive material layer and a transition conductive material layer, wherein the transition conductive material layer is formed between the semiconductor material layer and the metal conductive material layer; The material of the transition conductive material layer includes the metal elements in the metal conductive material layer and the semiconductor elements in the semiconductor material layer.

18. A method for manufacturing a semiconductor structure, characterized in that: The manufacturing method comprises: providing a substrate; At least one memory device layer stacked in a vertical direction is formed on the substrate, wherein the method for forming the memory device layer comprises: A first signal line, a transistor, a second signal line and a selection line are formed on the substrate, one of the first signal line and the second signal line is a reference voltage line, and the other is a read / write line, a gate layer of the transistor is connected to the selection line, an active layer of the transistor extends in a vertical direction and is independently arranged relative to the substrate, a bottom end of the active layer is connected to the first signal line, and a top end of the active layer is connected to the second signal line.

19. The manufacturing method according to claim 18, characterized in that: The step of forming a transistor on the substrate comprises: forming a first insulating dielectric layer on the substrate, wherein the first insulating dielectric layer at least covers a top surface of the first signal line; Forming a conductive film layer and a second insulating dielectric layer stacked in sequence along a vertical direction on the top surface of the first insulating dielectric layer; forming a filling hole penetrating the second insulating dielectric layer, the conductive film layer and the first insulating dielectric layer in a vertical direction, wherein the filling hole exposes a portion of the first signal line; forming a ring-shaped gate insulating layer on the inner wall of the filling hole, wherein the inner wall of the gate insulating layer is formed as a through hole penetrating in a vertical direction, and the through hole exposes a portion of the first signal line; forming an active layer in the through hole of the gate insulating layer; Patterning the conductive film layer to form a plurality of gate lines arranged at intervals, wherein the gate lines intersect with the extending direction of the read / write lines; The gate line includes at least one gate layer, and each gate layer is at least partially arranged around one of the active layers.

20. The manufacturing method according to claim 19, characterized in that: The step of forming an active layer includes: sequentially forming a first electrode region, a channel region, and a second electrode region in the through hole of the gate insulating layer, wherein the top surface of the first electrode region is higher than the bottom surface of the gate layer, the bottom surface of the second electrode region is lower than the top surface of the gate layer, and the first electrode region and the second electrode region have the same conductivity type, which is different from the conductivity type of the channel region.

21. The manufacturing method according to claim 20, characterized in that: The first signal line includes a semiconductor material layer, and the semiconductor material layer of the first signal line is exposed at the through hole, wherein the step of forming the first electrode region in the through hole of the gate insulation layer includes: Depositing a semiconductor material having the same conductivity type as that of the semiconductor material layer of the first signal line in the through hole to form the first electrode region; or An epitaxial growth process is performed on the semiconductor material layer of the first signal line exposed at the through hole to form the first electrode region.

22. The manufacturing method according to claim 20, characterized in that: The second signal line includes a semiconductor material layer, and the semiconductor material layer of the second signal line is in direct contact with or integrally formed with the second electrode region of the active layer.

23. The manufacturing method according to claim 22, characterized in that: The second signal line includes the semiconductor material layer, the metal conductive material layer, and the transition conductive material layer located between the semiconductor material layer and the metal conductive material layer stacked on the substrate; wherein, when the second signal line is used as a read / write line, the step of forming the second signal line includes: forming a semiconductor thin film layer of the same conductivity type as the semiconductor material layer of the first signal line, wherein the semiconductor thin film layer covers the channel region, the gate insulating layer and the second insulating dielectric layer; A first break extending in a first horizontal direction and a second break extending in a second horizontal direction are formed, wherein the first break sequentially penetrates the semiconductor film layer, the second insulating dielectric layer and the conductive film layer in a vertical direction and is located between adjacent filling holes in the second horizontal direction, the second break penetrates the semiconductor film layer and is located between adjacent filling holes in the first horizontal direction, the conductive film layer forms a plurality of gate lines extending in the first horizontal direction under the action of the first break, and the semiconductor film layer forms a plurality of semiconductor parts arranged at intervals in the first horizontal direction and the second horizontal direction under the action of the first break and the second break, the semiconductor part includes the second electrode region and the semiconductor material layer of the second signal line, the second electrode region is filled in the through hole, and the semiconductor material layer of the second signal line covers the second electrode region, the gate insulating layer and the second insulating dielectric layer; forming an insulating filling portion in the first break and the second break, wherein the top surface of the insulating filling portion is flush with the top surface of the semiconductor portion; A plurality of transition conductive material layers of the second signal lines arranged at intervals in the first horizontal direction and extending along the second horizontal direction and a plurality of metal conductive material layers of the second signal lines arranged at intervals in the first horizontal direction and extending along the second horizontal direction are formed, wherein in the second signal lines: the metal conductive material layers correspond one to one with the transition conductive material layers in the vertical direction, and each of the transition conductive material layers is connected to the top surfaces of the plurality of semiconductor parts arranged in the second horizontal direction.

24. The manufacturing method according to claim 18, characterized in that: The step of forming a transistor on the substrate comprises: forming a first insulating dielectric layer on the substrate, wherein the first insulating dielectric layer at least covers a top surface of the first signal line; forming a filling hole penetrating the first insulating dielectric layer in a vertical direction, wherein the filling hole exposes a portion of the first signal line; forming an annular active layer on the inner wall of the filling hole, wherein the inner wall of the annular active layer forms a through hole penetrating in a vertical direction, wherein the through hole exposes a portion of the first signal line; forming a groove-shaped gate insulating layer in the through hole, wherein the groove-shaped gate insulating layer covers the inner wall of the ring-shaped active layer and the area of ​​the first signal line exposed by the through hole; A gate layer is formed in the groove of the groove-shaped gate insulating layer.

25. The manufacturing method according to claim 24, characterized in that: After forming the gate layer and before forming the second signal line, the manufacturing method further includes: An isolation insulating portion is formed, wherein the isolation insulating portion completely covers the top of the gate layer and exposes at least a portion of the top surface of the annular active layer.

26. The manufacturing method according to claim 25, characterized in that: The multiple memory device layers are divided into at least one common unit, the common unit includes two adjacent memory device layers, and the memory device layer far from the substrate in the common unit is defined as a top memory device layer, and the memory device layer close to the substrate is defined as a bottom memory device layer; Wherein, in the shared unit: the gate layers of two transistors arranged in the vertical direction are connected to form a shared gate layer, and share the same gate line, and at least part of the first signal line in the top storage device layer and at least part of the second signal line in the bottom storage device layer are shared, so that the first signal line of the top storage device layer and the second signal line of the bottom storage device layer are used together as the reference voltage line of the shared unit, and the second signal line of the top storage device layer and the first signal line of the bottom storage device layer are both the read-write lines and are independently provided. When manufacturing the shared unit, the manufacturing method further includes: After forming the reference voltage line of the common unit, forming a third insulating dielectric layer and a top read / write line in sequence; Forming a first alignment hole penetrating the top read / write line and the third insulating dielectric layer, wherein the first alignment hole corresponds to the filling hole one by one and exposes a portion of the reference voltage line; A groove-shaped active layer is formed on the inner wall of the first alignment hole, wherein the groove-shaped active layer covers the top read / write line and the hole surface of the third insulating dielectric layer and covers the area of ​​the reference voltage line corresponding to the first alignment hole; forming a second alignment hole, wherein the second alignment hole penetrates at least the groove bottom of the groove active layer and the reference voltage line from the inner side wall of the groove active layer; An annular gate insulating layer is formed on the inner wall of the second alignment hole, the inner wall of the annular gate insulating layer is formed into a third alignment hole, the third alignment hole exposes the top surface of the bottom gate layer, a top gate layer is formed in the third alignment hole, and the top gate layer contacts the top surface of the bottom gate layer; Forming a fourth insulating dielectric layer covering the groove-shaped active layer and the top read / write line, wherein the fourth insulating dielectric layer exposes the top surface of the top gate layer; A gate line is formed on the top surface of the fourth insulating dielectric layer and is in contact with the top surface of the top gate layer.

27. The manufacturing method according to claim 26, characterized in that: In the shared unit: the active layer is one of an N-type semiconductor and a P-type semiconductor, the top read-write line and the bottom read-write line both include a semiconductor material layer, and the semiconductor material layers of the top read-write line and the bottom read-write line are both the other of an N-type semiconductor and a P-type semiconductor; wherein, The bottom of the groove of the groove-shaped gate insulating layer in the bottom storage device layer is embedded in the semiconductor material layer of the bottom read-write line, and the top surface of the bottom of the groove in the groove-shaped gate insulating layer is lower than the bottom surface of the active layer in the bottom storage device layer, so that the bottom surface of the common gate layer is lower than the bottom surface of the active layer in the bottom storage device layer; In the orthographic projection of the substrate: the gate line covers the boundary of the first alignment hole; The fourth insulating dielectric layer is located between the semiconductor material layer of the gate line and the top read / write line, and the fourth insulating dielectric layer and the annular gate insulating layer are prepared in the same layer to form a continuous film layer with equal thickness.

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