Semiconductor common block structure, semiconductor memory and its fabrication method

Abstract

This disclosure relates to the field of semiconductor technology, providing a semiconductor common block structure, a semiconductor memory, and a method for fabricating the same. The semiconductor common block structure includes a semiconductor common cell structure, a source / drain layer, and a shielding structure. The semiconductor common cell structure includes a first memory cell and a second memory cell arranged side-by-side in a mirror image along a first direction. The first memory cell and the second memory cell share the same source / drain cell layer, and the first direction is parallel to the surface of the substrate. Each of the first and second memory cells includes a first transistor and a second transistor. The fourth source / drain region of the second transistor in the first memory cell and the fourth source / drain region of the second transistor in the second memory cell are respectively connected to opposite sides of the source / drain cell layer. The source / drain layer is formed by sequentially connecting all source / drain cell layers in the same plane end-to-end. The shielding structure houses all the second transistors, while all the first transistors are located outside the shielding structure.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and more specifically, to a semiconductor common block structure, a semiconductor memory, and a method for fabricating the same. Background Technology

[0002] Dynamic Random Access Memory (DRAM) is a commonly used semiconductor device in computers and other electronic devices. A traditional DRAM memory cell typically includes a transistor and a capacitor. The transistor's gate is electrically connected to the word line, its source to the bit line, and its drain to the capacitor. The word line voltage controls the transistor's on and off states, allowing data to be read from or written to the capacitor via the bit line. This structure requires constantly refreshing the capacitor's charge to prevent data loss, and during reading, the charge in the capacitor must be released, followed by rewriting, resulting in high power consumption. Furthermore, the large area required for capacitor manufacturing makes miniaturization a significant challenge.

[0003] Dual-transistor capacitorless dynamic random access memory (2T0C) uses two vertically stacked transistors as its unit structure. The drain of one transistor is connected to the gate of the other, utilizing gate capacitance to store charge and altering the transistor's transconductance to store information. This structure can increase storage density by continuously increasing the number of vertically stacked layers without reducing critical dimensions. However, it requires the fabrication of each layer before moving on to the next, resulting in a longer manufacturing process, higher costs, and lower device reliability.

[0004] It should be noted that the information disclosed in the background section above is only used to enhance the understanding of the background of this disclosure, and therefore may include information that does not constitute prior art known to those skilled in the art. Summary of the Invention

[0005] This disclosure provides a semiconductor common block structure, a semiconductor memory and a method for fabricating the same, which can simplify the process flow, reduce manufacturing costs, increase storage density and reduce the interference of external electric fields on the charge storage area.

[0006] According to one aspect of this disclosure, a semiconductor common block structure is provided, fabricated on a substrate, comprising:

[0007] A plurality of semiconductor shared cell structures located on the substrate, the semiconductor shared cell structure including: a first memory cell and a second memory cell, the first memory cell and the second memory cell being arranged side by side in a mirror image along a first direction, the first memory cell and the second memory cell sharing the same source and drain cell layer, the first direction being parallel to the surface of the substrate;

[0008] Both the first storage unit and the second storage unit include:

[0009] A first transistor, located above the top surface of the substrate, includes a first gate, a first gate dielectric layer, and a first semiconductor layer. The first gate extends along the first direction. The first gate dielectric layer conformally covers the sidewalls and one end of the first gate. The first semiconductor layer covers the surface of the first gate dielectric layer and includes a first source / drain region, a first channel region, and a second source / drain region sequentially distributed along the first direction. A second transistor, arranged side-by-side with the first transistor along the first direction, includes a second gate, a second gate dielectric layer, and a second semiconductor layer. The second gate extends along the first direction. The second gate dielectric layer conformally covers the sidewalls and the end of the second gate away from the first transistor. The second semiconductor layer covers the surface of the second gate dielectric layer and includes a third source / drain region, a second channel region, and a fourth source / drain region sequentially distributed along the first direction. The second source / drain region is electrically connected to the second gate. The fourth source / drain region in the first memory cell and the fourth source / drain region in the second memory cell are respectively connected to opposite sides of the source / drain cell layer.

[0010] The plurality of semiconductor shared unit structures are arranged at intervals along a second direction and a third direction, the second direction being parallel to the substrate and intersecting the first direction, and the third direction being perpendicular to the first direction and the second direction;

[0011] A source / drain layer is formed by connecting all the aforementioned source / drain unit layers in the same plane end to end in sequence.

[0012] The shielding structure has a shielding cavity in which all the second transistors are housed, and all the first transistors are located outside the shielding structure.

[0013] In one exemplary embodiment of this disclosure, the shielding structure is a shell structure, which includes at least one conductive material shell layer.

[0014] In one exemplary embodiment of this disclosure, the semiconductor common block structure further includes:

[0015] Multiple word lines extending along the second direction and spaced apart along the first direction and the third direction, each word line being connected to the gate of a row of the first transistors arranged in the same plane along the second direction;

[0016] Multiple first bit lines extending along the third direction and spaced apart along the first and second directions, each first bit line covering the outer periphery of a row of first source / drain regions arranged along the third direction in the same plane;

[0017] Multiple second bit lines extending along the third direction and spaced apart along the first and second directions, each second bit line covering the outer periphery of a row of third source / drain regions arranged in the same plane along the third direction.

[0018] In an exemplary embodiment of this disclosure, the word line includes a main extension and a lead-out end located at at least one end of the main extension; in the third direction, the orthographic projections of the lead-out ends of any two word lines on the substrate do not overlap, and the orthographic projections of the main extensions of any two word lines on the substrate overlap; in the third direction and in the direction from the side closer to the substrate to the side farther from the substrate, the length of each word line decreases or increases sequentially.

[0019] In one exemplary embodiment of this disclosure, the semiconductor common block structure further includes:

[0020] A connecting line extends along the third direction and connects to the lead-out end of the word line.

[0021] According to one aspect of this disclosure, a semiconductor memory is provided, comprising:

[0022] A substrate and a plurality of semiconductor common block structures as described in any of the above, wherein the plurality of semiconductor common block structures are arranged along the first direction;

[0023] The two adjacent semiconductor shared block structures are set independently of each other.

[0024] According to one aspect of this disclosure, a method for fabricating a semiconductor memory is provided, comprising:

[0025] Provide substrate;

[0026] A first memory cell and a second memory cell are formed on the substrate. The first memory cell and the second memory cell are arranged side by side in a mirror image along a first direction, which is parallel to the surface of the substrate. Both the first memory cell and the second memory cell include a first transistor and a second transistor arranged side by side along the first direction. A source-drain region of the first transistor is electrically connected to the gate of the second transistor.

[0027] A shielding structure is formed that houses the second transistor of the first memory cell and the second transistor of the second memory cell within a shielding cavity;

[0028] A source-drain cell layer is formed between the first memory cell and the second memory cell; a source-drain region of the second transistor of the first memory cell and a source-drain region of the second transistor of the second memory cell are respectively connected to opposite sides of the source-drain cell layer.

[0029] In one exemplary embodiment of this disclosure, the preparation method further includes:

[0030] A word line material layer is formed before the second transistor is formed;

[0031] The formation of the first transistor, the second transistor, the word line material layer, and the shielding structure on the substrate includes:

[0032] A first insulating material layer and a semiconductor material layer are sequentially and alternately deposited on the substrate to form a stacked structure;

[0033] The stacked structure is patterned to form a patterned stacked structure. The pattern of the patterned stacked structure includes multiple first patterns extending along a first direction and spaced apart along a second direction, and multiple second patterns extending along the second direction and spaced apart along the first direction. The first direction is parallel to the surface of the substrate, and the second direction is parallel to the substrate and intersects the first direction. The first patterns and the second patterns overlap.

[0034] A second insulating material layer is formed to fill the gaps in the patterned layered structure;

[0035] Multiple first openings are formed along a third direction, penetrating the patterned stacked structure and the second insulating material layer. Each first opening corresponds to a second pattern, and the first opening divides the corresponding second pattern into two sub-patterns that are mirror-image arranged side by side along the first direction. The third direction is perpendicular to the first direction and the second direction, and the first opening is parallel to the plane containing the second direction and the third direction.

[0036] Part of the semiconductor material layer is etched laterally to both sides through the first opening to form a plurality of accommodating portions. The accommodating portions include a row of first transistor accommodating grooves extending along the first direction and arranged along the second direction, and word line accommodating grooves extending along the second direction and communicating with the row of first transistor accommodating grooves.

[0037] A first semiconductor layer, a first gate dielectric layer, and a first gate material layer are sequentially deposited within the accommodating portion; the first semiconductor layer covers the sidewalls and bottom surface of the accommodating portion, the first gate dielectric layer conformally covers the surface of the first semiconductor layer, and the first gate material layer fills the remaining space of the accommodating portion.

[0038] The first gate material layer deposited in the word line receiving groove is etched away to form the first gate of the first transistor. Then, word line material is filled into the word line receiving groove to form a word line material layer. The word line material layer is in contact with the first gate. The first transistor includes the first gate, the first gate dielectric layer that conformally covers the sidewalls and one end of the first gate, and the first semiconductor layer that conformally covers the first gate dielectric layer. The first semiconductor layer on the first gate includes a first source / drain region, a first channel region, and a second source / drain region that are sequentially distributed along the first direction.

[0039] Multiple second openings are formed that penetrate the patterned stacked structure and the second insulating material layer filling the interior of the patterned stacked structure along the third direction. The second openings are located at the midpoint between two adjacent first openings and are parallel to the plane containing the second direction and the third direction.

[0040] Part of the first insulating material layer is etched laterally to both sides through the second opening to form the second gate of the second transistor, and part of the second insulating material layer is etched along the second direction to both sides of the patterned stacked structure to define the outline of the shield structure.

[0041] A second gate dielectric layer and a second semiconductor layer are sequentially deposited on the exposed surface of the second gate and the contour surface of the shield structure. The second gate dielectric layer conformally covers the sidewall of the second gate, the end of the second gate away from the first transistor, and the contour surface of the shield structure. The second semiconductor layer covers the surface of the second gate dielectric layer, and the second semiconductor layer on the second gate includes a third source / drain region, a second channel region, and a fourth source / drain region sequentially distributed along the first direction.

[0042] In one exemplary embodiment of this disclosure, before forming a plurality of first openings extending through the patterned stacked structure and the second insulating material layer in a third direction, the method for fabricating the semiconductor memory further includes:

[0043] An etch stop layer is formed embedded within the second insulating material layer;

[0044] Forming the second insulating material layer and the etch stop layer includes:

[0045] A third insulating material layer is deposited on the exposed surfaces of the substrate and the patterned stack structure, the third insulating material layer filling the gaps between two adjacent first patterns in the patterned stack structure, and an etch stop material layer is deposited on the surface of the third insulating material layer.

[0046] The remaining gaps in the patterned stacked structure are filled with insulating material and planarized to form the second insulating material layer and the etch stop layer. The upper surfaces of the second insulating material layer, the etch stop layer and the patterned stacked structure are flush. The etch stop layer is used to define the shape and size of the shielding structure in the first direction.

[0047] In an exemplary embodiment of this disclosure, the step of etching away a portion of the first insulating material layer laterally through the second opening to form the second gate of the second transistor, and etching away a portion of the second insulating material layer along the second direction to both sides of the patterned stacked structure to define the outline of the shielding structure includes:

[0048] The first insulating material layer is etched laterally to both sides through the second opening, while the second insulating material layer is etched along the second direction to both sides of the patterned stacked structure. Etching stops when the etching stop layer is reached.

[0049] In one exemplary embodiment of this disclosure, the preparation method further includes:

[0050] After the second semiconductor layer is formed, a filling layer is formed to fill the shield cavity of the shield structure, and the filling layer closes the second opening.

[0051] In one exemplary embodiment of this disclosure, a source-drain cell layer is formed between the first memory cell and the second memory cell, including:

[0052] Multiple third openings are formed along the third direction through the filling layer. The third openings are located within the second openings and expose the fourth source / drain region in the second transistor. The third openings are parallel to the plane containing the second direction and the third direction.

[0053] The third opening is filled with conductive material to form a source / drain cell layer;

[0054] The method for fabricating the semiconductor memory further includes:

[0055] The first insulating material layer and the second insulating material layer are etched to form a plurality of first bit line receiving holes and second bit line receiving holes extending along the third direction;

[0056] A first bit line is formed in the first bit line receiving hole, and a second bit line is formed in the second bit line receiving hole; each first bit line covers the outer periphery of a row of first source / drain regions arranged in the same plane along the third direction, and each second bit line covers the outer periphery of a row of third source / drain regions arranged in the same plane along the third direction.

[0057] In one exemplary embodiment of this disclosure, the preparation method further includes:

[0058] Each of the word line material layers and the first and second insulating material layers covering each of the word lines are processed to form a plurality of word lines extending along the second direction and spaced apart along the third direction. Each word line includes a main body extension and a lead-out end located at at least one end of the main body extension. In the word line lead-out structure, the orthographic projections of the lead-out ends of any two word lines on the substrate do not overlap, while the orthographic projections of the main body extensions of any two word lines on the substrate do overlap. In the third direction and in the direction from the side closer to the substrate to the side farther from the substrate, the length of each word line decreases sequentially.

[0059] In one exemplary embodiment of this disclosure, the preparation method further includes:

[0060] A cover layer is formed on the side of each lead-out end away from the substrate;

[0061] The cover layer is etched to form a plurality of connection holes penetrating the cover layer along the third direction, wherein the orthographic projections of different connection holes on the substrate at least partially overlap with the orthographic projections of different lead-out ends on the substrate;

[0062] Conductive material is deposited within the connection hole to form a connection wire.

[0063] In the semiconductor shared block structure disclosed herein, the first and second memory cells in each semiconductor shared cell structure can be laterally distributed on the substrate surface along a direction parallel to the substrate. During the fabrication process, the first and second memory cells can be formed simultaneously without waiting for the first memory cell to be fabricated before forming the second memory cell, resulting in a shorter process flow and lower manufacturing cost. Since the first and second memory cells share the same source and drain cell layer, the signal paths and conditions received by both are consistent, which helps reduce read errors and data inconsistencies caused by differences in signal transmission; it also reduces the area of ​​the region where the first and second memory cells are located, increases device integration, and thus increases memory density. Multiple semiconductor shared cell structures are arranged at intervals along the second and third directions, maximizing substrate area utilization and further increasing memory density. In addition, by housing all the second transistors in the shielded cavity of the shield structure, the shield structure can effectively isolate the interference of external electric fields (e.g., the electric field generated by the first transistor) generated by conductive structures located outside the shield structure and adjacent to the second transistors from the second transistors, reducing the impact of external electric fields on the memory area and enhancing the stability and reliability of the memory.

[0064] The semiconductor memory disclosed herein is a dual-transistor capacitorless dynamic random access memory. The two transistors in the memory cell are located above the substrate and are horizontally arranged. The channel is parallel to the substrate direction. The storage density is increased by vertical stacking. Compared with the existing vertical structure dual-transistor capacitorless dynamic random access memory that increases storage density by vertical stacking, the height of each layer in the semiconductor memory disclosed herein is greatly reduced, resulting in higher storage density.

[0065] Compared to existing vertically stacked dual-transistor capacitorless dynamic random access memory (DRAM) fabrication methods that require fabricating storage functional layers one by one to increase storage density, the semiconductor memory fabrication method disclosed herein allows for the simultaneous fabrication of all storage cells. Therefore, the semiconductor memory fabrication method of this disclosure has a shorter process flow and lower manufacturing cost. Furthermore, during the fabrication process, a shielding structure capable of accommodating all second transistors can be fabricated in a single process. This shielding structure effectively isolates the interference of external electric fields (e.g., the electric field generated by the first transistor) generated by conductive structures located outside the shielding structure and adjacent to the second transistors from the second transistors, mitigating the impact of external electric fields on the storage region and enhancing the stability and reliability of the memory.

[0066] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and are not intended to limit this disclosure. Attached Figure Description

[0067] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this disclosure and, together with the description, serve to explain the principles of this disclosure. It is obvious that the drawings described below are merely some embodiments of this disclosure, and those skilled in the art can obtain other drawings based on these drawings without any inventive effort.

[0068] Figure 1 This is a schematic diagram of the semiconductor common block structure in an embodiment of this disclosure.

[0069] Figure 2 This is a schematic diagram of the semiconductor shared cell structure in an embodiment of this disclosure.

[0070] Figure 3 For along Figure 1 A cross-sectional view taken along the AA direction.

[0071] Figure 4 This is a schematic diagram of a semiconductor memory in an embodiment of this disclosure.

[0072] Figure 5 This is a flowchart of a method for fabricating a semiconductor memory according to an embodiment of this disclosure.

[0073] Figure 6 This is a schematic diagram of the stacked structure in an embodiment of this disclosure.

[0074] Figure 7 This is a schematic diagram of the structure after step S2 is completed in an embodiment of this disclosure.

[0075] Figure 8 This is a schematic diagram of the structure after step S3 is completed in an embodiment of this disclosure.

[0076] Figure 9 This is a schematic diagram of the structure after step S4 is completed in an embodiment of this disclosure.

[0077] Figure 10 This is a schematic diagram of the second mask layer and the second photoresist layer in an embodiment of this disclosure.

[0078] Figure 11 This is a schematic diagram of the character line receiving groove in an embodiment of this disclosure.

[0079] Figure 12 For along Figure 11 A cross-sectional view taken along the AA direction.

[0080] Figure 13 for Figure 12 The structural diagram after step S6 is completed.

[0081] Figure 14 for Figure 13The structural diagram after step S7 is completed.

[0082] Figure 15 This is a schematic diagram of the insulating material filled in the first opening in an embodiment of this disclosure.

[0083] Figure 16 This is a schematic diagram of the second opening in an embodiment of this disclosure.

[0084] Figure 17 This is a cross-sectional view after step S9 is completed in an embodiment of this disclosure.

[0085] Figure 18 This is a cross-sectional view after step S10 is completed in an embodiment of this disclosure.

[0086] Figure 19 This is a cross-sectional view after step S310 is completed in an embodiment of this disclosure.

[0087] Figure 20 This is a schematic diagram of the source / drain cell layer in an embodiment of this disclosure.

[0088] Figure 21 This is a schematic diagram of the third opening in an embodiment of this disclosure.

[0089] Figure 22 This is a schematic diagram of the fourth mask layer and the fourth photoresist layer in an embodiment of this disclosure.

[0090] Figure 23 This is a schematic diagram of the first and second bit line receiving holes in an embodiment of this disclosure.

[0091] Figure 24 For along Figure 23 A cross-sectional view taken along the direction of the dashed line.

[0092] Figure 25 This is a schematic diagram of the first bit line and the second bit line in an embodiment of this disclosure.

[0093] Figure 26 This is a schematic diagram of the etching barrier layer and mask material layer in an embodiment of this disclosure.

[0094] Figure 27 This is a schematic diagram of the first pattern mask layer in an embodiment of this disclosure.

[0095] Figure 28 This is a schematic diagram of the (n-1)th graphical stacked structure in an embodiment of this disclosure.

[0096] Figure 29 This is a schematic diagram of the cover layer and connection holes in an embodiment of this disclosure.

[0097] Figure 30 This is a partial cross-sectional view of multiple character lines in a stepped shape in an embodiment of this disclosure.

[0098] Explanation of reference numerals in the attached figures:

[0099] 1. Substrate; 2. First memory cell; 3. Second memory cell; 4. Source / drain layer; 410. Source / drain cell layer; 10. First transistor; 101. First gate; 1011. First gate material layer; 102. First gate dielectric layer; 103. First semiconductor layer; 20. Second transistor; 201. Second gate; 202. Second gate dielectric layer; 203. Second semiconductor layer; 5. Word line; 510. Word line material layer; 51. Conductive barrier material layer; 52. Metal material layer; 501. Main body extension; 502. Lead-out end; 6. First bit line; 601. First bit line receiving hole; 7. Second bit line; 701. Second bit line receiving hole; 8. Insulating material; 81. Third opening; 9. Protective layer; 30. Stacked structure; 301. First insulating material layer; 302. Semiconductor material layer; 303. Second insulating material layer; Material layer; 304, Etching stop layer; 40, Patterned stacked structure; 401, First pattern; 402, Second pattern; 4021, Sub-pattern; 403, First opening; 404, First transistor receiving groove; 405, Word line receiving groove; 406, Second opening; 50, Development pattern; 60, Second photoresist layer; 6001, First development area; 70, Shielding structure; 710, Shielding cavity; 80, Connecting line; 801, Connecting hole; 90, Filling layer; 100, First mask layer; 200, Second mask layer; 300, Cover layer; 400, Fourth mask layer; 500, Fourth photoresist layer; 5001, Third development area; 600, Stacked structure; 700, First pattern mask layer; 800, Etching stop layer; 900, Mask material layer; x, First direction; y, Second direction; z, Third direction. Detailed Implementation

[0100] Exemplary embodiments will now be described more fully with reference to the accompanying drawings. However, these exemplary embodiments can be implemented in many forms and should not be construed as limited to the embodiments set forth herein; rather, they are provided so that this disclosure will be thorough and complete, and will fully convey the concept of the exemplary embodiments to those skilled in the art. The same reference numerals in the drawings denote the same or similar structures, and therefore detailed descriptions of them will be omitted. Furthermore, the drawings are merely illustrative of this disclosure and are not necessarily drawn to scale.

[0101] Although relative terms such as "up" and "down" are used in this specification to describe the relative relationship of one component of an icon to another, these terms are used only for convenience, such as according to the orientation of the examples shown in the accompanying drawings. It is understood that if the device of the icon is flipped upside down, the component described as "up" will become the component described as "down." When a structure is "up" of another structure, it may mean that the structure is integrally formed on the other structure, or that the structure is "directly" mounted on the other structure, or that the structure is "indirectly" mounted on the other structure through another structure.

[0102] The terms “a,” “one,” “the,” “the,” and “at least one” are used to indicate the existence of one or more elements / components / etc.; the terms “including” and “having” are used to indicate an open-ended inclusion meaning and to mean that there may be other elements / components / etc. in addition to the listed elements / components / etc.; the terms “first,” “second,” “third,” and “fourth,” etc., are used only as markers and are not a limitation on the number of objects.

[0103] With the rapid development of the semiconductor industry, the demand for memory density is increasing. However, the traditional 1T1C (one transistor and one capacitor) structure faces severe challenges in improving memory density. Its critical dimension reduction is limited by the lithography capabilities of photolithography machines, making continuous shrinkage difficult. Simultaneously, the 1T1C structure is difficult to stack in three dimensions, thus severely restricting the improvement of memory density. To overcome this bottleneck, those skilled in the art have shifted their research focus to the 2T0C (two transistors, no capacitor) structure. Existing vertically stacked 2T0C DRAM memories have transistor channels in the memory cells perpendicular to the substrate, achieving a significant increase in memory density by sequentially stacking memory functional layers. However, the sequential stacking of memory functional layers results in a long manufacturing process, high manufacturing costs, and low device reliability.

[0104] Based on this, the present disclosure provides a semiconductor common block structure, which is fabricated on a substrate. Figure 1 A schematic diagram of the semiconductor common block structure of this disclosure is shown, as follows: Figure 1 As shown, the semiconductor common block structure includes multiple semiconductor common unit structures located on the substrate 1, a source / drain layer 4, and a shielding structure 70, as follows: Figure 2 As shown, the semiconductor shared cell structure includes: a first memory cell 2 and a second memory cell 3. The first memory cell 2 and the second memory cell 3 are arranged side by side in a mirror image along a first direction x. The first memory cell 2 and the second memory cell 3 share the same source and drain cell layer 410. The first direction x is parallel to the surface of the substrate 1.

[0105] The first memory cell 2 and the second memory cell 3 each include: a first transistor 10 located above the top surface of the substrate 1; the first transistor 10 includes: a first gate 101, a first gate dielectric layer 102, and a first semiconductor layer 103; the first gate 101 extends along a first direction x; the first gate dielectric layer 102 conformally covers the sidewalls and one end of the first gate 101; the first semiconductor layer 103 covers the surface of the first gate dielectric layer 102; and the first semiconductor layer 103 includes a first source / drain region, a first channel region, and a second source / drain region sequentially distributed along the first direction x; and a second transistor 20 arranged side-by-side with the first transistor 10 along the first direction x; the second transistor 20 includes a second gate 201 and a second gate dielectric layer 202. 02 and a second semiconductor layer 203, the second gate 201 extends along the first direction x, the second gate dielectric layer 202 conformally covers the sidewall of the second gate 201 and the end of the second gate 201 away from the first transistor 10, the second semiconductor layer 203 covers the surface of the second gate dielectric layer 202, and the second semiconductor layer 203 includes a third source / drain region, a second channel region and a fourth source / drain region sequentially distributed along the first direction x; the second source / drain region is electrically connected to the second gate 201 (for example, the second source / drain region and the second gate 201 are electrically connected through the semiconductor material layer 302), the fourth source / drain region in the first memory cell 2 and the fourth source / drain region in the second memory cell 3 are respectively connected to opposite sides of the source / drain cell layer 410;

[0106] Multiple semiconductor shared unit structures are arranged at intervals along the second direction y and the third direction z. The second direction y is parallel to the substrate 1 and intersects the first direction x. The third direction z is perpendicular to the first direction x and the second direction y.

[0107] A source / drain layer 4 is formed by connecting all source / drain unit layers 410 in the same plane end to end in sequence.

[0108] The shielding structure 70 has a shielding cavity in which all the second transistors 20 are housed, and all the first transistors 10 are located outside the shielding structure 70.

[0109] In the semiconductor shared block structure disclosed herein, the first memory cell 2 and the second memory cell 3 in each semiconductor shared unit structure can be laterally distributed on the surface of the substrate 1 along a direction parallel to the substrate 1. During the manufacturing process, the first memory cell 2 and the second memory cell 3 can be formed simultaneously without waiting for the first memory cell 2 to be completed before forming the second memory cell 3, resulting in a shorter process flow and lower manufacturing cost. Since the first memory cell 2 and the second memory cell 3 share the same source-drain cell layer 410, the signal paths and conditions received by them are consistent, which helps to reduce read errors and data inconsistencies caused by differences in signal transmission; it also reduces the area of ​​the region where the first memory cell 2 and the second memory cell 3 are located, improves device integration, and thus increases the memory storage density. Multiple semiconductor shared unit structures are arranged at intervals along the second direction y and the third direction z, which can maximize the utilization of the substrate 1 area and further increase the storage density. In addition, by housing all the second transistors 20 in the shielded cavity of the shielding structure 70, the shielding structure 70 can effectively isolate the interference of external electric fields (e.g., the electric field generated by the first transistor 10) generated by each conductive structure located outside the shielding structure 70 and adjacent to the second transistors 20 on each second transistor 20, reduce the influence of external electric fields on the storage area, and enhance the stability and reliability of the memory.

[0110] The following provides a detailed description of the various parts and specific details of the semiconductor common block structure disclosed herein:

[0111] Please continue reading Figure 1 As shown, the semiconductor block structure may include multiple semiconductor shared unit structures located on substrate 1, wherein: substrate 1 may be a flat plate structure, for example, it may be a flat plate structure. Substrate 1 may be rectangular, circular, elliptical, polygonal or irregular shape, and its material may be a semiconductor material, for example, its material may be silicon, but is not limited to silicon or other semiconductor materials. No special limitation is made on the shape and material of substrate 1 here.

[0112] Please continue reading Figure 2 As shown, the semiconductor shared cell structure may include a first memory cell 2 and a second memory cell 3. The first memory cell 2 and the second memory cell 3 may be formed on a substrate 1. Both the first memory cell 2 and the second memory cell 3 may be a 2TOC (i.e., including two transistors, without capacitors) structure. The first memory cell 2 and the second memory cell 3 may be arranged side-by-side in a mirror image along a first direction x, and the first memory cell 2 and the second memory cell 3 may share the same source / drain cell layer 410. This can reduce the area of ​​the region where the first memory cell 2 and the second memory cell 3 are located, improve device integration, and thus increase the memory density. In an exemplary embodiment of this disclosure, the first direction x may be parallel to the surface of the substrate 1.

[0113] In one exemplary embodiment of this disclosure, please continue to refer to Figure 2 As shown, both the first storage cell 2 and the second storage cell 3 include a first transistor 10 and a second transistor 20, wherein:

[0114] The first transistor 10 is located above the top surface of the substrate 1. The first transistor 10 may be a CAA (Channel-All-Around) structure transistor with the channel parallel to the plane of the substrate 1 and extending along the first direction x. The first transistor 10 may include: a first gate 101, a first gate dielectric layer 102, and a first semiconductor layer 103. The first gate 101 may be strip-shaped and extend along the first direction x. The material of the first gate 101 may be a conductive material, for example, indium zinc oxide (IZO) or polycrystalline silicon. The first gate dielectric layer 102 may conformally cover the sidewalls and one end of the first gate 101. The material of the first gate dielectric layer 102 may be a material with a high dielectric constant, for example, it may be aluminum oxide, hafnium oxide, lanthanum oxide, titanium oxide, zirconium oxide, or a mixture thereof. Of course, other materials may also be used, which will not be listed here. The first semiconductor layer 103 can conformally cover the surface of the first gate dielectric layer 102, and the first semiconductor layer 103 may include a first source / drain region, a first channel region, and a second source / drain region sequentially distributed along a first direction x. The first source / drain region is located on the side of the first channel region away from the source / drain cell layer 410, and the second source / drain region is located on the side of the first channel region closer to the source / drain cell layer 410. The material of the first semiconductor layer 103 can be compatible with the material of the first gate 101; for example, when the material of the first gate 101 is indium zinc oxide (IZO), the material of the first semiconductor layer 103 can be indium gallium zinc oxide (IGZO); when the material of the first gate 101 is polycrystalline silicon, the material of the first semiconductor layer 103 can be monocrystalline silicon.

[0115] Optionally, the material of the first semiconductor layer 103 in this disclosure is indium gallium zinc oxide (IGZO). Compared with the traditional use of single-crystal silicon as the material of the first semiconductor layer 103, the material of the first semiconductor layer 103 in this disclosure is indium gallium zinc oxide (IGZO). This is because the off-state current of IGZO thin film transistors (TFTs) is extremely small. When used in 2T0C DRAM memory cells, it can significantly reduce leakage current, which helps to reduce device power consumption and improve device reliability.

[0116] The second transistor 20 may also be located above the top surface of the substrate 1. The second transistor 20 may be a CAA structure transistor with its channel parallel to the plane of the substrate 1 and extending along the first direction x. The second transistor 20 may be distributed side by side with the first transistor 10 along the first direction x, that is, the second transistor 20 and the first transistor 10 are laterally distributed on the surface of the substrate 1. The second transistor 20 may include a second gate 201, a second gate dielectric layer 202, and a second semiconductor layer 203. The second gate 201 may be strip-shaped and extend along the first direction x. For example, the second gate 201 and the first gate 101 may be distributed sequentially along the first direction x. The material of the second gate 201 may be a conductive material, such as indium zinc oxide (IZO) or polycrystalline silicon. In some embodiments of this disclosure, the material of the second gate 201 is the same as the material of the first gate 101. For example, the materials of both the second gate 201 and the first gate 101 may be indium zinc oxide (IZO). The second gate dielectric layer 202 can conformally cover the sidewalls of the second gate 201 and the end of the second gate 201 away from the first transistor 10. The material of the second gate dielectric layer 202 can be a material with a high dielectric constant, such as aluminum oxide, hafnium oxide, lanthanum oxide, titanium oxide, zirconium oxide, or mixtures thereof. Of course, other materials can also be used, which will not be listed here. It should be noted that the material of the second gate dielectric layer 202 can be the same as the material of the first gate dielectric layer 102. The second semiconductor layer 203 can conformally cover the surface of the second gate dielectric layer 202, and the second semiconductor layer 203 includes a third source / drain region, a second channel region, and a fourth source / drain region sequentially distributed along the first direction x. The third source / drain region is located on the side of the second channel region away from the source / drain cell layer 410, and the fourth source / drain region is located on the side of the second channel region closer to the source / drain cell layer 410. The material of the second semiconductor layer 203 can be compatible with the material of the second gate 201. For example, when the material of the second gate 201 is indium zinc oxide (IZO), the material of the second semiconductor layer 203 can be indium gallium zinc oxide (IGZO); when the material of the second gate 201 is polycrystalline silicon, the material of the second semiconductor layer 203 can be monocrystalline silicon. In some embodiments of this disclosure, the material of the second semiconductor layer 203 can be the same as the material of the first semiconductor layer 103. For example, both the material of the second semiconductor layer 203 and the material of the first semiconductor layer 103 can be indium gallium zinc oxide (IGZO).

[0117] In an exemplary embodiment of this disclosure, the first transistor 10 may be a write transistor, and the second transistor 20 may be a read transistor. The second source-drain region of the first transistor 10 may be electrically connected to the second gate 201 of the second transistor 20 through a semiconductor material layer 302 (e.g., indium zinc oxide). The charge in the gate capacitance of the second transistor 20 (i.e., the read transistor) can be changed by the first transistor 10 (i.e., the write transistor), thereby affecting the resistance state between the source and drain of the second transistor 20 (i.e., the read transistor), thereby realizing the distinction between "0" and "1".

[0118] In an exemplary embodiment of this disclosure, the source / drain cell layer 410 may extend along a direction perpendicular to the substrate 1, that is, the plane where the source / drain cell layer 410 is located is perpendicular to the first direction x. The fourth source / drain region in the first memory cell 2 and the fourth source / drain region in the second memory cell 3 are respectively connected to two opposite sides of the source / drain cell layer 410 distributed along the first direction x. This design can ensure that the signal paths and conditions received by the first memory cell 2 and the second memory cell 3 are consistent, which helps to reduce read errors and data inconsistencies caused by differences in signal transmission.

[0119] In some embodiments of this disclosure, multiple semiconductor shared cell structures may be arranged along a second direction y and a third direction z. For example, multiple semiconductor shared cell structures may form multiple shared cell structure groups arranged along the third direction z, and each shared cell structure group may include multiple semiconductor shared cell structures arranged along the second direction y. All source / drain cell layers 410 located in the same plane in different shared cell structure groups are sequentially connected end to end to form a source / drain layer 4.

[0120] The second direction y is parallel to the substrate 1 and intersects the first direction x. For example, the second direction y can be perpendicular to the first direction x, and the third direction z is perpendicular to both the first direction x and the second direction y. It should be noted that parallelism can be absolute or approximately parallel; similarly, perpendicularity can be absolute or approximately perpendicular. Deviations are inevitable during the manufacturing process. In this disclosure, angular deviations may occur due to limitations in the manufacturing process, resulting in a certain deviation in the angle between the first direction x (or the second direction y) and the surface of the substrate 1, or a certain deviation in the angle between the third direction z and the first direction x (or the second direction y). As long as the angular deviation is within a preset range, the first direction x (or the second direction y) can be considered parallel to the substrate 1; or, the third direction z can be considered perpendicular to the first direction x (or the second direction y). For example, the preset range can be 10°, that is: when the angle between the first direction x (or the second direction y) and the surface of the substrate 1 is less than or equal to 10°, the first direction x (or the second direction y) can be considered parallel to the surface of the substrate 1; when the angle between the third direction z and the first direction x (or the second direction y) is greater than or equal to 80° and less than or equal to 100°, the third direction z can be considered perpendicular to the first direction x (or the second direction y).

[0121] like Figure 3 As shown, the shielding structure 70 may have a shielding cavity 710, in which all the second transistors 20 in the semiconductor common block structure are housed, and all the first transistors 10 are located outside the shielding structure 70. Since the second transistors 20 are mainly used for storing charge, each second transistor 20 constitutes a charge storage region; all the second transistors 20 are enclosed in the shielding structure 70, that is, the storage region can be isolated from the outside by the shielding structure 70, which can reduce the influence of the external electric field (e.g., the electric field generated by the first transistor 10) generated by the conductive structures located outside the shielding structure 70 and adjacent to the second transistors 20 on the storage region, thereby improving the stability and reliability of the device.

[0122] In one exemplary embodiment of this disclosure, the shielding structure 70 may be a shell structure, which may include at least a conductive material shell layer. For example, the material of the conductive material shell layer may be indium gallium zinc oxide (IGZO). During device use, the conductive material shell layer, due to its conductivity, allows the charges in the external electric field to be rapidly redistributed within it, thereby dispersing and limiting the penetration of the electric field, thus serving to shield the external electric field.

[0123] In some other embodiments of this disclosure, the shielding structure 70 may further include a dielectric layer, which may be located on the surface of the conductive material shell layer. For example, the dielectric layer may conformally cover the surface of the conductive material shell layer. The material of the dielectric layer may be a material with a high dielectric constant. A dielectric layer with a high dielectric constant can induce a strong reverse electric field under the action of an electric field, thereby effectively canceling or weakening the penetration of the external electric field. For example, the material of the dielectric layer may be alumina, hafnium oxide, lanthanum oxide, titanium oxide, zirconium oxide, or mixtures thereof. In the shielding structure 70 formed by the combination of the dielectric layer and the conductive material shell layer, when an external electric field acts on the shielding structure 70, the dielectric layer with a high dielectric constant will induce an internal electric field opposite to the direction of the external electric field to cancel the external electric field, thereby weakening the influence of the external electric field on the internal region. At the same time, the high conductivity of the conductive material shell layer allows the charge to be rapidly redistributed within it, further dispersing and restricting the penetration of the electric field, resulting in a significant reduction in the electric field strength inside the shielding structure 70.

[0124] In one exemplary embodiment of this disclosure, please continue to refer to Figure 1 As shown, the semiconductor common block structure may also include multiple word lines 5, multiple first bit lines 6, and multiple second bit lines 7, wherein:

[0125] Multiple word lines 5 can extend along a second direction y and be spaced apart along a first direction x and a third direction z. Each word line 5 is connected to the gate of a row of first transistors 10 arranged along the second direction y in the same plane. For example, each shared cell structure group may include two word lines 5, which can be spaced apart along the first direction x. One word line 5 can contact and connect to all the ends of a row of first gates 101 arranged along the second direction y in all first memory cells 2 in the same shared cell structure group that are not covered by the first gate dielectric layer 102; the other word line 5 can contact and connect to all the ends of a row of first gates 101 arranged along the second direction y in all second memory cells 3 in the same shared cell structure group that are not covered by the first gate dielectric layer 102. The word lines 5 connected to the first memory cells 2 in multiple shared cell structure groups arranged along the third direction z can be spaced apart along the third direction z.

[0126] The material of word line 5 can be at least one of tungsten, copper, aluminum, tungsten nitride, titanium, titanium nitride, or polycrystalline silicon. Of course, the material of word line 5 can also be other materials with good conductivity, which will not be listed here.

[0127] Please refer to some embodiments of this disclosure. Figure 1 and Figure 3As shown, the word line 5 may include a main body extension 501 and a lead-out end 502 located at at least one end of the main body extension 501; in the third direction z, the orthographic projections of the lead-out ends 502 of any two word lines 5 on the substrate 1 do not overlap, while the orthographic projections of the main body extensions 501 of any two word lines 5 on the substrate 1 do overlap; in the third direction z and from the side closer to the substrate 1 to the side farther from the substrate 1, the length of each word line 5 decreases or increases sequentially. That is, at least one end of the multiple word lines 5 arranged along the third direction z is stepped; at this time, the lead-out ends 502 of each word line 5 are exposed.

[0128] In one exemplary embodiment of this disclosure, each word line 5 includes two lead-out ends 502 located at both ends of the main body extension 501 in the second direction y, and each lead-out end 502 has the same size in the second direction y. For example, the two lead-out ends 502 in the same word line 5 have the same size in the second direction y, and the lead-out ends 502 in different word lines 5 also have the same size in the second direction y.

[0129] In one exemplary embodiment of this disclosure, please continue to refer to Figure 1 and Figure 3 As shown, the semiconductor common block structure also includes connection lines 80, which are connected to the lead-out ends 502 of the word lines 5. That is, each lead-out end 502 is provided with a corresponding connection line 80. The material of the connection lines 80 can be a conductive material, for example, titanium nitride or a combined titanium nitride and tungsten film structure. Signals can be transmitted to the lead-out ends 502 of the word lines 5 through the connection lines 80, and then to the interior of the word lines 5. For example, the connection lines 80 can extend in a third direction z, and adjacent connection lines 80 are insulated from each other. When the word line 5 includes two lead-out ends 502, both lead-out ends 502 are provided with connection lines 80.

[0130] In one exemplary embodiment of this disclosure, the word line 5 can be electrically led out simultaneously via two connecting lines 80. During signal transmission, the two connecting lines 80 allow for a more uniform signal distribution, helping to reduce signal reflection and attenuation during transmission, thereby improving the integrity and stability of signal transmission. Simultaneously, the design of having connecting lines 80 at both ends can, to some extent, balance the electromagnetic field distribution around the word line 5, reducing the impact of external electromagnetic interference on signal transmission and improving the circuit's anti-interference capability.

[0131] In one exemplary embodiment of this disclosure, when the length of each word line 5 decreases sequentially in the third direction z, from the side closest to the substrate 1 to the side furthest from the substrate 1, the connecting line 80 is connected to the side of the lead-out end 502 furthest from the substrate 1 to guide each word line 5 upward from the front. Alternatively, when the length of each word line 5 increases sequentially in the third direction z, from the side closest to the substrate 1 to the side furthest from the substrate 1, the connecting line 80 is connected to the side of the lead-out end 502 closest to the substrate 1 to guide each word line 5 upward and downward from the back. Different connecting lines 80 may be distributed in parallel and all extend along the third direction z.

[0132] Please continue reading Figure 1 As shown, the multiple first bit lines 6 in this disclosure can extend along a third direction z and are arranged at intervals along a first direction x and a second direction y. Each first bit line 6 covers the outer periphery of a row of first source / drain regions arranged along a third direction z in the same plane. For example, the semiconductor common block structure of this disclosure may include multiple bit line groups distributed at intervals along the second direction y. Each bit line group may include two first bit lines 6, which can be distributed at intervals along the first direction x. One first bit line 6 can cover the outer periphery of a row of first source / drain regions arranged along a third direction z in each of the multiple common cell structure groups arranged along a third direction z; the other first bit line 6 can cover the outer periphery of a row of first source / drain regions arranged along a third direction z in each of the multiple common cell structure groups arranged along a third direction z. It should be noted that different semiconductor common cell structures arranged along the second direction y are respectively provided with a bit line group, and each first bit line 6 in different bit line groups can be arranged at intervals along the second direction y and distributed in parallel.

[0133] Please continue reading Figure 1 As shown, the multiple second bit lines 7 in this disclosure can extend along a third direction z and be arranged at intervals along a first direction x and a second direction y. Each second bit line 7 covers the outer periphery of a row of third source / drain regions arranged along the third direction z in the same plane. For example, each bit line group may include two second bit lines 7, which can be distributed at intervals along the first direction x. One second bit line 7 can cover the outer periphery of a row of third source / drain regions arranged along the third direction z in each of the first memory cells 2 in the multiple shared cell structure groups arranged along the third direction z; the other second bit line 7 can cover the outer periphery of a row of third source / drain regions arranged along the third direction z in each of the multiple shared cell structure groups arranged along the third direction z. It should be noted that each second bit line 7 in different bit line groups can be arranged at intervals along the second direction y and distributed in parallel.

[0134] In one exemplary embodiment of this disclosure, both the first bit line 6 and the second bit line 7 are made of conductive materials, which may be independently selected from at least one of tungsten, copper, aluminum, tungsten nitride, titanium, and titanium nitride. For example, both the first bit line 6 and the second bit line 7 may include a conductive barrier layer and a metal layer; taking the first bit line 6 as an example, the metal layer may be strip-shaped and extend along a third direction z. The metal layer may cover the outer periphery of each first source / drain region in a plurality of shared unit structure groups arranged along the third direction z. The conductive barrier layer may conformally cover at least the surface of the metal layer, which can prevent metal ions in the metal layer from diffusing into other surrounding structures, thereby helping to reduce the risk of short circuits or coupling and improve device reliability. In some embodiments of this disclosure, the material of the conductive barrier layer may be titanium nitride, and the material of the metal layer may be tungsten, which can prevent tungsten ions from diffusing into other surrounding structures.

[0135] The read / write process of the semiconductor common block structure disclosed herein is described below:

[0136] The process of writing a "1" involves applying a positive voltage (greater than the threshold voltage Vth) to the write word line WWL, turning on the first transistor 10 (the write transistor). A positive voltage is also applied to the write bit line WBL, injecting charge into the gate capacitance (i.e., the storage node) of the second transistor 20 (the read transistor). After charge injection, the positive voltages applied to both the write word line WWL and the write bit line WBL are removed, preserving the "1" state. The process of reading a "1" involves applying a read voltage to the drain of the second transistor 20 (the read transistor). Due to the charge stored in the gate capacitance, the second transistor 20 is in a lower resistance state, resulting in a larger current. This current is then amplified and identified by the external circuitry, completing the process of reading a "1". During the writing "0" process, a positive voltage (greater than the threshold voltage Vth) is applied to the write word line WWL, turning on the first transistor 10 (the write transistor). A negative voltage is applied to the write bit line WBL, drawing charge from the gate capacitance (i.e., the storage node) of the second transistor 20 (the read transistor). After the charge is drawn, the positive voltage applied to the write word line WWL and the negative voltage applied to the write bit line WBL are removed, preserving the "0" state. During the reading "0" process, a read voltage is applied to the drain of the second transistor 20 (the read transistor). Since there is no charge in the gate capacitance, the second transistor 20 (the read transistor) is in a high-resistivity state, receiving a small current. This current is then amplified and identified by the external circuitry to complete the reading of the "0".

[0137] This disclosure also provides a semiconductor memory, such as... Figure 4As shown, the semiconductor memory includes a substrate 1 and a plurality of semiconductor common block structures as described in any of the above embodiments located on the substrate 1. The plurality of semiconductor common block structures are arranged along a first direction x; and adjacent semiconductor common block structures are independently arranged. For example, adjacent semiconductor common block structures in the semiconductor memory are spaced apart. Other details and beneficial effects of the semiconductor memory disclosed herein have been described in detail in the embodiments of the corresponding semiconductor common block structures, and therefore will not be repeated here.

[0138] A semiconductor shared block structure is defined as comprising two semiconductor memory block structures that are mirror-symmetrically distributed along the source-drain layer 4: a first semiconductor memory block structure and a second semiconductor memory block structure, wherein the first semiconductor memory block structure and the second semiconductor memory block structure share a source-drain layer 4.

[0139] The specific principles of reading and writing the semiconductor memory disclosed in this paper are as follows:

[0140] During writing: Selecting a word line 5 and a first bit line 6 selects a memory cell (including a first transistor 10 (i.e., the write transistor) and a second transistor 20 (i.e., the read transistor)). By applying voltage to the selected word line 5 and the selected first bit line 6 respectively to turn on the first transistor 10 (i.e., the write transistor), charge can be injected or extracted into the gate capacitance of the second transistor 20 (i.e., the read transistor) to realize the write operation.

[0141] During reading: When selecting a memory cell (including a first transistor 10 (i.e., a write transistor) and a second transistor 20 (i.e., a read transistor) for reading, all first transistors 10 in the semiconductor memory block structure where the selected memory cell is located are turned on (except for the first transistor 10 corresponding to the selected memory cell), charge is drawn from the gate capacitance of all second transistors 20 (i.e., read transistors) except for the selected memory cell, and then all first transistors 10 (i.e., write transistors) are turned off; a read voltage is applied to a second bit line 7 corresponding to the selected memory cell and the source / drain layer 4 to realize the read operation of the selected memory cell.

[0142] It should be understood that after each read operation, a refresh operation is required on the semiconductor memory block structure where the selected memory cell is located to restore the stored data of the semiconductor memory block structure before the read operation.

[0143] The semiconductor memory disclosed herein is a dual-transistor capacitorless dynamic random access memory. The two transistors in the memory cell are located above the substrate 1 and are horizontally arranged. The channel is parallel to the direction of the substrate 1. The storage density is increased by vertical stacking. Compared with the existing vertical structure dual-transistor capacitorless dynamic random access memory that increases storage density by vertical stacking, the height of each layer in the semiconductor memory disclosed herein is greatly reduced, resulting in a higher storage density.

[0144] This disclosure also provides a method for fabricating a semiconductor memory, such as... Figure 5 As shown, the preparation method may include steps S110-S140, wherein:

[0145] Step S110, provide substrate 1;

[0146] In step S120, a first memory cell 2 and a second memory cell 3 are formed on the substrate 1. The first memory cell 2 and the second memory cell 3 are arranged side by side in a mirror image along a first direction x, which is parallel to the surface of the substrate 1. The first memory cell 2 and the second memory cell 3 each include a first transistor 10 and a second transistor 20 arranged side by side along the first direction x. A source-drain region of the first transistor 10 is electrically connected to the gate of the second transistor 20.

[0147] Step S130: A shielding structure 70 is formed in which the second transistor 20 of the first memory cell 2 and the second transistor 20 of the second memory cell 3 are housed in the shielding cavity 710.

[0148] In step S140, a source-drain cell layer 410 is formed between the first storage cell 2 and the second storage cell 3; a source-drain region of the second transistor 20 of the first storage cell 2 and a source-drain region of the second transistor 20 of the second storage cell 3 are respectively connected to opposite sides of the source-drain cell layer 410.

[0149] Compared to existing vertically stacked dual-transistor capacitorless dynamic random access memory (DRAM) fabrication methods that require fabricating storage functional layers one by one to increase storage density, the semiconductor memory fabrication method disclosed herein allows all storage cells to be fabricated simultaneously. Therefore, the semiconductor memory fabrication method of this disclosure has a shorter process flow and lower manufacturing cost. Furthermore, during the fabrication process, a shielding structure 70 capable of accommodating all second transistors 20 can be fabricated in a single process. This shielding structure 70 effectively isolates the interference of external electric fields (e.g., the electric field generated by the first transistor 10) generated by conductive structures located outside the shielding structure 70 and adjacent to the second transistors 20 from the second transistors 20, reducing the impact of external electric fields on the storage area and enhancing the stability and reliability of the memory.

[0150] The following provides a detailed description of each step and specific details of the semiconductor memory fabrication method disclosed herein:

[0151] In step S110, substrate 1 is provided.

[0152] Substrate 1 may be in the form of a flat plate structure, for example, it may be a flat plate structure. Substrate 1 may be rectangular, circular, elliptical, polygonal or irregular shape, and its material may be a semiconductor material, for example, it may be silicon, but is not limited to silicon or other semiconductor materials. No special limitation is made on the shape and material of substrate 1 here.

[0153] In step S120, a first memory cell 2 and a second memory cell 3 are formed on the substrate 1. The first memory cell 2 and the second memory cell 3 are arranged side by side in a mirror image along a first direction x, which is parallel to the surface of the substrate 1. The first memory cell 2 and the second memory cell 3 each include a first transistor 10 and a second transistor 20 arranged side by side along the first direction x. A source-drain region of the first transistor 10 is electrically connected to the gate of the second transistor 20.

[0154] Please continue reading Figure 2 As shown, both the first memory cell 2 and the second memory cell 3 can be 2TOC (i.e., including two transistors, without capacitors) structures. Both the first memory cell 2 and the second memory cell 3 include a first transistor 10 and a second transistor 20. Both the first transistor 10 and the second transistor 20 can be CAA (Channel-All-Around) structure transistors with the channel parallel to the plane of the substrate 1 and extending along the first direction x. The first transistor 10 may include a first gate 101, a first gate dielectric layer 102, and a first semiconductor layer 103. The first gate 101 may be strip-shaped and extend along the first direction x. The first gate dielectric layer 102 may conformally cover the sidewalls and one end of the first gate 101. The first semiconductor layer 103 may conformally cover the surface of the first gate dielectric layer 102. The second transistor 20 and the first transistor 10 are laterally distributed on the surface of the substrate 1. The second transistor 20 may include a second gate 201, a second gate dielectric layer 202, and a second semiconductor layer 203. The second gate 201 may be strip-shaped and extend along a first direction x. For example, the second gate 201 and the first gate 101 may be sequentially distributed along the first direction x. The second gate dielectric layer 202 may conformally cover the sidewalls of the second gate 201 and the ends of the second gate 201 away from the first transistor 10. The second semiconductor layer 203 may conformally cover the surface of the second gate dielectric layer 202.

[0155] In step S130, a shielding structure 70 is formed in which the second transistor 20 of the first storage unit 2 and the second transistor 20 of the second storage unit 3 are housed in the shielding cavity 710.

[0156] Please continue reading Figure 3 As shown, the shielding structure 70 may have a shielding cavity 710, in which all the second transistors 20 in the semiconductor common block structure are housed, and all the first transistors 10 are located outside the shielding structure 70. Since the second transistors 20 are mainly used for storing charge, each second transistor 20 constitutes a charge storage region; all the second transistors 20 are enclosed in the shielding structure 70, that is, the storage region can be isolated from the outside world by the shielding structure 70, which can reduce the influence of the external electric field on the storage region and improve the stability and reliability of the device.

[0157] In one exemplary embodiment of this disclosure, the shielding structure 70 may be a shell structure, which may include at least a conductive material shell layer. For example, the material of the conductive material shell layer may be indium gallium zinc oxide (IGZO). During device use, the conductive material shell layer, due to its conductivity, allows the charges in the external electric field to be rapidly redistributed within it, thereby dispersing and limiting the penetration of the electric field, thus serving to shield the external electric field.

[0158] In some other embodiments of this disclosure, the shielding structure 70 may further include a dielectric layer, which may be located on the surface of the conductive material shell layer. For example, the dielectric layer may conformally cover the surface of the conductive material shell layer. The material of the dielectric layer may be a material with a high dielectric constant. A dielectric layer with a high dielectric constant can induce a strong reverse electric field under the action of an electric field, thereby effectively canceling or weakening the penetration of the external electric field. For example, the material of the dielectric layer may be alumina, hafnium oxide, lanthanum oxide, titanium oxide, zirconium oxide, or mixtures thereof. In the shielding structure 70 formed by the combination of the dielectric layer and the conductive material shell layer, when an external electric field acts on the shielding structure 70, the dielectric layer with a high dielectric constant will induce an internal electric field opposite to the direction of the external electric field to cancel the external electric field, thereby weakening the influence of the external electric field on the internal region. At the same time, the high conductivity of the conductive material shell layer allows the charge to be rapidly redistributed within it, further dispersing and restricting the penetration of the electric field, resulting in a significant reduction in the electric field strength inside the shielding structure 70.

[0159] In an exemplary embodiment of this disclosure, the method for fabricating the semiconductor memory of this disclosure may further include: forming a word line material layer before forming the second transistor 20. The word line material layer may extend along a second direction y, and the word line material layer may be connected to the gate of the first transistor 10. Forming the first transistor 10, the second transistor 20, the word line material layer, and the shielding structure 70 on the substrate 1 may include steps S1-S10, wherein:

[0160] Step S1: A first insulating material layer 301 and a semiconductor material layer 302 are sequentially and alternately deposited on the substrate 1 to form a stacked structure 30.

[0161] like Figure 6 As shown, the stacked structure 30 may include multiple layers of first insulating material 301 and multiple layers of semiconductor material 302, which may be alternately distributed along a direction perpendicular to the substrate 1 (i.e., the third direction z). In an exemplary embodiment of this disclosure, the material of the first insulating material layer 301 may be silicon oxide, and the material of the semiconductor material layer 302 may be indium zinc oxide (IZO). The first insulating material layer 301 and the semiconductor material layer 302 may be alternately deposited on the substrate 1 by chemical vapor deposition, physical vapor deposition, or atomic layer deposition. It should be noted that the film layer in the stacked structure 30 that is in contact with the substrate 1 is the first insulating material layer 301, and the film layer in the stacked structure 30 that is farthest from the substrate 1 is also the first insulating material layer 301.

[0162] In one exemplary embodiment of this disclosure, after forming the stacked structure 30, a protective layer 9 may be formed on the surface of the stacked structure 30. The protective layer 9 can prevent damage to the first insulating material layer 301 located at the top of the stacked structure 30 during subsequent etching. The material of the protective layer 9 is different from the material of the first insulating material layer 301; for example, its material may be silicon nitride.

[0163] Step S2: The stacked structure 30 is patterned to form a patterned stacked structure 40. The pattern of the patterned stacked structure 40 includes multiple first patterns 401 extending along the first direction x and spaced apart along the second direction y, and multiple second patterns 402 extending along the second direction y and spaced apart along the first direction x. The first direction x is parallel to the surface of the substrate 1, and the second direction y is parallel to the substrate 1 and intersects with the first direction x. The first patterns 401 and the second patterns 402 overlap.

[0164] The stacked structure 30 can be patterned by etching. A first mask layer 100 can be formed on the side of the stacked structure 30 away from the substrate 1. For example, when a protective layer 9 is formed on the surface of the stacked structure 30, the first mask layer 100 can be formed on the surface of the protective layer 9. Subsequently, a first photoresist layer can be formed on the surface of the first mask layer 100. The first photoresist layer can be exposed and developed to form a developed pattern 50, which corresponds to the first pattern 401 and the second pattern 402. The developed pattern 50 can be used as a mask to perform anisotropic etching on the protective layer 9 and the stacked structure 30 to form a patterned stacked structure 40. It should be noted that after the patterned stacked structure 40 is formed, the developed pattern 50 and the first mask layer 100 can be removed to expose the surface of the protective layer 9. It should be noted that, for the sake of subsequent description, the protective layer 9 can be considered as part of the patterned stacked structure 40, that is, the patterned stacked structure 40 includes the protective layer 9. In the embodiments of this disclosure, the structure after step S2 is as follows: Figure 7 As shown.

[0165] In some embodiments of this disclosure, the first pattern 401 and the second pattern 402 are both strip-shaped, and the second direction y is perpendicular to the first direction x. In this case, the second pattern 402 is distributed perpendicularly to the first pattern 401.

[0166] Step S3, forming a second insulating material layer 303 that fills the gaps in the patterned layered structure 40.

[0167] The second insulating material layer 303 is made of the same material as the first insulating material layer 301. For example, both the second insulating material layer 303 and the first insulating material layer 301 can be made of silicon oxide. The second insulating material layer 303 can fill the gaps in the patterned stacked structure 40, and the surface of the second insulating material layer 303 away from the substrate 1 is flush with the surface of the patterned stacked structure 40 away from the substrate 1. For example, when the topmost layer in the patterned stacked structure 40 is the protective layer 9, the surface of the second insulating layer 303 away from the substrate 1 is flush with the surface of the protective layer 9 away from the substrate 1. In this embodiment of the present disclosure, the structure after step S3 is as follows: Figure 8 As shown.

[0168] Please refer to some embodiments of this disclosure. Figure 8 As shown, before forming multiple first openings along the third direction z through the patterned stacked structure 40 and the second insulating material layer 303, i.e., before performing step S4, the semiconductor memory fabrication method of this disclosure further includes: forming an etch stop layer 304 embedded in the second insulating material layer 303, wherein the end of the etch stop layer 304 away from the substrate 1 is flush with the top surface of the second insulating material layer 303. The material of the etch stop layer 304 may be a material with a large etch selectivity ratio to the first insulating material layer 301 and the second insulating material layer 303, used to control the amount of etching during subsequent etching of the first insulating material layer 301 and / or the second insulating material layer 303, defining the outline pattern of the shielding structure 70.

[0169] In an exemplary embodiment of this disclosure, forming the second insulating material layer 303 and the etch stop layer 304 includes steps S210 and S220, wherein:

[0170] In step S210, a third insulating material layer is deposited on the exposed surfaces of the substrate 1 and the patterned stacked structure 40. The third insulating material layer fills the gaps between two adjacent first patterns 401 in the patterned stacked structure 40. An etch stop material layer is deposited on the surface of the third insulating material layer.

[0171] The material of the third insulating material layer can be the same as that of the first insulating material layer 301. For example, both the third insulating material layer and the first insulating material layer 301 can be made of silicon oxide. The third insulating material layer can be formed by chemical vapor deposition, physical vapor deposition, or atomic layer deposition. In this process, the third insulating material layer can fill the gaps between two adjacent first patterns 401 in the patterned stacked structure 40, and can also cover the sidewall surface of the patterned stacked structure 40. Subsequently, an etch stop material layer can be formed on the surface of the structure formed by the third insulating material layer and the patterned stacked structure 40. That is, at least part of the etch stop material layer can extend along the third direction z and can cover the surface of the third insulating material layer located on the sidewall of the patterned stacked structure 40.

[0172] In step S220, the remaining gaps in the patterned stacked structure 40 are filled with insulating material 8 and planarized to form a second insulating material layer 303 and an etch stop layer 304. The second insulating material layer 303, the etch stop layer 304 and the upper surface of the patterned stacked structure 40 are flush. The etch stop layer 304 is used to define the shape and size of the shield structure 70 in the first direction x.

[0173] After the etch stop material layer is formed, insulating material can be deposited until the remaining gaps in the patterned stack structure 40 are filled with insulating material. This insulating material is the same as the material of the third insulating material layer. After the insulating material fills the remaining gaps in the patterned stack structure 40, the structure consisting of the patterned stack structure 40, the third insulating material layer, the etch stop material layer, and the insulating material can be chemically mechanically polished to make the surfaces of the patterned stack structure 40, the third insulating material layer, the etch stop material layer, and the insulating material flush with the surfaces away from the substrate 1. The remaining third insulating material layer and the insulating material after polishing can be used as the second insulating material layer 303, and the remaining etch stop material layer after polishing can be used as the etch stop layer 304.

[0174] Step S4: Multiple first openings 403 are formed along the third direction z through the patterned stacked structure 40 and the second insulating material layer 303. The first openings 403 are set in a one-to-one correspondence with the second patterns 402. The first openings 403 divide the corresponding second patterns 402 into two sub-patterns 4021 that are mirror images of each other along the first direction x. The third direction z is perpendicular to the first direction x and the second direction y, and the first openings 403 are parallel to the plane containing the second direction y and the third direction z.

[0175] like Figure 9As shown, the patterned stacked structure 40 and the second insulating material layer 303 can be etched to form a first opening 403 extending along the second direction y and penetrating the second pattern 402 along the third direction z. The number of first openings 403 can be multiple, and multiple first openings 403 are set one-to-one with multiple second patterns 402. Different first openings 403 are distributed at intervals along the first direction x and are parallel to each other.

[0176] In some embodiments of this disclosure, before forming the first opening 403, a protective material may be deposited on the surface of the structure jointly formed by the second insulating material layer 303, the etch stop layer 304, and the patterned stacked structure 40 to form a new protective layer 9 (the new protective layer 9 consists of the original protective layer 9 on top of the patterned stacked structure 40 and the newly deposited protective material). The protective material is the same as the original protective layer 9 on top of the patterned stacked structure 40; for example, the protective material may be silicon nitride. Figure 10 As shown, a second mask layer 200 can be formed on the surface of the new protective layer 9, and a second photoresist layer 60 can be formed on the surface of the second mask layer 200. The second photoresist layer 60 is exposed and developed to form a plurality of first developing areas 6001 extending along the second direction y and spaced apart along the first direction x. In the first direction x, each first developing area 6001 is located in the middle region of each second pattern 402. The second mask layer 200 and the second pattern 402 can be etched in the first developing areas 6001 to form a first opening 403 in the patterned stacked structure 40. The first opening 403 divides the second pattern 402 into two sub-patterns 4021 that are mirror-distributed along the first direction x.

[0177] It should be noted that after forming the first opening 403, the second photoresist layer 60 and the second mask layer 200 can be removed, thereby exposing the surface of the protective layer 9. In this embodiment of the disclosure, the structure after completing step S4 is as follows: Figure 9 As shown.

[0178] Step S5: Part of the semiconductor material layer 302 is etched laterally to both sides through the first opening 403 to form a plurality of accommodating portions. The accommodating portions include a row of first transistor accommodating grooves 404 extending along the first direction x and arranged along the second direction y, and word line accommodating grooves 405 extending along the second direction y and communicating with the row of first transistor accommodating grooves 404.

[0179] like Figure 11 and Figure 12As shown, the semiconductor material layers 302 on both sides of the first opening 403 can be etched using an isotropic etching process to form multiple accommodating portions arranged along the third direction z. The word line accommodating groove 405 in the accommodating portion is located in the area of ​​the sub-pattern 4021 of the second pattern 402. The semiconductor material layer 302 in the area corresponding to the sub-pattern 4021 of the second pattern 402 can be completely etched away, thereby forming the word line accommodating groove 405. The first transistor accommodating groove 404 is located in the area of ​​the first pattern 401. During the etching of the semiconductor material layer 302, the semiconductor material layer 302 corresponding to the first pattern 401 is not completely etched, and the depth of the first transistor accommodating groove 404 is less than half the length of the first pattern 401 between two adjacent first openings 403. The etching depth of the first transistor accommodating groove 404 can be controlled by controlling the etching time during the etching process.

[0180] In step S6, a first semiconductor layer 103, a first gate dielectric layer 102, and a first gate material layer 1011 are sequentially deposited in the accommodating portion. The first semiconductor layer 103 covers the sidewalls and bottom surface of the accommodating portion, the first gate dielectric layer 102 conformally covers the surface of the first semiconductor layer 103, and the first gate material layer 1011 fills the remaining space of the accommodating portion.

[0181] The material of the first semiconductor layer 103 can be indium gallium zinc oxide (IGZO) or single-crystal silicon. The material of the first gate dielectric layer 102 can be a material with a high dielectric constant, such as aluminum oxide, hafnium oxide, lanthanum oxide, titanium oxide, zirconium oxide, or mixtures thereof. The material of the first gate material layer 1011 can be indium zinc oxide (IZO) or polycrystalline silicon. It should be noted that the material of the first gate material layer 1011 is matched with the material of the first semiconductor layer 103; for example, when the material of the first semiconductor layer 103 is indium gallium zinc oxide (IGZO), the material of the first gate material layer 1011 is indium zinc oxide (IZO); when the material of the first semiconductor layer 103 is single-crystal silicon, the material of the first gate material layer 1011 is polycrystalline silicon.

[0182] In some embodiments of this disclosure, a first semiconductor layer 103, a first gate dielectric layer 102, and a first gate material layer 1011 can be sequentially deposited on the side of the protective layer 9 away from the substrate 1 by chemical vapor deposition, physical vapor deposition, or atomic layer deposition. During this process, the first semiconductor layer 103 can conformally cover the inner wall of the accommodating portion. For ease of fabrication, the first semiconductor layer 103 can also cover the surface of the protective layer 9 and the sidewalls of the insulating materials 8 layers exposed in the first opening 403. The first gate dielectric layer 102 can conformally cover the surface of the first semiconductor layer 103, and the first gate material layer 1011 is located on the surface of the first gate dielectric layer 102 and can fill the remaining space of the accommodating portion. During this process, to ensure that the first gate material layer 1011 can fill the remaining space of the accommodating portion, the first gate material layer 1011 can simultaneously fill the first opening 403. Subsequently, the first gate material layer 1011 located in the first opening 403 and the first gate material layer 1011 located on top of the protective layer 9 can be removed. In this embodiment of the disclosure, the structure after step S6 is as follows: Figure 13 As shown.

[0183] Step S7: Etch away the first gate material layer 1011 deposited in the word line receiving groove 405 to form the first gate 101 of the first transistor 10. Then fill the word line receiving groove 405 with word line 5 material to form a word line material layer 510. The word line material layer 510 is in contact with the first gate 101. The first transistor 10 includes a first gate 101, a first gate dielectric layer 102 that conformally covers the sidewalls and one end of the first gate 101, and a first semiconductor layer 103 that conformally covers the first gate dielectric layer 102. The first semiconductor layer 103 on the first gate 101 includes a first source / drain region, a first channel region, and a second source / drain region that are sequentially distributed along the first direction x.

[0184] The first gate material layer 1011 can be etched back using isotropic etching to remove the first gate material layer 1011 within the word line receiving groove 405. The first gate material layer 1011 within the first transistor receiving groove 404 then serves as the first gate 101 of the first transistor 10. The first gate dielectric layer 102 covering the surface of the first gate 101 serves as the first gate dielectric layer 102 of the first transistor 10. The first semiconductor layer 103 covering the surface of the first gate dielectric layer 102 serves as the active region of the first transistor 10. The active region can be divided into a first source / drain region, a first channel region, and a second source / drain region sequentially distributed along the first direction x. The region of the active region closest to the word line receiving groove 405 can be used as the first source / drain region. The first gate 101, the first gate dielectric layer 102, and the first semiconductor layer 103 together constitute the first transistor 10.

[0185] After forming the first gate 101, word line 5 material can be filled into the word line receiving groove 405 to form a word line material layer 510. The material of the word line material layer 510 can be a conductive material, which can be independently selected from at least one of tungsten, copper, aluminum, tungsten nitride, titanium, and titanium nitride. In this embodiment of the present disclosure, the structure after completing step S7 is as follows: Figure 14 As shown.

[0186] In one exemplary embodiment of this disclosure, please continue to refer to Figure 14 As shown, the word line material layer 510 may include a conductive barrier material layer 51 and a metal material layer 52. The conductive barrier material layer 51 may be located on the sidewall and bottom of the word line receiving groove 405, that is, the conductive barrier material layer 51 may be in contact with the first gate 101 at the bottom of the word line receiving groove 405. The metal material layer 52 may fill the remaining space in the word line receiving groove 405. It should be noted that, for process convenience, during the formation of the conductive barrier material layer 51, the conductive barrier material layer 51 may be deposited simultaneously on the top of the protective layer 9 and the sidewall of the first opening 403. At the same time, the metal material layer 52 may also fill the first opening 403. Subsequently, the metal material layer 52, the conductive barrier material layer 51, the first gate dielectric layer 102, and the first semiconductor layer 103 located on the top of the protective layer 9 and in the first opening 403 may be removed. The remaining conductive barrier material layer 51 and metal layer 52 in the word line receiving groove 405 shall be used as the word line material layer 510.

[0187] In one exemplary embodiment of this disclosure, such as Figure 15 As shown, after forming the word line material layer 510, an insulating material 8 can be filled into the first opening 403. This insulating material 8 can be made of the same material as both the first insulating material layer 301 and the second insulating material layer 303; for example, the insulating material 8 can be silicon oxide. The insulating material 8 can be filled into the first opening 403 by chemical vapor deposition, physical vapor deposition, or atomic layer deposition. During this process, for ease of fabrication, the insulating material 8 can simultaneously cover the surface of the protective layer 9. Subsequently, the insulating material 8 can be chemically mechanically polished, so that the surface of the insulating material 8 away from the substrate 1 is flush with the surface of the protective layer 9 away from the substrate 1.

[0188] In one exemplary embodiment of this disclosure, after the first opening 403 is filled with insulating material 8, a protective material can be deposited on the surface of the insulating material 8 and the protective layer 9 to form a new protective layer 9. The new protective layer 9 is composed of the original protective layer 9 and the newly deposited protective material.

[0189] Step S8: Form multiple second openings 406 that penetrate the patterned stacked structure 40 and the second insulating material layer 303 filled inside the patterned stacked structure 40 along the third direction z. The second openings 406 are located at the middle position between two adjacent first openings 403 and are parallel to the plane containing the second direction y and the third direction z.

[0190] like Figure 16 As shown, after the first opening 403 is filled with insulating material 8, the patterned stacked structure 40 and the second insulating material layer 303 can be anisotropically etched to form a plurality of second openings 406 extending along the second direction y and penetrating the patterned stacked structure 40 along the third direction z. A second opening 406 can be formed between every two first openings 403; and in the first direction x, the second opening 406 is located at the middle position of two adjacent first openings 403.

[0191] For example, a third mask layer can be formed on the surface of the new protective layer 9, and a third photoresist layer can be formed on the surface of the third mask layer. The third photoresist layer can be etched to form multiple second developing areas. The second developing areas can be strip-shaped and can extend along the second direction y. A second developing area can be formed between every two first openings 403 on the patterned stacked structure 40, and the orthogonal projection of the second developing area on the patterned stacked structure 40 is located at the midpoint between two adjacent first openings 403. The third mask layer, the patterned stacked structure 40, and the second insulating material layer 303 can be anisotropically etched in the second developing areas to form a second opening 406 penetrating the patterned stacked structure 40 and the second insulating material layer 303 along the third direction z. After forming the second opening 406, the third photoresist layer and the third mask layer can be removed.

[0192] In step S9, a portion of the first insulating material layer 301 is etched laterally to both sides through the second opening 406 to form the second gate 201 of the second transistor 20, and a portion of the second insulating material layer 303 is etched to both sides of the patterned stacked structure 40 along the second direction y to define the outline of the shield structure 70.

[0193] like Figure 17As shown, an isotropic etching process can be used to etch away the first insulating material layer 301 laterally (i.e., in the first direction x) through the second opening 406, while simultaneously etching the second insulating material layer 303 laterally along the second direction y. If an etching stop layer 304 embedded in the second insulating material layer 303 was previously formed, etching is stopped when the second opening 406 isotropically etched to the etching stop layer 304, forming the outline of the shield structure 70; if an etching stop layer 304 embedded in the second insulating material layer 303 was not previously formed, the outline of the shield structure 70 is formed by controlling the etching time through isotropic etching through the second opening 406. At this time, the sidewalls of the semiconductor material layer 302 located on both sides of the second opening 406 are exposed. It should be noted that when etching the first insulating material layer 301, the first insulating material layer 301 corresponding to the first pattern 401 is not completely etched, and the length of the semiconductor material layer 302 exposed after this etching is less than half the length of the first insulating material layer 301 between two adjacent first openings 403. The portion of the semiconductor material layer 302 exposed after etching the first insulating material layer 301 and the second insulating material layer 303 can be used as the second gate 201 of the second transistor 20.

[0194] In step S10, a second gate dielectric layer 202 and a second semiconductor layer 203 are sequentially deposited on the exposed surface of the second gate 201 and the contour surface of the shield structure 70. The second gate dielectric layer 202 conformally covers the sidewall of the second gate 201, the end of the second gate 201 away from the first transistor 10, and the contour surface of the shield structure 70. The second semiconductor layer 203 covers the surface of the second gate dielectric layer 202, and the second semiconductor layer 203 located on the second gate 201 includes a third source / drain region, a second channel region, and a fourth source / drain region sequentially distributed along the first direction x.

[0195] like Figure 18As shown, a second gate dielectric layer 202 and a second semiconductor layer 203 can be sequentially formed on the exposed surface of the second gate 201 and the contour surface of the shielding structure 70 by methods such as chemical vapor deposition, physical vapor deposition, or atomic layer deposition. The material of the second gate dielectric layer 202 can be a material with a high dielectric constant, such as aluminum oxide, hafnium oxide, lanthanum oxide, titanium oxide, zirconium oxide, or mixtures thereof. The second gate dielectric layer 202 located on the second gate 201 can be the gate dielectric layer of the second transistor 20, and the second gate dielectric layer 202 located on the contour surface of the shielding structure 70 can serve as the dielectric layer in the shielding structure 70. The material of the second semiconductor layer 203 can correspond to the material of the second gate 201. For example, when the material of the second gate 201 is indium zinc oxide (IZO), the material of the second semiconductor layer 203 is indium gallium zinc oxide (IGZO). The second semiconductor layer 203 located on the second gate 201 can serve as the active region of the second transistor 20. The active region of the second transistor 20 can be divided into a third source-drain region, a second channel region, and a fourth source-drain region distributed sequentially along the first direction x. The region of the active region of the second transistor 20 near the word line receiving groove 405 can be used as the third source-drain region. The second semiconductor layer 203 located on the contour surface of the shielding structure 70 can serve as the conductive material shell layer of the shielding structure 70. The second gate 201, the second gate dielectric layer 202, and the second semiconductor layer 203 can together constitute the second transistor 20.

[0196] In one exemplary embodiment of this disclosure, the method for fabricating the semiconductor memory of this disclosure may further include:

[0197] In step S310, after forming the second semiconductor layer 203, a filling layer 90 is formed to fill the shielding cavity 710 of the shielding structure 70, and the filling layer 90 closes the second opening 406.

[0198] like Figure 19 As shown, insulating material can be filled into the shielded cavity 710 by chemical vapor deposition, physical vapor deposition, or atomic layer deposition to form a filling layer 90. The filling layer 90 can fill the shielded cavity 710 and close the second opening 406. During this process, for ease of fabrication, insulating material can be deposited simultaneously on top of the patterned laminated structure 40. After the second opening 406 is filled with insulating material, the insulating material located on top of the patterned laminated structure 40 can be removed.

[0199] In step S140, a source-drain cell layer 410 is formed between the first storage cell 2 and the second storage cell 3; a source-drain region of the second transistor 20 of the first storage cell 2 and a source-drain region of the second transistor 20 of the second storage cell 3 are respectively connected to opposite sides of the source-drain cell layer 410.

[0200] like Figure 20 As shown, the source / drain cell layer 410 extends along a direction perpendicular to the substrate 1. That is, the plane containing the source / drain cell layer 410 is perpendicular to the first direction x. The fourth source / drain region in the first memory cell 2 and the fourth source / drain region in the second memory cell 3 are respectively connected to opposite sides of the source / drain cell layer 410 distributed along the first direction x. All source / drain cell layers 410 in the same plane are connected end to end to form a source / drain layer 4. This design ensures that the signal paths and conditions received by each first memory cell 2 and each second memory cell 3 are consistent, which helps to reduce read errors and data inconsistencies caused by differences in signal transmission.

[0201] In an exemplary embodiment of this disclosure, a source-drain cell layer 410 is formed between the first storage cell 2 and the second storage cell 3, including steps S410 and S420, wherein:

[0202] In step S410, a plurality of third openings 81 are formed that penetrate the filling layer 90 along the third direction z. The third openings 81 are located within the second opening 406 and expose the fourth source / drain region in the second transistor 20. The third openings 81 are parallel to the plane containing the second direction y and the third direction z.

[0203] like Figure 21 As shown, the filling layer 90 can be non-isotropically etched along the third direction z to form a third opening 81 extending along the second direction y and penetrating the filling layer 90 along the third direction z in the region corresponding to each second opening 406. The third opening 81 can expose the fourth source / drain regions located at the ends of the second gate 201 in each second transistor 20.

[0204] In step S420, conductive material is filled into the third opening 81 to form the source / drain cell layer 410.

[0205] The conductive material can be at least one of tungsten, copper, aluminum, tungsten nitride, titanium, and titanium nitride. The conductive material can be filled into the third opening 81 to form the source / drain layer 4, which can completely fill the third opening 81. The portion of the source / drain layer 4 located between the first memory cells 2 and the second memory cells 3, which are spaced apart along the first direction x in the same plane, can be used as the source / drain cell layer 410; that is, in the third direction z, each source / drain cell layer 410 is connected end-to-end to form the source / drain layer 4. In an exemplary embodiment of this disclosure, the source / drain cell layer 410 may include a resistive barrier layer and a conductive metal layer. The material of the conductive barrier layer can be a conductive material with ion-blocking function, such as titanium nitride or tantalum nitride. A conformal conductive barrier layer covering the sidewalls and bottom of the third opening 81 can be formed by chemical vapor deposition, physical vapor deposition, or atomic layer deposition. In this case, the resistive barrier layer can be in contact with both the fourth source / drain region in the first memory cell 2 and the fourth source / drain region in the second memory cell 3 exposed in the third opening 81. The conductive metal layer can be made of a metal with good conductivity, such as tungsten. The metal material can be deposited within the third opening 81, which has a conductive barrier layer, using methods such as chemical vapor deposition, physical vapor deposition, or atomic layer deposition to form the conductive metal layer. The conductive barrier layer prevents metal ions in the conductive metal layer from diffusing into other surrounding structures, thus helping to improve device reliability.

[0206] In one exemplary embodiment of this disclosure, after the source / drain unit layer 410 is formed, a protective material may be deposited on the structure jointly formed by the source / drain unit layer 410 and the protective layer 9 to form a new protective layer 9 (the new protective layer 9 consists of the original protective layer 9 and the newly deposited protective material), the protective material being the same as the original protective layer 9.

[0207] In an exemplary embodiment of this disclosure, the method for fabricating a semiconductor memory further includes steps S510 and S520, wherein:

[0208] In step S510, the first insulating material layer 301 and the second insulating material layer 303 are etched to form a plurality of first bit line receiving holes 601 and second bit line receiving holes 701 extending along the third direction z.

[0209] like Figure 22As shown, a fourth mask layer 400 and a fourth photoresist layer 500 can be formed on the surface of the protective layer 9. The fourth photoresist layer 500 can be etched to form a plurality of arrayed third developing regions 5001. The third developing regions 5001 can be rectangular, square, circular, or elliptical. Anisotropic etching can be performed on the fourth mask layer 400, the protective layer 9, the patterned stacked structure 40, and the second insulating material layer 303 in the third developing regions 5001 to form a plurality of first bit line receiving holes 601 spaced apart along the second direction y and extending along the third direction z, and a plurality of second bit line receiving holes 701 spaced apart along the second direction y and extending along the third direction z. The first bit line receiving holes 601 can expose the surface of each first active region arranged along the third direction z, and the second bit line receiving holes 701 can expose the surface of each third active region arranged along the third direction z. After forming the first bit line receiving hole 601 and the second bit line receiving hole 701, the fourth photoresist layer 500 and the fourth mask layer 400 can be removed. In this embodiment, the structure after completing step S510 is as follows: Figure 23 and Figure 24 As shown.

[0210] In step S520, a first line 6 is formed in the first line receiving hole 601, and a second line 7 is formed in the second line receiving hole 701; each first line 6 covers the outer periphery of a row of first source / drain regions arranged along the third direction z in the same plane, and each second line 7 covers the outer periphery of a row of third source / drain regions arranged along the third direction z in the same plane.

[0211] like Figure 25 As shown, a first bit line 6 can be formed in each first bit line receiving hole 601, and a second bit line 7 can be formed in each second bit line receiving hole 701. The materials of the first bit line 6 and the second bit line 7 can both be conductive materials, which can be independently selected from at least one of tungsten, copper, aluminum, tungsten nitride, titanium, and titanium nitride. The first bit line 6 can cover the outer periphery of a row of first source / drain regions arranged along the third direction z in the same plane, and each second bit line 7 can cover the outer periphery of a row of third source / drain regions arranged along the third direction z in the same plane.

[0212] In one exemplary embodiment of this disclosure, forming the first bit line 6 and the second bit line 7 may include: forming a conductive barrier layer that conformally covers the first bit line receiving hole 601 and the second bit line receiving hole 701; filling the first bit line receiving hole 601 and the second bit line receiving hole 701 with the conductive barrier layer with a metal material to form a metal layer; the material of the conductive barrier layer is titanium nitride, and the material of the metal layer is tungsten; titanium nitride can prevent tungsten ions from diffusing into other surrounding structures, which helps to improve the reliability of the device.

[0213] In one exemplary embodiment of this disclosure, after forming the first bit line 6 and the second bit line 7, each word line material layer 510 and the first insulating material layer 301 and the second insulating material layer 303 covering each word line 5 can be processed to form a plurality of word lines 5 extending along the second direction y and spaced apart along the third direction z (e.g., Figure 1 As shown), the word line 5 includes a main extension 501 and a lead-out end 502 located at at least one end of the main extension 501; in the lead-out structure of the word line 5, the orthographic projections of the lead-out ends 502 of any two word lines 5 on the substrate 1 do not overlap, and the orthographic projections of the main extensions 501 of any two word lines 5 on the substrate 1 do overlap; in the third direction z and in the direction from the side closer to the substrate 1 to the side farther away from the substrate 1, the length of each word line 5 decreases sequentially.

[0214] For ease of subsequent description, the structure consisting of the patterned stacked structure 40, the second insulating material layer 303, and the word line material layer 510 is defined as the stacked structure 600. The stacked structure 600 can be cyclically processed using a trim-etch process to transform multiple word line material layers 510 extending along the second direction y and arranged along the third direction z into multiple word lines 5 extending along the second direction y and spaced apart along the third direction z. In the third direction z, the ends of the multiple word lines 5 can be stepped, and in two adjacent word lines 5, in the direction from the side closer to the substrate 1 to the side farther from the substrate 1, the word line 5 in the upper layer exposes the lead-out end 502 of the word line 5 in the lower layer.

[0215] In an exemplary embodiment of this disclosure, the number of word line material layers 510 in the stacked structure 600 is n, and the number of insulating material layers (including the first insulating material layer 301 and the second insulating material layer 303) covering the word line material layers 510 is n+1, where n>2; in the third direction z, each word line material layer 510 can be defined from top to bottom as the 1st to the nth word line material layer 510, and each insulating material layer can be defined from top to bottom as the 1st to the n+1th insulating material layer; processing the stacked structure 600 using a trimming etching process to form multiple word lines 5 extending along the second direction y and spaced apart along the third direction z may include the following steps:

[0216] S10, a first pattern mask layer is formed on the stacked structure. The length of the first pattern mask layer in the second direction y is less than the length of the first word line material layer 510, and the orthogonal projection of the first pattern mask layer on the stacked structure does not overlap with at least one end of the first word line material layer 510.

[0217] In one exemplary embodiment of this disclosure, such as Figure 26 and Figure 27As shown, before forming the first pattern mask layer 700, an etch barrier layer 800 can be formed on the surface of the stacked structure. A mask material layer 900 can be formed on the surface of the etch barrier layer 800. The mask material layer 900 includes a plurality of mask patterns extending along the second direction y and spaced apart along the first direction x. The orthographic projection of the mask patterns on the substrate 1 completely coincides with the orthographic projection of the stacked structure on the substrate 1. The mask material layer 900 with mask patterns can etch the etch barrier layer 800 (and simultaneously etch the protective layer 9 when the stacked structure also includes a protective layer 9) to form an opening exposing the first insulating material layer. Subsequently, the mask material layer 900 can be removed, and the first pattern mask layer 700 can be formed on the surface of the etch barrier layer 800. In the second direction y, the length of the first pattern mask layer 700 is less than the length of the word line material layer 510, and the orthographic projection of the first pattern mask layer 700 on the stacked structure does not overlap with at least one end of the first word line material layer 510. For example, in the second direction y, the first pattern mask layer 700 may be located in the middle region of the stacked structure, and the orthographic projection of the first pattern mask layer 700 on the stacked structure does not overlap with the two ends of the first word line material layer 510.

[0218] S20, using the first pattern mask layer 700 as a mask, the first insulating material layer and the first word line material layer 510 are etched to expose at least one end of the second insulating material layer 8, forming a first patterned stacked structure.

[0219] It should be noted that during the anisotropic etching process, the film structure in the semiconductor block structure other than the stacked structure can be protected by the etching barrier layer 800 and the protective layer 9 to prevent damage to other structures during the etching process.

[0220] S30, a second pattern mask layer is formed on the first patterned stack structure. The length of the second pattern mask layer in the second direction y is less than the length of the remaining first word line material layer 510 after the previous etching, and the orthogonal projection of the second pattern mask layer on the substrate 1 does not overlap with at least one end of the remaining first word line material layer 510 after the previous etching.

[0221] In some embodiments of this disclosure, the first pattern mask layer 700 may be removed before forming the second pattern mask layer, thereby exposing the surface of the first patterned stack structure, and then the second patterned stack structure is formed on the first patterned stack structure. In the second direction y, the length of the second patterned stack structure may be less than the length of the first word line material layer 510 in the first patterned stack structure, and the orthographic projection of the second pattern mask layer on the substrate 1 does not overlap with at least one end of the first word line material layer 510 of the first patterned stack structure. For example, in the second direction y, the second pattern mask layer may be located in the middle region of the first patterned stack structure, and the orthographic projection of the second pattern mask layer on the first patterned stack structure does not overlap with either end of the first word line material layer 510.

[0222] In some other embodiments of this disclosure, it is not necessary to remove the first pattern mask layer 700 before forming the second pattern mask layer. The edges of the first pattern mask layer 700 in the second direction y can be etched so that the length of the first pattern mask layer 700 in the second direction y is less than the length of the first word line material layer 510 in the first patterned stack structure, and the orthographic projection of the first pattern mask layer 700 on the substrate 1 does not overlap with at least one end of the first word line material layer 510 of the first patterned stack structure. The first pattern mask layer 700 after edge etching can be defined as the second pattern mask layer.

[0223] S40, using the second pattern mask layer as a mask, the exposed second layer insulating material layer and the second layer word line material layer 510 are etched to expose at least one end of the next layer insulating material layer, forming a second patterned stacked structure.

[0224] During the etching of the second insulating material layer and the second word line material layer 510, the film structure in the semiconductor block structure other than the stacked structure can still be protected by the etching barrier layer 800 and the protective layer 9 to prevent damage to other structures during the etching process.

[0225] Repeat steps S30-S40 until at least one end of the nth insulating material layer is exposed, forming the (n-1)th patterned stack structure; each remaining word line material layer 510 after etching is used as a word line 5, and the area of ​​each word line 5 that does not overlap with other word lines 5 is used as a lead-out end 502. After forming the (n-1)th patterned stack structure, the insulating material layer on the lead-out end 502 of each word line 5 can be removed, thereby exposing the lead-out end 502 of each word line 5. The part of the word line 5 that is not a lead-out end 502 can be used as the main body extension 501.

[0226] In this disclosure, the insulating material layer and the word line material layer 510 are etched downwards layer by layer by repeating steps S30 and S40 until at least one end of the nth insulating material layer is exposed, such as... Figure 28 As shown. Each repetition of steps S30 and S40 will form a new patterned stack structure. During each repetition of steps S30 and S40, the ends of each word line material layer 510 that has been previously etched will be etched again, so that the ends of each word line material layer 510 will be synchronously recessed inward during each etching process. Each word line material layer 510 in the (n-1)th patterned stack structure can be regarded as a word line 5, and the ends of each word line 5 are arranged in a stepped manner.

[0227] In an exemplary embodiment of this disclosure, the method for fabricating a semiconductor memory may further include steps S530-S550, wherein:

[0228] In step S530, a cover layer 300 is formed on the side of each lead-out end 502 away from the substrate 1.

[0229] like Figure 29 As shown, the material of the capping layer 300 is the same as that of the insulating material layer (e.g., the first insulating material layer 301 and the second insulating material layer 303). For example, both the material of the capping layer 300 and the material of the insulating material layer are silicon oxide. The capping layer 300 can be formed on the side of the lead-out end 502 away from the substrate 1 by means of chemical vapor deposition, physical vapor deposition, or atomic layer deposition.

[0230] In step S540, the cover layer 300 is etched to form a plurality of connection holes 801 penetrating the cover layer 300 along the third direction z. The orthographic projections of different connection holes 801 on the substrate 1 at least partially overlap with the orthographic projections of different lead-out ends 502 on the substrate 1.

[0231] A fifth mask layer can be formed on the capping layer 300. The fifth mask layer is then etched to form multiple mask holes penetrating the capping layer 300 along the third z-direction. Please refer to [link to relevant documentation]. Figure 29 As shown, the capping layer 300 can be etched at the mask holes using an anisotropic etching process to form multiple connecting holes 801 penetrating the capping layer 300 along a third direction z. The connecting holes 801 can be distributed one-to-one with the lead-out ends 502. For example, each connecting hole 801 can expose each lead-out end 502. The cross-sectional shape of the connecting hole 801 can be circular, elliptical, rectangular, polygonal, or irregular, without special limitation. It should be noted that after forming the connecting holes 801, the fifth mask layer can be removed, thereby exposing the etch barrier layer 800 or protective layer 9 on top of the stacked structure 30.

[0232] In step S550, conductive material is deposited in the connection hole 801 to form the connection line 80.

[0233] The conductive material can be a material with strong conductivity, and it may include one material or two materials. For example, the conductive material may be titanium nitride and / or tungsten. For instance, the conductive material may include titanium nitride and tungsten, and a titanium nitride layer can be formed to conformally cover the sidewalls and bottom of the connection hole 801 through chemical vapor deposition, physical vapor deposition, or atomic layer deposition. During this process, for ease of fabrication, the titanium nitride layer may simultaneously cover the etch barrier layer 800 or protective layer 9 on top of the stacked structure 30. Subsequently, tungsten can be filled into the connection hole 801 with the titanium nitride layer through chemical vapor deposition, physical vapor deposition, or atomic layer deposition, filling the connection hole completely. During this process, for ease of fabrication, the tungsten may simultaneously cover the surface of the titanium nitride layer located on top of the stacked structure 30. It should be noted that after the tungsten fills the connection hole 801, the titanium carbide layer, tungsten, and etch barrier layer 800 located on the top of the stacked structure can be removed by means of back etching or grinding, and the ends of the titanium carbide layer and tungsten in the connection hole away from the substrate 1 can be flush with the surface of the protective layer 9 away from the substrate 1. The remaining titanium carbide layer and tungsten in the connection hole 801 can be used as the connection line 80.

[0234] It should be noted that, please refer to Figure 1 and Figure 30 As shown, when the word line 5 includes two lead-out ends 502, each lead-out end 502 is provided with a connecting line 80. The word line 5 can be electrically led out simultaneously through two connecting lines 80. During signal transmission, the two connecting lines 80 allow for a more uniform signal distribution, helping to reduce signal reflection and attenuation during transmission, thereby improving the integrity and stability of signal transmission. Simultaneously, the design of providing connecting lines 80 at both ends can, to a certain extent, balance the electromagnetic field distribution around the word line 5, reducing the impact of external electromagnetic interference on signal transmission and improving the circuit's anti-interference capability.

[0235] It should be noted that although the steps of the semiconductor memory fabrication method of this disclosure are described in a specific order in the accompanying drawings, this does not require or imply that these steps must be performed in that specific order, or that all the steps shown must be performed to achieve the desired result. Additional or alternative steps may be omitted, multiple steps may be combined into one step, and / or one step may be broken down into multiple steps.

[0236] Other embodiments of this disclosure will readily occur to those skilled in the art upon consideration of the specification and practice of the invention disclosed herein. This disclosure is intended to cover any variations, uses, or adaptations of this disclosure that follow the general principles of this disclosure and include common knowledge or customary techniques in the art not disclosed herein. The specification and examples are to be considered exemplary only, and the true scope and spirit of this disclosure are indicated by the appended claims.

Claims

1. A semiconductor common block structure, fabricated on a substrate, characterized in that, include: A plurality of semiconductor shared cell structures located on the substrate, the semiconductor shared cell structure including: a first memory cell and a second memory cell, the first memory cell and the second memory cell being arranged side by side in a mirror image along a first direction, the first memory cell and the second memory cell sharing the same source and drain cell layer, the first direction being parallel to the surface of the substrate; Both the first storage unit and the second storage unit include: A first transistor, located above the top surface of the substrate, includes a first gate, a first gate dielectric layer, and a first semiconductor layer. The first gate extends along the first direction. The first gate dielectric layer conformally covers the sidewalls and one end of the first gate. The first semiconductor layer covers the surface of the first gate dielectric layer and includes a first source / drain region, a first channel region, and a second source / drain region sequentially distributed along the first direction. A second transistor, arranged side-by-side with the first transistor along the first direction, includes a second gate, a second gate dielectric layer, and a second semiconductor layer. The second gate extends along the first direction. The second gate dielectric layer conformally covers the sidewalls and the end of the second gate away from the first transistor. The second semiconductor layer covers the surface of the second gate dielectric layer and includes a third source / drain region, a second channel region, and a fourth source / drain region sequentially distributed along the first direction. The second source / drain region is electrically connected to the second gate. The fourth source / drain region in the first memory cell and the fourth source / drain region in the second memory cell are respectively connected to opposite sides of the source / drain cell layer. The plurality of semiconductor shared unit structures are arranged at intervals along a second direction and a third direction, the second direction being parallel to the substrate and intersecting the first direction, and the third direction being perpendicular to the first direction and the second direction; A source / drain layer is formed by connecting all the aforementioned source / drain unit layers in the same plane end to end in sequence. The shielding structure has a shielding cavity in which all the second transistors are housed, and all the first transistors are located outside the shielding structure.

2. The semiconductor common block structure according to claim 1, characterized in that, The shielding structure is a shell structure, which includes at least one conductive material shell layer.

3. The semiconductor common block structure according to claim 1, characterized in that, The semiconductor common block structure also includes: Multiple word lines extending along the second direction and spaced apart along the first direction and the third direction, each word line being connected to the gate of a row of the first transistors arranged in the same plane along the second direction; Multiple first bit lines extending along the third direction and spaced apart along the first and second directions, each first bit line covering the outer periphery of a row of first source / drain regions arranged along the third direction in the same plane; Multiple second bit lines extending along the third direction and spaced apart along the first and second directions, each second bit line covering the outer periphery of a row of third source / drain regions arranged in the same plane along the third direction.

4. The semiconductor common block structure according to claim 3, characterized in that, The word lines include a main extension and a lead-out end located at at least one end of the main extension; in the third direction, the orthographic projections of the lead-out ends of any two word lines on the substrate do not overlap, and the orthographic projections of the main extensions of any two word lines on the substrate overlap; in the third direction and in the direction from the side closer to the substrate to the side farther from the substrate, the length of each word line decreases or increases sequentially.

5. The semiconductor common block structure according to claim 4, characterized in that, The semiconductor common block structure also includes: A connecting line extends along the third direction and connects to the lead-out end of the word line.

6. A semiconductor memory, characterized in that, include: A substrate and a plurality of semiconductor common block structures as described in any one of claims 1-5 located on the substrate, wherein the plurality of semiconductor common block structures are arranged along the first direction; The two adjacent semiconductor shared block structures are set independently of each other.

7. A method for fabricating a semiconductor memory, characterized in that, include: Provide substrate; A first memory cell and a second memory cell are formed on the substrate. The first memory cell and the second memory cell are arranged side by side in a mirror image along a first direction, which is parallel to the surface of the substrate. Both the first memory cell and the second memory cell include a first transistor and a second transistor arranged side by side along the first direction. A source-drain region of the first transistor is electrically connected to the gate of the second transistor. A shielding structure is formed that houses the second transistor of the first memory cell and the second transistor of the second memory cell within a shielding cavity; A source-drain cell layer is formed between the first memory cell and the second memory cell; a source-drain region of the second transistor of the first memory cell and a source-drain region of the second transistor of the second memory cell are respectively connected to opposite sides of the source-drain cell layer.

8. The method for fabricating a semiconductor memory according to claim 7, characterized in that, The preparation method further includes: A word line material layer is formed before the second transistor is formed; The formation of the first transistor, the second transistor, the word line material layer, and the shielding structure on the substrate includes: A first insulating material layer and a semiconductor material layer are sequentially and alternately deposited on the substrate to form a stacked structure; The stacked structure is patterned to form a patterned stacked structure. The pattern of the patterned stacked structure includes multiple first patterns extending along a first direction and spaced apart along a second direction, and multiple second patterns extending along the second direction and spaced apart along the first direction. The first direction is parallel to the surface of the substrate, and the second direction is parallel to the substrate and intersects the first direction. The first patterns and the second patterns overlap. A second insulating material layer is formed to fill the gaps in the patterned layered structure; Multiple first openings are formed along a third direction, penetrating the patterned stacked structure and the second insulating material layer. Each first opening corresponds to a second pattern, and the first opening divides the corresponding second pattern into two sub-patterns that are mirror-image arranged side by side along the first direction. The third direction is perpendicular to the first direction and the second direction, and the first opening is parallel to the plane containing the second direction and the third direction. Part of the semiconductor material layer is etched laterally to both sides through the first opening to form a plurality of accommodating portions. The accommodating portions include a row of first transistor accommodating grooves extending along the first direction and arranged along the second direction, and word line accommodating grooves extending along the second direction and communicating with the row of first transistor accommodating grooves. A first semiconductor layer, a first gate dielectric layer, and a first gate material layer are sequentially deposited within the accommodating portion; the first semiconductor layer covers the sidewalls and bottom surface of the accommodating portion, the first gate dielectric layer conformally covers the surface of the first semiconductor layer, and the first gate material layer fills the remaining space of the accommodating portion. The first gate material layer deposited in the word line receiving groove is etched away to form the first gate of the first transistor. Then, word line material is filled into the word line receiving groove to form a word line material layer. The word line material layer is in contact with the first gate. The first transistor includes the first gate, the first gate dielectric layer that conformally covers the sidewalls and one end of the first gate, and the first semiconductor layer that conformally covers the first gate dielectric layer. The first semiconductor layer on the first gate includes a first source / drain region, a first channel region, and a second source / drain region that are sequentially distributed along the first direction. Multiple second openings are formed that penetrate the patterned stacked structure and the second insulating material layer filling the interior of the patterned stacked structure along the third direction. The second openings are located at the midpoint between two adjacent first openings and are parallel to the plane containing the second direction and the third direction. Part of the first insulating material layer is etched laterally to both sides through the second opening to form the second gate of the second transistor, and part of the second insulating material layer is etched along the second direction to both sides of the patterned stacked structure to define the outline of the shield structure. A second gate dielectric layer and a second semiconductor layer are sequentially deposited on the exposed surface of the second gate and the contour surface of the shield structure. The second gate dielectric layer conformally covers the sidewall of the second gate, the end of the second gate away from the first transistor, and the contour surface of the shield structure. The second semiconductor layer covers the surface of the second gate dielectric layer, and the second semiconductor layer on the second gate includes a third source / drain region, a second channel region, and a fourth source / drain region sequentially distributed along the first direction.

9. The method for fabricating a semiconductor memory according to claim 8, characterized in that, Before forming multiple first openings extending in a third direction through the patterned stacked structure and the second insulating material layer, the method for fabricating the semiconductor memory further includes: An etch stop layer is formed embedded within the second insulating material layer; Forming the second insulating material layer and the etch stop layer includes: A third insulating material layer is deposited on the exposed surfaces of the substrate and the patterned stack structure, the third insulating material layer filling the gaps between two adjacent first patterns in the patterned stack structure, and an etch stop material layer is deposited on the surface of the third insulating material layer. The remaining gaps in the patterned stacked structure are filled with insulating material and planarized to form the second insulating material layer and the etch stop layer. The upper surfaces of the second insulating material layer, the etch stop layer and the patterned stacked structure are flush. The etch stop layer is used to define the shape and size of the shielding structure in the first direction.

10. The method for fabricating a semiconductor memory according to claim 9, characterized in that, The step of etching away a portion of the first insulating material layer laterally through the second opening to form the second gate of the second transistor, and etching away a portion of the second insulating material layer along the second direction to define the outline of the shielding structure includes: The first insulating material layer is etched laterally to both sides through the second opening, while the second insulating material layer is etched along the second direction to both sides of the patterned stacked structure. Etching stops when the etching stop layer is reached.

11. The method for fabricating a semiconductor memory according to claim 8, characterized in that, The preparation method further includes: After the second semiconductor layer is formed, a filling layer is formed to fill the shield cavity of the shield structure, and the filling layer closes the second opening.

12. The method for fabricating a semiconductor memory according to claim 11, characterized in that, A source-drain cell layer is formed between the first memory cell and the second memory cell, including: Multiple third openings are formed along the third direction through the filling layer. The third openings are located within the second openings and expose the fourth source / drain region in the second transistor. The third openings are parallel to the plane containing the second direction and the third direction. The third opening is filled with conductive material to form a source / drain cell layer; The method for fabricating the semiconductor memory further includes: The first insulating material layer and the second insulating material layer are etched to form a plurality of first bit line receiving holes and second bit line receiving holes extending along the third direction; A first bit line is formed in the first bit line receiving hole, and a second bit line is formed in the second bit line receiving hole; each first bit line covers the outer periphery of a row of first source / drain regions arranged in the same plane along the third direction, and each second bit line covers the outer periphery of a row of third source / drain regions arranged in the same plane along the third direction.

13. The method for fabricating a semiconductor memory according to claim 8, characterized in that, The preparation method further includes: Each of the word line material layers and the first and second insulating material layers covering each of the word line material layers are processed to form a plurality of word lines extending along the second direction and spaced apart along the third direction. Each word line includes a main body extension and a lead-out end located at at least one end of the main body extension. Among the lead-out ends of the word lines, the orthographic projections of any two lead-out ends on the substrate do not overlap, while the orthographic projections of the main body extensions of any two word lines on the substrate do overlap. In the third direction and in the direction from the side closer to the substrate to the side farther from the substrate, the length of each word line decreases sequentially.

14. The method for fabricating a semiconductor memory according to claim 13, characterized in that, The preparation method further includes: A cover layer is formed on the side of each lead-out end away from the substrate; The cover layer is etched to form a plurality of connection holes penetrating the cover layer along the third direction, wherein the orthographic projections of different connection holes on the substrate at least partially overlap with the orthographic projections of different lead-out ends on the substrate; Conductive material is deposited within the connection hole to form a connection wire.

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