Single diffusion isolation method for fin field effect transistor

Abstract

The application provides a single diffusion isolation method for fin field effect transistors, which comprises the following steps: forming a ring-shaped semiconductor fin body on a substrate; forming a single diffusion isolation groove in the ring-shaped semiconductor fin body by an etching process to isolate a plurality of semiconductor fin body units; forming a protective layer on the top surface, the peripheral side surface of the semiconductor fin body unit and the surface of the substrate; removing the semiconductor fin body units to be removed by etching, removing the second photoresist mask and cleaning the semiconductor fin body units; removing the edges of the semiconductor fin body units by etching; removing the protective layer; depositing an insulating medium layer on the substrate; and performing a planarization treatment on the insulating medium layer. The application can ensure the uniformity and consistency of the fin body structure on the whole chip and improve the overall performance of the chip. Meanwhile, the manufacturing process of the application can avoid the problem of height difference of the boundary photoresist caused by the existence of the fin body area and the non-fin body area on the surface of the substrate, reduce the generation of defects in the manufacturing process and improve the yield of the product.

Description

TECHNICAL FIELD

[0001] The present application belongs to the field of semiconductor integrated circuit design and manufacturing, and particularly relates to a single diffusion isolation method for fin field effect transistors. BACKGROUND

[0002] Single diffusion isolation process (SDB) is a widely used process technology in the field of semiconductor manufacturing, mainly used for forming isolation regions in integrated circuits. In the process of fin field effect transistors, after the formation of fin body, the unnecessary fin body needs to be removed (Fin cut) through cutting process. For fin field effect transistors, the current common process way of single diffusion isolation process is to perform after the fin body is formed and the fin body removal process is completed.

[0003] At present, the critical dimension (CD) in SDB process has reached the limit of photolithography technology, and at the same time, due to the existence of fin body region and non-fin body region where the fin body is removed on the surface of silicon wafer, the above two regions will produce thickness difference in the process of photoresist coating, resulting in the following problems:

[0004] 1) Difficult exposure and development: due to the non-uniformity of photoresist thickness, the exposure and development process becomes more difficult, which not only affects the accurate transfer of pattern, but also makes the control of critical dimension (CD) of device more difficult.

[0005] 2) Boundary region defects: at the junction of fin body region and non-fin body region, due to the non-uniform etching caused by the difference in photoresist thickness, defects are easily produced, which may affect the performance and reliability of the device, and even cause the device to fail.

[0006] 3) In the process of photoresist removal and cleaning, the cleaning liquid causes corrosion to the fin body, which easily affects the critical dimension (CD) of the device.

[0007] It should be noted that the above introduction to the technical background is only for the convenience of clearly and completely describing the technical scheme of the present application, and for the convenience of understanding by those skilled in the art. The above technical scheme cannot be considered as known to those skilled in the art only because it is described in the background section of the present application. SUMMARY

[0008] In view of the above-mentioned shortcomings of the prior art, the purpose of the present application is to provide a single diffusion isolation method for fin field effect transistors, which solves the problem that in the preparation process of fin field effect transistors in the prior art, due to the difference in photoresist thickness, the critical dimension of the device is difficult to control and defects are easily produced.

[0009] To achieve the above object and other related objects, the present application provides a single diffusion isolation method for fin field effect transistors, which comprises the following steps: providing a substrate, forming annular semiconductor fin bodies on the substrate; defining a single diffusion isolation groove area on the annular semiconductor fin bodies by a first photoetching mask, and forming single diffusion isolation grooves in the semiconductor fin bodies by an etching process to isolate a plurality of semiconductor fin body units, and removing the first photoetching mask; forming a protective layer on the top surface, the peripheral side surface of the semiconductor fin body units and the substrate surface between the semiconductor fin body units; defining a semiconductor fin body unit area to be removed by a second photoetching mask, and removing the semiconductor fin body unit to be removed by etching, removing the second photoetching mask and cleaning the semiconductor fin body units; defining a semiconductor fin body unit edge area to be removed by a third photoetching mask, and removing the semiconductor fin body unit edge to be removed by etching to form a plurality of independent semiconductor fin strips, removing the third photoetching mask and cleaning the semiconductor fin strips; removing the protective layer; depositing an insulating medium layer on the substrate, the insulating medium layer at least filling the gap between adjacent semiconductor fin strips and the single diffusion isolation groove and covering the semiconductor fin strips; and performing a planarization treatment on the insulating medium layer.

[0010] Optionally, the top of the annular semiconductor fin body is further formed with a hard mask layer, and the hard mask layer comprises a silicon nitride layer and a silicon oxide layer.

[0011] Optionally, when the planarization treatment is performed on the insulating medium layer, the planarization treatment stops at the surface of the silicon nitride layer.

[0012] Optionally, the protective layer comprises a titanium nitride layer, and the thickness of the titanium nitride layer is 2-50 nanometers.

[0013] Optionally, the forming method of the protective layer comprises one of a sputtering process, an evaporation process and a chemical vapor deposition process.

[0014] Optionally, the step of defining a single diffusion isolation groove area by a first photoetching mask comprises the following steps: forming a spin-on carbon layer on the substrate, the spin-on carbon layer completely filling the gap between the annular semiconductor fin bodies and having a thickness greater than the height of the annular semiconductor fin bodies; forming an anti-reflection layer on the surface of the spin-on carbon layer; forming a photoresist layer on the anti-reflection layer; performing exposure and development on the photoresist layer to define a single diffusion isolation groove area in the photoresist layer.

[0015] Optionally, defining the semiconductor fin body unit regions to be removed by a second photolithography mask comprises the steps of: forming a spin-on carbon layer on the substrate, the spin-on carbon layer completely filling the gaps between the semiconductor fin body units and the single diffusion isolation trenches, and having a thickness greater than the height of the semiconductor fin body units; forming an anti-reflective layer on the surface of the spin-on carbon layer; forming a photoresist layer on the anti-reflective layer; exposing and developing the photoresist layer to define the semiconductor fin body unit regions to be removed in the photoresist layer.

[0016] Optionally, removing the semiconductor fin body units to be removed comprises: defining all the semiconductor fin body unit regions to be removed at one time by a second photolithography mask, and removing all the semiconductor fin body units to be removed at one time by etching.

[0017] Optionally, removing the semiconductor fin body units to be removed comprises: defining part of the semiconductor fin body unit regions to be removed by a second photolithography mask, and removing part of the semiconductor fin body units to be removed by etching, removing the second photolithography mask and cleaning the semiconductor fin body units; repeating the above steps until all the semiconductor fin body units to be removed are removed.

[0018] Optionally, defining the semiconductor fin body unit edge regions to be removed by a third photolithography mask comprises the steps of: forming a spin-on carbon layer on the substrate, the spin-on carbon layer completely filling the gaps between the semiconductor fin body units and the single diffusion isolation trenches, and having a thickness greater than the height of the semiconductor fin body units; forming an anti-reflective layer on the surface of the spin-on carbon layer; forming a photoresist layer on the anti-reflective layer; exposing and developing the photoresist layer to define the semiconductor fin body unit edge regions to be removed in the photoresist layer.

[0019] Optionally, removing the semiconductor fin body unit edges to be removed comprises: defining all the semiconductor fin body unit edge regions to be removed at one time by a third photolithography mask, and removing all the semiconductor fin body unit edges to be removed at one time by etching to form a plurality of independent semiconductor fin body strips.

[0020] Optionally, removing the semiconductor fin body unit edges to be removed comprises: defining part of the semiconductor fin body unit edge regions to be removed by a third photolithography mask, and removing part of the semiconductor fin body unit edges to be removed by etching, removing the third photolithography mask and cleaning the semiconductor fin body units; repeating the above steps until all the semiconductor fin body unit edges to be removed are removed to form a plurality of independent semiconductor fin body strips.

[0021] Optionally, the cleaning liquid used in cleaning the semiconductor fin body unit has a high etching selectivity between the object to be cleaned and the protective layer, and the high etching selectivity is greater than or equal to 10:1.

[0022] Optionally, the etchant used in removing the protective layer has a high etching selectivity between the protective layer and the semiconductor fin body strip, and the high etching selectivity is greater than or equal to 10:1.

[0023] As described above, the single diffusion isolation method of the fin field effect transistor of the present application has the following beneficial effects:

[0024] The present application etches the single diffusion isolation groove before removing the semiconductor fin body, which can avoid the problem of uneven exposure caused by the inconsistent height of photoresist due to the existence of fin body area and non-fin body area during the etching process of the single diffusion isolation groove, and can ensure the uniformity and consistency of the fin structure on the entire chip, thereby improving the overall performance of the chip. At the same time, through the manufacturing process of the present application, the problem of height difference of boundary photoresist caused by the existence of fin body area and non-fin body area on the substrate surface can be avoided, the generation of defects in the manufacturing process is reduced, and the yield of the product is improved.

[0025] The present application covers titanium nitride on the surface of the semiconductor fin body after the preparation of SDB, which has good corrosion resistance, so that the loss of the critical dimension of the semiconductor fin body (Fin CD loss) can be reduced during the subsequent degumming and cleaning process, and the design accuracy of the semiconductor fin body unit is ensured. BRIEF DESCRIPTION OF DRAWINGS

[0026] The accompanying drawings included to provide a further understanding of the embodiments of the present application, constitute a part of the specification and serve to explain the principles of the present application together with the text. Obviously, the drawings in the following description are only some embodiments of the present application.

[0027] Figures 1-16 The structure schematic diagram shown in each step of the single diffusion isolation method of the fin field effect transistor of the embodiment of the present application is shown in the figure, Figures 1-4 、 Figures 6-9 and Figures 13-15 The first cross-sectional view (left) and the second cross-sectional view (right) of the device are shown, Figure 5 、 10 , 11, 12 and Figure 16 The top view structure schematic diagram of the device is shown respectively.

[0028] Element number explanation

[0029] 101 substrate

[0030] 102 annular semiconductor fin

[0031] 1021 semiconductor fin unit

[0032] 1022 semiconductor fin strip

[0033] 103 silicon nitride layer

[0034] 104 silicon oxide layer

[0035] 105 spin-on carbon layer

[0036] 106 anti-reflective layer

[0037] 107 photoresist layer

[0038] 108 single diffusion isolation trench

[0039] 109 protective layer

[0040] 110 spin-on carbon layer

[0041] 111 anti-reflective layer

[0042] 112 photoresist layer

[0043] 113 desired removed semiconductor fin unit area

[0044] 114 insulating dielectric layer

[0045] 115 third photoetch mask DETAILED DESCRIPTION

[0046] The foregoing description of the application has been set forth in the context of particular embodiments thereof, and it is to be appreciated that numerous other modifications and / or enhancements can be effected therein by one skilled in the art without departing from the spirit and scope of the application. Accordingly, the aspects of the application are not to be limited to the specific embodiments set forth herein, but are to be accorded the full scope of the claims, and any equivalents thereof.

[0047] It should be emphasized that the term "comprises / comprising" when used in this specification is taken to mean the presence of stated features, integers, steps or components but not to the exclusion of one or more other features, integers, steps, components or groups thereof.

[0048] Features described and / or illustrated with respect to one implementation can be used in the same or similar manner in one or more other implementations, in combination with or in place of features in other implementations, or in place of or in addition to features described or illustrated herein.

[0049] As illustrated in the detailed description of the embodiments of the present application, the cross-sectional view of the device structure is partially enlarged without the general proportion for the convenience of description, and the schematic view is only an example which should not limit the scope of protection of the present application herein. In addition, the three-dimensional spatial dimensions of length, width and depth should be included in the actual manufacture.

[0050] For the convenience of description, spatial relationship words such as "under", "below", "lower", "underneath", "above", "upper" and the like can be used herein to describe the relationship of one element or feature with other elements or features shown in the drawings. It will be understood that these spatial relationship words are intended to include other directions of the device in use or operation in addition to the directions depicted in the drawings. In addition, when a layer is referred to as "between" two layers, it can be the only layer between the two layers, or one or more intervening layers can also exist.

[0051] In the context of the present application, the structure described as the first feature "on" the second feature can include the embodiment in which the first and second features are formed in direct contact, and can also include the embodiment in which another feature is formed between the first and second features, so that the first and second features can not be in direct contact.

[0052] It should be noted that the diagrams provided in the embodiments herein only schematically illustrate the basic concepts of the present application, and only the components related to the present application are shown in the diagrams, not the number, shape and size of the components when actually implemented. The actual implementation of each component can be a random change in shape, number and proportion, and the layout pattern of the components can also be more complex.

[0053] As Figures 1-16 shown, the present embodiment provides a single diffusion isolation method for fin field effect transistors, which comprises the following steps:

[0054] As Figure 1 shown, first, step 1) is performed to provide a substrate 101, and a ring-shaped semiconductor fin body 102 is formed on the substrate 101.

[0055] In some embodiments, the substrate 101 can be, for example, a silicon substrate, a germanium substrate, a germanium-silicon substrate, a silicon carbide substrate, and the like, and is not limited to the examples listed herein. In the present embodiment, the substrate 101 is a single crystal silicon substrate.

[0056] In one embodiment, forming the ring-shaped semiconductor fin body 102 on the substrate 101 comprises the following steps:

[0057] Step 1-1), forming a single crystal epitaxial layer such as a single crystal silicon epitaxial layer or the like on the substrate 101 by epitaxial process;

[0058] Steps 1-2) are performed by etching the single-crystal epitaxial layer through photolithography and etching processes to form a plurality of spaced semiconductor fins 102. The semiconductor fins 102 can be, for example, rectangular rings. The rectangular rings include opposite two sides and opposite two ends. The spacing between two adjacent rectangular rings is preferably equal, and the spacing between opposite two sides in the same rectangular ring is preferably equal to the spacing between two adjacent rectangular rings.

[0059] In one embodiment, a hard mask layer is also retained or formed on the top of the annular semiconductor fin 102, the hard mask layer comprising a stack of a silicon nitride layer 103 and a silicon oxide layer 104. The silicon nitride layer 103 can serve as a process stop layer for subsequent planarization processes.

[0060] like Figures 2-5 As shown, then step 2) is performed, a single diffusion isolation trench region is defined on the annular semiconductor fin 102 by the first photolithographic mask, and a single diffusion isolation trench 108 is formed in the annular semiconductor fin 102 by etching process to isolate multiple semiconductor fin units 1021, and the first photolithographic mask is removed.

[0061] In one embodiment, defining a single diffusion isolation trench region using a first photolithographic mask includes the following steps:

[0062] Step 2-1) A spin-coated carbon layer 105 is formed on the substrate 101. The spin-coated carbon layer 105 completely fills the gap between the annular semiconductor fins 102 and the thickness is greater than the height of the annular semiconductor fins 102.

[0063] Step 2-2), an anti-reflective layer 106 is formed on the surface of the spin-coated carbon layer 105;

[0064] Steps 2-3) A photoresist layer 107 is formed on the anti-reflection layer 106;

[0065] Steps 2-4) involve exposing and developing the photoresist layer 107 to define single-diffusion isolation trench regions within the photoresist layer 107, such as... Figure 2 As shown.

[0066] Then, the spin-coated carbon layer 107 and the annular semiconductor fin 102 within the single diffusion isolation trench region can be sequentially etched using a dry etching process. A single diffusion isolation trench 108 is formed in the annular semiconductor fin 102 to isolate multiple semiconductor fin units 1021, such as... Figure 3 As shown, the first photomask is finally removed by wet cleaning or a dry process, such as... Figure 4 and Figure 5 As shown.

[0067] The present application can avoid the problem of uneven exposure caused by the inconsistent height of photoresist due to the existence of fin region and non-fin region in the etching process of the single diffusion isolation groove 108, and can ensure the uniformity and consistency of the fin structure on the whole chip, thereby improving the overall performance of the chip. At the same time, through the manufacturing process of the present application, the problem of height difference of boundary photoresist caused by the existence of fin region and non-fin region on the surface of the substrate 101 can be avoided, the generation of defects in the manufacturing process is reduced, and the yield of the product is improved.

[0068] As shown in Figure 6 Step 3) is then performed to form a protective layer 109 on the top surface of the semiconductor fin unit 1021, the surrounding side surface, and the surface of the substrate 101 between the semiconductor fin units 1021. The protective layer 109 is used to protect the surrounding side surface of the semiconductor fin unit 1021 from corrosion during subsequent cleaning processes (such as cleaning photoresist residues, etc.), and to ensure the stability of the critical dimensions of the semiconductor fin unit 1021.

[0069] In one embodiment, the protective layer 109 preferably includes a titanium nitride layer, and the thickness of the protective layer 109 is preferably sufficient to ensure its protective function and its efficient removal in the later stage. Therefore, the thickness of the titanium nitride layer is preferably 2-50 nanometers, such as 2 nanometers, 3 nanometers, 5 nanometers, 10 nanometers, 50 nanometers, etc., and is not limited to the examples listed here.

[0070] In one embodiment, the method for forming the protective layer 109 includes one of sputtering process, evaporation process, and chemical vapor deposition process.

[0071] As shown in Figures 7-10 Step 4) is then performed to define the required cut-off semiconductor fin unit region 113 through a second photoresist mask, and to remove the required cut-off semiconductor fin unit 1021 through etching, remove the second photoresist mask, and clean the semiconductor fin unit 1021;

[0072] In one embodiment, defining the required cut-off semiconductor fin unit region 113 through the second photoresist mask includes the following steps:

[0073] Step 4-1) is to form a spin-on carbon layer 110 on the substrate 101, which completely fills the gap between the semiconductor fins 1021 and the single diffusion isolation groove 108, and has a thickness greater than the height of the semiconductor fins 1021;

[0074] Step 4-2) is to form an antireflection layer 111 on the surface of the spin-on carbon layer 110, and to form a photoresist layer 112 on the antireflection layer 111;

[0075] Step 4-3) Expose and develop the photoresist layer 112 to define the semiconductor fin unit region 113 to be removed in the photoresist layer 112.

[0076] In one embodiment, removing the semiconductor fin unit 1021 to be cut off includes: defining all semiconductor fin unit regions 113 to be cut off at once using a second photolithographic mask, and removing all semiconductor fin units 1021 to be cut off at once by etching. This method can effectively improve the removal efficiency of semiconductor fin units 1021.

[0077] In another embodiment, removing the semiconductor fin unit 1021 to be cut off includes: defining a portion of the semiconductor fin unit region 113 to be cut off using a second photomask, removing a portion of the semiconductor fin unit 1021 to be cut off by etching, removing the second photomask and cleaning the semiconductor fin unit 1021; repeating the above steps until all the semiconductor fin units 1021 to be cut off are removed. This method can effectively improve the removal accuracy of the semiconductor fin unit 1021.

[0078] After removing the second photolithography mask, since some mask material will remain on the device, this embodiment will clean the semiconductor fin unit 1021. During cleaning, the surface of the semiconductor fin 102 of the present invention is covered with titanium nitride, which has good corrosion resistance. Therefore, during the cleaning process, the loss of critical dimensions of the semiconductor fin unit 1021 can be reduced, and the design accuracy of the semiconductor fin 102 can be maintained.

[0079] In one embodiment, when cleaning the semiconductor fin unit 1021, the cleaning solution used has a high etch selectivity between the object to be cleaned and the protective layer 109, wherein the high etch selectivity is greater than or equal to 10:1. Preferably, the high etch selectivity is greater than or equal to 50:1.

[0080] like Figures 11-12 As shown, then step 5) is performed, the edge region of the semiconductor fin unit 1021 to be removed is defined by the third photolithography mask 115, and the edge of the semiconductor fin unit 1021 to be removed is removed by etching to form multiple independent semiconductor fin strips 1022, the third photolithography mask is removed and the semiconductor fin strips 1022 are cleaned.

[0081] In one embodiment, defining the edge region of the semiconductor fin unit 1021 to be removed using a third photomask 115 includes the steps of: forming a spin-coated carbon layer on the substrate, the spin-coated carbon layer completely filling the gaps between the semiconductor fin units 1021 and the single diffusion isolation trench 108, and having a thickness greater than the height of the semiconductor fin unit 1021; forming an anti-reflection layer on the surface of the spin-coated carbon layer; forming a photoresist layer on the anti-reflection layer; and exposing and developing the photoresist layer to define the edge region of the semiconductor fin unit 1021 to be removed in the photoresist layer.

[0082] In one embodiment, removing the edges of the semiconductor fin unit 1021 to be cut off includes: defining all edge regions of the semiconductor fin unit 1021 to be cut off at once using a third photolithography mask 115, and removing all edges of the semiconductor fin unit 1021 to be cut off at once by etching, so as to form a plurality of independent semiconductor fin strips 1022.

[0083] In one embodiment, removing the edges of the semiconductor fin unit 1021 to be cut off includes: defining a portion of the edge region of the semiconductor fin unit 1021 to be cut off using a third photolithographic mask 115, removing the portion of the edge of the semiconductor fin unit 1021 to be cut off by etching, removing the third photolithographic mask 115 and cleaning the semiconductor fin unit 1021; repeating the above steps until all the edges of the semiconductor fin units 1021 to be cut off are removed to form a plurality of independent semiconductor fin strips 1022.

[0084] like Figure 13 As shown, proceed to step 6) to remove the protective layer 109.

[0085] For example, when removing the protective layer 109, the etchant used has a high etch selectivity between the protective layer 109 and the semiconductor fin strip 1022, with a high etch selectivity of ≥10:1. Preferably, the high etch selectivity is ≥50:1.

[0086] like Figure 14 As shown, step 7) is then performed, in which an insulating dielectric layer 114 is deposited on the substrate 101. The insulating dielectric layer 114 at least fills the gap between adjacent semiconductor fin strips 1022 and the single diffusion isolation trench 108 and covers the semiconductor fin strips 1022.

[0087] In one embodiment, an insulating dielectric layer 114 can be deposited on the substrate 101 by a chemical vapor deposition (CVD) process. The insulating dielectric layer 114 can be made of, for example, silicon dioxide.

[0088] like Figures 15-16As shown, finally, step 8) is performed, and the insulating medium layer 114 is subjected to a planarization treatment.

[0089] In one embodiment, a chemical mechanical polishing process (CMP) can be used to planarize the insulating medium layer 114, and the planarization treatment is stopped at the surface of the silicon nitride layer 103.

[0090] As described above, the single diffusion isolation method for the fin field effect transistor of the present application has the following beneficial effects:

[0091] The present application first performs etching of the single diffusion isolation groove before removing the semiconductor fin, which can avoid the problem of uneven exposure caused by the inconsistent height of photoresist due to the presence of fin regions and non-fin regions during the etching process of the single diffusion isolation groove, and can ensure the uniformity and consistency of the fin structure on the entire chip, thereby improving the overall performance of the chip. At the same time, through the manufacturing process of the present application, the problem of height difference of the boundary photoresist caused by the presence of fin regions and non-fin regions on the substrate surface can be avoided, the generation of defects during the manufacturing process is reduced, and the yield of the product is improved.

[0092] The present application covers the titanium nitride on the surface of the semiconductor fin after the preparation of the SDB, which has good corrosion resistance, so that the loss of the critical dimension of the semiconductor fin (Fin CD loss) can be reduced during the subsequent stripping and cleaning process, and the design accuracy of the semiconductor fin unit is ensured.

[0093] Therefore, the present application effectively overcomes the various shortcomings in the prior art and has high industrial utilization value.

[0094] The above embodiments only exemplarily illustrate the principles and effects of the present application, and are not intended to limit the present application. Any person skilled in the art can modify or change the above embodiments without departing from the spirit and scope of the present application. Therefore, all equivalent modifications or changes made by those skilled in the art without departing from the spirit and technical idea disclosed by the present application should be covered by the claims of the present application.

Claims

1. A single diffusion isolation method for fin field effect transistors, comprising: The single diffusion isolation method comprises: providing a substrate, forming ring-shaped semiconductor fins on the substrate; defining a single diffusion isolation trench area on the ring-shaped semiconductor fins by a first photoetching mask, forming single diffusion isolation trenches in the semiconductor fins by an etching process to isolate a plurality of semiconductor fin units, and removing the first photoetching mask; forming a protective layer on the top surface, the surrounding side surface of the semiconductor fin units and the substrate surface between the semiconductor fin units; defining a semiconductor fin unit area to be removed by a second photoetching mask, and removing the semiconductor fin unit to be removed by etching, removing the second photoetching mask and cleaning the semiconductor fin units; defining a semiconductor fin unit edge area to be removed by a third photoetching mask, and removing the semiconductor fin unit edge to be removed by etching to form a plurality of independent semiconductor fin strips, removing the third photoetching mask and cleaning the semiconductor fin strips; removing the protective layer; depositing an insulating medium layer on the substrate, the insulating medium layer at least filling the gap between adjacent semiconductor fin strips and the single diffusion isolation trench and covering the semiconductor fin strips; planarizing the insulating medium layer.

2. The method of claim 1 wherein: The top of the ring-shaped semiconductor fin further forms a hard mask layer, and the hard mask layer comprises a silicon nitride layer and a silicon oxide layer.

3. The method of claim 2 wherein: the fin field effect transistor is a p-type fin field effect transistor. When the insulating medium layer is planarized, the planarization stops at the surface of the silicon nitride layer.

4. The method of claim 1 wherein: the fin field effect transistor is a p-type fin field effect transistor. The protective layer comprises a titanium nitride layer, and the thickness of the titanium nitride layer is 2-50 nanometers.

5. The method of claim 1 wherein: the fin field effect transistor is a p-type metal oxide semiconductor (PMOS) transistor. The forming method of the protective layer comprises one of a sputtering process, an evaporation process and a chemical vapor deposition process.

6. The method of claim 1 wherein: the fin field effect transistor is a p-type metal oxide semiconductor (PMOS) transistor. Defining a single diffusion isolation trench area by a first photoetching mask comprises the following steps: forming a spin-on carbon layer on the substrate, the spin-on carbon layer completely filling the gap between the ring-shaped semiconductor fins and having a thickness greater than the height of the ring-shaped semiconductor fins; forming an anti-reflection layer on the surface of the spin-on carbon layer; forming a photoresist layer on the anti-reflection layer; exposing and developing the photoresist layer to define a single diffusion isolation trench area in the photoresist layer.

7. The method of claim 1 wherein: the fin field effect transistor is a p-type metal oxide semiconductor (PMOS) transistor. Defining a semiconductor fin unit area to be removed by a second photoetching mask comprises the following steps: forming a spin-on carbon layer on the substrate, the spin-on carbon layer completely filling the gap between the semiconductor fin units and the single diffusion isolation trench and having a thickness greater than the height of the semiconductor fin units; forming an anti-reflection layer on the surface of the spin-on carbon layer; forming a photoresist layer on the anti-reflection layer; exposing and developing the photoresist layer to define a semiconductor fin unit area to be removed in the photoresist layer.

8. The method of claim 1 wherein: the fin field effect transistor is a p-type metal oxide semiconductor (PMOS) transistor. Removing the semiconductor fin unit to be removed comprises: defining all the semiconductor fin unit areas to be removed at one time by a second photoetching mask, and removing all the semiconductor fin units to be removed at one time by etching.

9. The method of claim 1 wherein: the fin field effect transistor is a p-type metal oxide semiconductor (PMOS) transistor. Removing the semiconductor fin unit to be removed comprises: Defining part of the required removed semiconductor fin body unit region by a second photoetching mask, and removing part of the required removed semiconductor fin body unit by etching, removing the second photoetching mask and cleaning the semiconductor fin body unit; Repeating the above steps until all the required removed semiconductor fin body units are removed.

10. The method of claim 1 wherein: the fin field effect transistor is a p-type metal oxide semiconductor (PMOS) transistor. Defining the required removed semiconductor fin body edge region by a third photoetching mask, including the steps of: Forming a spin-on carbon layer on the substrate, the spin-on carbon layer completely filling the gap between the semiconductor fin body units and the single diffusion isolation trench, and the thickness being greater than the height of the semiconductor fin body units; Forming an anti-reflection layer on the surface of the spin-on carbon layer; Forming a photoresist layer on the anti-reflection layer; Exposing and developing the photoresist layer to define the required removed semiconductor fin body edge region in the photoresist layer.

11. The method of claim 10, wherein: Removing the required removed semiconductor fin body edge includes: Defining all the required removed semiconductor fin body edge regions by a third photoetching mask at one time, and removing all the required removed semiconductor fin body edges by etching at one time to form a plurality of independent semiconductor fin body strips.

12. The method of claim 10, wherein: Removing the required removed semiconductor fin body edge includes: Defining part of the required removed semiconductor fin body edge region by a third photoetching mask, and removing part of the required removed semiconductor fin body edge by etching, removing the third photoetching mask and cleaning the semiconductor fin body unit; Repeating the above steps until all the required removed semiconductor fin body edges are removed to form a plurality of independent semiconductor fin body strips.

13. The method of claim 1 wherein: the fin field effect transistor is a p-type metal oxide semiconductor (PMOS) transistor. When cleaning the semiconductor fin body unit, the cleaning liquid used has a high etching selectivity between the to-be-cleaned object and the protective layer, and the high etching selectivity is greater than or equal to 10:

1.

14. The method of claim 1 wherein: the fin field effect transistor is a p-type metal oxide semiconductor (PMOS) transistor. When removing the protective layer, the etchant used has a high etching selectivity between the protective layer and the semiconductor fin body strip, and the high etching selectivity is greater than or equal to 10:1.

Images