Pseudo self-aligned p-gaN gate high electron mobility transistor and method of making same

Abstract

The application discloses a pseudo self-aligned p-type gallium nitride gate high electron mobility transistor and a preparation method thereof, relates to the technical field of transistors, and selects an existing epitaxial wafer, carries out mesa isolation, surface treatment, etches a p-GaN cap layer to expose a contact area, deposits a passivation layer, removes a gate region mask material, evaporates n-type ohmic contact metal to form a source electrode and a drain electrode, and evaporates gate contact metal, so as to finally prepare the pseudo self-aligned p-type gallium nitride gate high electron mobility transistor. On the basis of a conventional high electron mobility transistor, after etching of the pGaN is completed, the application continues to mask with a mask material, and after epitaxial growth of a passivation layer, the epitaxially grown passivation layer is selectively stripped through the mask material, so that the pGaN cap layer is exposed, and thus, gate pseudo self-alignment is realized.

Description

TECHNICAL FIELD

[0001] The application relates to the field of transistors, in particular to a pseudo self-aligned p-type gallium nitride gate high electron mobility transistor and a preparation method thereof. BACKGROUND

[0002] A conventional pGaN gate HEMT device works by using a two-dimensional electron gas with very high mobility, and can be used for ultra-high frequency and ultra-high speed operation. Currently, the most mature two pGaN gate HEMT manufacturing processes can be divided into two types - a post-gate misalignment process and a pre-gate self-alignment process. The post-gate misalignment process is a method of depositing the gate metal by aligning the mark after the high-temperature ohmic contact of the drain and source. Although this scheme can repair the surface state after etching by high temperature and achieve low ohmic contact, it has high requirements for the alignment of the photolithography equipment and needs to reserve sufficient alignment error.

[0003] However, the pre-gate self-alignment process is a process of using metal as a gate hard mask to simultaneously achieve pGaN cap layer etching and gate metal alignment deposition. However, due to the presence of the gate metal, most surface treatment processes cannot be used after the device is etched. SUMMARY

[0004] The purpose of the application is to provide a pseudo self-aligned p-type gallium nitride gate high electron mobility transistor and a preparation method thereof, which can realize gate pseudo self-alignment.

[0005] To achieve the above purpose, the application provides the following solutions:

[0006] In a first aspect, the application provides a preparation method of a pseudo self-aligned p-type gallium nitride gate high electron mobility transistor, comprising:

[0007] Selecting an epitaxial wafer having formed a substrate, a buffer layer, a GaN channel layer, an AlGaN barrier layer and a p-GaN cap layer.

[0008] Carrying out mesa isolation on the epitaxial wafer having formed a substrate, a buffer layer, a GaN channel layer, an AlGaN barrier layer and a p-GaN cap layer.

[0009] Carrying out surface treatment on the device after completing the mesa isolation.

[0010] Using a mask material to etch the p-GaN cap layer to expose the contact area of the source and drain electrodes.

[0011] Carrying out surface treatment on the device without removing or damaging the gate mask material.

[0012] Depositing a passivation layer on the basis of the gate mask material by PVD or CVD.

[0013] The mask material of the gate region is removed by lift-off.

[0014] The n-type ohmic contact metal is evaporated on the window of the drain electrode and the source electrode region by electron beam evaporation, thermal evaporation or magnetron sputtering process, and high temperature annealing is performed to form the source electrode and the drain electrode.

[0015] The gate contact metal is evaporated on the window of the gate electrode region by electron beam evaporation, thermal evaporation or magnetron sputtering process to obtain the prepared pseudo self-aligned p-type gallium nitride gate high electron mobility transistor.

[0016] In a second aspect, the application provides a pseudo self-aligned p-type gallium nitride gate high electron mobility transistor, comprising: a substrate, a buffer layer, a GaN channel layer, an AlGaN barrier layer, a p-GaN cap layer, a passivation layer, a gate, a source and a drain.

[0017] The buffer layer is covered on the substrate; the GaN channel layer is covered on the buffer layer; the AlGaN barrier layer is covered on the GaN channel layer; the source and the drain are arranged at two ends of the AlGaN barrier layer; the p-GaN cap layer is located above the AlGaN barrier layer and is not connected with the source and the drain; the passivation layer is located above the AlGaN barrier layer and part of the p-GaN cap layer; and the gate is located above the p-GaN cap layer and part of the passivation layer.

[0018] According to the specific embodiments provided by the application, the following technical effects are disclosed:

[0019] The application provides a pseudo self-aligned p-type gallium nitride gate high electron mobility transistor and a preparation method thereof. The application provides a pseudo self-aligned p-type gallium nitride gate high electron mobility transistor and a preparation method thereof. BRIEF DESCRIPTION OF DRAWINGS

[0020] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the following will briefly introduce the drawings needed to be used in the embodiments. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without any creative effort on the basis of these drawings.

[0021] Figure 1 The application provides a pseudo self-aligned p-type gallium nitride gate high electron mobility transistor and a preparation method thereof.

[0022] Figure 2 The application provides a pseudo self-aligned p-type gallium nitride gate high electron mobility transistor and a preparation method thereof.

[0023] Figure 3 The application provides a pseudo self-aligned p-type gallium nitride gate high electron mobility transistor and a preparation method thereof.

[0024] Figure 4 The application provides a pseudo self-aligned p-type gallium nitride gate high electron mobility transistor and a preparation method thereof.

[0025] Figure 5 This is a cross-sectional view 2 of a pseudo-self-aligned p-type gallium nitride gate high electron mobility transistor provided in one embodiment of this application.

[0026] Figure 6 This is a cross-sectional view (3) of a pseudo-self-aligned p-type gallium nitride gate high electron mobility transistor provided in one embodiment of this application.

[0027] Figure 7 An alternative process flow provided in one embodiment of this application Figure 1 .

[0028] Figure 8 An alternative process flow provided in one embodiment of this application Figure 2 .

[0029] Figure 9 An alternative process flow provided in one embodiment of this application Figure 3 .

[0030] Figure 10 An alternative process flow provided in one embodiment of this application Figure 4 .

[0031] Figure 11 An alternative process flow provided in one embodiment of this application Figure 5 .

[0032] Figure 12 An alternative process flow provided in one embodiment of this application Figure 6 .

[0033] Figure 13 An alternative process flow provided in one embodiment of this application Figure 7 . Detailed Implementation

[0034] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0035] To make the above-mentioned objectives, features and advantages of this application more apparent and understandable, the application will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0036] Example 1

[0037] like Figure 1As shown, the embodiment provides a preparation method of a pseudo self-aligned p-type GaN gate high electron mobility transistor, comprising:

[0038] Step 101: Select an epitaxial wafer having formed a substrate, a buffer layer, a GaN channel layer, an AlGaN barrier layer and a p-GaN cap layer.

[0039] Step 102: Perform mesa isolation on the epitaxial wafer having formed a substrate, a buffer layer, a GaN channel layer, an AlGaN barrier layer and a p-GaN cap layer.

[0040] Step 103: Perform surface treatment on the device after completing mesa isolation.

[0041] Step 104: Use a mask material to etch the p-GaN cap layer to expose the contact area of the source and drain electrodes.

[0042] Step 105: Perform surface treatment on the device without removing or damaging the gate mask material.

[0043] Step 106: Deposit a passivation layer on the basis of the gate mask material by PVD or CVD.

[0044] Step 107: Remove the mask material in the gate region by lift-off.

[0045] Step 108: Use electron beam evaporation, thermal evaporation or magnetron sputtering process to evaporate n-type ohmic contact metal on the source and drain electrode area window and form the source and drain electrode by high temperature annealing.

[0046] Step 109: Use electron beam evaporation, thermal evaporation or magnetron sputtering process to evaporate gate contact metal on the gate electrode area window to obtain a prepared pseudo self-aligned p-type GaN gate high electron mobility transistor.

[0047] In some embodiments, when performing the surface treatment step on the device after completing mesa isolation, the embodiment adopts various treatment methods, including but not limited to: using HCl (hydrogen chloride), H2SO4+H2O2 (sulfuric acid and hydrogen peroxide mixture), BOE (buffered oxide etching solution), aqua regia, TMAH and NH4OH, etc.

[0048] The above treatment methods are also used when performing surface treatment on the surface damage after etching the pGaN.

[0049] In some embodiments, when evaporating n-type ohmic contact metal on the source and drain electrode area window and forming the source and drain electrode by high temperature annealing, the n-type ohmic contact metal used is Ti / Al, Ti / Al / Ni / Au or Ti / Al / Ti / Au.

[0050] In some specific instances, such as Figure 2 The illustrated alternative process flow diagram shows that, in this embodiment, an epitaxial wafer comprising a pre-formed substrate, a buffer layer, a GaN channel layer, an AlGaN barrier layer, and a p-GaN cap layer is selected as the base material. Subsequently, this embodiment uses a mask material to finely etch the p-GaN cap layer to accurately expose the contact area between the source and drain electrodes. Next, this embodiment pre-treats the surface with the gate mask material to ensure the smooth progress of subsequent steps. Based on this, this embodiment uses PVD (Physical Vapor Deposition) or CVD (Chemical Vapor Deposition) technology to precisely deposit a passivation layer to enhance the device's protection performance. Subsequently, this embodiment utilizes a lift-off technique to cleverly remove the mask material in the gate region, freeing up space for subsequent process steps. Next, this embodiment employs high-precision processes such as electron beam evaporation, thermal evaporation, or magnetron sputtering to precisely deposit n-type ohmic contact metals (such as Ti / Al, Ti / Al / Ni / Au, or Ti / Al / Ti / Au) on the windows of the drain and source electrode regions. These are then subjected to high-temperature annealing to form stable source and drain electrodes. Finally, this embodiment again utilizes electron beam evaporation, thermal evaporation, or magnetron sputtering to evaporate gate contact metal on the windows of the gate electrode region, completing a key step in the entire process flow.

[0051] Example 2

[0052] like Figure 3 As shown, this embodiment provides a pseudo-self-aligned p-type gallium nitride gate high electron mobility transistor, which includes: a substrate, a buffer layer, a GaN channel layer, an AlGaN barrier layer, a p-GaN cap layer, a passivation layer, a gate, a source, and a drain.

[0053] The buffer layer covers the substrate; the GaN channel layer covers the buffer layer; the AlGaN barrier layer covers the GaN channel layer; the AlGaN barrier layer has a source and a drain at both ends; the p-GaN cap layer is located above the AlGaN barrier layer and is not connected to the source and drain; the passivation layer is located above the AlGaN barrier layer and part of the p-GaN cap layer; the gate is located above the p-GaN cap layer and part of the passivation layer.

[0054] In some embodiments, such as Figures 4-6As shown, the whole structure includes substrate, buffer layer, GaN channel layer (UID-GaN channel layer), AlGaN barrier layer, p-GaN cap layer, passivation layer, gate, source and drain from bottom to top. The source and drain are provided on both ends of the AlGaN barrier layer. The substrate is at the very bottom of the whole structure and serves as a support, which can be but is not limited to a silicon (Silicon) substrate, a sapphire (Sappire) substrate, a silicon carbide (SiC) substrate or a self-supporting gallium nitride substrate. The buffer layer is above the substrate, which can use but is not limited to a gallium nitride layer doped with iron (Fe) or carbon (C) or an Al(Ga)N / GaN superlattice structure. The GaN channel layer is above the buffer layer. The AlGaN barrier layer is above the GaN channel layer and generates a two-dimensional electron gas (2DEG) on the side close to the GaN channel layer at the interface between the AlGaN barrier layer and the GaN channel layer through piezoelectric polarization and spontaneous polarization effects. The p-GaN cap layer is above the AlGaN barrier layer, which suppresses the generation of 2DEG at the AlGaN / GaN interface through piezoelectric polarization and spontaneous polarization effects at the GaN / AlGaN interface and the p-type doping of the p-GaN cap layer itself, thereby realizing an enhancement n-FET device, wherein the p-GaN contact can be an ohmic contact, a Schottky contact and a dielectric layer isolation (MIS) and the like. The passivation layer is above the AlGaN barrier layer and part of the p-GaN cap layer, which can use but is not limited to silicon nitride (Si3N4), aluminum nitride (AlN), aluminum oxide (Al2O3), magnesium oxide (MgO) or silicon oxide (SiO2) as an insulating layer material. In order to achieve better stripping effect, the etching mask layer and the passivation layer should have a good chemical etching selectivity to achieve the stripping process of the passivation layer.

[0055] In addition, in some embodiments, as Figures 7-13 shown, another seven alternative process flows are also included, which are as follows:

[0056] Among them, as Figure 7 shown, the alternative process flow Figure 1 is as follows:

[0057] Step 1: Select an epitaxial wafer with formed substrate, buffer layer, GaN channel layer, AlGaN barrier layer and p-GaN cap layer.

[0058] Step 2: Perform mesa isolation on the epitaxial wafer with formed substrate, buffer layer, GaN channel layer, AlGaN barrier layer and p-GaN cap layer.

[0059] Step 3: Perform surface treatment on the device after completing the mesa isolation.

[0060] Step 4: Using a single layer mask material in the shape of a "T" or inverted triangle, the gate region is protected and the p-GaN cap layer is etched, removing the p-GaN cap layer in the non-gate region.

[0061] Step 5: The device is surface treated without removing or damaging the gate mask material.

[0062] Step 6: A passivation layer is deposited on top of the gate mask material by PVD or CVD, and due to the narrow gap under the mask layer, the passivation layer can partially deposit onto the surface of the p-GaN gate, providing better passivation.

[0063] Step 7: The mask material in the gate region is removed by lift-off.

[0064] Step 8: The passivation layer is etched to expose the contact area of the source and drain electrodes.

[0065] Step 9: The gate contact metal is evaporated on the gate electrode region window using electron beam evaporation, thermal evaporation, or magnetron sputtering process, resulting in a prepared pseudo self-aligned p-type gallium nitride gate high electron mobility transistor.

[0066] Alternatively, as shown in the process flow Figure 8 , the specific steps are as follows: Figure 2

[0067] Step 1: Select an epitaxial wafer with a formed substrate, buffer layer, GaN channel layer, AlGaN barrier layer, and p-GaN cap layer.

[0068] Step 2: The epitaxial wafer with a formed substrate, buffer layer, GaN channel layer, AlGaN barrier layer, and p-GaN cap layer is mesa isolated.

[0069] Step 3: The device with completed mesa isolation is surface treated.

[0070] Step 4: The gate region is protected using a mask material, and the p-GaN cap layer is etched, removing the p-GaN cap layer in the non-gate region.

[0071] Step 5: The device is surface treated without removing or damaging the gate mask material.

[0072] Step 6: A passivation layer is deposited on top of the gate mask material by PVD or CVD.

[0073] Step 7: The mask material in the gate region is removed by lift-off.

[0074] Step 8: A gate dielectric layer is deposited by PVD or CVD to provide better passivation and voltage resistance for the device gate.​

[0075] Step 9: Etching the dielectric layer and the passivation layer to expose the contact area of the source and drain electrodes.

[0076] Step 10: Evaporating the gate contact metal on the gate electrode area window by electron beam evaporation, thermal evaporation or magnetron sputtering process to obtain the prepared pseudo self-aligned p-type gallium nitride gate high electron mobility transistor.

[0077] In which, the alternative process flow is shown in Figure 9 Figure 3 The specific steps are as follows:

[0078] Step 1: Selecting an epitaxial wafer with formed substrate, buffer layer, GaN channel layer, AlGaN barrier layer and p-GaN cap layer.

[0079] Step 2: Performing mesa isolation on the epitaxial wafer with formed substrate, buffer layer, GaN channel layer, AlGaN barrier layer and p-GaN cap layer.

[0080] Step 3: Performing surface treatment on the device after completing mesa isolation.

[0081] Step 4: Using a single layer of mask material in the shape of "T" or inverted triangle to protect the gate region and etching the p-GaN cap layer to remove the p-GaN cap layer in the non-gate region.

[0082] Step 5: Performing surface treatment on the device without removing or damaging the gate mask material.

[0083] Step 6: Depositing a passivation layer on the basis of the gate mask material by PVD or CVD, and due to the narrower space below the mask layer, the passivation layer can partially deposit on the surface of the p-GaN gate, achieving better passivation effect.

[0084] Step 7: Removing the mask material in the gate region by lift-off.

[0085] Step 8: Depositing a gate dielectric layer by PVD or CVD to achieve better passivation and voltage resistance effect for the device gate.

[0086] Step 9: Etching the dielectric layer and the passivation layer to expose the contact area of the source and drain electrodes.

[0087] Step 10: Evaporating the gate contact metal on the gate electrode area window by electron beam evaporation, thermal evaporation or magnetron sputtering process to obtain the prepared pseudo self-aligned p-type gallium nitride gate high electron mobility transistor.

[0088] In which, the alternative process flow is shown in Figure 10 ​​Figure 4 The specific steps are as follows:

[0089] Step 1: Select an epitaxial wafer that has already formed a substrate, buffer layer, GaN channel layer, AlGaN barrier layer and p-GaN cap layer.

[0090] Step 2: Perform mesa isolation on the epitaxial wafer that has formed the substrate, buffer layer, GaN channel layer, AlGaN barrier layer and p-GaN cap layer.

[0091] Step 3: Perform surface treatment on the devices that have completed the platform isolation.

[0092] Step 4: Use a T-shaped double-layer mask material that is wider at the top and narrower at the bottom to protect the gate region and etch the p-GaN cap layer to remove the p-GaN cap layer in the non-gate region.

[0093] Step 5: Perform surface treatment on the device without removing or damaging the gate mask material.

[0094] Step 6: Based on the gate mask material, a passivation layer is deposited by PVD or CVD. Due to the narrowness of the underlying mask layer, the passivation layer can be partially deposited on the surface of the p-GaN gate, resulting in a better passivation effect.

[0095] Step 7: Remove the mask material from the gate region by lift-off.

[0096] Step 8: Etch the passivation layer to expose the contact area between the source and drain electrodes.

[0097] Step 9: Using electron beam evaporation, thermal evaporation or magnetron sputtering, evaporate the gate contact metal on the gate electrode region window to obtain the prepared pseudo-self-aligned p-type gallium nitride gate high electron mobility transistor.

[0098] Among them, such as Figure 11 The alternative process flow shown Figure 5 The specific steps are as follows:

[0099] Step 1: Select an epitaxial wafer that has already formed a substrate, buffer layer, GaN channel layer, AlGaN barrier layer and p-GaN cap layer.

[0100] Step 2: Perform mesa isolation on the epitaxial wafer that has formed the substrate, buffer layer, GaN channel layer, AlGaN barrier layer and p-GaN cap layer.

[0101] Step 3: Perform surface treatment on the devices that have completed the platform isolation.

[0102] Step 4: Using the double-layer mask material with the "T" shape of wide top and narrow bottom, the gate region is protected and the p-GaN cap layer is etched to remove the p-GaN cap layer in the non-gate region.

[0103] Step 5: Removing the upper etching mask layer.

[0104] Step 6: Surface treatment of the device without removing or damaging the gate mask material.

[0105] Step 7: Deposition of the passivation layer on the basis of the gate mask material by PVD or CVD, and due to the narrower mask layer below the p-GaN gate, the passivation layer can partially deposit on the surface of the p-GaN gate, achieving better passivation effect.

[0106] Step 8: Removing the mask material in the gate region by lift-off.

[0107] Step 9: Etching the passivation layer to expose the contact area of the source and drain electrodes.

[0108] Step 10: Evaporating the gate contact metal on the gate electrode region window by electron beam evaporation, thermal evaporation or magnetron sputtering process to obtain the prepared pseudo-self-aligned p-type gallium nitride gate high electron mobility transistor.

[0109] Among them, the alternative process flow is shown in Figure 12 , and the specific steps are as follows: Figure 6 , and the specific steps are as follows:

[0110] Step 1: Selecting an epitaxial wafer with formed substrate, buffer layer, GaN channel layer, AlGaN barrier layer and p-GaN cap layer.

[0111] Step 2: Mesa isolation of the epitaxial wafer with formed substrate, buffer layer, GaN channel layer, AlGaN barrier layer and p-GaN cap layer.

[0112] Step 3: Surface treatment of the device after mesa isolation.

[0113] Step 4: Using the double-layer mask material with the "T" shape of wide top and narrow bottom, the gate region is protected and the p-GaN cap layer is etched to remove the p-GaN cap layer in the non-gate region.

[0114] Step 5: Surface treatment of the device without removing or damaging the gate mask material.

[0115] Step 6: Deposition of the passivation layer on the basis of the gate mask material by PVD or CVD, and due to the narrower mask layer below the p-GaN gate, the passivation layer can partially deposit on the surface of the p-GaN gate, achieving better passivation effect.

[0116] Step 7: Remove the mask material of the gate region by lift-off.

[0117] Step 8: Deposit a gate dielectric layer by PVD or CVD to obtain better passivation and voltage resistance effect for the device gate.

[0118] Step 9: Etch the dielectric layer and passivation layer to expose the contact area of the source and drain electrodes.

[0119] Step 10: Evaporate the gate contact metal on the gate electrode region window by electron beam evaporation, thermal evaporation or magnetron sputtering process to obtain the prepared pseudo self-aligned p-type gallium nitride gate high electron mobility transistor.

[0120] In which, the alternative process flow is shown in Figure 13 , and the specific steps are as follows: Figure 7 , and the specific steps are as follows:

[0121] Step 1: Select an epitaxial wafer with formed substrate, buffer layer, GaN channel layer, AlGaN barrier layer and p-GaN cap layer.

[0122] Step 2: Perform mesa isolation on the epitaxial wafer with formed substrate, buffer layer, GaN channel layer, AlGaN barrier layer and p-GaN cap layer.

[0123] Step 3: Perform surface treatment on the device after completing mesa isolation.

[0124] Step 4: Use a double-layer mask material with a "T" shape that is wide at the top and narrow at the bottom to protect the gate region and etch the p-GaN cap layer to remove the p-GaN cap layer in the non-gate region.

[0125] Step 5: Remove the upper etching mask layer.

[0126] Step 6: Perform surface treatment on the device without removing or damaging the gate mask material.

[0127] Step 7: Deposit a passivation layer on the basis of the gate mask material by PVD or CVD, and due to the narrower mask layer below the p-GaN gate, the passivation layer can partially deposit on the surface of the p-GaN gate, achieving better passivation effect.

[0128] Step 8: Remove the mask material of the gate region by lift-off.

[0129] Step 9: Deposit a gate dielectric layer by PVD or CVD to obtain better passivation and voltage resistance effect for the device gate.

[0130] Step 10: etching the passivation layer to expose the contact area of the source and drain electrodes.

[0131] Step 11: evaporating the gate contact metal on the gate electrode area window by electron beam evaporation, thermal evaporation or magnetron sputtering process to obtain a prepared pseudo self-aligned p-type gallium nitride gate high electron mobility transistor.

[0132] In summary, the present application has the following technical effects:

[0133] On the basis of the conventional p-GaN gate HEMT, after etching the pGaN, the etching mask layer is not removed, and a passivation layer is directly epitaxially grown. After the growth of the passivation layer, the epitaxially grown passivation layer is selectively stripped through the mask material, and the pGaN cap layer is exposed to realize the pseudo self-alignment of the gate. Since the gate of the pseudo self-alignment process can be deposited after the ohmic contact, it is compatible with the high-temperature annealing process of the interface state repair and the ohmic contact, so it has very good current density and dynamic characteristics, and can greatly reduce the process complexity.

[0134] The technical features of the above embodiments can be combined in any manner. To make the description concise, not all possible combinations of the technical features in the above embodiments are described, however, as long as the combinations of the technical features do not exist contradictions, they should be considered as the scope of the present application.

[0135] The principles and implementation modes of the present application are described by using specific examples in this paper, and the above embodiments are only used to help understand the method of the present application and its core idea; at the same time, for those skilled in the art, according to the idea of the present application, the specific implementation mode and application range will be changed. In summary, the content of the present application should not be understood as a limitation.

Claims

1. A method for fabricating a pseudo-self-aligned p-type gallium nitride gate high electron mobility transistor, characterized in that, include: An epitaxial wafer with a pre-formed substrate, buffer layer, GaN channel layer, AlGaN barrier layer, and p-GaN cap layer is selected. Mesa isolation is performed on the epitaxial wafer that has formed a substrate, buffer layer, GaN channel layer, AlGaN barrier layer and p-GaN cap layer; Perform surface treatment on the devices that have completed the mezzanine isolation; Using a mask material, the p-GaN cap layer is etched to expose the contact area between the source and drain electrodes; Surface treatment of the device without removing or damaging the gate mask material; A passivation layer is deposited on the basis of the gate mask material using PVD or CVD. Remove the mask material from the gate region via lift-off; The n-type ohmic contact metal is deposited on the drain and source electrode region windows using electron beam evaporation, thermal evaporation or magnetron sputtering processes, and then the source and drain electrodes are formed by high-temperature annealing. The gate contact metal is evaporated on the gate electrode region window using electron beam evaporation, thermal evaporation or magnetron sputtering processes to obtain a pseudo-self-aligned p-type gallium nitride gate high electron mobility transistor.

2. The method of claim 1, wherein the method further comprises: forming a p-type GaN layer on the n-type GaN layer; forming a p-type contact layer on the p-type GaN layer; forming a p-type contact on the p-type contact layer; and forming a p-type gate on the p-type GaN layer. The surface treatment is one of acid treatment, alkali treatment, or alternating acid and alkali treatment.

3. The method of claim 1, wherein the method further comprises: forming a p-type GaN layer on the n-type GaN layer; forming a p-type contact layer on the p-type GaN layer; forming a p-type contact on the p-type contact layer; and forming a p-type gate on the p-type GaN layer. The n-type ohmic contact metal is Ti / Al, Ti / Al / Ni / Au, or Ti / Al / Ti / Au.

4. A pseudo self-aligned p-type GaN-gate high electron mobility transistor, prepared by the method of claim 1, characterized in that, The pseudo-self-aligned p-type gallium nitride gate high electron mobility transistor includes: a substrate, a buffer layer, a GaN channel layer, an AlGaN barrier layer, a p-GaN cap layer, a passivation layer, a gate, a source, and a drain; The buffer layer covers the substrate; the GaN channel layer covers the buffer layer; the AlGaN barrier layer covers the GaN channel layer; the AlGaN barrier layer has a source and a drain at both ends; the p-GaN cap layer is located above the AlGaN barrier layer and is not connected to the source and drain; the passivation layer is located above the AlGaN barrier layer and part of the p-GaN cap layer; the gate is located above the p-GaN cap layer and part of the passivation layer.

5. The pseudo-self-aligned p-GaN gate high electron mobility transistor of claim 4, wherein, The substrate is one of a silicon substrate, a sapphire substrate, a silicon carbide substrate, or a self-supporting gallium nitride substrate.

6. The pseudo-self-aligned p-GaN gate high electron mobility transistor of claim 4, wherein, The buffer layer consists of a gallium nitride layer doped with iron or carbon, or an AlN / GaN superlattice structure.

7. The pseudo-self-aligned p-GaN gate high electron mobility transistor of claim 4, wherein the p-GaN gate is formed on the p-GaN layer. At the interface between the AlGaN barrier layer and the GaN channel layer, a two-dimensional electron gas is generated on the side near the GaN channel layer through piezoelectric polarization and spontaneous polarization effects.

8. The pseudo-self-aligned p-type GaN gate high electron mobility transistor of claim 4, wherein, The p-GaN cap layer is used to suppress the generation of 2DEG at the AlGaN / GaN interface through the piezoelectric polarization and spontaneous polarization effects at the GaN / AlGaN interface and the p-type doping of the p-GaN cap layer itself.

9. The pseudo-self-aligned p-type GaN gate high electron mobility transistor of claim 5, wherein, The contact between the p-GaN cap layer and the AlGaN barrier layer includes an ohmic contact, a Schottky contact, and a dielectric layer isolation.

10. The pseudo-self-aligned p-GaN gate high electron mobility transistor of claim 4, wherein, The passivation layer is made of one of silicon nitride, aluminum nitride, aluminum oxide, magnesium oxide, or silicon oxide.

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