SiC device with terminal ohmic contact arranged at intervals and preparation method
By adopting a spacing-arranged ohmic contact layout design on the top surface of the Pwell main junction of the terminal area of the SiC MOSFET device, the problem of the increase in drain-source parasitic capacitance Cds caused by the grounding of the Pwell main junction is solved, and the device's reverse voltage withstandability and switching are improved performance.
Patent Information
- Application Number
- CN202411544375.4
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-10-31
- Publication Date
- 2025-02-11
AI Technical Summary
When the existing SiC MOSFET devices are grounded in the terminal area Pwell main junction, the drain-source parasitic capacitor Cds will be added, affecting the switching performance of the device.
The ohmic contact layout is designed with interval arrangement on the top surface of the Pwell main junction of the terminal area of the SiC MOSFET device, reducing the ohmic contact area and thus reducing the drain-source parasitic capacitance Cds.
Through the interval arrangement of ohmic contact design, the grounding of the Pwell main junction is achieved, the reverse voltage withstandability of the device is improved, and the drain-source parasitic capacitance Cds is reduced, thereby improving the switching performance of the device.
Smart Images
Figure CN119421437A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the field of semiconductor technology, and in particular to a SiC device with terminal ohmic contacts arranged at intervals and a preparation method thereof. Background Art
[0002] The third generation of wide bandgap semiconductor materials are mainly silicon carbide (SiC) and gallium nitride (GaN). The switching performance of GaN power devices is very excellent, and its switching frequency can reach megahertz. However, since GaN power devices in the industry are all horizontal structures, it is difficult to achieve high voltage. Currently, GaN power devices are mainly low voltage. Although SiC power devices cannot reach the switching frequency of GaN, SiC MOSFET can simultaneously have excellent comprehensive performance such as high withstand voltage, low conduction loss, and high switching frequency. Especially in the field of high voltage, it has begun to gradually replace Si IGBT devices.
[0003] The SiC MOSFET device structure consists of a source region and a terminal region, where the source region serves as the current path of the device, while the terminal region serves to improve the reverse voltage withstand capability of the device during the blocking process, ensuring that the device will not be damaged during system applications. At present, in order to further improve the reverse voltage withstand capability of SiCMOSFET devices, an ohmic contact is prepared on the top surface of the Pwell main junction in the terminal region of the device to achieve grounding of the Pwell main junction. However, grounding the Pwell main junction will also have a negative impact, which will increase the drain-source parasitic capacitance Cds of the device. The increase in Cds will affect the switching performance of the device. Therefore, how to achieve grounding of the Pwell main junction in the terminal region of the device while reducing the drain-source parasitic capacitance Cds, so that the SiC MOSFET device can perform better performance, is a technical problem that needs to be solved. Summary of the invention
[0004] In view of the above problems, the present invention provides a SiC device with terminal ohmic contacts arranged at intervals and a preparation method thereof, which reduces the drain-source parasitic capacitance Cds caused by the grounding of the main junction Pwell in the terminal region of the device and improves the reverse withstand voltage capability of the device.
[0005] The technical solution of the present invention is: A method for preparing a SiC device with terminal ohmic contacts arranged at intervals comprises the following steps: S100, epitaxially growing a SiC Drift layer on the SiC Sub layer, and ion implanting on the top surface thereof to form a Pwell region; S200, forming NP region, PP region and JTE region on the top surface of the Pwell region by implantation in sequence; S300, a gate oxide layer and a field oxide layer are sequentially grown on the top surface of the SiC Drift layer; S400, forming a Poly layer on the top surface of the gate oxide layer and the field oxide layer as a gate electrode path of the device; S500, forming an isolation dielectric layer on the top surface of the SiC Drift layer, the NP region and the Poly layer to isolate the gate electrode and the source electrode of the device to avoid short circuit between the two; S600, forming an ohmic contact alloy layer on the top surfaces of the NP region and the PP region; S700, forming a front electrode metal layer above the device to serve as a source electrode and a gate electrode of the device.
[0006] Specifically, the doping concentration of the SiC Sub layer in step S100 is 1E19 cm -2 , the doping concentration of SiC Drift layer is 5E16-1.2E16cm -2 .
[0007] Specifically, in step S200, the bottom depth of the Pwell region is 1um-1.2um, and the doping concentration is 1E17-3E18cm -2 .
[0008] Specifically, in step S200, the bottom depth of the NP region is 0.3um-0.6um, and the doping concentration is 1E18-1E19cm -2 .
[0009] Specifically, in step S200, the bottom depth of the PP region is 0.5um-1um, and the doping concentration is 1E18-1E19cm -2 .
[0010] Specifically, in step S200, the bottom depth of the JTE region is 0.5um-1um, and the doping concentration is 1E17-1E18cm -2 .
[0011] Specifically, in step S300 , the thickness of the gate oxide layer is 40 nm-60 nm.
[0012] Specifically, in step S300, the thickness of the field oxide layer is 0.8um-1.2um.
[0013] Specifically, in step S400, the thickness of the deposited Poly layer is 0.5um-1um.
[0014] A SiC device with terminal ohmic contacts arranged at intervals, comprising a SiC Sub layer and a SiC Drift layer arranged in sequence from bottom to top; The SiC Drift layer is provided with: A Pwell region is provided, each extending downward from the top surface of the SiC Drift layer at intervals and having a spacing from the bottom surface of the SiC Drift layer (2); An NP region, extending downward from the top surface of the Pwell region of the source region, and having a spacing from the bottom surface of the Pwell region; There are several PP regions, each extending downward from the top surface of the Pwell region; the PP region in the source region is connected to the NP region; A JTE region, located in the terminal region, extending downward from the top surface of the SiC Drift layer and connected to the PP region; The gate oxide layer is provided with several gate oxide layers, the gate oxide layer of the source region is respectively connected to the NP region, the Pwell region and the SiC Drift layer; the gate oxide layer of the terminal region is respectively connected to the PP region and the Pwell region; A field oxide layer connected to the side of the gate oxide layer in the terminal region, and a bottom surface of the field oxide layer connected to the JTE region and the SiCDrift layer respectively; A Poly layer is provided, wherein the Poly layer in the source region is arranged on the top surface of the gate oxide layer, and the Poly layer in the terminal region is arranged on the top surface of the gate oxide layer and the field oxide layer; An isolation dielectric layer is disposed on the top surface of the Poly layer, with its side extending downward, and is respectively connected to the NP region, the Pwell region of the source region, the PP region of the source region, and the SiC Drift layer; The ohmic contact alloy layer is provided with a plurality of layers, which are spaced apart and arranged on the top surfaces of the PP region and the NP region of the terminal and the top surface of the PP region of the source region; Front electrode metal layer, set on the top of the device.
[0015] The present invention adopts an ohmic contact layout design with interval arrangement on the top surface of the Pwell main junction in the terminal area of the SiC MOSFET device. Since the size of the drain-source parasitic capacitance Cds depends on the ohmic contact area, the ohmic contacts arranged at intervals can greatly reduce the contact area, thereby reducing the drain-source parasitic capacitance Cds caused by the grounding of the Pwell main junction in the terminal area of the device, while improving the reverse withstand voltage capability of the device and reducing the impact of the drain-source parasitic capacitance Cds on the switching performance. BRIEF DESCRIPTION OF THE DRAWINGS
[0016] Figure 1 1 is a top view of the SiC MOSFET device of the present invention (the Pwell region 3, NP region 4, PP region 5, JTE region 6, gate oxide layer 7, field oxide layer 8, Poly layer 9, and front electrode metal layer 12 are hidden in the figure); Figure 2 yes Figure 1 The structural diagram of the AA section along the X direction; Figure 3 yes Figure 1 The structural diagram of the BB section along the X direction; In the figure, 1 is SiC Sub layer, 2 is SiCDrift layer, 3 is Pwell region, 4 is NP region, 5 is PP region, 6 is JTE region, 7 is gate oxide layer, 8 is field oxide layer, 9 is Poly layer, 10 is isolation dielectric layer, 11 is ohmic contact alloy layer, and 12 is front electrode metal layer. DETAILED DESCRIPTION
[0017] The present invention is described in detail below in conjunction with specific practical cases. Examples of the embodiments are shown in the accompanying drawings, and the schematic implementation methods of the present invention and their descriptions are only used to explain the present invention and are not intended to limit the present invention.
[0018] In the description of the present invention, it should be understood that the terms "upper", "lower", "left", "right", "vertical", "horizontal", etc. indicate positions or positional relationships based on the positions or positional relationships shown in the drawings, and are only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific position, be constructed and operated in a specific position, and therefore cannot be understood as limiting the present invention. In the description of the present invention, unless otherwise specified, "plurality" means two or more.
[0019] In the description of the present invention, it should be noted that, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection, or it can be indirectly connected through an intermediate medium, or it can be the internal communication of two components. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.
[0020] A method for preparing a SiC device with terminal ohmic contacts arranged at intervals comprises the following steps: S100, epitaxially growing a SiC Drift layer 2 on the SiC Sub layer 1; The doping concentration of the SiC Sub layer 1 in step S100 is 1E19 cm -2 , the doping concentration of SiC Drift layer 2 is 5E16-1.2E16cm -2 .
[0021] S200, forming a plurality of Pwell regions 3 spaced apart on the top surface of the SiC Drift layer 2 by Al ion implantation; The bottom depth of the Pwell region 3 in step S200 is 1um-1.2um, and the doping concentration is 1E17-3E18cm -2 .
[0022] S300, forming an NP region 4 by N ion implantation on the top surface of the Pwell region 3 at the source region position; The bottom depth of the NP region 4 in step S300 is 0.3um-0.6um, and the doping concentration is 1E18-1E19cm -2 .
[0023] S400, forming a PP region 5 on the top surface of the Pwell region 3 by Al ion implantation; the PP region 5 at the source region position is connected to the NP region 4; The bottom depth of the PP region 5 in step S400 is 0.5um-1um, and the doping concentration is 1E18-1E19cm -2 .
[0024] S500, forming a JTE region 6 on the top surface of the SiC Drift layer 2 by Al ion implantation, the JTE region 6 is connected to the Pwell region 3 at the terminal region position, and the JTE region 6 serves as a protection structure for the device terminal to improve the reverse withstand voltage capability of the device; The bottom depth of the JTE region 6 in step S500 is 0.5um-1um, and the doping concentration is 1E17-1E18cm -2 .
[0025] S600, the Pwell region 3, the NP region 4, the PP region 5 and the JTE region 6 are activated and formed by high temperature ion activation; The high temperature ion activation temperature in step S600 ranges from 1600°C to 1700°C.
[0026] S700, forming a gate oxide layer 7 on the top surface of the SiC Drift layer 2 by dry oxygen oxidation; The thickness of the gate oxide layer 7 in step S700 is 40 nm-60 nm.
[0027] S800, forming a field oxide layer 8 on the top surface of the SiC Drift layer 2 by oxide deposition; The thickness of the field oxide layer 8 in step S800 is 0.8 um-1.2 um.
[0028] S900, forming a Poly layer 9 on the top surface of the gate oxide layer 7 and the field oxide layer 8 by polysilicon Poly deposition, the Poly layer 9 is used as a gate electrode path of the device; The thickness of the deposited Poly layer 9 in step S900 is 0.5um-1um.
[0029] S1000, forming an isolation dielectric layer 10 on the top surfaces of the SiC Drift layer 2, the NP region 4 and the Poly layer 9 by oxide deposition. The isolation dielectric layer 10 is used to isolate the gate electrode and the source electrode of the device to prevent the two from being short-circuited; S1100, forming an ohmic contact alloy layer 11 on the top surfaces of the NP region 4 and the PP region 5 by sputtering Ni metal and then performing rapid thermal annealing; The Ni metal sputtering thickness in step S1100 is 0.1um-0.3um.
[0030] S1200, forming a front electrode metal layer 12 on the device by sputtering Ti and AlCu metals, the front electrode metal layer 12 is used as a source electrode and a gate electrode of the device; The thickness of the Ti metal in step S1200 is 0.1um-0.3um, and the thickness of the AlCu metal is 3um-5um.
[0031] A SiC device with terminal ohmic contacts arranged at intervals, comprising a SiC Sub layer 1 and a SiC Drift layer 2 arranged in sequence from bottom to top; The SiC Drift layer 2 is provided with: Pwell regions 3 are provided, each extending downward from the top surface of the SiC Drift layer 2 at intervals, and having a spacing from the bottom surface of the SiC Drift layer 2; NP region 4, extending downward from the top surface of the Pwell region 3 of the source region, and having a spacing from the bottom surface of the Pwell region 3; There are several PP regions 5, each extending downward from the top surface of the Pwell region 3; the PP region 5 in the source region is connected to the NP region 4; A JTE region 6, located in the terminal region, extending downward from the top surface of the SiC Drift layer 2 and connected to the PP region 5; The gate oxide layer 7 is provided with several gate oxide layers, the gate oxide layer 7 in the source region is respectively connected to the NP region 4, the Pwell region 3 and the SiC Drift layer 2; the gate oxide layer 7 in the terminal region is respectively connected to the PP region 5 and the Pwell region 3; A field oxide layer 8 is connected to the side of the gate oxide layer 7 in the terminal region, and the bottom surface of the field oxide layer 8 is respectively connected to the JTE region 6 and the SiC Drift layer 2; Poly layer 9, provided with a plurality of layers, the Poly layer 9 in the source region is arranged on the top surface of the gate oxide layer 7, and the Poly layer 9 in the terminal region is arranged on the top surface of the gate oxide layer 7 and the field oxide layer 8; An isolation dielectric layer 10 is disposed on the top surface of the Poly layer 9, with the side portion extending downward, and is respectively connected to the NP region 4, the Pwell region 3 of the source region, the PP region 5 of the source region, and the SiC Drift layer 2; The ohmic contact alloy layer 11 is provided with a plurality of layers, which are spaced apart and arranged at the top surfaces of the PP region 5 and the NP region 4 of the terminal and the top surface of the PP region 5 of the source region; The front electrode metal layer 12 is arranged on the top of the device.
[0032] The bottom surface of the front electrode metal layer 12 at the terminal area is connected to the ohmic contact alloy layer 11 and the isolation dielectric layer 10 respectively; The bottom surface of the front electrode metal layer 12 at the terminal area passes through the isolation dielectric layer 10 and is connected to the Poly layer 9 .
[0033] At present, the industry prepares ohmic contacts on the top surface of the Pwell main junction in the terminal area of the SiC MOSFET device to achieve Pwell main junction grounding, which can further improve the reverse voltage withstand capability of the device during the blocking process. However, the negative impact of Pwell main junction grounding is that it will increase the drain-source parasitic capacitance Cds of the device. The increase in Cds will reduce the switching performance of the device. Therefore, the present invention is to Figure 1 The structure shown in the figure greatly reduces the area of the ohmic contacts by arranging the ohmic contacts on the top surface of the Pwell main junction in the terminal area in an intermittent layout design. The benefit brought is that it not only realizes the grounding of the Pwell main junction to improve the voltage resistance, but also reduces the drain-source parasitic capacitance Cds, thereby minimizing the influence of Cds on the switching performance of the device.
Claims
1. A method for preparing a SiC device with terminal ohmic contacts arranged at intervals, characterized in that: The steps include: S100, epitaxially growing a SiC Drift layer (2) on the SiC Sub layer (1), and ion implanting on the top surface thereof to form a Pwell region (3); S200, forming an NP region (4), a PP region (5) and a JTE region (6) on the top surface of the Pwell region (3) by injection in sequence; S300, sequentially growing a gate oxide layer (7) and a field oxide layer (8) on the top surface of the SiC Drift layer (2); S400, forming a Poly layer (9) on the top surface of the gate oxide layer (7) and the field oxide layer (8) to serve as a gate electrode path of the device; S500, forming an isolation dielectric layer (10) on the top surfaces of the SiC Drift layer (2), the NP region (4) and the Poly layer (9) to isolate the gate electrode and the source electrode of the device to prevent the two from being short-circuited; S600, forming an ohmic contact alloy layer (11) on the top surfaces of the NP region (4) and the PP region (5); S700, forming a front electrode metal layer (12) above the device to serve as a source electrode and a gate electrode of the device.
2. The method for preparing a SiC device with terminal ohmic contacts arranged at intervals according to claim 1, characterized in that: The doping concentration of the SiC Sub layer (1) in step S100 is 1E19 cm -2 , the doping concentration of the SiC Drift layer (2) is 5E16-1.2E16cm -2 .
3. The method for preparing a SiC device with terminal ohmic contacts arranged at intervals according to claim 1, characterized in that: In step S200, the bottom depth of the Pwell region (3) is 1um-1.2um, and the doping concentration is 1E17-3E18cm -2 .
4. The method for preparing a SiC device with terminal ohmic contacts arranged at intervals according to claim 1, characterized in that: In step S200, the bottom depth of the NP region (4) is 0.3um-0.6um, and the doping concentration is 1E18-1E19cm -2 .
5. The method for preparing a SiC device with terminal ohmic contacts arranged at intervals according to claim 1, characterized in that: In step S200, the bottom depth of the PP region (5) is 0.5um-1um, and the doping concentration is 1E18-1E19cm -2 .
6. The method for preparing a SiC device with terminal ohmic contacts arranged at intervals according to claim 1, characterized in that: In step S200, the bottom depth of the JTE region (6) is 0.5um-1um, and the doping concentration is 1E17-1E18cm -2 .
7. The method for preparing a SiC device with terminal ohmic contacts arranged at intervals according to claim 1, characterized in that: In step S300, the thickness of the gate oxide layer (7) is 40nm-60nm.
8. The method for preparing a SiC device with terminal ohmic contacts arranged at intervals according to claim 1, characterized in that: In step S300, the thickness of the mid-oxygen layer (8) is 0.8um-1.2um.
9. The method for preparing a SiC device with terminal ohmic contacts arranged at intervals according to claim 1, characterized in that: In step S400, the Poly layer (9) is deposited to a thickness of 0.5 um-1 um.
10. A SiC device with terminal ohmic contacts arranged at intervals, prepared by the method for preparing a SiC device with terminal ohmic contacts arranged at intervals according to any one of claims 1 to 9, characterized in that: It includes a SiC Sub layer (1) and a SiC Drift layer (2) arranged sequentially from bottom to top; The SiC Drift layer (2) is provided with: The Pwell region (3) is provided with a plurality of Pwell regions, each extending downward from the top surface of the SiC Drift layer (2) at intervals and having a spacing from the bottom surface of the SiC Drift layer (2); An NP region (4) extending downward from the top surface of the Pwell region (3) of the source region and having a spacing from the bottom surface of the Pwell region (3); A plurality of PP regions (5) are provided, each extending downward from the top surface of the Pwell region (3); the PP region (5) in the source region is connected to the NP region (4); A JTE region (6), located in the terminal region, extending downward from the top surface of the SiC Drift layer (2) and connected to the PP region (5); The gate oxide layer (7) is provided with a plurality of gate oxide layers, wherein the gate oxide layer (7) in the source region is respectively connected to the NP region (4), the Pwell region (3) and the SiCDrift layer (2); and the gate oxide layer (7) in the terminal region is respectively connected to the PP region (5) and the Pwell region (3); A field oxide layer (8) connected to the side of the gate oxide layer (7) in the terminal region, and a bottom surface of the field oxide layer (8) connected to the JTE region (6) and the SiC Drift layer (2) respectively; A plurality of Poly layers (9) are provided, wherein the Poly layer (9) in the source region is arranged on the top surface of the gate oxide layer (7), and the Poly layer (9) in the terminal region is arranged on the top surfaces of the gate oxide layer (7) and the field oxide layer (8); An isolation dielectric layer (10) is arranged on the top surface of the Poly layer (9), with the side portion extending downward and connected to the NP region (4), the Pwell region (3) of the source region, the PP region (5) of the source region, and the SiC Drift layer (2) respectively; The ohmic contact alloy layer (11) is provided with a plurality of layers, which are spaced apart and arranged on the top surfaces of the PP region (5) and the NP region (4) at the terminal and the top surface of the PP region (5) in the source region; A front electrode metal layer (12) is arranged on the top of the device.