Semiconductor device and method for manufacturing the same

Abstract

The present invention provides a semiconductor device and a manufacturing method thereof, wherein the semiconductor device comprises: a substrate; two body regions formed in the substrate, a groove formed in the substrate between the two body regions; a second epitaxial layer formed on the substrate, the second epitaxial layer extending from part of the body region to the side wall of the groove; a source region formed in the body region, the source region extending from a side of the second epitaxial layer away from the groove to below the second epitaxial layer, the doping type of the substrate, the second epitaxial layer, and the source region being opposite to the doping type of the body region; a gate oxide layer formed on the surface of the second epitaxial layer and the bottom wall of the groove; a gate layer formed on the gate oxide layer, the gate layer extending from the gate oxide layer above the second epitaxial layer to the gate oxide layer on the side wall of the groove. The technical solution of the present invention enables to improve the device performance.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor integrated circuit manufacturing, and in particular to a semiconductor device and a manufacturing method thereof. Background Art

[0002] Compared with silicon materials, silicon carbide materials have a higher bandgap width, a higher critical breakdown electric field, a higher electron saturation drift velocity and a higher thermal conductivity.

[0003] However, silicon carbide devices have the following problems:

[0004] (1) Silicon carbide power devices have the problem of high turn-on loss in high-frequency applications;

[0005] (2) The on-resistance of planar silicon carbide MOS devices has not reached the ideal level to a certain extent, which restricts the current capability of the device;

[0006] (3) Planar silicon carbide MOS devices often require the use of PN junction body diodes for freewheeling in applications. However, when the body diode is bipolarly turned on, the bipolar degradation effect of silicon carbide will occur, reducing the reliability of the device.

[0007] (4) Due to the wide bandgap of silicon carbide, the turn-on voltage of the body diode is high, resulting in high follow-on loss of the device.

[0008] Therefore, the above problems need to be solved to improve the performance of silicon carbide devices. Summary of the invention

[0009] An object of the present invention is to provide a semiconductor device and a method for manufacturing the same, so as to improve the performance of the device.

[0010] To achieve the above object, the present invention provides a semiconductor device, comprising:

[0011] substrate;

[0012] Two body regions are formed in the substrate, and a groove is formed in the substrate between the two body regions;

[0013] A second epitaxial layer is formed on the substrate, wherein the second epitaxial layer extends from a portion of the body region to a sidewall of the groove;

[0014] a source region formed in the body region, the source region extending from a side of the second epitaxial layer away from the groove to below the second epitaxial layer, and the doping type of the substrate, the second epitaxial layer, and the source region is opposite to the doping type of the body region;

[0015] a gate oxide layer formed on a surface of the second epitaxial layer and a bottom wall of the groove;

[0016] A gate layer is formed on the gate oxide layer, and the gate layer extends from the gate oxide layer above the second epitaxial layer to the gate oxide layer on the sidewall of the groove.

[0017] Optionally, the base includes a substrate and a first epitaxial layer from bottom to top, and the body region is formed in the first epitaxial layer.

[0018] Optionally, the substrate and the second epitaxial layer are made of silicon carbide.

[0019] Optionally, a bottom wall of the groove is higher than a bottom surface of the body region.

[0020] Optionally, the doping concentration of the second epitaxial layer is greater than the doping concentration of the substrate and less than the doping concentration of the source region.

[0021] Optionally, the semiconductor device further includes:

[0022] A doping region is formed in the substrate at the bottom wall of the groove, the gate oxide layer covers the doping region, the doping type of the doping region is the same as the doping type of the body region, and the doping concentration of the doping region is greater than or equal to the doping concentration of the body region.

[0023] Optionally, the semiconductor device further includes:

[0024] An insulating dielectric layer is formed on the substrate, the insulating dielectric layer fills the groove, and the insulating dielectric layer covers the gate oxide layer and the gate layer;

[0025] A conductive structure is formed on the source region and the body region of the second epitaxial layer at a side away from the groove.

[0026] The present invention also provides a method for manufacturing a semiconductor device, comprising:

[0027] providing a substrate;

[0028] forming two body regions in the substrate, and forming a groove in the substrate between the two body regions;

[0029] forming a second epitaxial layer on the substrate, wherein the second epitaxial layer extends from a portion of the body region to a sidewall of the recess;

[0030] forming a source region in the body region, wherein the source region extends from a side of the second epitaxial layer away from the groove to below the second epitaxial layer, and the doping type of the substrate, the second epitaxial layer, and the source region is opposite to the doping type of the body region;

[0031] forming a gate oxide layer on the surface of the second epitaxial layer and the bottom wall of the groove;

[0032] A gate layer is formed on the gate oxide layer, wherein the gate layer extends from the gate oxide layer above the second epitaxial layer to the gate oxide layer on the sidewall of the groove.

[0033] Optionally, the base includes a substrate and a first epitaxial layer from bottom to top, and the body region is formed in the first epitaxial layer.

[0034] Optionally, the substrate and the second epitaxial layer are made of silicon carbide.

[0035] Optionally, a bottom wall of the groove is higher than a bottom surface of the body region.

[0036] Optionally, the doping concentration of the second epitaxial layer is greater than the doping concentration of the substrate and less than the doping concentration of the source region.

[0037] Optionally, after forming the second epitaxial layer on the substrate and before forming the gate oxide layer on the surface of the second epitaxial layer and the bottom wall of the groove, the method for manufacturing the semiconductor device further includes:

[0038] A doping region is formed in the substrate at the bottom wall of the groove, wherein the doping type of the doping region is the same as the doping type of the body region, and the doping concentration of the doping region is greater than or equal to the doping concentration of the body region.

[0039] Optionally, the method for manufacturing the semiconductor device further includes:

[0040] forming an insulating dielectric layer on the substrate, wherein the insulating dielectric layer fills the groove and covers the gate oxide layer, the gate layer, and the source region and the body region of the second epitaxial layer away from the groove;

[0041] forming a contact hole in the insulating dielectric layer, wherein the contact hole exposes the source region and the body region of the second epitaxial layer on a side away from the groove;

[0042] A conductive structure is formed in the contact hole.

[0043] Compared with the prior art, the technical solution of the present invention has the following beneficial effects:

[0044] 1. The manufacturing method of the semiconductor device of the present invention comprises: a substrate; two body regions formed in the substrate, a groove is formed in the substrate between the two body regions; a second epitaxial layer formed on the substrate, the second epitaxial layer extends from part of the body region to the side wall of the groove; a source region formed in the body region, the source region extends from the side of the second epitaxial layer away from the groove to below the second epitaxial layer, and the doping type of the substrate, the second epitaxial layer, and the source region is opposite to the doping type of the body region; a gate oxide layer formed on the surface of the second epitaxial layer and the bottom wall of the groove; a gate layer formed on the gate oxide layer, the gate layer extends from the gate oxide layer above the second epitaxial layer to the gate oxide layer on the side wall of the groove. It is possible to reduce turn-on loss, reduce on-resistance, improve bipolar degradation effect, etc., thereby improving device performance.

[0045] 2. The semiconductor device of the present invention comprises: providing a substrate; forming two body regions in the substrate, and forming a groove in the substrate between the two body regions; forming a second epitaxial layer on the substrate, the second epitaxial layer extending from part of the body region to the side wall of the groove; forming a source region in the body region, the source region extending from the side of the second epitaxial layer away from the groove to below the second epitaxial layer, the doping type of the substrate, the second epitaxial layer, and the source region is opposite to the doping type of the body region; forming a gate oxide layer on the surface of the second epitaxial layer and the bottom wall of the groove; forming a gate layer on the gate oxide layer, the gate layer extending from the gate oxide layer above the second epitaxial layer to the gate oxide layer on the side wall of the groove. This makes it possible to reduce turn-on loss, reduce on-resistance, improve bipolar degradation effects, etc., thereby improving device performance. BRIEF DESCRIPTION OF THE DRAWINGS

[0046] Figure 1 is a schematic structural diagram of a semiconductor device according to an embodiment of the present invention;

[0047] Figure 2 is a flow chart of a method for manufacturing a semiconductor device according to an embodiment of the present invention;

[0048] Figure 3~Figure 13 yes Figure 2 FIG. 1 is a schematic diagram of a device in a method for manufacturing a semiconductor device according to an embodiment of the present invention.

[0049] Among them, Figure 1 to Figure 13 The reference numerals are described as follows:

[0050] 10-base; 101-substrate; 102-first epitaxial layer; 11-body region; 111-body contact region; 12-groove; 13-second epitaxial layer; 131-epitaxial material layer; 14-source region; 15-doped region; 16-gate oxide layer; 17-gate layer; 18-insulating dielectric layer; 181-contact hole; 19-conductive structure. DETAILED DESCRIPTION

[0051] In order to make the purpose, advantages and features of the present invention more clear, the semiconductor device and the manufacturing method thereof proposed by the present invention are further described in detail below. It should be noted that the drawings are all in a very simplified form and are not in precise proportions, which are only used to conveniently and clearly assist in explaining the purpose of the embodiments of the present invention.

[0052] An embodiment of the present invention provides a semiconductor device, comprising: a substrate; two body regions formed in the substrate, a groove formed in the substrate between the two body regions; a second epitaxial layer formed on the substrate, the second epitaxial layer extending from part of the body region to the side wall of the groove; a source region formed in the body region, the source region extending from a side of the second epitaxial layer away from the groove to below the second epitaxial layer, the doping types of the substrate, the second epitaxial layer, and the source region are opposite to the doping type of the body region; a gate oxide layer formed on the surface of the second epitaxial layer and the bottom wall of the groove; a gate layer formed on the gate oxide layer, the gate layer extending from the gate oxide layer above the second epitaxial layer to the gate oxide layer on the side wall of the groove.

[0053] See below Figure 1 Describe in detail the semiconductor device provided by this embodiment, Figure 1 Shown is a schematic diagram of a longitudinal cross-section of the device.

[0054] The base 10 includes a substrate 101 and a first epitaxial layer 102 from bottom to top.

[0055] The first epitaxial layer 102 serves as a drift region.

[0056] In one embodiment, the substrate 10 is made of silicon carbide.

[0057] The two body regions 11 are formed in the substrate 10 , and a groove 12 is formed in the substrate 10 between the two body regions 11 .

[0058] The body region 11 extends from a side of the first epitaxial layer 102 away from the substrate 101 into the first epitaxial layer 102 , and the groove 12 is formed in the first epitaxial layer 102 between two body regions 11 .

[0059] The region between the two body regions 11 may be a JFET (Junction Field Effect Transistor) region, and the depth of the JFET region is the same as the depth of the body region 11 , and the groove 12 is formed in the JFET region.

[0060] The groove 12 is spaced apart from the body region 11 by a distance, that is, the sidewall of the groove 12 is not in contact with the side surface of the body region 11 .

[0061] Preferably, the bottom wall of the groove 12 is higher than the bottom surface of the body region 11 , that is, the depth of the groove 12 is less than the depth of the body region 11 .

[0062] The second epitaxial layer 13 is formed on the substrate 10 , and the second epitaxial layer 13 extends from a portion of the body region 11 to a sidewall of the groove 12 .

[0063] In one embodiment, the second epitaxial layer 13 is made of silicon carbide.

[0064] The source region 14 is formed in the body region 11 , and the source region 14 extends from a side of the second epitaxial layer 13 away from the groove 12 to below the second epitaxial layer 13 . The doping types of the substrate 10 , the second epitaxial layer 13 , and the source region 14 are opposite to the doping type of the body region 11 .

[0065] The second epitaxial layer 13 between an upper side of the source region 14 close to the groove 12 and a bottom wall of the groove 12 is used to form a channel.

[0066] In one embodiment, the semiconductor device further includes: a body contact region 111, formed in the body region 11 on a side of the source region 14 away from the groove 12. The doping type of the body contact region 111 is the same as the doping type of the body region 11, the doping concentration of the body contact region 111 is greater than the doping concentration of the body region 11, and the body contact region 111 is used to lead out the body region 11.

[0067] Preferably, the doping concentration of the second epitaxial layer 13 is greater than the doping concentration of the substrate 10 and less than the doping concentration of the source region 14 .

[0068] The gate oxide layer 16 is formed on the surface of the second epitaxial layer 13 and the bottom wall of the groove 12 .

[0069] If the depletion layer below the gate oxide layer 16 at the bottom wall of the groove 12 and between the two body regions 11 (i.e., the depletion layer in the PN junction formed by the body region 11 and the substrate 10) cannot be completely depleted, the electric field will cause the gate oxide layer 16 at the bottom wall of the groove 12 to be broken down. Therefore, by forming the doping region 15 with the same doping type as the body region 11 in the substrate 10 at the bottom wall of the groove 12, the depletion layer below the gate oxide layer 16 at the bottom wall of the groove 12 can be completely depleted, thereby preventing the electric field from breaking down the gate oxide layer 16 at the bottom wall of the groove 12.

[0070] The gate layer 17 is formed on the gate oxide layer 16 , and the gate layer 17 extends from the gate oxide layer 16 above the second epitaxial layer 13 to the gate oxide layer 16 at the sidewall of the groove 12 .

[0071] Portions of the two gate layers 17 located on the bottom wall of the groove 12 are not connected, that is, the two gate layers 17 are split gates.

[0072] In one embodiment, the semiconductor device further includes: a doping region 15 formed in the substrate 10 at the bottom wall of the groove 12 , the gate oxide layer 16 covers the doping region 15 , and the doping type of the doping region 15 is the same as the doping type of the body region 11 .

[0073] In one embodiment, the doping concentration of the doping region 15 is greater than or equal to the doping concentration of the body region 11 , and the doping concentration of the doping region 15 is less than the doping concentration of the body contact region 111 .

[0074] In one embodiment, the doping type of the substrate 10 , the second epitaxial layer 13 and the source region 14 is N-type, and the doping type of the body region 11 , the body contact region 111 and the doping region 15 is P-type.

[0075] The semiconductor device further comprises:

[0076] An insulating dielectric layer 18 is formed on the substrate 10 , wherein the insulating dielectric layer 18 fills the groove 12 and covers the gate oxide layer 16 and the gate layer 17 ;

[0077] The conductive structure 19 is formed on the source region 14 and the body region 11 on the side of the second epitaxial layer 13 away from the groove 12 , and the conductive structure 19 is electrically connected to the source region 14 and the body region 11 . The conductive structure 19 may also extend onto the insulating dielectric layer 18 .

[0078] The conductive structure 19 may include an adhesive layer (not shown) and a metal layer (not shown), wherein the adhesive layer is formed on the inner wall of the contact hole where the conductive structure 19 is located, and the metal layer fills the contact hole. The adhesive layer and the metal layer also extend to the insulating dielectric layer 18 outside the contact hole.

[0079] If the body contact region 111 is formed in the body region 11 on the side of the source region 14 away from the groove 12, the contact hole exposes the source region 14 and the body contact region 111 on the side of the second epitaxial layer 13 away from the groove 12, and the conductive structure 19 is electrically connected to the source region 14 and the body contact region 111.

[0080] The semiconductor device further includes a drain (not shown) formed on a surface of the substrate 10 away from the groove 12 .

[0081] In the existing planar silicon carbide MOS device, after voltage is applied to the gate layer and the source region, the current path flows from the source region to the drain through the body region and the drift region in sequence; however, in the present invention, after voltage is applied to the gate layer 17 and the source region 14, Fig.13 In the direction of the arrow in FIG. 1 , the current path flows from the source region 14 to the drain through the second epitaxial layer 13 and the drift region (ie, the first epitaxial layer 102 ) in sequence.

[0082] In the existing planar silicon carbide MOS devices, the body diode composed of the body region and the drift region can only be turned on under a relatively high turn-on voltage Vsd (i.e., the voltage of the source region relative to the drain); in the present invention, since the second epitaxial layer 13 extending from part of the body region 11 to the side wall of the groove 12 is formed as a channel, when Vgs (i.e., the voltage of the gate layer 17 relative to the source region 14) is 0, a very small turn-on voltage Vsd (i.e., the voltage of the source region 14 relative to the drain) can turn on the forward current path, thereby avoiding the conduction of the body diode composed of the body region 11 and the drift region caused by high Vsd, which is equivalent to eliminating the body diode during module packaging, thereby saving the overall production cost and reducing the device's freewheeling loss.

[0083] Furthermore, if the body diode formed by the body region 11 and the drift region is turned on, the holes in the body region 11 (taking the doping type of the body region 11 as P type as an example) will be injected into the drift region, and due to the limitation of the epitaxial process, there will be a basal plane dislocation defect (BPD) in the drift region, and the holes will recombine with electrons in the basal plane dislocation defect, thereby releasing energy; the basal plane dislocation defect absorbs the energy released by the carrier recombination to form a stacking fault defect (SF), and the continuous conduction of the device will cause the stacking fault defect to continue to expand in the drift region. The existence of the stacking fault defect will increase the on-resistance and leakage current of the device, and the higher the density of the stacking fault defect, the greater the impact, that is, the bipolar degradation effect occurs. Therefore, in the present invention, by avoiding the conduction of the body diode, the bipolar degradation effect can be improved, thereby improving the reliability of the device.

[0084] If the groove 12 is not formed between the two body regions 11, that is, the substrate 10 between the two body regions 11 is not partially etched away, then a depletion layer will be formed between the two body regions 11 (located in the PN junction formed by the body region 11 and the substrate 10), and if the depletion layer is to be widened and reduced, it is necessary for the gate current to continuously charge Cgd (i.e., gate-drain capacitance) under a certain Vgs voltage, so there will be a plateau period during the turn-on process of the device; in the present invention, by forming the groove 12 between the two body regions 11, that is, etching away most of the substrate 10 between the two body regions 11, most of the depletion layer between the two body regions 11 is removed, thereby reducing the portion of the gate current used to charge the depletion layer in Cgd, so that the gate current is mainly used to charge Cgs (i.e., gate-source capacitance), that is, the plateau period is shortened, the device turn-on process is accelerated, and the turn-on loss of the device is reduced.

[0085] Furthermore, if the portions of the two gate layers 17 located above the bottom wall of the groove 12 are connected, a capacitor structure will be formed between the gate layer 17 and the drain electrode above the bottom wall of the groove 12, and this capacitor structure is a part of the Miller capacitance (i.e., gate-drain capacitance). Therefore, in the present invention, by forming a split gate, that is, the portions of the two gate layers 17 located above the bottom wall of the groove 12 are not connected, the capacitance value of the Miller capacitance can be reduced, and the capacitance value of the Miller capacitance is positively correlated with the turn-on loss, thereby further reducing the turn-on loss of the device.

[0086] In addition, by forming the groove 12 between the two body regions 11, most of the depletion layer between the two body regions 11 (that is, the depletion layer in the PN junction formed by the body region 11 and the substrate 10) is removed, thereby eliminating part of the on-resistance of the JFET region between the two body regions 11, that is, the on-resistance of the JFET region between the two body regions 11 is reduced, thereby reducing the overall on-resistance of the device and improving the current capability of the device.

[0087] If the doping concentration of the second epitaxial layer 13 is greater than the doping concentration of the substrate 10, the carrier mobility of the channel can be increased, thereby reducing the channel resistance, and the on-resistance of the accumulation layer in the substrate 10 directly below the gate layer 17 located on the side wall of the groove 12 can be reduced, so that the current can not only flow from the second epitaxial layer 13 on the side wall of the groove 12 toward the drain, but also diffuse from the area where the accumulation layer is located to flow toward the drain, that is, the flow path of the current becomes wider, so that the current can flow to the drain more quickly, thereby improving device performance.

[0088] In summary, the present invention provides a semiconductor device, comprising: a substrate; two body regions formed in the substrate, a groove formed in the substrate between the two body regions; a second epitaxial layer formed on the substrate, the second epitaxial layer extending from part of the body region to the sidewall of the groove; a source region formed in the body region, the source region extending from the side of the second epitaxial layer away from the groove to below the second epitaxial layer, the doping type of the substrate, the second epitaxial layer, and the source region is opposite to the doping type of the body region; a gate oxide layer formed on the surface of the second epitaxial layer and the bottom wall of the groove; a gate layer formed on the gate oxide layer, the gate layer extending from the gate oxide layer above the second epitaxial layer to the gate oxide layer on the sidewall of the groove. The semiconductor device provided by the present invention enables to improve the device performance.

[0089] An embodiment of the present invention provides a method for manufacturing a semiconductor device. Figure 2 ,from Figure 2 It can be seen that the method for manufacturing the semiconductor device includes:

[0090] Step S1, providing a substrate;

[0091] Step S2, forming two body regions in the substrate, and forming a groove in the substrate between the two body regions;

[0092] Step S3, forming a second epitaxial layer on the substrate, wherein the second epitaxial layer extends from a portion of the body region to a sidewall of the recess;

[0093] Step S4, forming a source region in the body region, wherein the source region extends from a side of the second epitaxial layer away from the groove to below the second epitaxial layer, and the doping type of the substrate, the second epitaxial layer, and the source region is opposite to the doping type of the body region;

[0094] Step S5, forming a gate oxide layer on the surface of the second epitaxial layer and the bottom wall of the groove;

[0095] Step S6, forming a gate layer on the gate oxide layer, wherein the gate layer extends from the gate oxide layer above the second epitaxial layer to the gate oxide layer on the sidewall of the groove.

[0096] See below Figure 3~Figure 13 The method for manufacturing the semiconductor device provided in this embodiment is described in detail. Figure 3~Figure 13 Shown is a schematic diagram of a longitudinal cross-section of the device.

[0097] Follow step S1, refer to Figure 3 , a substrate 10 is provided.

[0098] The base 10 includes a substrate 101 and a first epitaxial layer 102 from bottom to top.

[0099] The first epitaxial layer 102 serves as a drift region.

[0100] In one embodiment, the substrate 10 is made of silicon carbide.

[0101] According to step S2, refer to Figure 4~Figure 5 , two body regions 11 are formed in the substrate 10 , and a groove 12 is formed in the substrate 10 between the two body regions 11 .

[0102] The body region 11 extends from a side of the first epitaxial layer 102 away from the substrate 101 into the first epitaxial layer 102 , and the groove 12 is formed in the first epitaxial layer 102 between two body regions 11 .

[0103] The region between the two body regions 11 may be a JFET (Junction Field Effect Transistor) region, and the depth of the JFET region is the same as the depth of the body region 11 , and the groove 12 is formed in the JFET region.

[0104] The groove 12 is spaced apart from the body region 11 by a distance, that is, the sidewall of the groove 12 is not in contact with the side surface of the body region 11 .

[0105] The body region 11 is formed by photolithography and ion implantation processes, and the groove 12 is formed by photolithography and etching processes.

[0106] Among them, Figure 4~Figure 5 As shown, the body region 11 may be formed first, and then the groove 12 may be formed; or, the groove 12 may be formed first, and then the body region 11 may be formed.

[0107] Preferably, the bottom wall of the groove 12 is higher than the bottom surface of the body region 11 , that is, the depth of the groove 12 is less than the depth of the body region 11 .

[0108] According to step S3, refer to Figure 6~Figure 7 , a second epitaxial layer 13 is formed on the substrate 10 , wherein the second epitaxial layer 13 extends from a portion of the body region 11 to a sidewall of the recess 12 .

[0109] The step of forming the second epitaxial layer 13 on the substrate 10 may include: Figure 6 As shown, an epitaxial material layer 131 is formed on the substrate 10 by an epitaxial process, and the epitaxial material layer 131 covers the body region 11 and fills the groove 12; then, a photolithography and etching process is performed to remove a portion of the epitaxial material layer 131 on the body region 11 away from the groove 12 and a portion of the epitaxial material layer 131 in the groove 12, and the epitaxial material layer 131 on the side wall of the groove 12 and on the substrate 11 outside the groove 12 is retained as a second epitaxial layer 13.

[0110] In one embodiment, the second epitaxial layer 13 is made of silicon carbide.

[0111] According to step S4, refer to Figure 8 , forming a source region 14 in the body region 11, the source region 14 extending from a side of the second epitaxial layer 13 away from the groove 12 to below the second epitaxial layer 13, and the doping types of the substrate 10, the second epitaxial layer 13, and the source region 14 are opposite to the doping type of the body region 11.

[0112] The second epitaxial layer 13 between an upper side of the source region 14 close to the groove 12 and a bottom wall of the groove 12 is used to form a channel.

[0113] In one embodiment, after forming the second epitaxial layer 13 on the substrate 10 and before subsequently forming the gate oxide layer 16 on the surface of the second epitaxial layer 13 and the bottom wall of the groove 12, the method for manufacturing the semiconductor device further includes: forming a body contact region 111 in the body region 11 on a side of the source region 14 away from the groove 12. The doping type of the body contact region 111 is the same as the doping type of the body region 11, the doping concentration of the body contact region 111 is greater than the doping concentration of the body region 11, and the body contact region 111 is used to lead out the body region 11.

[0114] Preferably, the doping concentration of the second epitaxial layer 13 is greater than the doping concentration of the substrate 10 and less than the doping concentration of the source region 14 .

[0115] Preferably, Fig. 9 As shown, after forming the second epitaxial layer 13 on the substrate 10 and before subsequently forming a gate oxide layer 16 on the surface of the second epitaxial layer 13 and the bottom wall of the groove 12, the method for manufacturing the semiconductor device also includes: forming a doping region 15 in the substrate 10 at the bottom wall of the groove 12, and the doping type of the doping region 15 is the same as the doping type of the body region 11.

[0116] In one embodiment, the doping concentration of the doping region 15 is greater than or equal to the doping concentration of the body region 11 , and the doping concentration of the doping region 15 is less than the doping concentration of the body contact region 111 .

[0117] In one embodiment, the doping type of the substrate 10 , the second epitaxial layer 13 and the source region 14 is N-type, and the doping type of the body region 11 , the body contact region 111 and the doping region 15 is P-type.

[0118] The source region 14, the body contact region 111 and the doping region 15 may be formed in any order. The source region 14, the body contact region 111 and the doping region 15 may be formed by photolithography and ion implantation.

[0119] Furthermore, after the ion implantation processes corresponding to the body region 11 , the source region 14 , the body contact region 111 , and the doping region 15 are all completed, an annealing process is performed to perform post-implantation activation.

[0120] According to step S5, refer to Fig.10 , forming a gate oxide layer 16 on the surface of the second epitaxial layer 13 and the bottom wall of the groove 12 .

[0121] In one embodiment, the step of forming the gate oxide layer 16 may include: performing a thermal oxidation process to form an oxide layer (not shown), the oxide layer covering the body contact region 111, the source region 14, the surface of the second epitaxial layer 13 and the doped region 15 on the bottom wall of the groove 12; then, performing a photolithography and etching process to remove the oxide layer on the body contact region 111 and the source region 14, and the retained oxide layer serves as the gate oxide layer 16.

[0122] If the depletion layer below the gate oxide layer 16 at the bottom wall of the groove 12 and between the two body regions 11 (i.e., the depletion layer in the PN junction formed by the body region 11 and the substrate 10) cannot be completely depleted, the electric field will cause the gate oxide layer 16 at the bottom wall of the groove 12 to be broken down. Therefore, by forming the doping region 15 with the same doping type as the body region 11 in the substrate 10 at the bottom wall of the groove 12, the depletion layer below the gate oxide layer 16 at the bottom wall of the groove 12 can be completely depleted, thereby preventing the electric field from breaking down the gate oxide layer 16 at the bottom wall of the groove 12.

[0123] According to step S6, refer to Fig.11 , forming a gate layer 17 on the gate oxide layer 16 , wherein the gate layer 17 extends from the gate oxide layer 16 above the second epitaxial layer 13 to the gate oxide layer 16 on the sidewall of the groove 12 .

[0124] The gate layer 17 may be formed by deposition, photolithography and etching processes.

[0125] Portions of the two gate layers 17 located on the bottom wall of the groove 12 are not connected, that is, the two gate layers 17 are split gates.

[0126] After forming the gate layer 17 on the gate oxide layer 16, the method for manufacturing the semiconductor device further includes:

[0127] like Fig.12 As shown, an insulating dielectric layer 18 is formed on the substrate 10, the insulating dielectric layer 18 fills the groove 12, and the insulating dielectric layer 18 covers the gate oxide layer 16, the gate layer 17, and the source region 14 and the body region 11 of the second epitaxial layer 13 away from the groove 12;

[0128] like Fig.12 As shown, a contact hole 181 is formed in the insulating dielectric layer 18 , and the contact hole 181 exposes the source region 14 and the body region 11 of the second epitaxial layer 13 away from the groove 12 ;

[0129] like Fig.13 As shown, a conductive structure 19 is formed in the contact hole 181, and the conductive structure 19 is electrically connected to the source region 14 and the body region 11. The conductive structure 19 can also extend from the contact hole 181 to the insulating dielectric layer 18 outside the contact hole 181.

[0130] The conductive structure 19 may include an adhesive layer (not shown) formed on the inner wall of the contact hole 181 and a metal layer (not shown) filling the contact hole 181 . The adhesive layer and the metal layer also extend onto the insulating dielectric layer 18 outside the contact hole 181 .

[0131] If the body contact region 111 is formed in the body region 11 on the side of the source region 14 away from the groove 12, the contact hole 181 exposes the source region 14 and the body contact region 111 on the side of the second epitaxial layer 13 away from the groove 12, and the conductive structure 19 is electrically connected to the source region 14 and the body contact region 111.

[0132] The method for manufacturing the semiconductor device further includes: forming a drain (not shown) on a surface of the substrate 10 away from the groove 12 .

[0133] In the existing planar silicon carbide MOS device, after voltage is applied to the gate layer and the source region, the current path flows from the source region to the drain through the body region and the drift region in sequence; however, in the present invention, after voltage is applied to the gate layer 17 and the source region 14, Fig.13 In the direction of the arrow in FIG. 1 , the current path flows from the source region 14 to the drain through the second epitaxial layer 13 and the drift region (ie, the first epitaxial layer 102 ) in sequence.

[0134] In the existing planar silicon carbide MOS devices, the body diode composed of the body region and the drift region can only be turned on under a relatively high turn-on voltage Vsd (i.e., the voltage of the source region relative to the drain); in the present invention, since the second epitaxial layer 13 extending from part of the body region 11 to the side wall of the groove 12 is formed as a channel, when Vgs (i.e., the voltage of the gate layer 17 relative to the source region 14) is 0, a very small turn-on voltage Vsd (i.e., the voltage of the source region 14 relative to the drain) can turn on the forward current path, thereby avoiding the conduction of the body diode composed of the body region 11 and the drift region caused by high Vsd, which is equivalent to eliminating the body diode during module packaging, thereby saving the overall production cost and reducing the device's freewheeling loss.

[0135] Furthermore, if the body diode formed by the body region 11 and the drift region is turned on, the holes in the body region 11 (taking the doping type of the body region 11 as P type as an example) will be injected into the drift region, and due to the limitation of the epitaxial process, there will be a basal plane dislocation defect (BPD) in the drift region, and the holes will recombine with electrons in the basal plane dislocation defect, thereby releasing energy; the basal plane dislocation defect absorbs the energy released by the carrier recombination to form a stacking fault defect (SF), and the continuous conduction of the device will cause the stacking fault defect to continue to expand in the drift region. The existence of the stacking fault defect will increase the on-resistance and leakage current of the device, and the higher the density of the stacking fault defect, the greater the impact, that is, the bipolar degradation effect occurs. Therefore, in the present invention, by avoiding the conduction of the body diode, the bipolar degradation effect can be improved, thereby improving the reliability of the device.

[0136] If the groove 12 is not formed between the two body regions 11, that is, the substrate 10 between the two body regions 11 is not partially etched away, then a depletion layer will be formed between the two body regions 11 (located in the PN junction formed by the body region 11 and the substrate 10), and if the depletion layer is to be widened and reduced, it is necessary for the gate current to continuously charge Cgd (i.e., gate-drain capacitance) under a certain Vgs voltage, so there will be a plateau period during the turn-on process of the device; in the present invention, by forming the groove 12 between the two body regions 11, that is, etching away most of the substrate 10 between the two body regions 11, most of the depletion layer between the two body regions 11 is removed, thereby reducing the portion of the gate current used to charge the depletion layer in Cgd, so that the gate current is mainly used to charge Cgs (i.e., gate-source capacitance), that is, the plateau period is shortened, the device turn-on process is accelerated, and the turn-on loss of the device is reduced.

[0137] Furthermore, if the portions of the two gate layers 17 located above the bottom wall of the groove 12 are connected, a capacitor structure will be formed between the gate layer 17 and the drain electrode above the bottom wall of the groove 12, and this capacitor structure is a part of the Miller capacitance (i.e., gate-drain capacitance). Therefore, in the present invention, by forming a split gate, that is, the portions of the two gate layers 17 located above the bottom wall of the groove 12 are not connected, the capacitance value of the Miller capacitance can be reduced, and the capacitance value of the Miller capacitance is positively correlated with the turn-on loss, thereby further reducing the turn-on loss of the device.

[0138] In addition, by forming the groove 12 between the two body regions 11, most of the depletion layer between the two body regions 11 (that is, the depletion layer in the PN junction formed by the body region 11 and the substrate 10) is removed, thereby eliminating part of the on-resistance of the JFET region between the two body regions 11, that is, the on-resistance of the JFET region between the two body regions 11 is reduced, thereby reducing the overall on-resistance of the device and improving the current capability of the device.

[0139] If the doping concentration of the second epitaxial layer 13 is greater than the doping concentration of the substrate 10, the carrier mobility of the channel can be increased, thereby reducing the channel resistance, and the on-resistance of the accumulation layer in the substrate 10 directly below the gate layer 17 located on the side wall of the groove 12 can be reduced, so that the current can not only flow from the second epitaxial layer 13 on the side wall of the groove 12 toward the drain, but also diffuse from the area where the accumulation layer is located to flow toward the drain, that is, the flow path of the current becomes wider, so that the current can flow to the drain more quickly, thereby improving device performance.

[0140] In summary, the present invention provides a method for manufacturing a semiconductor device, comprising: providing a substrate; forming two body regions in the substrate, and forming a groove in the substrate between the two body regions; forming a second epitaxial layer on the substrate, the second epitaxial layer extending from part of the body region to the side wall of the groove; forming a source region in the body region, the source region extending from the side of the second epitaxial layer away from the groove to below the second epitaxial layer, the doping type of the substrate, the second epitaxial layer, and the source region is opposite to the doping type of the body region; forming a gate oxide layer on the surface of the second epitaxial layer and the bottom wall of the groove; forming a gate layer on the gate oxide layer, the gate layer extending from the gate oxide layer above the second epitaxial layer to the gate oxide layer on the side wall of the groove. The method for manufacturing a semiconductor device provided by the present invention can improve device performance.

[0141] The above description is only a description of the preferred embodiments of the present invention, and is not intended to limit the scope of the present invention. Any changes or modifications made by a person skilled in the art in the field of the present invention based on the above disclosure shall fall within the scope of protection of the claims.

Claims

1. A semiconductor device, characterized in that: include: substrate; Two body regions are formed in the substrate, a groove is formed in the substrate between the two body regions, and the bottom wall of the groove is higher than the bottom surface of the body region; A second epitaxial layer is formed on the substrate, wherein the second epitaxial layer extends from a portion of the body region to a sidewall of the groove; a source region formed in the body region, the source region extending from a side of the second epitaxial layer away from the groove to below the second epitaxial layer, and the doping type of the substrate, the second epitaxial layer, and the source region is opposite to the doping type of the body region; a gate oxide layer formed on a surface of the second epitaxial layer and a bottom wall of the groove; A gate layer is formed on the gate oxide layer, and the gate layer extends from the gate oxide layer above the second epitaxial layer to the gate oxide layer on the sidewall of the groove.

2. The semiconductor device according to claim 1, wherein The base comprises a substrate and a first epitaxial layer from bottom to top, and the body region is formed in the first epitaxial layer.

3. The semiconductor device according to claim 1, wherein The substrate and the second epitaxial layer are made of silicon carbide.

4. The semiconductor device according to claim 1, wherein The doping concentration of the second epitaxial layer is greater than the doping concentration of the substrate and less than the doping concentration of the source region.

5. The semiconductor device according to claim 1, wherein The semiconductor device further comprises: A doping region is formed in the substrate at the bottom wall of the groove, the gate oxide layer covers the doping region, the doping type of the doping region is the same as the doping type of the body region, and the doping concentration of the doping region is greater than or equal to the doping concentration of the body region.

6. The semiconductor device according to claim 1, wherein: The semiconductor device further comprises: An insulating dielectric layer is formed on the substrate, the insulating dielectric layer fills the groove, and the insulating dielectric layer covers the gate oxide layer and the gate layer; A conductive structure is formed on the source region and the body region of the second epitaxial layer at a side away from the groove.

7. A method for manufacturing a semiconductor device, characterized in that: include: providing a substrate; Forming two body regions in the substrate, and forming a groove in the substrate between the two body regions, wherein a bottom wall of the groove is higher than a bottom surface of the body region; forming a second epitaxial layer on the substrate, wherein the second epitaxial layer extends from a portion of the body region to a sidewall of the recess; forming a source region in the body region, wherein the source region extends from a side of the second epitaxial layer away from the groove to below the second epitaxial layer, and the doping type of the substrate, the second epitaxial layer, and the source region is opposite to the doping type of the body region; forming a gate oxide layer on the surface of the second epitaxial layer and the bottom wall of the groove; A gate layer is formed on the gate oxide layer, wherein the gate layer extends from the gate oxide layer above the second epitaxial layer to the gate oxide layer on the sidewall of the groove.

8. The method for manufacturing a semiconductor device according to claim 7, wherein: The base comprises a substrate and a first epitaxial layer from bottom to top, and the body region is formed in the first epitaxial layer.

9. The method for manufacturing a semiconductor device according to claim 7, wherein: The substrate and the second epitaxial layer are made of silicon carbide.

10. The method for manufacturing a semiconductor device according to claim 7, wherein: The doping concentration of the second epitaxial layer is greater than the doping concentration of the substrate and less than the doping concentration of the source region.

11. The method for manufacturing a semiconductor device according to claim 7, wherein: After forming the second epitaxial layer on the substrate and before forming the gate oxide layer on the surface of the second epitaxial layer and the bottom wall of the groove, the method for manufacturing the semiconductor device further includes: A doping region is formed in the substrate at the bottom wall of the groove, wherein the doping type of the doping region is the same as the doping type of the body region, and the doping concentration of the doping region is greater than or equal to the doping concentration of the body region.

12. The method for manufacturing a semiconductor device according to claim 7, wherein: The method for manufacturing the semiconductor device further includes: forming an insulating dielectric layer on the substrate, wherein the insulating dielectric layer fills the groove and covers the gate oxide layer, the gate layer, and the source region and the body region of the second epitaxial layer away from the groove; forming a contact hole in the insulating dielectric layer, wherein the contact hole exposes the source region and the body region of the second epitaxial layer on a side away from the groove; A conductive structure is formed in the contact hole.

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