Edge contact type field effect transistor and method for manufacturing the same

Abstract

The application belongs to the technical field of semiconductor devices, and discloses an edge contact type field effect transistor and a preparation method thereof, wherein the transistor comprises a substrate layer and a gate layer protruding on the surface of the substrate layer, a channel layer is arranged above the gate layer, the channel layer has a channel region located directly above the gate layer, two electrode regions located on the opposite sides of the gate layer, and a rising region connected between the electrode regions and the channel region, the material of the channel layer is a transition metal chalcogenide, and the electrode regions are used for inducing phase transition through a lithium intercalation method to realize edge contact of a metal phase and a semiconductor phase. The application proposes stress limiting lithium intercalation, locally introduces stress in the channel layer by using the step formed by the gate layer and the substrate layer, thereby blocking and limiting the diffusion behavior of lithium ions at the position where the stress exists, i.e. the rising region, and the preparation of a more sharp phase transition interface can be realized, and the high consistency facilitates large-scale integration.

Description

TECHNICAL FIELD

[0001] The present application belongs to the technical field of semiconductor devices, and more particularly, to an edge-contact field effect transistor and a method for manufacturing the same. BACKGROUND

[0002] With the gradual reduction of semiconductor feature size, silicon technology is rapidly approaching its fundamental limit at the sub-10 nanometer node. Field effect transistors need new channel materials. Two-dimensional (2D) semiconductors have outstanding advantages such as atomic-level thickness, no surface dangling bonds, and high carrier mobility, making two-dimensional semiconductor transistors have better electrostatic control and on-state performance, and are strong competitors for the next generation of channel materials. Internationally, the Institute of Electrical and Electronics Engineers (IEEE) has listed two-dimensional materials as key materials for further improving transistor integration density in its annual technology roadmap (IRDS).

[0003] In traditional silicon-based transistors, by heavily doping the source and drain, ohmic contact between the metal electrode and the semiconductor at the source and drain is achieved, and the contact resistance is reduced. At the same time, the polysilicon gate above the channel is used as an ion diffusion barrier layer for the channel region during heavy doping, so that high-quality metal-semiconductor contact at the source and drain can be achieved while ensuring the self-alignment effect of the source and drain active region and the gate. However, the thin atomic nature of two-dimensional materials makes them difficult to withstand the structural damage caused by traditional doping methods, and high-concentration doping of the source and drain cannot be used to achieve ohmic contact between the metal and the semiconductor, so the low-quality contact interface between the metal and the semiconductor in two-dimensional transistor devices limits further performance improvement.

[0004] According to the unique 2H / 1T structure of transition metal dichalcogenides (TMDCs) and the associated semiconductor / metallic transition, a new idea of realizing a new type of homologous edge-type metal-semiconductor contact through phase transition engineering is provided. In 2014, Professor Chhowalla.M of Rutgers University in the United States used Li intercalation method to induce MoS2 to transform from 2H phase to 1T phase, and first prepared an edge-contact transistor by phase transition engineering, which converted the surface contact between metal and semiconductor into homologous edge contact between in-plane metal phase and semiconductor phase, greatly improving the on-state current of MoS2 semiconductor transistor.

[0005] However, the Li insertion method is based on the intercalation of lithium ions between the TMDCs layers and the induced phase transition, and the disordered diffusion of lithium ions in the layers causes the roughness and poor precision of the phase transition interface. The existing photoresist blocking process cannot achieve the precise preparation of the atomically sharp phase transition interface, which leads to potential interface defect states and pinning effects of the interface, and even causes the problem of device short circuit, thereby limiting the performance of the transistor. The uncontrollable position of the phase transition interface also leads to poor uniformity of device preparation, and the gate and the source / drain regions of the phase transition cannot be aligned, thereby limiting the further array integration of the two-dimensional transistor and hindering the application of the two-dimensional transistor.

[0006] In summary, in the two-dimensional semiconductor transistor device, the Li insertion method is used to prepare the edge contact under the existing process, and it is difficult to achieve the atomically sharp phase transition interface and the controllable preparation of the phase transition interface position, which greatly limits the further improvement of the performance of the two-dimensional transistor and the array integration. SUMMARY

[0007] In view of the above defects or improvement needs of the prior art, the present application provides an edge contact type field effect transistor and a preparation method thereof, which is used to solve the problem that the existing Li insertion method is difficult to achieve the controllable preparation of the phase transition interface position in the process of preparing the edge contact in the two-dimensional semiconductor transistor device. The present application can control the phase transition interface in the prepared two-dimensional transistor, thereby obtaining a high-quality metal-semiconductor contact interface, and has high consistency and is convenient for large-scale integration.

[0008] To achieve the above-mentioned purpose, according to one aspect of the present application, an edge contact type field effect transistor is provided, which comprises a substrate layer and a gate layer protruding on the surface of the substrate layer. A channel layer is arranged above the gate layer, and the channel layer is arranged across the gate layer, so that the channel layer has a channel region located directly above the gate layer, two electrode regions located on the opposite sides of the gate layer, and a rising region connected between any of the electrode regions and the channel region. The material of the channel layer is a transition metal chalcogenide, and the electrode region is used to induce phase transition by lithium insertion method and then be converted into a metal phase to realize the edge contact of the metal phase and the semiconductor phase.

[0009] The edge contact type field effect transistor provided by the present application further comprises an insulating layer arranged between the gate layer and the channel layer, and the gate layer and the channel layer are separated by the insulating layer.

[0010] And / or, the electrode region is connected with a metal electrode.

[0011] When the transistor is a floating gate field effect transistor structure for storage, the gate layer is a floating gate layer.

[0012] The edge contact type field effect transistor provided by the application has a graphene layer as the floating gate layer, a molybdenum sulfide layer as the channel layer, and a silicon wafer with a silicon oxide layer as the substrate layer.

[0013] The edge contact type field effect transistor provided by the application has an electrode region which is induced to change into a metal phase by lithium ion intercalation through phase transition of the electrode region to a metal phase by lithium intercalation of at least a partial part of the electrode region exposed to a n-butyl lithium solution.

[0014] The edge contact type field effect transistor provided by the application has a gate layer protruding from the substrate layer by a height of 10-20 nm, a n-butyl lithium solution with a concentration of 2-3 M, and the electrode region exposed to the n-butyl lithium solution for a time of 1-3 h.

[0015] According to another aspect of the application, a preparation method of an edge contact type field effect transistor is provided for preparing the edge contact type field effect transistor as described in any of the above, and the preparation method comprises:

[0016] cleaning and pretreating the substrate layer;

[0017] preparing the gate layer on the surface of the substrate layer, wherein the gate layer is obtained by mechanical exfoliation;

[0018] preparing the channel layer on the surface of the substrate layer, wherein the channel layer is arranged across the gate layer so that the channel layer has a channel region located directly above the gate layer, two electrode regions located on opposite sides of the gate layer, and a rising region connected between any of the electrode regions and the channel region, and the channel layer is obtained by mechanical exfoliation;

[0019] arranging a protection layer on the surface of the channel layer, wherein the protection layer covers the channel region and the rising region, and at least a partial part of the electrode region is in an exposed state;

[0020] immersing the device after the protection layer is arranged into a lithium solution for lithium intercalation induction, taking out after a preset time, and obtaining the transistor with the electrode region changed into a metal phase to realize edge contact between the metal phase and the semiconductor phase.

[0021] The preparation method of the edge contact type field effect transistor provided by the application further comprises, after the gate layer is prepared on the surface of the substrate layer and before the channel layer is prepared:

[0022] preparing an insulating layer above the gate layer, wherein the insulating layer is obtained by mechanical exfoliation;

[0023] Correspondingly, the channel layer is prepared above the insulating layer.

[0024] The preparation method of the edge contact type field effect transistor provided by the application further comprises the following steps after the substrate layer is pretreated by cleaning and before the gate layer is prepared:

[0025] A cross mark is prepared on the surface of the substrate layer, which is used to mark the position of the gate layer when the gate layer is prepared.

[0026] The preparation method of the edge contact type field effect transistor provided by the application further comprises the following steps after the transistor is obtained by transforming the electrode area into a metal phase:

[0027] A metal electrode is prepared on the electrode area by using a metal thermal evaporation process.

[0028] Compared with the prior art, the edge contact type field effect transistor and the preparation method thereof provided by the application have the following advantages:

[0029] 1. The transistor structure and preparation process of stress limiting lithium intercalation phase change are provided, a step with a sudden height difference is formed by using the gate layer material and the substrate layer, local stress is additionally introduced in the transition metal chalcogenide channel layer, local deformation is generated in the stress area, i.e., an ascending area is formed, the interlayer spacing is reduced at this position, the diffusion energy barrier is improved, the diffusion behavior of lithium ions is blocked and limited at the position where the stress exists, i.e., the position of the physical edge of the gate layer, and the phase change induced by lithium ions is also stopped at this position. Compared with the conventional method of protecting only by using a photolithography mask, the contact interface is greatly optimized, the defect state density is reduced, the preparation of a more sharp phase transition interface can be realized, and the problem of irregular expansion of the phase transition interface is avoided. At the same time, the position of the lithium intercalation phase change can be accurately limited, the uniformity problem of the device preparation is improved, and the uniformity and success rate of the preparation of the array device are particularly improved, which is convenient for large-scale integrated manufacturing.

[0030] 2. The transistor structure and preparation process of stress limiting lithium intercalation phase change can also realize the self-alignment effect of the edge of the floating gate material and the edge of the semiconductor channel, avoid the parasitic capacitance caused by the overlap of the source and the drain and the floating gate, and avoid the problem that the channel part cannot be adjusted due to the floating gate area being smaller than the semiconductor channel area, thereby significantly improving the performance of the transistor. BRIEF DESCRIPTION OF DRAWINGS

[0031] Figure 1 is a structural schematic diagram of the preparation of the gate layer on the surface of the substrate layer provided by the application;

[0032] Figure 2 is a structural schematic diagram of the preparation of the insulating layer by transferring material on the gate layer provided by the application;

[0033] Figure 3is a structure schematic diagram of transferring and preparing a channel layer on the basis of the gate layer and the insulating layer provided by the application;

[0034] Figure 4 is a structure schematic diagram of protecting a device surface with an inert material provided by the application;

[0035] Figure 5 is a structure schematic diagram of exposing an electrode region of a channel layer to be intercalated provided by the application;

[0036] Figure 6 is a structure schematic diagram of performing lithium intercalation / intercalation treatment on a device provided by the application;

[0037] Figure 7 is a structure schematic diagram of depositing Cr / Au metal to prepare source and drain electrodes in an exposed region after lithium intercalation / intercalation treatment, and obtaining a complete transistor unit device structure provided by the application;

[0038] Figure 8 is a photo diagram of an actually prepared self-aligned edge contact type field effect transistor provided by the application;

[0039] Figure 9 is a structure and photo diagram contrast of an edge contact type field effect transistor provided by the application;

[0040] Figure 10 is a flowchart of a preparation method of an edge contact type field effect transistor provided by the application;

[0041] Figure 11 is a back gate transfer characteristic curve diagram of a source and drain current of a field effect transistor with different back gate scanning voltages, and a diagram of a storage window size extracted from the back gate scanning voltage provided by the application;

[0042] Figure 12 is a diagram of a source and drain current level change of a field effect transistor after applying a back gate pulse write voltage of different widths of-15V, and a diagram of a source and drain current ratio before and after the pulse extracted, wherein a constant bias voltage of 0.1V is applied to the source and drain provided by the application;

[0043] Figure 13 is a diagram of a source and drain current level change of a field effect transistor after applying a back gate pulse erase voltage of different widths of 15V, and a diagram of a source and drain current ratio before and after the pulse extracted, wherein a constant bias voltage of 0.1V is applied to the source and drain provided by the application;

[0044] Figure 14 is a comparison diagram of a traditional photoresist blocking method prepared edge contact type field effect transistor and a self-aligned edge contact type field effect transistor prepared based on a stress limiting process provided by the application;

[0045] The same reference signs are used throughout the drawings to represent the same elements or structures. In all the drawings:

[0046] 201 - substrate layer, 202 - gate layer, 203 - insulation layer, 204 - channel layer, 205 - protection layer, 206 - exposed area, 207 - lithium ion, 208 - metal electrode. DETAILED DESCRIPTION

[0047] In order to make the objectives, technical solutions and advantages of the present application clearer, the present application will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and should not be used to limit the present application. In addition, the technical features involved in the various embodiments of the present application described below can be combined with each other as long as they do not conflict with each other.

[0048] Reference should be made to Figures 1 to 7 The embodiment one provides an edge contact type field effect transistor, which comprises a substrate layer 201 and a gate layer 202 protruding from the surface of the substrate layer 201, as shown in Figure 1 A channel layer 204 is arranged above the gate layer 202, and the channel layer 204 is arranged across the gate layer 202, so that the channel layer 204 has a channel region located directly above the gate layer 202, two electrode regions located on opposite sides of the gate layer 202, and a rising region connected between any of the electrode regions and the channel region, as shown in Figure 3

[0049] Reference should be made to Figure 6 and Figure 7 The material of the channel layer 204 is a transition metal chalcogenide, and the electrode region is used to induce phase transition by lithium intercalation method to convert into a metal phase, so as to realize edge contact between the metal phase and the semiconductor phase. Due to the step limitation of the gate layer 202, the channel layer 204 is arranged to form the channel region and the electrode region with height difference, and the rising region is connected between the electrode region and the channel region. The channel layer 204 is an integral structure, so that the rising region is squeezed and connected between the electrode region and the channel region, resulting in an increase in the interlayer pressure of the material layer of the rising region. Therefore, when the electrode region is induced to phase transition by lithium intercalation method, the interlayer pressure of the material layer of the rising region can block the diffusion of lithium ions 207, so that the lithium ions 207 will stop continuing to diffuse due to resistance when diffusing from the electrode region to the rising region, thereby being able to control the phase transition interface at the rising region, i.e. control the position of the phase transition interface.

[0050] ​That is, the rising region is used to block the diffusion of lithium ions 207 from the electrode region to the channel region during lithium intercalation, so that the channel region remains in a semiconductor phase, thereby achieving edge contact between the metal phase and the semiconductor phase; and the phase transition interface can be controlled at the rising region, achieving precise preparation of an atomic-level sharp phase transition interface, while also achieving self-alignment of the phase transition interface with the edge of the gate layer 202, facilitating large-scale integrated manufacturing.

[0051] The present embodiment takes into account that in the prior art, when preparing an edge-contact floating gate transistor using a lithium intercalation / intercalation method, the disordered diffusion of lithium ions 207 leads to a rough phase transition interface and an inability to accurately control the position, which limits the further improvement of transistor performance and subsequent array integration. The present embodiment proposes a stress limiting process to improve the lithium intercalation / intercalation phase transition method, and based on this, an edge-contact field effect transistor that can achieve a self-alignment effect is prepared, which can achieve fast erasing and writing when storing, and has the potential for array integration.

[0052] The present embodiment proposes a new edge-contact field effect transistor structure, which achieves precise preparation of an atomic-level sharp phase transition interface, thereby significantly reducing interface defects and improving the performance of unit transistor devices. Through structural design, the position of the phase transition contact interface is accurately controlled, enabling self-alignment with the edge of the floating gate layer, facilitating large-scale integrated manufacturing.

[0053] The above edge contact is achieved by inducing the electrode region transition metal chalcogenide to transition into a metal phase through lithium intercalation. The electrode region transition metal chalcogenide is exposed to a lithium solution such as n-butyllithium solution for lithium intercalation, lithium ions 207 intercalate between the transition metal chalcogenide layers and diffuse inward, the transition metal chalcogenide with lithium ion 207 intercalation is induced to phase transition into a metal phase, and the position without lithium ion 207 intercalation remains in a semiconductor phase, finally achieving edge contact between the two metal phase transition metal chalcogenides and the middle untransformed semiconductor phase channel region.

[0054] By utilizing the characteristics of different phase structures of transition metal chalcogenides, the rough surface contact between traditional electrodes and two-dimensional semiconductors is converted into edge contact between the same two-dimensional material in-plane metal phase and semiconductor phase through phase transition, which has more efficient carrier injection and achieves high-speed operation of the transistor during operation, for example, high-speed erasing and writing when the transistor is used as a memory.

[0055] The realization of the above-mentioned atomically sharp phase transition interface and self-alignment effect is through structural design, using the physical edge of the gate layer 202 material and the step with abrupt height difference formed by the substrate layer 201 to introduce local stress in the plane of the transition metal chalcogenide channel layer 204 (i.e. the force of the gate layer 202 on the channel layer 204 when the channel layer 204 is set), so that the material produces local deformation (i.e. forms an uplift area) in the stress area, resulting in a smaller interlayer spacing at this position, which increases the diffusion energy barrier, thereby blocking the diffusion behavior of lithium ions 207 at the position where the stress exists, i.e. the uplift area at the physical edge of the gate layer 202, and the phase transition induced by lithium ions 207 is also stopped at this position, finally realizing the atomically sharp phase transition interface and the self-alignment effect of the edge contact position and the physical edge of the floating gate.

[0056] Further, referring to Figure 2 , the edge-contact field effect transistor further comprises an insulating layer 203 arranged between the gate layer 202 and the channel layer 204, and the gate layer 202 and the channel layer 204 are separated by the insulating layer 203; the insulating layer 203 should completely separate the gate layer 202 and the channel layer 204, so that there is no contact between them. The insulating layer 203 is also arranged to fit the upper surface and the side surface of the gate layer 202, and has a stress deformation area at the side surface of the gate layer 202.

[0057] Referring to Figure 7 , the electrode regions are connected with metal electrodes 208. The metal electrode 208 connected to one of the electrode regions is the source electrode, and the metal electrode 208 connected to the other electrode region is the drain electrode.

[0058] In some specific embodiments, when the transistor is a floating gate field effect transistor structure for storage, the gate layer 202 is a floating gate layer. Specifically, the floating gate layer is a few-layer graphene; the channel layer 204 is molybdenum sulfide; and the substrate layer 201 is a silicon wafer with a silicon oxide layer.

[0059] Referring to Figure 7 , the transistor uses a silicon wafer with a silicon oxide layer as the substrate layer 201, and from the substrate layer 201 upwards, there are in turn a floating gate layer, an insulating layer 203, a transition metal chalcogenide as the channel layer 204, and a source electrode and a drain electrode prepared above the channel layer 204 by electrode evaporation process. For the transition metal chalcogenide of the channel layer 204, it is phase transitioned into a metal phase near the contact area with the metal electrode 208, while the middle part is a semiconductor phase, thereby realizing edge contact, and the phase transition edge is self-aligned with the edge of the few-layer graphene as the floating gate layer.

[0060] Specifically, the physical edge of the floating gate layer material together with the substrate layer 201 forms a structure with a sudden height difference, on which the insulating layer 203 and the transition metal chalcogenide as the channel layer 204 introduce stress deformation, further limiting the lithium intercalation diffusion position in the transition metal chalcogenide of the channel layer 204 to the stress deformation position, i.e. the material edge of the floating gate layer. Finally, the self-alignment effect of the semiconductor channel and the floating gate layer position is realized. The transistor is formed by stacking the layers of materials in sequence on the substrate layer 201 through the means of mechanical peeling and transferring.

[0061] In some specific embodiments, the electrode region is specifically subjected to lithium intercalation by exposing at least a local part to a n-butyllithium solution, and a phase transition of the electrode region to a metal phase is induced by intercalating lithium ions 207 into the electrode region. That is, the electrode region is provided with an exposed region 206, which is a local part of the electrode region or the entire electrode region. Optionally, the exposed region 206 is located at the edge of the electrode region, i.e. the edge part of the electrode region is the exposed region 206, which facilitates the intercalation of lithium ions in the lithium solution into the channel layer material through the edge of the electrode region.

[0062] For the channel layer 204 of the transistor, the lithium intercalation method is used to induce a phase transition of the transition metal chalcogenide of the electrode region, in the process, lithium ions 207 intercalate between the transition metal chalcogenide layers and inwardly diffuse, so that the transition metal chalcogenide with lithium ion 207 intercalation position is converted from a semiconductor phase to a metal phase, and then forms an edge contact with the semiconductor phase transition metal chalcogenide in the middle that has not been phase transitioned.

[0063] In some specific embodiments, the height of the floating gate layer protruding from the substrate layer 201 is 10-20 nm; the concentration of the n-butyllithium solution is 2-3 M; and the time for which the electrode region is exposed to the n-butyllithium solution is 1-3 h. This embodiment comprehensively considers that the height of the floating gate layer, the concentration of the lithium solution, and the exposure time of the electrode region in the lithium solution all affect the degree of inward diffusion of lithium ions 207 from the electrode region, and research shows that within the above parameter range, the phase transition interface can be better controlled in the rising region to achieve a better phase transition interface.

[0064] This embodiment two provides a preparation method of an edge contact type field effect transistor, which is used for preparing the edge contact type field effect transistor described in any of the above embodiments, and the preparation method comprises:

[0065] The substrate layer 201 is subjected to cleaning pretreatment; specifically, the substrate layer 201 is selected; a silicon wafer with a 300 nm silicon oxide layer on the surface is selected as the substrate layer 201, and the substrate layer 201 is cleaned through an ultrasonic cleaning instrument with acetone, ethanol, and deionized water, respectively, and the surface moisture is blown dry.

[0066] The gate layer 202 is prepared on the surface of the substrate layer 201, wherein the gate layer 202 is obtained by mechanical exfoliation; the construction of the gate layer 202 is as follows: taking a single crystal as the gate material, mechanically exfoliating and thinning, and then transferring to the substrate layer 201, and selecting the material with appropriate shape and thickness under a light microscope as the gate layer 202.

[0067] The channel layer 204 is prepared on the surface of the substrate layer 201, referring to Figure 3 and Figure 8 , the channel layer 204 is arranged across the gate layer 202, so that the channel layer 204 has a channel region located directly above the gate layer 202, two electrode regions located on the opposite sides of the gate layer 202, and a rising region connected between any of the electrode regions and the channel region, wherein the channel layer 204 is obtained by mechanical exfoliation; the construction of the channel layer 204 is as follows: taking a two-dimensional material as the channel layer 204, mechanically exfoliating and thinning, and then selecting the material with appropriate shape and thickness, and transferring to the substrate layer 201 at a suitable angle according to the required structure requirements, that is, it is required to cross the gate layer 202, so that the channel layer 204 has two electrode regions located on the opposite sides of the gate layer 202, a channel region located above the gate layer 202, and a rising region.

[0068] The protection layer 205 is arranged on the surface of the channel layer 204, wherein the protection layer 205 covers the channel region and the rising region, and at least part of the electrode region is in an exposed state; referring to Figure 5 and Figure 6 , the protection of the phase-change region, i.e., the rising region, and the non-phase-change region, i.e., the channel region, and the exposure of the remaining phase-change region, i.e., the electrode region, are as follows: according to the characteristics of the phase-change material, the inert materials such as photoresist and oxide are used to protect the non-phase-change channel region above the gate layer 202 and the rising region near the step, and the edge region of the channel material, i.e., the electrode region, on both sides of the gate layer 202 is exposed.

[0069] The device after the protection layer 205 is arranged is immersed in a lithium solution for lithium intercalation induction, taken out after a preset time, and a transistor is obtained, in which the electrode region is changed to a metal phase to realize the edge contact of the metal phase and the semiconductor phase. Referring to Figure 6 and Figure 7 , the realization of the self-aligned phase-change edge contact is as follows: the device after the above steps is immersed in a n-butyl lithium solution together with the substrate, taken out after a certain time, and then washed with n-hexane and anhydrous ethanol in sequence and dried.

[0070] Further, after the gate layer 202 is prepared on the surface of the substrate layer 201 and before the channel layer 204 is prepared, the method further comprises:

[0071] An insulating layer 203 is prepared above the gate layer 202, wherein the insulating layer 203 is obtained by mechanical exfoliation; correspondingly, the channel layer 204 is prepared above the insulating layer 203. That is, the two-dimensional material serving as the insulating layer 203 and the channel layer 204 is mechanically exfoliated to thin, and then the material with a suitable shape and thickness is selected and transferred to the gate layer 202 at a suitable angle according to the required structure.

[0072] After the substrate layer 201 is cleaned and pretreated, the gate layer 202 is prepared.

[0073] A cross mark is prepared on the surface of the substrate layer 201, which is used to mark the position of the gate layer 202 when the gate layer 202 is prepared. The cross mark is prepared on the substrate surface by sequentially performing spin coating photoresist, photoresist baking, ultraviolet lithography, development, fixation, and metal thermal evaporation process, and a coordinate system for later material point transfer is formed. For example, when the gate layer 202 is constructed, the gate layer 202 is transferred to the above-mentioned mark substrate, and a material with a suitable shape and thickness is selected as the gate layer 202 under a light microscope, and the coordinates are recorded. The point transfer of the insulating layer 203 and the channel layer 204 can be performed according to the coordinates of the gate layer 202.

[0074] Further, after the electrode region of the transistor is obtained by the phase change to the metal phase, the following steps are further included:

[0075] A metal electrode 208 is prepared on the electrode region by a metal thermal evaporation process. Referring to Figure 7 , the construction of the electrode; for the device after the phase change treatment, a metal thermal evaporation process is used to cover the metal electrode 208 on both sides of the exposed region of the electrode region, which is used as the source and the drain, respectively, and the electrode is led out by combining further lithography and other patterning processing methods, as shown in Figure 8 and Figure 9 .

[0076] The following is a specific embodiment:

[0077] Embodiment 1

[0078] As shown in Figures 1 to 7 , in this embodiment, few-layer graphene is used as the floating gate layer material, hexagonal boron nitride is used as the insulating layer 203 material, and molybdenum sulfide is used as the channel layer 204 material, to realize the construction of the edge contact type field effect transistor unit device with self-alignment effect, as shown in Figure 10 , which can include the following steps:

[0079] Step S1, selection and processing of the substrate silicon wafer; in this embodiment, a silicon wafer with a 300 nm thick oxide layer is selected as the substrate of the unit device, and then the surface impurities are removed by cleaning to obtain a clean substrate, and the cleaning method is as follows: the silicon wafer is immersed in beakers containing acetone, ethanol and deionized water in turn, and then placed in an ultrasonic cleaner for 5 minutes, taken out with tweezers after cleaning, and immediately blown with a nitrogen gun to remove the surface deionized water, and then stored in a vacuum environment for standby.

[0080] Step S2, preparation of cross marks on the substrate surface; spin-coat AR-P 5350 type ultraviolet photoresist on the clean substrate surface, spin-coat machine speed 4000 r / min, spin-coat time 1 min, and then place on a heating plate at 150°C for 5 min to volatilize the solvent. Select a suitable mark mask, and use a ultraviolet photoetching machine for contact exposure, and then use corresponding AR300-26 developer for development. After successful development, evaporate Cr (10 nm) / Au (40 nm) using a high vacuum coating machine, and then use acetone to remove the photoresist and the Cr / Au metal above the photoresist, leaving the mark metal mark on the exposed area on the substrate surface, thus completing the preparation of the cross marks on the substrate surface.

[0081] Step S3, construction of the floating gate layer; select a small piece of graphite single crystal, place it on a high-transparency adhesive tape, and thin it by repeated mechanical peeling to obtain a suitable few-layer graphene as the floating gate layer. Perform O2 Plasma hydrophilic treatment on the substrate using a plasma cleaning instrument, then paste the few-layer graphene-coated adhesive tape on the substrate, press gently and then remove it, and the material is transferred to the substrate silicon wafer. Find the few-layer graphene with appropriate thickness and shape under a light microscope and record the coordinates as the floating gate layer of the device, as shown in Figure 1

[0082] Step S4, construction of the insulating layer 203 and the channel layer 204; the insulating layer 203 and the channel layer 204 are both constructed by mechanical peeling and fixed-point transfer, and the specific process is as follows: thin layers of h-BN, i.e. the insulating layer 203 and MoS2 material, are obtained by the above mechanical peeling method, the adhesive tape with thin layer of material is pasted on a block of polydimethylsiloxane (PDMS), pressed gently and then removed, the material is transferred to the PDMS, and the material with appropriate thickness and shape is found under a light microscope, and then transferred to the top of the graphene floating gate layer in step S3 as the insulating layer 203 and the channel layer 204, and sequentially constitutes Figure 2 and Figure 3 ​The physical edge of the floating gate layer few-layer graphene material and the substrate form a step stress structure during the construction process, which introduces external stress in the in-plane of the h-BN and MoS2 materials, and the stress position is the edge position of the graphene material. The MoS2 directly above the graphene material is a controllable channel region, and the two sides thereof are electrode regions that need to be phase transition treated.

[0083] In step S5, the deformation region and the non-phase transition region are protected, and the remaining phase transition region is exposed. In this embodiment, the PMMA is spin-coated to protect the deformation region and the non-phase transition region. As shown in FIG. 5, the edge region of the MoS2 on the two sides of the source and the drain is subjected to the EBL treatment and development, the PMMA protective layer 205 in the region is removed, and the exposed region 206 is formed as shown in FIG. 6 to achieve the exposure of the region. However, the present application is not limited thereto, and other resists, oxides, and other inert materials can be used according to the characteristics of the intercalation material, and other reasonable protective materials and removal methods can be used as long as the deformation region and the non-intercalation region can be protected and the remaining phase transition region can be exposed. Figure 4 Figure 5 In step S6, the self-aligned phase transition edge contact is achieved. The Li intercalation / embedding phase transition method is used. A 2.5M n-butyllithium solution is selected, and the device after the above steps is immersed in the n-butyllithium solution together with the substrate silicon wafer in the glove box inert gas environment. The lithium ion 207 starts to embed from the edge of the MoS2 on the two sides of the source and the drain, diffuses along the material layers to the middle step position, changes the MoS2 at the path from the semiconductor phase to the metal phase, and stops at the floating gate material physical edge with the step stress, as shown in FIG. 7. After 2h, the silicon wafer is taken out, and the surface residual reagent is removed by washing with n-hexane and anhydrous ethanol in sequence. However, the present application is not limited thereto, and the appropriate concentration of organic lithium solution can be selected according to the material thickness, temperature, and other conditions, the phase transition treatment time can be adjusted, and the appropriate washing reagent can be selected as long as the lithium ion 207 intercalation of the material and the successful realization of the diffusion behavior of the step stress can be limited.

[0084] In step S7, the electrodes are constructed. After the phase transition treatment and the cleaning of the phase transition reagent, the Cr(10nm) / Au(40nm) is thermally evaporated by the high-vacuum evaporation instrument, and then the photoresist and the Cr / Au metal thereon are removed by acetone, leaving the Cr / Au metal in the exposed region 206 in step S5 as the source and the drain of the device, which also plays a protective role for the intercalation starting region, as shown in FIG. 8. Then, referring to the process flow in step S5, the source and the drain electrodes of the device are respectively led out by the processes of spin-coating PMMA, EBL treatment, development, and thermally evaporating Cr(10nm) / Au(40nm) in sequence, which facilitates the subsequent electrical testing by the probe station, and reference can be made to FIG. 9. Figure 6

[0085] In step S7, the electrodes are constructed. After the phase transition treatment and the cleaning of the phase transition reagent, the Cr(10nm) / Au(40nm) is thermally evaporated by the high-vacuum evaporation instrument, and then the photoresist and the Cr / Au metal thereon are removed by acetone, leaving the Cr / Au metal in the exposed region 206 in step S5 as the source and the drain of the device, which also plays a protective role for the intercalation starting region, as shown in FIG. 8. Then, referring to the process flow in step S5, the source and the drain electrodes of the device are respectively led out by the processes of spin-coating PMMA, EBL treatment, development, and thermally evaporating Cr(10nm) / Au(40nm) in sequence, which facilitates the subsequent electrical testing by the probe station, and reference can be made to FIG. 9. Figure 7 ​​​Figure 8 and Figure 9 .

[0086] Step S8, performance test; the transistor unit device constructed is tested for transistor related performance by means of a probe station test system and a semiconductor analyzer. The results are shown in Figure 11 , Figure 12 , Figure 13 It can be concluded from Figure 11 that the transistor has an on-state current as high as microampere level and an off-state current as low as picoampere level, and has a large storage window. The storage window is about 30 V under a back gate scanning voltage of positive and negative 20 V, and is further improved as the scanning voltage increases. Figure 12 and Figure 13 are the source-drain current level changes after applying back gate pulse voltages of different widths, and the extracted source-drain current ratio before and after the pulse, respectively. The source-drain is applied with a constant bias of 0.1 V, and the back gate pulse voltage is-15 V and 15 V, respectively. This reflects the write / erase speed of the transistor for storage, which is a core performance indicator of the memory. It can be seen from the results that the transistor memory can achieve a switching ratio of nearly 10 4 under a write voltage of 10 ns, and a complete write / erase of 10 8 switching ratio under a write / erase pulse of 1 μs, with extremely excellent erase / write speed.

[0087] Comparative Example 1

[0088] As Figure 14 , the edge contact field effect transistor prepared by the conventional photoresist blocking method is compared with the self-aligned edge contact field effect transistor prepared based on the stress limiting process of the application. Figure 14 (a)(c)(e) are data graphs of the edge contact field effect transistor prepared by the conventional photoresist blocking method, and (b)(d)(f) are data graphs of the self-aligned edge contact field effect transistor prepared based on the stress limiting process of the application. Among them, (a)(b) are optical microscope graphs after the transfer of each layer of material and the exposure of the to-be-inserted layer region. (c)(d) are data graphs obtained by Raman mapping characterization of the device after phase transition induction treatment by Li intercalation / insertion method. (e)(f) are the source-drain current changes of the two prepared field effect transistors with floating gate voltage, i.e. floating gate transfer characteristic curves.

[0089] from Figure 14(a)(b) can be seen in the traditional photoresist block method for preparing edge contact transistor, source and drain are at the same height with the channel, both above the floating gate layer, using stress limiting process based on the preparation of self-aligned edge contact transistor, with the help of the step structure formed by the physical edge of the floating gate material and the substrate, the floating gate layer is just above the semiconductor channel, the floating gate layer on both sides is the source and drain area to be phase transition, during phase transition, lithium ion 207 is embedded in MoS2 from the exposed window and diffuses around.

[0090] Figure 14 (c)(d) is the data graph obtained by Raman mapping characterization of the device after phase transition induced treatment by Li intercalation / intercalation method. Taking the area of semiconductor phase MoS2 characteristic peak as reference, brighter position indicates that MoS2 here is semiconductor phase, dark place indicates that there is no semiconductor phase MoS2 here, i.e. lithium ion 207 has induced MoS2 here to phase transition to metal phase, the interface between metal phase and semiconductor phase has been shown in the graph with white dotted line. From the graph, it can be seen that the traditional photoresist block method cannot effectively limit the diffusion of lithium ion 207, and lithium ion 207 has diffused beyond the photoresist block position to the middle channel area, and the metal phases on both sides have the tendency to connect together, and the phase transition interface is very rough. On the contrary, Figure 14 (d) in the graph, the phase transition interface is very sharp, and self-aligned with the edge of the floating gate layer below, which shows that the stress limiting process can effectively limit the diffusion of lithium ion 207, and prepare a sharp phase transition interface, and realize the self-alignment of semiconductor channel and floating gate layer in the field effect transistor structure.

[0091] Figure 14 (e)(f) are the floating gate transfer characteristics curves of the two prepared transistors, i.e. the change of source and drain current with floating gate voltage, the horizontal coordinate is the voltage applied to the floating gate layer, and the vertical coordinate is the source and drain current, which shows the regulation effect of floating gate layer on the middle semiconductor channel region. It can be concluded that the self-aligned edge contact transistor prepared based on stress limiting process has lower off-state current, lower subthreshold swing, and can realize higher on-off ratio, which reflects its high quality contact interface and better channel regulation effect. On the contrary, the edge contact transistor prepared by traditional photoresist block method is opposite, which is consistent with the rough phase transition interface and channel metal phase phase transition in (c).

[0092] In summary, the structure constructed in the embodiment is a self-aligned edge contact type field effect transistor of molybdenum disulfide / hexagonal boron nitride / few-layer graphene, the molybdenum disulfide near the source and drain is subjected to phase transition induction treatment by using lithium intercalation / intercalation method, so that it is changed into a metal phase, the step structure formed by the physical edge of the floating gate layer material and the substrate is used to accurately limit the phase transition behavior, so that the high-quality metal-semiconductor contact is realized on the basis of the preparation of sharp phase transition interface, and the transistor prepared has high storage window (the storage window reaches 30V under the back gate scanning of ±20V), high erasing speed (10ns writing, 1μs erasing), high on-off ratio (10 6 -10 8 ), low sub-threshold swing (the floating gate sub-threshold swing is about 80mv / dec), at the same time, the self-alignment of the semiconductor channel and the floating gate layer is realized, the uniformity of the device preparation is improved, and the array integration is facilitated.

[0093] Those skilled in the art can easily understand that the above description is only the preferred embodiment of the present application, and is not used to limit the present application, and any modification, equivalent replacement and improvement made within the spirit and principle of the present application should be included in the protection scope of the present application.

Claims

1. An edge contact type field effect transistor, characterized by, The edge-contact type field effect transistor comprises a substrate layer and a gate layer protruding from the surface of the substrate layer, a channel layer is arranged above the gate layer, the channel layer is arranged across the gate layer, so that the channel layer has a channel region above the gate layer, two electrode regions on the opposite sides of the gate layer, and a rising region connecting any of the electrode regions and the channel region, the material of the channel layer is a transition metal chalcogenide compound, and the electrode region is used to induce phase transition by lithium intercalation method to be converted into a metal phase to realize the edge contact of the metal phase and the semiconductor phase.

2. The edge contact field effect transistor of claim 1, wherein, The edge-contact type field effect transistor further comprises an insulating layer arranged between the gate layer and the channel layer, and the gate layer and the channel layer are separated by the insulating layer. The electrode region is connected with a metal electrode.

3. The edge contact field effect transistor of claim 1, wherein the gate electrode is formed of a material having a work function of 4.9 eV or more. When the transistor is a floating gate field effect transistor structure for storage, the gate layer is a floating gate layer.

4. The edge contact field effect transistor of claim 3, wherein the gate electrode is formed of a material having a work function of 4.9 eV or more. The floating gate layer is a graphene layer, the channel layer is a molybdenum sulfide layer, and the substrate layer is a silicon wafer with a silicon oxide layer.

5. The edge-contact field effect transistor according to any one of claims 1 to 4, wherein The electrode region is specifically subjected to lithium intercalation by being exposed to a n-butyllithium solution in at least a partial region, and lithium ions are intercalated into the electrode region to induce phase transition of the electrode region to be converted into a metal phase.

6. The edge-contact field effect transistor of claim 5, wherein the gate electrode is formed of a material having a work function of 4.9 eV or more. The height of the gate layer protruding from the substrate layer is 10-20 nm, the concentration of the n-butyllithium solution is 2-3 M, and the electrode region is exposed to the n-butyllithium solution for 1-3 h.

7. A method for manufacturing an edge contact type field effect transistor, characterized by, The preparation method of the edge-contact type field effect transistor comprises the following steps: The substrate layer is subjected to cleaning pretreatment; The gate layer is prepared on the surface of the substrate layer, wherein the gate layer is obtained by mechanical exfoliation; The channel layer is prepared on the surface of the substrate layer, the channel layer is arranged across the gate layer, so that the channel layer has a channel region above the gate layer, two electrode regions on the opposite sides of the gate layer, and a rising region connecting any of the electrode regions and the channel region, wherein the channel layer is obtained by mechanical exfoliation; A protective layer is arranged on the surface of the channel layer, wherein the protective layer covers the channel region and the rising region, and at least a partial region of the electrode region is in an exposed state; The device after the protective layer is arranged is immersed in a lithium solution to induce lithium intercalation, and is taken out after a preset time to obtain a transistor in which the electrode region is converted into a metal phase to realize the edge contact of the metal phase and the semiconductor phase.

8. The method for manufacturing an edge contact type field effect transistor according to claim 7, wherein After the gate layer is prepared on the surface of the substrate layer, the following step is further included before the channel layer is prepared: An insulating layer is prepared above the gate layer, wherein the insulating layer is obtained by mechanical exfoliation; Correspondingly, the channel layer is prepared above the insulating layer.

9. The method for manufacturing an edge contact type field effect transistor according to claim 7, wherein After the substrate layer is subjected to cleaning pretreatment, the following step is further included before the gate layer is prepared: A cross mark is prepared on the surface of the substrate layer to mark the position of the gate layer when the gate layer is prepared.

10. The method for manufacturing an edge contact type field effect transistor according to claim 7, wherein After the transistor in which the electrode region is converted into a metal phase is obtained, the following step is further included: A metal electrode is prepared on the electrode region by a metal thermal evaporation process.

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