Integrated gallium nitride and gallium oxide power chip, preparation method thereof and electronic equipment

Abstract

The invention provides an integrated gallium nitride and gallium oxide power chip, a preparation method thereof and electronic equipment, and relates to the technical field of semiconductors. According to the epitaxial structure in the integrated gallium nitride and gallium oxide power chip, a GaN layer and a Ga2O3 layer are integrated and epitaxially arranged on the same substrate, heteroepitaxial lattice mismatch is reduced by adopting a method of epitaxially extending the Ga2O3 layer on the GaN layer, and the crystal quality is improved. According to the epitaxial structure, a first functional component is formed on the first area, a second functional component is formed on the second area, the surface of the first area is the surface of the side, deviating from the substrate, of the barrier layer, the surface of the second area is the surface of the side, deviating from the substrate, of the Ga2O3 layer, and the aim that a Ga2O3 power chip and a GaN power chip are integrally arranged on the same substrate is achieved. The processes of lead interconnection, bonding and the like are reduced, the size of a wide bandgap semiconductor power system can be further reduced, and the problems of parasitic loss, response delay, noise and the like caused when discrete chips are integrated are avoided.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to an integrated gallium nitride and gallium oxide power chip and a preparation method thereof, and an electronic device. Background Art

[0002] Ga2O3 can effectively improve the voltage resistance of power chips and reduce on-resistance by virtue of its ultra-wide bandgap characteristics (4.8 eV ~ 5.1eV) and device quality factors (such as DC low-loss Baliga quality factor, etc.) and low defect density (at least three orders of magnitude lower than silicon carbide wafers). Therefore, Ga2O3 power chips can significantly improve the chip output current density and power density, and are expected to promote the rapid development of the next generation of high-voltage and high-power electronic devices. However, Ga2O3 materials have very low thermal conductivity and are prone to failure under high junction temperature conditions. In addition, Ga2O3 power chips are mostly used in the form of discrete devices. Multiple interconnections between chips can easily increase contact resistance, further accelerating the increase in chip temperature.

[0003] Similarly, GaN, which is a hot topic in power chip research together with Ga2O3, can achieve high gain, high power density and high power stability due to its wide bandgap and the high electron mobility and electron surface density of the heterojunction it forms. In addition, GaN power chips also have good temperature characteristics and greatly improve their performance in variable temperature environments, which enables them to achieve high-performance power control. However, GaN power chips currently exist in the form of discrete chips. Integrating GaN power chips into circuit systems through wire leads, bonding, etc. will inevitably introduce parasitic losses, response delays, noise and other problems, making it difficult to bring out the performance advantages of GaN chips in integrated circuits. Summary of the invention

[0004] In view of the above problems, the present application provides an integrated gallium nitride and gallium oxide power chip and its preparation method, and an electronic device, which integrates the Ga2O3 power chip and the GaN power chip on the same substrate, which can further reduce the volume of the wide bandgap semiconductor power system and avoid the problems of parasitic loss, response delay and noise introduced when integrating discrete chips. The specific solution is as follows:

[0005] In a first aspect, the present application provides an integrated gallium nitride and gallium oxide power chip, the integrated gallium nitride and gallium oxide power chip comprising:

[0006] substrate;

[0007] An epitaxial structure located on one side of the substrate; the epitaxial structure comprises: a GaN channel layer, a barrier layer, a first Ga2O3 layer and a second Ga2O3 layer located on one side of the substrate in sequence in a first direction, the doping concentration of the first Ga2O3 layer being greater than the doping concentration of the second Ga2O3 layer; the first direction is perpendicular to the plane where the substrate is located, and points from the substrate to the GaN channel layer;

[0008] The epitaxial structure comprises a first region and a second region, the surface of the first region is the surface of the barrier layer facing away from the substrate, and the surface of the second region is partly the surface of the first Ga2O3 layer facing away from the substrate, and partly the surface of the second Ga2O3 layer facing away from the substrate;

[0009] A first functional component is arranged on the first region, and a second functional component is arranged on the second region; wherein the epitaxial structure corresponding to the first functional component and the first region constitutes a GaN power chip, and the epitaxial structure corresponding to the second functional component and the second region constitutes a Ga2O3 power chip.

[0010] Preferably, in the above-mentioned integrated gallium nitride and gallium oxide power chip, the integrated gallium nitride and gallium oxide power chip further comprises:

[0011] An isolation region is located between the first region and the second region.

[0012] Preferably, in the above-mentioned integrated gallium nitride and gallium oxide power chip, the first functional component includes:

[0013] A source electrode, a drain electrode and a gate electrode are located on a side of the barrier layer away from the substrate, and the source electrode and the drain electrode are located on both sides of the gate electrode.

[0014] Preferably, in the above integrated gallium nitride and gallium oxide power chip, the source electrode, the drain electrode and the barrier layer form an ohmic contact, and the gate electrode and the barrier layer form a Schottky contact.

[0015] Preferably, in the above-mentioned integrated gallium nitride and gallium oxide power chip, the second functional component includes:

[0016] a cathode located on a side of the first Ga2O3 layer facing away from the substrate;

[0017] An anode is located on a side of the second Ga2O3 layer facing away from the substrate.

[0018] Preferably, in the above-mentioned integrated gallium nitride and gallium oxide power chip, the integrated gallium nitride and gallium oxide power chip further comprises:

[0019] A passivation layer is located on a side of the epitaxial structure facing away from the substrate.

[0020] Preferably, in the above-mentioned integrated gallium nitride and gallium oxide power chip, the integrated gallium nitride and gallium oxide power chip further comprises:

[0021] A first pad, a second pad, a third pad, a fourth pad and a fifth pad located on a side of the passivation layer away from the substrate;

[0022] Among them, the first pad is connected to the source through a through hole penetrating the passivation layer; the second pad is connected to the gate through a through hole penetrating the passivation layer; the third pad is connected to the drain through a through hole penetrating the passivation layer; the fourth pad is connected to the anode through a through hole penetrating the passivation layer; and the fifth pad is connected to the cathode through a through hole penetrating the passivation layer.

[0023] Preferably, in the above-mentioned integrated gallium nitride and gallium oxide power chip, the third pad and the fourth pad are an integrally formed pad structure.

[0024] A second aspect of the present application provides a method for preparing an integrated gallium nitride and gallium oxide power chip, the method for preparing an integrated gallium nitride and gallium oxide power chip comprising:

[0025] providing a substrate;

[0026] An epitaxial structure is formed on one side of the substrate; the epitaxial structure comprises: a GaN channel layer, a barrier layer, a first Ga2O3 layer and a second Ga2O3 layer sequentially located on one side of the substrate in a first direction, the doping concentration of the first Ga2O3 layer being greater than the doping concentration of the second Ga2O3 layer; the first direction is perpendicular to the plane where the substrate is located, and points from the substrate to the GaN channel layer; the epitaxial structure comprises a first region and a second region, the surface of the first region is the surface of the barrier layer facing away from the substrate, and the surface of the second region is partly the surface of the first Ga2O3 layer facing away from the substrate, and partly the surface of the second Ga2O3 layer facing away from the substrate;

[0027] A first functional component is formed on the first region, and a second functional component is formed on the second region; wherein the epitaxial structure corresponding to the first functional component and the first region constitutes a GaN power chip, and the epitaxial structure corresponding to the second functional component and the second region constitutes a Ga2O3 power chip.

[0028] A third aspect of the present application provides an electronic device, comprising the integrated gallium nitride and gallium oxide power chip as described in any one of the above items.

[0029] By means of the above technical scheme, the present application provides an integrated gallium nitride and gallium oxide power chip and its preparation method and electronic device. The epitaxial structure in the integrated gallium nitride and gallium oxide power chip is to integrate the GaN layer and the Ga2O3 layer on the same substrate, and the method of epitaxially growing the Ga2O3 layer on the GaN layer is adopted to reduce the heteroepitaxial lattice mismatch and improve the crystal quality. Based on the epitaxial structure, a first functional component is formed on the first region, and a second functional component is formed on the second region. The surface of the first region is the surface of the barrier layer facing away from the substrate, and the surface of the second region is the surface of the Ga2O3 layer facing away from the substrate. The purpose of integrating the Ga2O3 power chip and the GaN power chip on the same substrate is achieved, and the processes such as wire interconnection and bonding are reduced. The volume of the wide bandgap semiconductor power system can be further reduced, and the problems of parasitic loss, response delay and noise introduced when discrete chips are integrated can be avoided. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] The above and other features, advantages and aspects of the embodiments of the present disclosure will become more apparent with reference to the following detailed description in conjunction with the accompanying drawings. Throughout the accompanying drawings, the same or similar reference numerals represent the same or similar elements. It should be understood that the drawings are schematic and the originals and elements are not necessarily drawn to scale.

[0031] Figure 1 A schematic diagram of the structure of an integrated gallium nitride and gallium oxide power chip provided in an embodiment of the present invention;

[0032] Figure 2 A schematic diagram of the structure of another integrated gallium nitride and gallium oxide power chip provided in an embodiment of the present invention;

[0033] Figure 3 A schematic diagram of the structure of another integrated gallium nitride and gallium oxide power chip provided in an embodiment of the present invention;

[0034] Figure 4 A schematic flow chart of a method for preparing an integrated gallium nitride and gallium oxide power chip provided in an embodiment of the present invention. DETAILED DESCRIPTION

[0035] The embodiments of the present application are described below in conjunction with the drawings in the embodiments of the present application. The terms used in the implementation mode of the present application are only used to explain the specific embodiments of the present application, and are not intended to limit the present application. It is known to those skilled in the art that with the development of technology and the emergence of new scenarios, the technical solutions provided in the embodiments of the present application are also applicable to similar technical problems.

[0036] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, the present invention is further described in detail below with reference to the accompanying drawings and specific embodiments.

[0037] It should be noted that the directional words appearing in the present invention are based on the relative position relationship shown in the drawings and cannot be used as an absolute limitation to the present application.

[0038] refer to Figure 1 , Figure 1 The schematic diagram of the structure of an integrated gallium nitride and gallium oxide power chip provided by an embodiment of the present invention. The integrated power device provided by an embodiment of the present invention includes: a substrate 11.

[0039] An epitaxial structure located on one side of the substrate 11; the epitaxial structure includes: a GaN channel layer 12, a barrier layer 13, a first Ga2O3 layer 14 and a second Ga2O3 layer 15 located in sequence on one side of the substrate 11 in a first direction, the doping concentration of the first Ga2O3 layer 14 is greater than the doping concentration of the second Ga2O3 layer 15; the first direction is perpendicular to the plane where the substrate 11 is located, and points from the substrate 11 to the GaN channel layer 12.

[0040] The epitaxial structure includes a first region AA and a second region BB, wherein the surface of the first region AA is the surface of the barrier layer 13 facing away from the substrate 11, and the surface of the second region BB is partially the surface of the first Ga2O3 layer 14 facing away from the substrate 11, and partially the surface of the second Ga2O3 layer 15 facing away from the substrate 11.

[0041] A first functional component is arranged on the first area AA, and a second functional component is arranged on the second area BB; wherein the first functional component and the epitaxial structure corresponding to the first area AA constitute a GaN power chip, and the second functional component and the epitaxial structure corresponding to the second area BB constitute a Ga2O3 power chip. The first functional component is a functional component required for preparing a GaN power chip, and the second functional component is a functional component required for preparing a Ga2O3 power chip.

[0042] The epitaxial structure corresponding to the first region AA includes: a GaN channel layer 12 and a barrier layer 13 ; the epitaxial structure corresponding to the second region BB includes: a GaN channel layer 12 , a barrier layer 13 , a first Ga2O3 layer 14 and a second Ga2O3 layer 15 .

[0043] Specifically, in the embodiment of the present invention, the substrate 11 includes but is not limited to at least one of a silicon substrate, a sapphire substrate, a silicon carbide substrate, and a diamond substrate.

[0044] The thickness of the GaN channel layer 12 is in the range of 0.5 μm to 15 μm. For example, the thickness of the GaN channel layer 12 may be 0.5 μm, 8 μm, or 15 μm.

[0045] The barrier layer 13 includes but is not limited to at least one of a single-layer AlN layer, a single-layer AlGaN layer, a single-layer InAlGaN layer, a single-layer InAlN layer, and an AlN / GaN superlattice structure. The thickness of the barrier layer 13 ranges from 2nm to 40nm. Exemplarily, the thickness of the barrier layer 13 is 2nm, 20.5nm, 34.5nm, or 40nm.

[0046] The doping elements of the first Ga2O3 layer 14 and the second Ga2O3 layer 15 are Si, Sn or Ge, etc. The source used in the preparation process of the first Ga2O3 layer 14 and the second Ga2O3 layer 15 is SiH4, etc. The thickness of the first Ga2O3 layer 14 is in the range of 0.1μm-5μm. Exemplarily, the thickness of the first Ga2O3 layer 14 is 0.1μm, 2.6μm or 5μm, etc. The thickness of the second Ga2O3 layer 15 is in the range of 0.1μm-5μm. Exemplarily, the thickness of the second Ga2O3 layer 15 is 0.1μm, 3.7μm or 5μm, etc.

[0047] The doping concentration of the first Ga2O3 layer 14 is greater than or equal to 1×10 18 / cm 3 The doping concentration of the second Ga2O3 layer 15 is greater than or equal to 1×10 15 / cm 3 , and less than 1×10 18 / cm 3 .

[0048] During the invention process of the present application, it was found that the heteroepitaxial growth of a Ga2O3 layer on a high thermal conductivity substrate is limited by the substrate lattice mismatch, and it is usually difficult to achieve a high-quality Ga2O3 layer, which in turn affects the chip performance.

[0049] Based on this, in the embodiment of the present application, the heteroepitaxial growth of the GaN layer 12 is first performed on the high thermal conductivity substrate 11, and then the heteroepitaxial Ga2O3 layer (including the first Ga2O3 layer 14 and the second Ga2O3 layer 15) is heteroepitaxially grown on the GaN layer 12, so as to achieve the purpose of integrating the GaN layer 12 and the Ga2O3 layer on the same substrate 11. And the method of heteroepitaxially growing the Ga2O3 layer on the GaN layer 12 can reduce the heteroepitaxial lattice mismatch and improve the crystal quality. Among them, the lattice mismatch between the GaN layer 12 and the Ga2O3 layer is only 2.6%, which is better than high thermal conductivity substrates such as SiC, Si and sapphire. The epitaxial structure integrates a variety of wide bandgap semiconductor materials in an epitaxial manner, which can simplify the material preparation process. The preparation process of the epitaxial structure is simple and efficient, laying the foundation for the monolithic integration of wide bandgap power semiconductor systems.

[0050] Furthermore, in an embodiment of the present invention, a first functional component is formed on the first area AA based on the epitaxial structure, and a second functional component is formed on the second area BB. The surface of the first area AA is the surface of the barrier layer 13 facing away from the substrate 11, and the surface of the second area BB is the surface of the Ga2O3 layer facing away from the substrate 11. The purpose of integrating the Ga2O3 power chip and the GaN power chip on the same substrate 11 is achieved, and processes such as wire interconnection and bonding are reduced. The volume of the wide bandgap semiconductor power system can be further reduced, and problems such as parasitic loss, response delay and noise introduced when discrete chips are integrated can be avoided.

[0051] That is to say, in the prior art, the applicant has found that the integration of circuit systems requires the circuit connection of multiple discrete chips, and the interconnection of discrete chips is mostly done by bonding, wire bonding, etc. At the bonding interface, the wire contact interface is prone to generate contact resistance and parasitic capacitance, etc., resulting in increased circuit system losses, delay effects, etc. In the embodiment of the present application, the monolithic integration preparation of different wide bandgap semiconductor chips on the same substrate 11 is realized, which can further reduce the volume of the wide bandgap semiconductor power system and avoid the introduction of parasitic losses, response delays, noise, and other problems when integrating discrete chips.

[0052] In an optional embodiment of the present invention, Figure 1 As shown, the first functional component includes:

[0053] The source 16 , the drain 17 and the gate 18 are located on the side of the barrier layer 13 away from the substrate 11 . The source 16 and the drain 17 are located on both sides of the gate 18 .

[0054] Specifically, in the embodiments of the present invention, a GaN power chip is a high electron mobility transistor (HEMT) as an example for description.

[0055] The source electrode 16 and the drain electrode 17 form an ohmic contact with the barrier layer 13 , and the gate electrode 18 forms a Schottky contact with the barrier layer 13 , so as to achieve better electrical connection and improve the working performance of the GaN power chip.

[0056] In an optional embodiment of the present invention, Figure 1 As shown, the second functional component includes:

[0057] A cathode 19 is located on a side of the first Ga2O3 layer 14 facing away from the substrate 11.

[0058] The anode 20 is located on the side of the second Ga2O3 layer 15 facing away from the substrate 11.

[0059] Specifically, in the embodiment of the present invention, the Ga2O3 power chip is taken as an example of a Schottky Barrier Diode (SBD).

[0060] In an optional embodiment of the present invention, Figure 1 As shown, the integrated gallium nitride and gallium oxide power chip also includes:

[0061] A passivation layer 21 is located on a side of the epitaxial structure away from the substrate 11 .

[0062] Specifically, in the embodiment of the present invention, the passivation layer 21 covers the source 16, the drain 17, the gate 18, the cathode 19 and the anode 20, so as to realize the passivation protection of the integrated power chip and the isolation between the components. Exemplarily, the passivation layer 21 is covered between the source 16 and the gate 18 and between the drain 17 and the gate 18.

[0063] It should be noted that the material of the passivation layer 21 can be SiO 2 or SiN x or other materials with passivation effect, which is not limited in the embodiment of the present invention.

[0064] In an optional embodiment of the present invention, Figure 1 As shown, the integrated gallium nitride and gallium oxide power chip also includes:

[0065] A first pad 22 , a second pad 23 , a third pad 24 , a fourth pad 25 and a fifth pad 26 are located on a side of the passivation layer 21 away from the substrate 11 .

[0066] Among them, the first pad 22 is connected to the source electrode 16 through a through hole penetrating the passivation layer 21; the second pad 23 is connected to the gate electrode 18 through a through hole penetrating the passivation layer 21; the third pad 24 is connected to the drain electrode 17 through a through hole penetrating the passivation layer 21; the fourth pad 25 is connected to the anode 20 through a through hole penetrating the passivation layer 21; the fifth pad 26 is connected to the cathode 19 through a through hole penetrating the passivation layer 21.

[0067] Specifically, in the embodiment of the present invention, a pad is provided on the surface of the passivation layer 21 facing away from the substrate 11 to externally lead the source 16, drain 17, gate 18, cathode 19 and anode 20 to achieve electrical connection between the integrated power chip and other chips.

[0068] refer to Figure 2 , Figure 2A schematic diagram of another structure of an integrated gallium nitride and gallium oxide power chip provided by an embodiment of the present invention. In the integrated gallium nitride and gallium oxide power chip provided by an embodiment of the present invention, the third pad 24 and the fourth pad 25 are an integrally formed pad structure 27.

[0069] That is to say, the GaN power chip and the Ga2O3 power chip in the integrated gallium nitride and gallium oxide power chip provided in the embodiment of the present invention are electrically connected through the integrally formed pad structure 27. When the Ga2O3 power chip and the GaN power chip are integrated on the same substrate 11, the wire interconnection and bonding processes required for the discrete chips are reduced, the volume of the wide bandgap semiconductor power system can be further reduced, and the problems of parasitic loss, response delay and noise introduced when the discrete chips are integrated can be avoided.

[0070] In an optional embodiment of the present invention, reference Figure 3 , Figure 3 A schematic diagram of the structure of another integrated gallium nitride and gallium oxide power chip provided by an embodiment of the present invention. The epitaxial structure provided by an embodiment of the present invention also includes:

[0071] A nucleation layer 28 and a buffer layer 29 are located between the substrate 11 and the GaN channel layer 12 and are sequentially stacked in the first direction.

[0072] Specifically, in the embodiment of the present invention, the nucleation layer 28 includes but is not limited to at least one of an AlN layer, a GaN layer, and an AlGaN layer. The thickness of the nucleation layer 28 ranges from 5 nm to 500 nm. Exemplarily, the thickness of the nucleation layer 28 is 5 nm, 20.5 nm, 30 nm, 200 nm, 316 nm, 500 nm, etc.

[0073] The buffer layer 29 includes but is not limited to a single AlN layer, a single GaN layer, a single InGaN layer, a single AlGaN layer, an AlN / GaN superlattice structure, an AlN / AlGaN superlattice structure, or a multi-layer AlGaN layer with different Al components and a variety of nitride layers. The thickness of the buffer layer 29 ranges from 0.02 μm to 3 μm. Exemplarily, the thickness of the buffer layer 29 ranges from 0.02 μm, 1.5 μm, or 3 μm, etc.

[0074] Further, such as Figure 1-Figure 3 As shown, the integrated gallium nitride and gallium oxide power chip provided in the embodiment of the present invention further includes: an isolation region CC located between the first region AA and the second region BB to achieve isolation of the GaN power chip and the Ga2O3 power chip. The isolation region can be achieved by ion implantation.

[0075] Based on the above embodiments of the present invention, another embodiment of the present invention further provides a method for preparing an integrated gallium nitride and gallium oxide power chip, referring to Figure 4 , Figure 4 A schematic diagram of a process for preparing a method for an integrated gallium nitride and gallium oxide power chip provided in an embodiment of the present invention. The method for preparing an integrated gallium nitride and gallium oxide power chip provided in an embodiment of the present invention comprises:

[0076] S101: providing a substrate 11.

[0077] Specifically, the substrate 11 includes but is not limited to at least one of a silicon substrate, a sapphire substrate, a silicon carbide substrate, and a diamond substrate. It should be noted that the substrate 11 may also be other substrates with high thermal conductivity, which is not limited in the embodiment of the present invention.

[0078] S102: forming an epitaxial structure on one side of the substrate 11; the epitaxial structure comprises: a GaN channel layer 12, a barrier layer 13, a first Ga2O3 layer 14 and a second Ga2O3 layer 15 which are sequentially located on one side of the substrate in a first direction, and the doping concentration of the first Ga2O3 layer 14 is greater than the doping concentration of the second Ga2O3 layer 15; the first direction is perpendicular to the plane where the substrate 11 is located, and points from the substrate 11 to the GaN channel layer 12; the epitaxial structure comprises a first region AA and a second region BB, the surface of the first region AA is the surface of the barrier layer 13 on the side facing away from the substrate 11, and the surface of the second region BB is partly the surface of the first Ga2O3 layer 14 on the side facing away from the substrate 11, and partly the surface of the second Ga2O3 layer 15 on the side facing away from the substrate 11.

[0079] S103: forming a first functional component on the first area AA, and forming a second functional component on the second area BB; wherein the first functional component and the epitaxial structure corresponding to the first area AA constitute a GaN power chip, and the second functional component and the epitaxial structure corresponding to the second area BB constitute a Ga2O3 power chip.

[0080] Specifically, it includes but is not limited to the method of using MOCVD to sequentially grow a nucleation layer 28, a buffer layer 29, a GaN channel layer 12, a barrier layer 13, a first Ga2O3 layer 14, and a second Ga2O3 layer 15 on the substrate 11. Exemplarily, an AlN nucleation layer with a thickness of 200 nm, a GaN buffer layer with a thickness of 3 μm, a GaN channel layer 12 with a thickness of 200 nm, an AlGaN barrier layer with a thickness of 20 nm, a first Ga2O3 layer 13 with a thickness of 1 μm, and a second Ga2O3 layer 14 with a thickness of 1 μm are sequentially grown on the substrate 11 by using MOCVD.

[0081] In an optional embodiment of the present invention, trimethylgallium is used as a gallium source, trimethylaluminum is used as an aluminum source, high-purity oxygen is used as an oxygen source, high-purity argon is used as a carrier gas for the MO source, silane is used as a silicon doping source during the thin film growth process, and ammonia is used as a nitrogen source. On a silicon carbide substrate, in a growth environment with a chamber pressure of 50 torr, a growth temperature of 1100°C, and an aluminum source flow rate of 100 sccm, an AlN nucleation layer with a thickness of 0.02 μm is grown; in a growth environment with a chamber pressure of 200 torr, a growth temperature of 1080°C, and a gallium source flow rate of 650 sccm, a GaN buffer layer with a thickness of 1.5 μm is grown; in a growth environment with a chamber pressure of 150 torr, a growth temperature of 1060°C, and a gallium source flow rate of 650 sccm, a GaN channel layer 12 with a thickness of 0.15 μm is grown; in a growth environment with a chamber pressure of 50 torr, a growth temperature of 1060°C, and a gallium source flow rate of 650 sccm, a GaN channel layer 12 with a thickness of 0.15 μm is grown. rr, in a growth environment with a growth temperature of 1100°C and an aluminum source flow rate of 100sccm, an AlN barrier layer with a thickness of 0.005μm is grown; in a growth environment with an oxygen flow rate of 2800sccm, a growth temperature of 750°C, and a SiH4 flow rate of 150sccm, a first Ga2O3 layer 14 with a thickness of 0.5μm is grown; in a growth environment with an oxygen flow rate of 2800sccm, a growth temperature of 850°C, and a SiH4 flow rate of 90sccm, a second Ga2O3 layer 15 with a thickness of 1μm is grown; after the growth is completed, the temperature is cooled to room temperature to complete the preparation of the epitaxial structure.

[0082] After the epitaxial structure is cleaned, a first area AA and a second area BB are defined by photolithography, wherein the first area AA is the area where the GaN power chip is located, and the second area BB is the area where the Ga2O3 power chip is located. Based on the second area BB, a mixed gas of BCl3 and Ar is used, including but not limited to, to perform RIE etching on the second Ga2O3 layer 15 until a portion of the surface of the first Ga2O3 layer 14 is exposed.

[0083] A cathode 19 is formed on the side of the first Ga2O3 layer 14 away from the substrate 11, and an anode 20 is formed on the side of the second Ga2O3 layer 15 away from the substrate 11. The anode 20 may be a stacked structure of a Ti layer and an Au layer, and the cathode 19 may be a stacked structure of a Ti layer and an Au layer. In an optional embodiment of the present invention, the thickness of the Ti layer may be 20 nm, and the thickness of the Au layer may be 120 nm.

[0084] The hard mask deposition is performed, including but not limited to etching the first Ga2O3 layer 14 and the second Ga2O3 layer 15 of the first region AA pair by dry etching until the surface of the barrier layer 13 is exposed.

[0085] After removing the hard mask, an isolation region CC is formed by, but not limited to, photolithography and ion implantation to isolate the GaN power chip from the Ga2O3 power chip. The depth of the isolation region CC may be 3.5 μm.

[0086] A passivation layer 21 is deposited, and the passivation layer 21 may be a SiNx layer with a thickness of 0.5 μm.

[0087] The passivation layer 21 is etched to form a first through hole and a second through hole, wherein the first through hole and the second through hole expose a portion of the surface of the barrier layer 13 .

[0088] A source electrode 16 is formed on the surface of the barrier layer 13 based on the first through hole; a drain electrode 17 is formed on the surface of the barrier layer 13 based on the second through hole. The source electrode 16 and the drain electrode 17 are in ohmic contact with the barrier layer 13, respectively. In an optional embodiment of the present invention, it includes but is not limited to the method of depositing ohmic metal by electron beam evaporation, and forming the source electrode 16 and the drain electrode 17 after peeling and laser annealing. The source electrode 16 can be a stacked structure of a Ti layer, an Al layer, a Ni layer and an Au layer. The drain electrode 17 can also be a stacked structure of a Ti layer, an Al layer, a Ni layer and an Au layer. The thickness of the Ti layer can be 20nm, the thickness of the Al layer can be 120nm, the thickness of the Ni layer can be 40nm, and the thickness of the Au layer can be 50nm.

[0089] The method includes but is not limited to removing the passivation layer 21 by chemical etching to form the third through hole, wherein the third through hole exposes a portion of the surface of the barrier layer 13 .

[0090] A gate 18 is formed on the surface of the barrier layer 13 based on the third through hole. The gate 18 forms a Schottky contact with the barrier layer 13. The gate 18 may be a stacked structure of a Ni layer and an Au layer, the Ni layer may be 60 nm thick, and the Au layer may be 100 nm thick.

[0091] A passivation layer 21 of a certain thickness is further deposited on the basis of the passivation layer 21, and then each electrode window is opened through processes including but not limited to photolithography and etching to prepare a pad structure to realize the externalization of the source 16, drain 17, gate 18, cathode 19 and anode 20 to achieve electrical connection between the integrated power chip and other chips.

[0092] The preparation method of the integrated gallium nitride and gallium oxide power chip is applicable to the device preparation process of traditional integrated circuits, does not increase the additional device preparation cost, and lays the foundation for the monolithic integration of wide bandgap power semiconductor systems. The prepared integrated gallium nitride and gallium oxide power chips can be widely used in various high-power demand system modules such as industrial power grids, new energy power conversion, and data center power conversion.

[0093] Based on the above embodiment of the present invention, another embodiment of the present invention further provides an electronic device, which includes the integrated gallium nitride and gallium oxide power chip described in the above embodiment.

[0094] In general, the technical solution of the present application solves the problems of increased loss and delay effect caused by the integration of Ga2O3 discrete chips and GaN discrete chips by epitaxially growing a GaN layer 12 and a Ga2O3 layer on the same substrate 11 and preparing a corresponding power chip.

[0095] The above is a detailed introduction to an integrated gallium nitride and gallium oxide power chip and a preparation method and an electronic device provided by the present invention. Specific examples are used in this article to illustrate the principles and implementation methods of the present invention. The description of the above embodiments is only used to help understand the method of the present invention and its core idea. At the same time, for those skilled in the art, according to the idea of ​​the present invention, there will be changes in the specific implementation methods and application scopes. In summary, the content of this specification should not be understood as limiting the present invention.

[0096] It should be noted that each embodiment in this specification is described in a progressive manner, and each embodiment focuses on the differences from other embodiments, and the same or similar parts between the embodiments can be referred to each other. For the device disclosed in the embodiment, since it corresponds to the method disclosed in the embodiment, the description is relatively simple, and the relevant parts can be referred to the method part description.

[0097] It should also be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that the process, method, article or device that includes a series of elements is inherent to the elements, or also includes elements inherent to these processes, methods, articles or devices. In the absence of further restrictions, the elements defined by the sentence "including a..." do not exclude the presence of other identical elements in the process, method, article or device that includes the elements.

[0098] The above description of the disclosed embodiments enables one skilled in the art to implement or use the present invention. Various modifications to these embodiments will be apparent to one skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present invention. Therefore, the present invention will not be limited to the embodiments shown herein, but rather to the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. An integrated gallium nitride and gallium oxide power chip, characterized in that: The integrated gallium nitride and gallium oxide power chip comprises: substrate; An epitaxial structure located on one side of the substrate; the epitaxial structure comprises: a GaN channel layer, a barrier layer, a first Ga2O3 layer and a second Ga2O3 layer located on one side of the substrate in sequence in a first direction, the doping concentration of the first Ga2O3 layer being greater than the doping concentration of the second Ga2O3 layer; the first direction is perpendicular to the plane where the substrate is located, and points from the substrate to the GaN channel layer; The epitaxial structure comprises a first region and a second region, the surface of the first region is the surface of the barrier layer facing away from the substrate, and the surface of the second region is partly the surface of the first Ga2O3 layer facing away from the substrate, and partly the surface of the second Ga2O3 layer facing away from the substrate; A first functional component is arranged on the first region, and a second functional component is arranged on the second region; wherein the epitaxial structure corresponding to the first functional component and the first region constitutes a GaN power chip, and the epitaxial structure corresponding to the second functional component and the second region constitutes a Ga2O3 power chip.

2. The integrated gallium nitride and gallium oxide power chip according to claim 1, characterized in that: The integrated gallium nitride and gallium oxide power chip also includes: An isolation region is located between the first region and the second region.

3. The integrated gallium nitride and gallium oxide power chip according to claim 1, characterized in that: The first functional component comprises: A source electrode, a drain electrode and a gate electrode are located on a side of the barrier layer away from the substrate, and the source electrode and the drain electrode are located on both sides of the gate electrode.

4. The integrated gallium nitride and gallium oxide power chip according to claim 3, characterized in that: The source electrode, the drain electrode and the barrier layer form an ohmic contact, and the gate electrode and the barrier layer form a Schottky contact.

5. The integrated gallium nitride and gallium oxide power chip according to claim 3 or 4, characterized in that: The second functional component comprises: a cathode located on a side of the first Ga2O3 layer facing away from the substrate; An anode is located on a side of the second Ga2O3 layer facing away from the substrate.

6. The integrated gallium nitride and gallium oxide power chip according to claim 5, characterized in that: The integrated gallium nitride and gallium oxide power chip also includes: A passivation layer is located on a side of the epitaxial structure facing away from the substrate.

7. The integrated gallium nitride and gallium oxide power chip according to claim 6, characterized in that: The integrated gallium nitride and gallium oxide power chip also includes: A first pad, a second pad, a third pad, a fourth pad and a fifth pad located on a side of the passivation layer away from the substrate; Among them, the first pad is connected to the source through a through hole penetrating the passivation layer; the second pad is connected to the gate through a through hole penetrating the passivation layer; the third pad is connected to the drain through a through hole penetrating the passivation layer; the fourth pad is connected to the anode through a through hole penetrating the passivation layer; and the fifth pad is connected to the cathode through a through hole penetrating the passivation layer.

8. The integrated gallium nitride and gallium oxide power chip according to claim 7, characterized in that: The third pad and the fourth pad are an integrally formed pad structure.

9. A method for preparing an integrated gallium nitride and gallium oxide power chip, characterized in that: The method for preparing the integrated gallium nitride and gallium oxide power chip comprises: providing a substrate; An epitaxial structure is formed on one side of the substrate; the epitaxial structure comprises: a GaN channel layer, a barrier layer, a first Ga2O3 layer and a second Ga2O3 layer sequentially located on one side of the substrate in a first direction, the doping concentration of the first Ga2O3 layer being greater than the doping concentration of the second Ga2O3 layer; the first direction is perpendicular to the plane where the substrate is located, and points from the substrate to the GaN channel layer; the epitaxial structure comprises a first region and a second region, the surface of the first region is the surface of the barrier layer facing away from the substrate, and the surface of the second region is partly the surface of the first Ga2O3 layer facing away from the substrate, and partly the surface of the second Ga2O3 layer facing away from the substrate; A first functional component is formed on the first region, and a second functional component is formed on the second region; wherein the epitaxial structure corresponding to the first functional component and the first region constitutes a GaN power chip, and the epitaxial structure corresponding to the second functional component and the second region constitutes a Ga2O3 power chip.

10. An electronic device, characterized in that: The electronic device comprises the integrated gallium nitride and gallium oxide power chip according to any one of claims 1 to 8.

Images