Solar cells and photovoltaic modules

Abstract

The present application provides a solar cell and a photovoltaic module, belonging to the technical field of semiconductor devices. The solar cell of the present application includes: a semiconductor substrate, including a first surface having a plurality of first texture structures, along the direction away from the first surface, the first texture structure includes a bottom surface, a side surface and a top surface, and the side surface is located between the bottom surface and the top surface; a tunneling layer, located on the first surface of the semiconductor substrate, and the thickness of the tunneling layer located on the top surface and / or the bottom surface is greater than the thickness of the tunneling layer located on the side surface; and a doped semiconductor layer, located on the surface of the tunneling layer away from the semiconductor substrate.

Description

Technical Field

[0001] This application relates to the technical field of photovoltaic cells. Specifically, this application relates to a solar cell and a photovoltaic module. Background Art

[0002] Different passivated contact schemes are increasingly applied to solar cells to improve the cell conversion efficiency. Among them, the tunneling passivated contact technology can achieve excellent surface passivation and carrier selective collection. It usually deposits a tunneling layer and a doped semiconductor layer on the surface of the cell, and the tunneling layer and the doped semiconductor layer together form a tunneling passivated contact structure to achieve the passivation effect.

[0003] Generally, for the light trapping ability of the cell surface, the cell surface usually has an uneven microstructure. However, there is still room for improvement in how to form a well - contacted tunneling passivated contact structure on the microstructure. Summary of the Invention

[0004] In view of this, in order to at least partially solve at least one of the above - mentioned technical problems, this application provides a solar cell and a photovoltaic module.

[0005] To achieve the above object, the technical solution of this application is as follows.

[0006] According to an embodiment of one aspect of this application, a solar cell is provided, including: a semiconductor substrate, including a first surface having a plurality of first texture structures. Along the direction away from the first surface, the first texture structure includes a bottom surface, a side surface, and a top surface, and the side surface is located between the bottom surface and the top surface; a tunneling layer, located on the first surface of the semiconductor substrate, and the thickness of the tunneling layer located on the top surface and / or the bottom surface is greater than the thickness of the tunneling layer located on the side surface; and a doped semiconductor layer, located on the surface of the tunneling layer away from the semiconductor substrate.

[0007] According to an embodiment of another aspect of this application, a photovoltaic module is provided, including: a plurality of the above - mentioned solar cells connected into a solar cell string; and a packaging structure surrounding the outer periphery of the solar cell string.

[0008] In an embodiment of the present application, a tunneling layer is deposited on a semiconductor substrate, and a doped semiconductor layer is deposited on the tunneling layer. The semiconductor substrate includes a first surface having a plurality of first texture structures. Among them, the thickness of the tunneling layer deposited on the top surface and / or bottom surface of the first texture structure is greater than the thickness of the tunneling layer deposited on the side surface, which results in different interface state densities between the tunneling layer and the semiconductor substrate on the top, bottom, and side surfaces. Specifically, on the top surface or the bottom surface, setting a thicker tunneling layer is more conducive to reducing the interface state density between the tunneling layer and the semiconductor substrate, thereby being more conducive to improving the passivation effect. Together with the tunneling passivation structure formed by the doped polysilicon layer, the passivation effect on the surface of the silicon substrate can be further improved; on the side surface, setting a thinner tunneling layer is more conducive to retaining the conductive channel, thereby being more conducive to reducing the contact resistance. By having different thicknesses of the tunneling layer on the top, bottom, and side surfaces of the first texture structure, the balance and improvement of passivation and contact performance can be achieved simultaneously.

[0009] In an embodiment of the present application, when the solar cell and the photovoltaic module of the present application use the selective passivation contact structure provided by the present application, it helps to improve the passivation contact effect and the electrical transmission effect, thereby enhancing the photoelectric conversion efficiency of the solar cell and the photovoltaic module. Description of the Drawings

[0010] Through the following description of the embodiments of the present application with reference to the drawings, the above and other objects, features, and advantages of the present application will become clearer. In the drawings:

[0011] Figure 1 It is a schematic structural diagram of the solar cell according to the embodiment of the present application;

[0012] Figure 2 It is a side view schematic diagram of the first texture structure according to the embodiment of the present application;

[0013] Figure 3 It is a transmission electron microscope (TEM) image of a partial cross-section of the solar cell according to the embodiment of the present application;

[0014] Figure 4 It is a TEM image of the top surface cross-section of the first texture structure according to the embodiment of the present application;

[0015] Figure 5 It is a TEM image of the side surface cross-section of the first texture structure according to the embodiment of the present application;

[0016] Figure 6 It is a side view schematic diagram of the convex structure of the first texture structure according to the embodiment of the present application;

[0017] Figure 7 It is a method flow chart of the solar cell according to the embodiment of the present application;

[0018] Figure 8 Schematic structural diagram of a solar cell according to another embodiment of the present application;

[0019] Figure 9 Schematic structural diagram of a solar cell according to still another embodiment of the present application. Detailed implementation manners

[0020] In order to make the objectives, technical solutions and advantages of the present application more clear and understandable, the present application will be further described in detail below with reference to specific embodiments and the accompanying drawings.

[0021] The terms used herein are only for describing specific embodiments and are not intended to limit the present application. The terms "including", "comprising", etc. used herein indicate the presence of features, steps, operations and / or components, but do not exclude the presence or addition of one or more other features, steps, operations or components. All terms (including technical and scientific terms) used herein have the meanings commonly understood by those skilled in the art, unless otherwise defined. It should be noted that the terms used herein should be interpreted as having a meaning consistent with the context of this specification and should not be interpreted in an idealized or overly rigid manner.

[0022] Regarding the relative position between two components (such as a film layer or a region) mentioned in the present application, such as "above", "on" or "over", it may mean that the two components are in direct contact, or it may mean that the two components are not in direct contact. Similarly, regarding the relative position between two components mentioned in the present application, such as "below", "under" or "beneath", it may mean that the two components are in direct contact, or it may mean that the two components are not in direct contact. For example, when one component (such as a film layer or a region) is referred to as "on another component", it may be directly on another component, or there may be other components between the two. On the other hand, when a component is referred to as "directly on another component", there are no components between the two. In addition, when one component is referred to as "on another component", there is an up-and-down relationship between the two in the top view direction, and this component may be above or below the other component. Therefore, this up-and-down relationship depends on the orientation of the device.

[0023] For a solar cell with a tunneling passivation contact structure, in order to improve the surface light trapping ability, an uneven structure is usually fabricated on the surface of the semiconductor substrate, and a tunneling passivation contact structure is deposited on the surface of the uneven structure. The tunneling passivation contact structure includes a tunneling layer and a doped semiconductor layer, which can block the transport of minority carriers and selectively allow majority carriers to pass through, effectively reducing the surface recombination of majority carriers and minority carriers. However, the layered structure formed by the tunneling layer and the doped semiconductor layer on the surface of the uneven structure is not uniform, which results in room for improvement in the passivation effect and electrical contact performance.

[0024] In the process of implementing the technical concept of the present application, it is found that by selecting appropriate deposition conditions, tunneling layers with different thicknesses can be deposited on different surfaces of the uneven structure. Based on the different carrier transport mechanisms of the tunneling layers with different thicknesses, regulating the side surfaces of the uneven structure is more conducive to reducing the contact resistance, and the top and bottom surfaces are more conducive to improving the passivation effect. Therefore, the passivation effect and the contact resistance can be synergistically improved, and the electrical performance of the battery can be enhanced.

[0025] Specifically, according to an embodiment of one aspect of the present application, a solar cell is provided. Figure 1 It is a schematic structural diagram of the solar cell according to the embodiment of the present application. Figure 2 It is a side view schematic diagram of the first texture structure according to the embodiment of the present application. Among them, (a) is a side view schematic diagram when the first texture structure is a convex structure, (b) is a side view schematic diagram when the first texture structure is a groove structure, and (c) is a side view schematic diagram when the first texture structure is another convex structure. As Figure 1 、 Figure 2 As shown in FIGS. (a)-(c) in

[0026] According to the embodiment of the present application, a tunneling layer is deposited on the semiconductor substrate, and a doped semiconductor layer is deposited on the tunneling layer. The semiconductor substrate includes a first surface having a plurality of first texture structures. Among them, the thickness of the tunneling layer deposited on the top surface or the bottom surface of the first texture structure is greater than the thickness of the tunneling layer deposited on the side surface, which results in different interface state densities between the tunneling layer and the semiconductor substrate on the top, bottom, and side surfaces. Specifically, on the top surface or the bottom surface, setting a thicker tunneling layer is more conducive to reducing the interface state density between the tunneling layer and the semiconductor substrate, thereby being conducive to improving the passivation effect; on the side surface, setting a thinner tunneling layer is more conducive to retaining the conductive channel, thereby being conducive to reducing the contact resistance. Therefore, by setting the thicknesses of the tunneling layers on the top, bottom, and side surfaces of the first texture structure to be different, the balance and improvement of the passivation and contact performances can be taken into account.

[0027] According to an embodiment of the present application, please continue to refer to Figure 2 As shown in (a) - (c) in Figure 2 , along the direction s away from the first surface 101a, the first texture structure 1011 can be a convex structure or a groove structure. When the proportion of the projected area of the top surface 1011c in the extension direction of the first surface 101a is larger than the proportion of the projected area of the bottom surface 1011a in the extension direction of the first surface 101a, it can indicate that the first texture structure 1011 is a convex structure, as shown in Figure 2 Figures (a) and (c) in

[0028] In the above two cases, define the "tilt angle" as the angle formed by the bottom surface 1011a, the side surface 1011b, or the top surface 1011c and the extension direction of the first surface 101a respectively. Then the bottom surface 1011a or the top surface 1011c has a smaller tilt angle compared to the side surface 1011b, so that there are distinctions among the top surface, the bottom surface, and the side surface. Further optionally, the top surface 1011c and / or the bottom surface 1011a can be substantially in the form of a plane parallel to the extension direction of the first surface 101a. For example, a small tilt angle is allowed, such as in the range of 0 - 10°, preferably 0 - 5°, more preferably 0 - 2°, and most preferably 0 - 0.5°. Additionally, micro - nano structures such as grains are allowed on it, rather than necessarily being a smooth surface.

[0029] According to an embodiment of the present application, again, as shown in Figure 2 Figure (c) in

[0030] along the direction s away from the first surface 101a, the side surface of at least one first texture structure 1011 can include at least two sub - side surfaces that are discontinuously arranged. The first texture structure 1011 further includes a transition surface 1011d located between two adjacent sub - side surfaces. Thus, the first texture structure 1011 has a stacked - tower - base structure. The setting of the stacked - tower - base structure is beneficial to increasing the light - trapping effect. Figure 2 Similarly, the transition surface 1011d has a smaller tilt angle compared to the side surface 1011b, and further optionally, the transition surface 1011d can be substantially in the form of a plane parallel to the extension direction of the first surface 101a. It can be understood that the first texture structures shown in

[0031] According to an embodiment of the present application, the formation of the first texture structure 1011 makes the surface of the semiconductor substrate 101 have an uneven texture structure, which helps to increase the light trapping effect and improve the photoelectric conversion efficiency of the solar cell.

[0032] Further optionally, the "first texture structure 1011" on the semiconductor substrate 101 can be a microstructure obtained by texturing the first surface of the initial substrate and then polishing; or it can be a microstructure obtained by directly polishing without texturing the first surface of the initial substrate.

[0033] According to an embodiment of the present application, the semiconductor substrate 101 can be an N-type or P-type silicon substrate. For example, it can be a semiconductor material such as single crystal silicon, polycrystalline silicon, or microcrystalline silicon, preferably an N-type or P-type single crystal silicon substrate. The conversion efficiency of the cell based on the single crystal silicon substrate is relatively high compared to other types such as polycrystalline silicon cells. By introducing donor impurities such as phosphorus (P), arsenic (As), or antimony (Sb) into these semiconductor materials, an N-type silicon substrate is obtained, or by introducing acceptor impurities such as boron (B), aluminum (Al), or gallium (Ga) into these semiconductor materials, a P-type silicon substrate is obtained.

[0034] According to an embodiment of the present application, the first surface 101a of the semiconductor substrate 101 can be a light-receiving surface or a backlight surface, preferably a backlight surface. With this setting, the doped semiconductor layer 103 has less optical parasitic absorption when located on the backlight surface than when located on the light-receiving surface.

[0035] According to an embodiment of the present application, the tunneling layer 102 and the doped semiconductor layer 103 cooperate to form a tunneling passivation contact structure. Among them, the tunneling layer 102 is used to transport majority carriers and achieve a passivation effect, and its material is silicon oxide, which can be obtained by plasma-enhanced chemical vapor deposition (PECVD) or physical vapor deposition (PVD). The doped semiconductor layer 103 can be at least one semiconductor material such as a polycrystalline silicon layer or a microcrystalline silicon layer, and its doping type can be the same as or different from the doping type of the semiconductor substrate 101, which can be specifically determined according to the cell type and the semiconductor substrate 101.

[0036] For example, taking a TOPcon cell as an example, when the semiconductor substrate 101 is an N-type silicon substrate, the doped semiconductor layer 103 can be N-type doped or P-type doped, or when the semiconductor substrate 101 is a P-type silicon substrate, the doped semiconductor layer 103 can be N-type doped or P-type doped. The thickness of the doped semiconductor layer 103 is 50 - 300 nm, preferably 80 - 180 nm, and can be, for example, 50 nm, 80 nm, 100 nm, 120 nm, 150 nm, 180 nm, 200 nm, 250 nm, 280 nm, 300 nm, etc. A suitable polysilicon thickness can better match the tunneling layer, improve the field passivation performance, and ensure the passivation effect.

[0037] Figure 3 It is a transmission electron microscope (TEM) image of a partial cross-section of the solar cell according to an embodiment of the present application. Figure 4 It is a TEM image of the top surface cross-section of the first texture structure according to an embodiment of the present application. Figure 5 It is a TEM image of the side surface cross-section of the first texture structure according to an embodiment of the present application.

[0038] According to an embodiment of the present application, as Figures 3 to 5 shown, it can be seen that the thickness of the tunneling layer located on the top surface 1011c is greater than the thickness of the tunneling layer located on the side surface 1011b, and the thickness of the tunneling layer located on the bottom surface 1011a can also be set to a thickness similar to that of the tunneling layer located on the top surface 1011c. Further optionally, the ratio of the thickness of the tunneling layer 102 located on the top surface 1011c and / or the bottom surface 1011a to the thickness of the tunneling layer 102 located on the side surface 1011b is greater than 1 and less than or equal to 4, and can be, for example, 1.5, 2, 2.5, 3, 3.5, 4, etc. The tunneling layer on the top surface 1011c and / or the bottom surface 1011a requires a relatively thick thickness to provide a better passivation effect. A thicker tunneling layer can better isolate and reduce the interface state density, thereby reducing interface recombination and improving the stability and electrical performance of the device. The thickness of the tunneling layer on the side surface 1011b is relatively thin. A thinner tunneling layer has a relatively high interface state density, providing a conductive channel for carrier transport, thereby helping to reduce the contact resistance and enabling carriers to be transported more effectively in the device. However, an overly thin tunneling layer will sacrifice a certain passivation effect. The ratio of the thickness of the tunneling layer on the top surface and the side surface is an important factor in balancing the passivation effect and the contact resistance. This ratio is beneficial for having a sufficient thickness of the tunneling layer on the top surface to achieve a good passivation effect, while the thickness of the tunneling layer on the side surface is not too thick to increase the contact resistance. Having a suitable thickness ratio of the tunneling layer on the top surface and the side surface can be beneficial for taking into account both the passivation effect and the contact resistance.

[0039] According to an embodiment of the present application, the thickness of the tunneling layer 102 located on the top surface 1011c and / or the bottom surface 1011a may be greater than or equal to 0.5 nm, preferably 0.5 - 2.5 nm, for example, it may be 0.5 nm, 1 nm, 1.5 nm, 2 nm, 2.5 nm, etc.; and / or, the thickness of the tunneling layer 102 located on the side surface 1011b is greater than or equal to 0.2 nm, preferably 0.2 - 2 nm, for example, it may be 0.2 nm, 0.5 nm, 1 nm, 1.5 nm, 2 nm, etc.

[0040] By setting an appropriate thickness of the tunneling layer, it can be further beneficial to simultaneously improve the passivation effect and the contact resistance. If the thickness of the tunneling layer is too thin, it will be difficult to form a tunneling layer that can uniformly cover the first surface, which is not conducive to the passivation effect. If the thickness of the tunneling layer is too thick, the contact resistance will be too high, which is not conducive to carrier transport.

[0041] More specifically, there are two main mechanisms for carrier transport in the tunneling layer: hole transport and tunneling effect. Hole transport mainly occurs when the tunneling layer is relatively thick (usually greater than 2 nm). In this case, there may be defects, pinholes, or locally weak regions in the tunneling layer, which provide direct channels for carriers, enabling carriers to be transported through these holes. However, the efficiency and reliability of hole transport are often affected by the quality of the tunneling layer and the manufacturing process. On the other hand, the tunneling effect mainly occurs when the tunneling layer is relatively thin (usually less than 2 nm). The tunneling effect is a quantum mechanical phenomenon. When the thickness of the tunneling layer is thin enough, carriers have a certain probability of directly passing through the oxide layer barrier to achieve transport. The efficiency of the tunneling effect is closely related to factors such as the thickness of the tunneling layer, the energy of the carriers, and the barrier height on both sides of the tunneling layer. As the thickness of the tunneling layer decreases, the tunneling effect becomes more significant, and the transport efficiency of carriers will also increase accordingly. Therefore, the tunneling effect is not only beneficial to carrier transport but also can retain the conductive channels and form a good resistivity.

[0042] According to an embodiment of the present application, the tunneling layer 102 may preferably be silicon oxide, but is not limited thereto. Other materials suitable for forming a tunneling layer with a thicker top surface and a thinner side surface thickness feature should also be equally applicable.

[0043] According to an embodiment of the present application, Figure 6 is a side view schematic diagram of the convex structure of the first texture structure of the embodiment of the present application. As Figure 6As shown, in the direction S away from the first surface 101a, the first texture structure 1011 includes a side surface 1011b and a top surface 1011c. The projected area of at least one of the top surface 1011c and the bottom surface 1011a in the extending direction of the first surface 101a is larger than the projected area of the side surface 1011b in the extending direction of the first surface 101a. The tunneling layer 102 mainly plays a passivation effect. Without changing the inclination angles of the top surface 1011c and the side surface 1011b, the area ratios of the tunneling layers 102 with different thicknesses located on the top surface 1011c, the bottom surface 1011a, and the side surface 1011b are controlled by the area ratios of the top surface 1011c, the bottom surface 1011a, and the side surface 1011b on the first texture structure 1011, so that the passivation effect of the tunneling layer 102 located on the top surface 1011c or the bottom surface 1011a is dominant, ensuring the overall passivation effect, and at the same time making the contact performance of the tunneling layer 102 located on the side surface 1011b good, so as to facilitate the improvement of the overall contact performance of the tunneling layer 102, thereby balancing the contact resistance and the passivation effect.

[0044] According to an embodiment of the present application, the lateral dimension W of the top surface 1011c and / or the bottom surface 1011a is 5 to 80 μm, preferably 10 to 30 μm, and for example, it can be 5 μm, 8 μm, 10 μm, 15 μm, 20 μm, 25 μm, 30 μm, 40 μm, 60 μm, 80 μm, etc.; and / or, the height L between the top surface 1011c and the bottom surface 1011a is 1 to 10 μm, preferably 1 to 2 μm, and for example, it can be 1 μm, 3 μm, 5 μm, 8 μm, 10 μm, etc. It can be understood that the "lateral dimension" can be the dimension along the direction of the surface. For example, for the rectangular top surface 1011c, its lateral dimension can be the side length, and for the circular top surface 1011c, its lateral dimension can be the diameter length. The appropriate size of the convex structure helps to ensure a good light trapping effect of the first texture structure 1011 while meeting the aforementioned area requirements, and at the same time, it can also ensure that the doped semiconductor layer 103 can be prepared conformally on the first texture structure 1011.

[0045] According to an embodiment of the present application, the first texture structure 1011 is a convex structure or a groove structure, and for example, it can be Figure 3 as shown in the frustum shape, but not limited thereto, and it can also be a truncated cone shape, a prism shape, etc. Here, the "frustum shape" means generally in the shape of a frustum, and the same applies to the "truncated cone shape" and the "prism shape". The frustum shape can further be, for example, an interlaced stacked pyramid base structure.

[0046] According to an embodiment of the present application, for another example Figure 1As shown, taking the TOPCon cell as an example, the semiconductor substrate 101 further includes a second surface 101b opposite to the first surface 101a, and the second surface has a plurality of second texture structures 1012. The second texture structures 1012 can be convex structures or groove structures. The formed second texture structures help to improve the light trapping effect, increase light absorption, and thus improve the photoelectric conversion efficiency.

[0047] According to an embodiment of the present application, further optionally, the second texture structures 1012 can be cylindrical, conical, pyramidal, etc. Similarly, the "conical" here means a shape roughly like a cone, and the same applies to "cylindrical" and "pyramidal". The pyramidal shape can further be, for example, a staggered stacked regular pyramid structure or an inverted pyramid structure, etc.

[0048] According to an embodiment of the present application, further optionally, the solar cell further includes an emitter 106 and a second passivation and antireflection layer 107.

[0049] The emitter 106 is formed in the second surface 101b of the semiconductor substrate 101 and usually has a relatively high doping concentration to form a good ohmic contact, reduce the contact resistance, and improve the current injection efficiency. The emitter 106 can be N-type doped or P-type doped, and its doping type can be the same as or different from that of the semiconductor substrate. Further optionally, the N-type doping can be achieved by doping a relatively high concentration of donor elements such as phosphorus (P), arsenic (As), or antimony (Sb), etc. in the second surface 101b of the semiconductor substrate 101, or by introducing acceptor elements such as boron (B), aluminum (Al), or gallium (Ga), etc. in the second surface 101b of the semiconductor substrate 101.

[0050] The second passivation and antireflection layer 107 is located on the surface of the emitter 106, that is, on the second surface. The second passivation and antireflection layer 107 helps to achieve a good passivation and antireflection effect, improve the dark saturation current density and the implicit open-circuit voltage of the solar cell. The second passivation and antireflection layer 107 can be, for example, silicon dioxide, silicon nitride, or a stacked film composed of both.

[0051] According to an embodiment of the present application, even further optionally, the back surface of the solar cell further includes a first passivation and antireflection layer 104 and an electrode 105. The first passivation and antireflection layer 104 is formed on the doped semiconductor layer 103, and the electrode 105 is located on the first passivation and antireflection layer 104 and passes through the first passivation and antireflection layer 104 to contact the doped semiconductor layer 103, and is also located on the second passivation and antireflection layer 107 and passes through the second passivation and antireflection layer 107 to contact the emitter 106.

[0052] Exemplarily, the first passivation and antireflection layer 104 and the second passivation and antireflection layer 107 may respectively include an alumina layer and a silicon nitride layer sequentially arranged in a direction away from the semiconductor substrate 101. Further optionally, the thickness of the alumina layer may be 3 to 5 nm, such as 3 nm, 3.5 nm, 4 nm, 4.5 nm, 5 nm, etc., and the thickness of the silicon nitride layer may be 80 to 120 nm, such as 80 nm, 90 nm, 100 nm, 110 nm, 120 nm, etc.

[0053] According to an embodiment of the present application, further, Figure 7 is a flowchart of a method for a solar cell according to an embodiment of the present application. As shown in combination with Figure 1 shown, the method for preparing the solar cell of the present application may include operations S701 to S703:

[0054] In operation S701, wet polishing is performed on the first surface of the initial substrate to form a plurality of first texture structures on the first surface 101a, obtaining the semiconductor substrate 101; wherein, along the direction away from the first surface 101a, the first texture structure includes a bottom surface 1011a, a side surface 1011b, and a top surface 1011c, and the side surface 1011b is located between the bottom surface 1011a and the top surface 1011c;

[0055] In operation S702, a tunneling layer 102 is deposited on the first surface 101a of the semiconductor substrate 101 by plasma enhanced chemical vapor deposition (PECVD) or physical vapor deposition (PVD), such that the thickness of the tunneling layer located on the top surface 1011c and / or the bottom surface 1011a is greater than the thickness of the tunneling layer 102 located on the side surface 1011b;

[0056] In operation S703, a doped semiconductor layer 103 is prepared on the surface of the tunneling layer 102 away from the semiconductor substrate 101.

[0057] According to an embodiment of the present application, by selecting a suitable deposition method, compared with other methods such as atomic layer deposition (ALD method), it is more beneficial to form the tunneling layer 102 with a specific thickness distribution of the present application on the first surface 101a, thereby using the tunneling layer 102 located on the side surface 1011b to improve the contact performance, and using the tunneling layer 102 located on the top surface 1011c and / or the bottom surface 1011a to improve the passivation effect, so as to balance the contact resistance and the passivation effect.

[0058] According to an embodiment of the present application, in operation S701, the wet polishing mainly includes two steps of cleaning and alkali polishing.

[0059] The cleaning steps may include: cleaning with the SC-1 cleaning solution in the wet chemical cleaning method (or the RCA standard cleaning method) to remove organic residues and some metals; then washing with deionized water and neutralizing the chemicals remaining after cleaning with the SC-1 cleaning solution.

[0060] The alkali polishing step may include: using a KOH alkali solution to remove the surface damage layer caused by cutting, and the initial substrate surface after cleaning is polished; then using the SC-1 cleaning solution to perform high-efficiency cleaning on the initially alkali-polished substrate; then using the SC-2 cleaning solution to remove the metal ions remaining after cleaning with the SC-1 cleaning solution; finally, cleaning with 5wt% hydrofluoric acid to complete the polishing of the initial substrate surface. The polishing thickness of the initial substrate is 5-10 μm, and a semiconductor substrate with a plurality of first texture structures is formed after polishing.

[0061] According to an embodiment of the present application, in operation S702, taking the tunneling layer as silicon oxide as an example, the conditions for depositing the tunneling layer by PECVD include: the power is 1500-2000 W (for example, it can be 1500 W, 1600 W, 1700 W, 1800 W, 1900 W, 2000 W, etc.), the pressure is 200-300 Pa (for example, it can be 200 Pa, 220 Pa, 240 Pa, 260 Pa, 280 Pa, 300 Pa, etc.), the flow rate of silane (i.e., SiH4) is: 40-70 sccm (for example, it can be 40 sccm, 50 sccm, 60 sccm, 70 sccm, etc.), the flow rate of carbon dioxide (CO2) is: 300-500 sccm (for example, it can be 300 sccm, 350 sccm, 400 sccm, 450 sccm, 500 sccm, etc.), and hydrogen (H2): 1000-2000 sccm (for example, it can be 1000 sccm, 1200 sccm, 1400 sccm, 1600 sccm, 1800 sccm, 2000 sccm, etc.). Selecting the deposition conditions of the above conditions is more conducive to preparing the tunneling layer with a specific thickness distribution in the present application.

[0062] According to an embodiment of the present application, in operation S703, taking the doped semiconductor layer as doped polysilicon as an example, a low-pressure chemical vapor deposition method (LPCVD) can be used to fabricate an amorphous silicon layer or a polysilicon layer, and further doped to form a doped polysilicon layer through a diffusion process, etc. Since the doped semiconductor layer can be prepared by a conventional process and is not the key of the present application, it will not be elaborated here.

[0063] Further exemplarily, in order to prepare as Figure 1For the TOPCon cell shown, the preparation method of the present application may further include: performing wet texturing on the second surface of the initial substrate to form a plurality of second texture structures 1012 on the second surface; then preparing an emitter 106 and a second passivation and antireflection layer 107 on the second surface 101b having the second texture structures 1012; and preparing a first passivation and antireflection layer 104 on the doped semiconductor layer 103; and preparing electrodes 105 on the first passivation and antireflection layer 104 and the second passivation and antireflection layer 107 respectively.

[0064] The passivated contact structure of the present application can be widely applied to various battery types. Exemplarily, the solar cell of the present application can be, in addition to the TOPCon cell as Figure 1 shown, also a back contact cell, for example, it can be a TBC (TopCon - Back Contact, tunneling oxidation passivated contact - back contact) cell, an HPBC (Hybrid Passivated BackContact, composite passivated back contact) cell, or a hybrid BC (Back Contact, back contact) cell, etc.

[0065] Figure 8 is a schematic structural diagram of a solar cell according to another embodiment of the present application. The main difference from the Figure 1 solar cell structure shown is that the first surface 101a is the backlight surface of the solar cell, and the first surface 101a includes alternately distributed N regions and P regions at intervals. The above-mentioned tunneling passivated contact structure formed by the tunneling layer 102 and the doped semiconductor layer 103 is located on one of the N region and the P region or respectively located on the N region and the P region. At this time, the first surface 101a has a plurality of first texture structures 1011, which can be distributed on the entire surface of the first surface 101a or on a part of the first surface 101a, for example, can be located in the N region and / or the P region. The first texture structure 1011 includes a bottom surface 1011a, a side surface 1011b, and a top surface 1011c. The side surface 1011b is located between the bottom surface 1011a and the top surface 1011c. The thickness relationship of the tunneling layer on the side surface 1011b, the top surface 1011c, and the bottom surface 1011a is the same as that described above and will not be elaborated here.

[0066] Exemplarily, taking Figure 8As shown, in one embodiment, the tunneling passivation contact structure can be located on the N region and the P region respectively. At this time, the tunneling layer 102 can cover the first surface 101a on the front, or be set as a patterned layer structure. The doped semiconductor layer 103 can be set as a patterned layer structure. The corresponding back-contact solar cell is a TBC (TopCon - Back Contact) cell. And the doping types of the doped semiconductor layer 103 located on the N region and the doped semiconductor layer 103 located on the P region are different, that is, the doped semiconductor layer 103 located on the N region is N-type doped, and the doped semiconductor layer 103 located on the P region is P-type doped. At this time, the first texture structure can be located on the N region and the P region, and the thickness distribution law of the foregoing tunneling layer can be respectively present on the N region and the P region.

[0067] According to an embodiment of the present application, more preferably, in the extending direction of the first surface, the sum of the projected areas of the top surface and the bottom surface of the first texture structure 1011 located in the P region is less than the sum of the projected areas of the top surface and the bottom surface of the first texture structure 1011 located in the N region.

[0068] With such a setting, when the semiconductor substrate is an N-type substrate, the electron collection efficiency is higher than the hole collection efficiency, that is, the tunneling efficiency of the N region is higher than that of the P region. Therefore, compared with the N region, the proportion of the top and bottom surfaces of the P region is relatively smaller, and the proportion of the side surfaces is relatively larger, so that more conductive channels are retained, which is beneficial to the improvement of the hole collection efficiency, and thus more beneficial to the balance of carrier collection.

[0069] Exemplarily, in another embodiment, the tunneling passivation contact structure located on the N region or the P region can be replaced with other passivation contact structures. For example, the tunneling layer 102 and the doped semiconductor layer 103 located on the P region are integrally replaced with an aluminum back surface field, so as to form an aluminum back surface field passivation structure on the P region. The corresponding back-contact solar cell can be an HPBC (Hybrid Passivated Back Contact) cell. Or, for another example, the tunneling layer 102 and the doped semiconductor layer 103 located on the P region are integrally replaced with an intrinsic amorphous silicon and a P-type doped amorphous silicon arranged in sequence along the direction away from the second region, so as to form a heterojunction passivation contact structure on the P region. The corresponding back-contact solar cell can be a hybrid BC (Back Contact) cell.

[0070] Exemplarily, for the sake of convenience of description, further taking the hybrid BC as an example, Figure 9 is a schematic structural diagram of a solar cell according to another embodiment of the present application. As Figure 9 shown, the first texture structure can be, for example, located on one of the N region and the P region, and the other can have a second texture structure 1012. And Figure 8The main difference of the solar cell structure shown is that, in the direction away from the first surface, the cell further includes an intrinsic semiconductor layer 108 and another doped semiconductor layer 109 located on the N region or P region with the second texture structure 1012, thereby forming a heterojunction passivation contact structure.

[0071] Furthermore, if Figure 9 As shown, the solar cell further includes: a patterned transparent conductive layer 110 , which is respectively located on the surface of the doped semiconductor layer 103 away from the semiconductor substrate 101 , and on the surface of another doped semiconductor layer 109 away from the semiconductor substrate 101 .

[0072] According to the embodiments of the present application, Figure 8 and Figure 9 The method for preparing the back contact solar cell is similar to the method described above. Figure 1 The TOPCon cell shown is similar to the one shown in the figure, and the main difference is that the second passivation anti-reflection layer 107 is directly prepared on the second surface of the semiconductor substrate 101 after texturing; the tunneling layer 102 and the doped semiconductor layer 103 are patterned on the first surface of the semiconductor substrate 101 to retain the tunneling layer 102 and the doped semiconductor layer 103 located on the N region or the P region, and the remaining first surface is exposed; and then a doped semiconductor layer with a conductivity type opposite to that of the doped semiconductor layer 103 is made on the exposed first surface, and insulation between the doped semiconductor layer 103 and the semiconductor layer located on the P region is achieved.

[0073] For the hybrid BC battery, one of the N region and the P region can be polished first to produce a patterned tunneling layer 102 and a doped semiconductor layer 103, and then covered with a mask, and then after the second texture structure is formed by milling the P region, an intrinsic semiconductor layer 108 and another doped semiconductor layer 109 are produced.

[0074] According to another embodiment of the present application, a photovoltaic assembly is provided, comprising a plurality of the above-mentioned solar cells and a packaging structure, wherein the plurality of solar cells are connected into a solar cell string, and the packaging structure is disposed around the periphery of the solar cell string.

[0075] According to the embodiments of the present application, the packaging structure may include, for example, a glass panel, an adhesive film and a back panel, wherein the glass panel is located on the front side (or light-receiving side) of the solar cell string, and the back panel is located on the back side (or backlight side) of the solar cell string, both of which play a protective role; the adhesive film is an adhesive film between the solar cell string and the glass panel and the back panel, which plays a role of bonding and fixing, and a transparent material must be used.

[0076] In the embodiments of the present application, when the solar cell and the photovoltaic module of the present application use the selective passivation contact structure provided by the present application, it helps to improve the passivation contact effect and the electrical transmission effect, thereby improving the photoelectric conversion efficiency of the solar cell and the photovoltaic module.

[0077] The specific embodiments described above further elaborate on the purpose, technical solutions, and beneficial effects of the present application. It should be understood that the above are only specific embodiments of the present application and are not used to limit the present application. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of the present application shall be included within the protection scope of the present application.

Claims

1. A solar cell, comprising: A semiconductor substrate, including a first surface having a plurality of first texture structures. Along the direction away from the first surface, the first texture structure includes a bottom surface, a side surface, and a top surface. The side surface is located between the bottom surface and the top surface, and the first texture structure is in the shape of a frustum of a pyramid, a frustum of a cone, or a prism; A tunneling layer, located on the first surface of the semiconductor substrate, and the thickness of the tunneling layer on the top surface and / or the bottom surface is greater than the thickness of the tunneling layer on the side surface; And A doped semiconductor layer, located on the surface of the tunneling layer away from the semiconductor substrate.

2. The solar cell according to claim 1, wherein, The ratio between the thickness of the tunneling layer on the top surface and / or the bottom surface and the thickness of the tunneling layer on the side surface is greater than 1 and less than or equal to 4.

3. The solar cell according to claim 1 or 2, wherein, The thickness of the tunneling layer on the top surface and / or the bottom surface is greater than or equal to 0.5 nm; and / or The thickness of the tunneling layer on the side surface is greater than or equal to 0.2 nm.

4. The solar cell according to claim 1 or 2, wherein, The thickness of the tunneling layer on the top surface and / or the bottom surface is 0.5 - 2.5 nm; and / or The thickness of the tunneling layer on the side surface is 0.2 - 2 nm.

5. The solar cell according to claim 1, wherein, The projected area of at least one of the top surface and the bottom surface in the extending direction of the first surface is greater than the projected area of the side surface in the extending direction of the first surface.

6. The solar cell according to claim 1 or 5, wherein The projected area of the top surface in the extending direction of the first surface is greater than the projected area of the bottom surface in the extending direction of the first surface; Or the projected area of the top surface in the extending direction of the first surface is less than the projected area of the bottom surface in the extending direction of the first surface.

7. The solar cell according to claim 1, wherein: The lateral dimension of the top surface and / or the bottom surface is 5 - 80 μm; and / or The height between the top surface and the bottom surface is 1 - 10 μm.

8. The solar cell according to claim 1, wherein: The lateral dimension of the top surface and / or the bottom surface is 10 - 30 μm; and / or The height between the top surface and the bottom surface is 1 - 2 μm.

9. The solar cell according to claim 1 or 2, wherein The top surface and / or the bottom surface is a plane parallel to the extending direction of the first surface.

10. The solar cell according to claim 1, wherein, Along the direction away from the first surface, the side surface of at least one of the first texture structures includes at least two sub - side surfaces that are discontinuously arranged, and the first texture structure further includes a transition surface located between two adjacent sub - side surfaces; The thickness of the tunneling layer on the transition surface is greater than the thickness of the tunneling layer on the sub - side surfaces on both sides of the transition surface.

11. The solar cell according to claim 1, wherein, The thickness of the doped semiconductor layer is 50 - 300 nm.

12. The solar cell according to claim 1, wherein, The thickness of the doped semiconductor layer is 80 - 180 nm.

13. The solar cell according to claim 1, wherein, The semiconductor substrate is an N - type substrate, and the first surface includes alternately spaced N regions and P regions, where: In the extending direction of the first surface, the sum of the projected areas of the top surface and the bottom surface of the first texture structure in the P region is less than the sum of the projected areas of the top surface and the bottom surface of the first texture structure in the N region.

14. A photovoltaic module, comprising: A plurality of solar cells as described in any one of claims 1 to 13, connected into a solar cell string; And The encapsulation structure surrounds the outer periphery of the solar cell string.

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