Back passivation structure capable of reducing phosphorus internal expansion, preparation method of back passivation structure and TOPCon battery

Abstract

The invention relates to a back passivation structure capable of reducing phosphorus internal expansion. The back passivation structure comprises an N-type crystal silicon wafer, and a tunneling oxide layer, an intrinsic amorphous silicon layer, a silicon oxynitride layer and a phosphorus-doped polycrystalline silicon layer which are sequentially arranged on the back surface of the N-type crystal silicon wafer. According to the back passivation structure capable of reducing phosphorus internal expansion, in the preparation process, P atoms can be diffused towards the silicon substrate after high-temperature crystallization, the silicon oxynitride layer serves as a first barrier layer, silicon oxynitride has higher barrier efficiency on the P atoms compared with silicon oxide, most of the P atoms can be effectively blocked, and the performance of the silicon oxynitride layer is improved. The intrinsic amorphous silicon layer serves as a second barrier layer, P atoms which are not blocked by the silicon oxynitride layer can be subjected to P doping with intrinsic amorphous silicon and are converted into doped polycrystalline silicon with low P concentration, and the tunneling oxide layer serves as the last barrier layer to further block the P atoms, so that the P atoms can be effectively prevented from being internally expanded to a crystalline silicon substrate, surface recombination is reduced, and the performance of the crystalline silicon is improved. Therefore, the cell conversion efficiency is improved.

Description

Technical Field

[0001] The invention relates to the technical field of photovoltaic cells, and in particular to a back passivation structure for reducing phosphorus internal diffusion, a preparation method thereof, and a TOPCon cell. Background Art

[0002] After several years of development, TOPCon (Tunnel Oxide Passivating Contacts) cells have become the mainstream technology in the cell market and have entered large-scale mass production. The feature of TOPCon cells is that they use ultra-thin tunneling silicon oxide and doped polysilicon poly structure on the surface. First, a 1-2nm tunneling oxide layer is prepared on the back of the silicon wafer, and then a layer of doped polysilicon is deposited. The two together form a passivation contact structure, which provides good interface passivation for the back of the silicon wafer. The tunneling oxide passivation contact structure enables majority carriers to penetrate the tunneling oxide layer and blocks minority carriers, which can effectively achieve the selective passage of carriers, thereby greatly reducing the recombination rate of minority carriers and improving battery performance.

[0003] However, since the tunnel oxide layer is only 1 to 2 nm thick, it cannot effectively prevent phosphorus atoms from diffusing into the silicon matrix during the phosphorus atom activation step. Phosphorus atoms diffusing into the silicon matrix will form new recombination centers, which will increase carrier recombination and reduce minority carrier lifetime, further reducing the conversion efficiency of the cell. In the TOPCon cell manufacturing process, due to high temperatures, phosphorus atom inward expansion is unavoidable, so how to reduce phosphorus atom inward expansion is a problem that needs to be solved. Summary of the invention

[0004] Based on this, the purpose of the present invention is to provide a back passivation structure for reducing phosphorus inward expansion and a preparation method thereof and a TOPCon battery, so as to reduce the inward expansion of phosphorus atoms, reduce carrier recombination, and improve battery efficiency.

[0005] To achieve the above object, the present invention adopts the following technical solutions:

[0006] The invention provides a back passivation structure for reducing phosphorus inward diffusion, which comprises an N-type crystalline silicon wafer and a tunneling oxide layer, an intrinsic amorphous silicon layer, a silicon oxynitride layer, and a phosphorus-doped polysilicon layer sequentially arranged on the back of the N-type crystalline silicon wafer.

[0007] The back passivation structure for reducing phosphorus inward diffusion proposed in the present invention has the following characteristics: during the preparation process, P atoms will diffuse toward the silicon substrate after high-temperature crystallization; the silicon oxynitride layer serves as the first barrier layer, and silicon oxynitride has a higher barrier efficiency for P atoms than silicon oxide, and can effectively block most of the P atoms; the intrinsic amorphous silicon layer serves as the second barrier layer, and the P atoms not blocked by the silicon oxynitride layer will be P-doped with the intrinsic amorphous silicon to be converted into doped polysilicon with a lower P concentration; the tunneling oxide layer serves as the last barrier layer to further block the P atoms, and can effectively reduce the inward diffusion of P atoms into the crystalline silicon substrate and reduce surface recombination, thereby improving the battery conversion efficiency.

[0008] As a further improvement of the above solution of the present invention, the thickness of the intrinsic amorphous silicon layer is 1-20 nm.

[0009] As a further improvement of the above solution of the present invention, the thickness of the silicon oxynitride layer is 1-5 nm.

[0010] As a further improvement of the above solution of the present invention, the thickness of the tunnel oxide layer is 0.5-3 nm.

[0011] As a further improvement of the above solution of the present invention, the thickness of the phosphorus-doped polysilicon layer is 20-150 nm.

[0012] The present invention also provides a method for preparing the above-mentioned back passivation structure for reducing phosphorus in-diffusion, which comprises the following steps:

[0013] S1. Place an N-type crystalline silicon wafer in a furnace tube, introduce nitrous oxide into the furnace tube at 380 to 500° C., the flow rate of nitrous oxide is 7000 to 15000 sccm, the pressure in the furnace tube is 1000 to 3000 mtorr, and a tunneling oxide layer is deposited on the back of the N-type crystalline silicon wafer by PECVD process, and the deposition time is 10 to 200 s;

[0014] S2. Then, silane and hydrogen are introduced into the furnace tube at 380 to 500°C, the silane flow rate is 2000 to 4000 sccm, the hydrogen flow rate is 8000 to 13000 sccm, the pressure in the furnace tube is 2000 to 4000 mtorr, and an intrinsic amorphous silicon layer is deposited on the tunneling oxide layer for a deposition time of 10-300 s;

[0015] S3. Then at 380~500 ℃, silane, ammonia and nitrous oxide are added to the furnace tube, the nitrous oxide flow rate is 5000~10000sccm, the silane flow rate is 800~4000sccm, the ammonia flow rate is 3000~6000sccm, the pressure in the furnace tube is 1000~3000mtorr, and a silicon oxynitride layer is deposited on the intrinsic amorphous silicon layer for a deposition time of 10~200s;

[0016] S4. Then, at 380 to 500 ° C, silane, phosphine and hydrogen are introduced into the furnace tube, the silane flow rate is 2000 to 4000 sccm, the hydrogen flow rate is 8000 to 12000 sccm, the phosphine flow rate is 100 to 1000 sccm, the pressure in the furnace tube is 2000 to 4000 mtorr, and a phosphorus-doped amorphous silicon layer is deposited on the silicon oxynitride layer for a deposition time of 10 to 700 s;

[0017] S5. Then, silane and nitrous oxide are introduced into the furnace tube at 380-500° C., the nitrous oxide flow rate is 5000-10000 sccm, the silane flow rate is 800-4000 sccm, the pressure in the furnace tube is 1000-3000 mtorr, and a silicon dioxide layer is deposited on the phosphorus-doped amorphous silicon layer for a deposition time of 10-200 s.

[0018] The present invention also provides a TOPCon battery, which includes the back passivation structure for reducing phosphorus in-diffusion as described above.

[0019] Compared with the prior art, the present invention has the following beneficial effects:

[0020] The back passivation structure for reducing phosphorus inward expansion proposed by the present invention, during the preparation process, P atoms will diffuse toward the silicon substrate after high-temperature crystallization, the silicon oxynitride layer is used as the first barrier layer, silicon oxynitride has a higher blocking efficiency for P atoms than silicon oxide, and can effectively block most of the P atoms, the intrinsic amorphous silicon layer is used as the second barrier layer, the P atoms not blocked by the silicon oxynitride layer will be P-doped with the intrinsic amorphous silicon, and converted into doped polysilicon with a lower P concentration, the tunneling oxide layer is used as the last barrier layer, and the P atoms are further blocked, which can effectively reduce the inward expansion of P atoms to the crystalline silicon substrate, reduce surface recombination, and thus improve the battery conversion efficiency. The composite poly structure of the present invention can effectively reduce the inward expansion of phosphorus atoms, reduce carrier recombination, and improve the efficiency of the battery cell. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] Figure 1 A schematic diagram of the structure of a TOPCon battery proposed in the embodiment;

[0022] Figure 2 is an ECV curve diagram of the wafer after the annealing step in the embodiment and the comparative example;

[0023] Figure 3 EQE curves of TOPCon cells prepared in examples and comparative examples.

[0024] Figure numerals: 10, N-type crystalline silicon wafer; 11, tunneling oxide layer; 12, intrinsic amorphous silicon layer; 13, silicon oxynitride layer; 14, phosphorus-doped polysilicon layer; 15, back aluminum oxide layer; 16, back anti-reflection film; 17, P-type emitter; 18, front aluminum oxide layer; 19, front anti-reflection film. DETAILED DESCRIPTION

[0025] For ease of understanding of the present invention, the present invention will be described more fully below in conjunction with specific embodiments. However, the present invention can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present invention more thoroughly understood.

[0026] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art of the present invention. The terms used in the specification of the present invention herein are only for the purpose of describing specific embodiments and are not intended to limit the present invention.

[0027] Example

[0028] This embodiment proposes a TOPCon cell, which includes an N-type crystalline silicon wafer, a front electrode, a back electrode, and a P-type emitter, a front aluminum oxide layer, and a front anti-reflection film arranged in sequence on the front side of the N-type crystalline silicon wafer, and a back passivation structure, a back aluminum oxide layer, and a back anti-reflection film arranged in sequence on the back side of the N-type crystalline silicon wafer, wherein the back passivation structure includes a 0.5-3nm tunneling oxide layer, a 1-20nm intrinsic amorphous silicon layer, a 1-5nm silicon oxynitride layer, and a 20-150nm phosphorus-doped polysilicon layer arranged in sequence on the back side of the N-type crystalline silicon wafer, the front electrode passes through the front anti-reflection film to be connected to the front aluminum oxide layer, and the back electrode passes through the back anti-reflection film, the back aluminum oxide layer, the phosphorus-doped polysilicon layer, and the silicon oxynitride layer to be connected to the intrinsic amorphous silicon layer in sequence.

[0029] The preparation method of the TOPCon battery of this embodiment comprises the following steps:

[0030] S1. Texturing: N-type crystalline silicon wafers are etched with alkali to form a pyramid velvet surface on the front of the N-type crystalline silicon wafer to enhance light absorption;

[0031] S2. Boron diffusion: Place the N-type crystalline silicon wafer with a velvet surface on the front side into a boron diffusion furnace to prepare a PN junction;

[0032] S3. Remove BSG + alkali polishing: Place the N-type crystalline silicon wafer after boron expansion in HF reagent for pickling to remove the BSG coating on the back and edge, then place it in an alkali polishing solution for alkali polishing and polishing the back;

[0033] S4. Prepare a back passivation structure on the back of the polished N-type crystalline silicon wafer, specifically:

[0034] S41. The N-type crystalline silicon wafer is placed in a furnace tube, nitrous oxide is introduced into the furnace tube at 430°C, the flow rate of nitrous oxide is 9600sccm, the pressure in the furnace tube is 1950mtorr, the power of the RF power supply discharge is 12000W, and a tunneling oxide layer is deposited on the back of the N-type crystalline silicon wafer by PECVD process, and the deposition time is 100s;

[0035] S42. Then, silane and hydrogen are introduced into the furnace at 430°C, the silane flow rate is 2700sccm, the hydrogen flow rate is 9600sccm, the furnace pressure is 3100mtorr, the power is 15000W, and an intrinsic amorphous silicon layer is deposited on the tunneling oxide layer for 120s;

[0036] S43. Then at 430°C, silane, ammonia and nitrous oxide are added to the furnace tube, the nitrous oxide flow rate is 7300sccm, the silane flow rate is 1300sccm, the ammonia flow rate is 4700sccm, the furnace pressure is 1500mtorr, the RF power supply discharge power is 13000W, and a silicon oxynitride layer is deposited on the intrinsic amorphous silicon layer for a deposition time of 60s;

[0037] S44. Then, at 430°C, silane, phosphine and hydrogen were introduced into the furnace tube, the silane flow rate was 2800sccm, the hydrogen flow rate was 9000sccm, the phosphine flow rate was 850sccm, the furnace pressure was 3100mtorr, the RF power supply discharge power was 13000W, and a phosphorus-doped amorphous silicon layer was deposited on the silicon oxynitride layer for a deposition time of 450s;

[0038] S45. Then, silane and nitrous oxide are introduced into the furnace tube at 430°C, the nitrous oxide flow rate is 9000sccm, the silane flow rate is 2000sccm, the pressure in the furnace tube is 1800mtorr, the discharge power of the RF power supply is 13000W, and a silicon dioxide layer is deposited on the phosphorus-doped amorphous silicon layer for 100s.

[0039] S5. Annealing: Place the N-type crystalline silicon wafer after Poly in an annealing furnace to activate the phosphorus atoms and convert amorphous silicon into polycrystalline silicon.

[0040] S6. Remove PSG+RCA: remove the front and edge PSG and polysilicon winding layer;

[0041] S7.ALD: ALD is used to deposit aluminum oxide on both sides to form a front aluminum oxide layer and a back aluminum oxide layer;

[0042] S8. Positive film: using PECVD to deposit a positive anti-reflection film on the ALD-post-crystalline silicon;

[0043] S9. Back film: Using PECVD method, deposit the back anti-reflection film on the crystalline silicon behind the front film;

[0044] S10. Metallization: Printing and sintering of front and back grid lines to form front and back electrodes, completing the preparation of the battery structure.

[0045] Comparative Example

[0046] This comparative example proposes a TOPCon cell, which differs from the embodiment in that the back passivation structure of the comparative example includes an N-type crystalline silicon wafer and a 1-2nm tunneling oxide layer and an 80-120nm phosphorus-doped polysilicon layer sequentially arranged on the back of the N-type crystalline silicon wafer.

[0047] The preparation method of the TOPCon battery in this comparative example is different from that in the embodiment in that the preparation method of the back passivation structure is different: in the comparative example, the preparation process of the back passivation structure includes:

[0048] S41. The N-type crystalline silicon wafer is placed in a furnace tube, nitrous oxide is introduced into the furnace tube at 430°C, the flow rate of nitrous oxide is 9600sccm, the pressure in the furnace tube is 1950mtorr, the power of the RF power supply discharge is 12000W, and a tunneling oxide layer is deposited on the back of the N-type crystalline silicon wafer by PECVD process, and the deposition time is 100s;

[0049] S42. Then, at 430°C, silane, phosphine and hydrogen were introduced into the furnace tube, the silane flow rate was 2800sccm, the hydrogen flow rate was 9000sccm, the phosphine flow rate was 850sccm, the furnace pressure was 3100mtorr, the power was 13000W, and a phosphorus-doped amorphous silicon layer was deposited on the silicon oxynitride layer for a deposition time of 450s.

[0050] S43. Then, silane and nitrous oxide are introduced into the furnace tube at 430° C., the nitrous oxide flow rate is 9000 sccm, the silane flow rate is 2000 sccm, the pressure in the furnace tube is 1800 mtorr, the power of the radio frequency power supply discharge is 13000 W, and a silicon dioxide layer is deposited on the phosphorus-doped amorphous silicon layer for 100 seconds. The remaining steps are the same as those in the embodiment.

[0051] Test Case

[0052] The electrical performance of the TOPCon cells prepared in the embodiment and the comparative example was tested using an IV test system. The test conditions were as follows: (1) Light intensity: The sunlight intensity under AM1.5G conditions should be 1000 W / m 2, that is, the light intensity is 100MW / cm; (2) Temperature: The temperature of the photovoltaic cell is 25°C. The test results are shown in Table 1.

[0053] Table 1

[0054]

[0055] From the results in Table 1, it can be seen that the conversion efficiency of the cell of the embodiment is improved by 0.072%, which is mainly manifested in the increase of the open circuit voltage by 0.7 mV, indicating that the efficiency of the TOPCon cell prepared in the embodiment of the present application in converting light energy into electrical energy is significantly improved.

[0056] The ECV test instrument was used to perform ECV test on the wafers after annealing in the embodiment and the comparative example. The test results are shown in FIG. Figure 2 As shown, from Figure 2 It can be seen that the phosphorus atom content of the embodiment at 70nm is significantly lower than that of the comparative example, which clearly shows the reduction of the internal expansion of phosphorus atoms.

[0057] The TOPCon cells prepared in the examples and comparative examples were subjected to QE tests using an EQE test instrument. The test results are shown in FIG. Figure 3 As shown, from Figure 3 It can be seen that the response of the embodiment of the present application at the long-wave 900-1000nm is higher than that of the comparison ratio, which means that the back side of the TOPCon cell prepared in the embodiment of the present application has better light energy utilization efficiency.

[0058] The technical features of the above-described embodiments may be arbitrarily combined. To make the description concise, not all possible combinations of the technical features in the above-described embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0059] The above-mentioned embodiments only express several implementation methods of the present invention, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the invention patent. It should be pointed out that, for ordinary technicians in this field, several variations and improvements can be made without departing from the concept of the present invention, and these all belong to the protection scope of the present invention. Therefore, the protection scope of the patent of the present invention shall be subject to the attached claims.

Claims

1. A back passivation structure for reducing phosphorus in-diffusion, characterized in that: The invention comprises an N-type crystalline silicon wafer and a tunneling oxide layer, an intrinsic amorphous silicon layer, a silicon oxynitride layer and a phosphorus-doped polysilicon layer which are sequentially arranged on the back of the N-type crystalline silicon wafer.

2. The back surface passivation structure for reducing phosphorus in-diffusion according to claim 1, characterized in that: The thickness of the intrinsic amorphous silicon layer is 1-20 nm.

3. The back surface passivation structure for reducing phosphorus in-diffusion according to claim 1, characterized in that: The thickness of the silicon oxynitride layer is 1-5 nm.

4. The back surface passivation structure for reducing phosphorus in-diffusion according to claim 1, characterized in that: The thickness of the tunnel oxide layer is 0.5-3nm.

5. The back surface passivation structure for reducing phosphorus in-diffusion according to claim 1, characterized in that: The thickness of the phosphorus-doped polysilicon layer is 20-150 nm.

6. A method for preparing a back passivation structure for reducing phosphorus in-diffusion as claimed in any one of claims 1 to 5, characterized in that: It includes the following steps: S1. Place an N-type crystalline silicon wafer in a furnace tube, introduce nitrous oxide into the furnace tube at 380 to 500° C., the flow rate of nitrous oxide is 7000 to 15000 sccm, the pressure in the furnace tube is 1000 to 3000 mtorr, and a tunneling oxide layer is deposited on the back of the N-type crystalline silicon wafer by PECVD process, and the deposition time is 10 to 200 s; S2. Then, silane and hydrogen are introduced into the furnace tube at 380 to 500°C, the silane flow rate is 2000 to 4000 sccm, the hydrogen flow rate is 8000 to 13000 sccm, the pressure in the furnace tube is 2000 to 4000 mtorr, and an intrinsic amorphous silicon layer is deposited on the tunneling oxide layer for a deposition time of 10-300 s; S3. Then at 380~500 ℃, silane, ammonia and nitrous oxide are added to the furnace tube, the nitrous oxide flow rate is 5000~10000sccm, the silane flow rate is 800~4000sccm, the ammonia flow rate is 3000~6000sccm, the pressure in the furnace tube is 1000~3000mtorr, and a silicon oxynitride layer is deposited on the intrinsic amorphous silicon layer for a deposition time of 10~200s; S4. Then, at 380 to 500 ° C, silane, phosphine and hydrogen are introduced into the furnace tube, the silane flow rate is 2000 to 4000 sccm, the hydrogen flow rate is 8000 to 12000 sccm, the phosphine flow rate is 100 to 1000 sccm, the pressure in the furnace tube is 2000 to 4000 mtorr, and a phosphorus-doped amorphous silicon layer is deposited on the silicon oxynitride layer for a deposition time of 10 to 700 s; S5. Then, silane and nitrous oxide are introduced into the furnace tube at 380-500° C., the nitrous oxide flow rate is 5000-10000 sccm, the silane flow rate is 800-4000 sccm, the pressure in the furnace tube is 1000-3000 mtorr, and a silicon dioxide layer is deposited on the phosphorus-doped amorphous silicon layer for a deposition time of 10-200 s.

7. A TOPCon battery, characterized in that: The invention comprises a back passivation structure for reducing phosphorus in-diffusion as claimed in any one of claims 1 to 5.

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