Reconstructed wafer, wafer reconstruction method and display panel preparation method

Abstract

The embodiment of the present invention discloses a method for preparing a reconstructed wafer, a wafer reconstruction method, and a display panel. The first intermediate structure is obtained by removing the first substrate on one side of the epitaxial structure layer of the wafer to be divided, and the first intermediate structure corresponding to the smaller wafer to be divided is divided into multiple wafers. The wafers are bonded to a larger carrier to obtain a reconstructed wafer. The small wafer to be divided can be reconstructed into a large reconstructed wafer, so that the size of the reconstructed wafer can meet the requirements of advanced process technology. In addition, removing the first substrate first can reduce the defects of the wafers obtained by wafer division in subsequent steps, and reduce the ion contamination in the subsequent wafer reconstruction process and the display panel preparation process after obtaining the reconstructed wafer, which is beneficial to improve the yield of the reconstructed wafer and the display panel. The first substrate containing gallium arsenide is prone to produce toxic gases during cutting. Removing the first substrate in advance is beneficial to improve production safety.

Description

Technical Field

[0001] The present invention relates to the field of display technologies, and particularly to a reconstructed wafer, a wafer reconstruction method, and a method for manufacturing a display panel. Background Art

[0002] Gallium arsenide-based epitaxial wafers have high application prospects in the field of light-emitting diodes.

[0003] The epitaxial growth technology for epitaxial wafers is relatively mature at smaller sizes (such as 4 inches or 6 inches), but is relatively weak at larger sizes (such as 8 inches or 12 inches).

[0004] However, some advanced process technologies are carried out on wafers of larger sizes, and the small-sized epitaxial wafers limit the development of the light-emitting diode field towards more advanced process technologies. Summary of the Invention

[0005] The present invention provides a reconstructed wafer, a wafer reconstruction method, and a method for manufacturing a display panel, so as to perform wafer reconstruction on a small-sized wafer to be divided to obtain a large-sized reconstructed wafer, such that the reconstructed wafer can meet the requirements of advanced process technologies.

[0006] According to one aspect of the present invention, there is provided a wafer reconstruction method, including:

[0007] Removing a first substrate on one side of the epitaxial structure layer of the wafer to be divided to obtain a first intermediate structure; the epitaxial structure layer includes a first semiconductor layer, a light-emitting layer, and a second semiconductor layer that are stacked, and the first semiconductor layer is located between the light-emitting layer and the first substrate; the material of the first substrate includes gallium arsenide;

[0008] Dividing the first intermediate structure into a plurality of wafers;

[0009] Bonding the wafers to a carrier to obtain a reconstructed wafer; wherein, the area of the carrier is larger than the area of the wafer to be divided.

[0010] Optionally, removing a first substrate on one side of the epitaxial structure layer of the wafer to be divided to obtain a first intermediate structure includes:

[0011] Bonding the side of the epitaxial structure layer of the wafer to be divided away from the first substrate to a second substrate; the second substrate is different from the first substrate in material;

[0012] Removing the first substrate.

[0013] Optionally, before removing a first substrate on one side of the epitaxial structure layer of the wafer to be divided to obtain a first intermediate structure, it further includes:

[0014] Forming a current spreading layer on the side of the second semiconductor layer away from the first semiconductor layer;

[0015] Bond the side of the epitaxial structure layer of the wafer to be divided away from the first substrate to the second substrate, including:

[0016] Bond the current spreading layer to the second substrate using a first bonding layer.

[0017] Optionally, the material of the second substrate is silicon, and the material of the first bonding layer is silicon dioxide.

[0018] Optionally, removing the first substrate on one side of the epitaxial structure layer of the wafer to be divided to obtain a first intermediate structure, including:

[0019] Remove the first substrate;

[0020] Form a plurality of ohmic contact structures on the side of the first semiconductor layer away from the light-emitting layer to obtain the first intermediate structure, and the material of the ohmic contact structure is a metal material.

[0021] Optionally, dividing the first intermediate structure into a plurality of wafers, including:

[0022] Use a patterning process to open isolation on one side of the first semiconductor layer to form isolation grooves that at least penetrate the epitaxial structure layer;

[0023] Form an insulating dielectric layer on the side of the first semiconductor layer away from the light-emitting layer and on the sidewalls of the isolation grooves;

[0024] On the side of the second substrate away from the epitaxial structure layer, perform cutting along the dicing streets to divide the first intermediate structure into a plurality of wafers; wherein, the positions of the dicing streets correspond to the positions of the isolation grooves.

[0025] Optionally, the width of the dicing street is smaller than the width of the corresponding isolation groove.

[0026] Optionally, the distance between adjacent wafers on the carrier is greater than the width of the dicing street, and the distance between adjacent wafers on the carrier is greater than the width of the isolation groove.

[0027] Optionally, using a patterning process to open isolation on one side of the first semiconductor layer to form isolation grooves that at least penetrate the epitaxial structure layer, including:

[0028] Use a patterning process to open isolation on one side of the first semiconductor layer to form isolation grooves that penetrate the epitaxial structure layer and the first bonding layer between the epitaxial structure layer and the second substrate;

[0029] On the side of the second substrate away from the epitaxial structure layer, perform cutting along the dicing streets to divide the first intermediate structure into a plurality of wafers, including:

[0030] On the side of the second substrate away from the epitaxial structure layer, cut the second substrate along the dicing streets to divide the first intermediate structure into a plurality of wafers.

[0031] Optionally, bonding the wafer to a carrier to obtain a reconstructed wafer, including:

[0032] Bonding the second substrate of the wafer to the carrier to obtain a second intermediate structure;

[0033] Bonding the side of the first semiconductor layer of the second intermediate structure away from the second substrate to a third substrate;

[0034] Removing the carrier and the second substrate.

[0035] Optionally, bonding the second substrate of the wafer to the carrier to obtain a second intermediate structure, including:

[0036] Bonding the second substrate of the wafer to the carrier through a second bonding layer to obtain a second intermediate structure; the second bonding layer includes a colloid;

[0037] Removing the carrier and the second substrate includes:

[0038] Removing the carrier and the second bonding layer;

[0039] Removing the second substrate and the first bonding layer between the second substrate and the epitaxial structure layer.

[0040] Optionally, bonding the wafer to a carrier to obtain a reconstructed wafer, including:

[0041] Bonding one side of the first semiconductor layer in the epitaxial structure layer of the wafer to the carrier to obtain a third intermediate structure;

[0042] Removing the second substrate.

[0043] Optionally, bonding the wafer to a carrier to obtain a reconstructed wafer, including:

[0044] Eliminating defective wafers among multiple wafers;

[0045] Bonding multiple non-defective wafers to a carrier to obtain a reconstructed wafer; and / or

[0046] Selecting wafers with similar uniformity and consistency among multiple wafers;

[0047] Bonding the side of the epitaxial structure layer of the wafers with similar uniformity and consistency among multiple wafers away from the first substrate to the carrier to obtain a reconstructed wafer.

[0048] Optionally, the first semiconductor layer is an N-type semiconductor layer and the second semiconductor layer is a P-type semiconductor layer.

[0049] According to another aspect of the present invention, there is provided a reconstructed wafer obtained by reconstructing using the wafer reconstruction method of any embodiment of the present invention.

[0050] According to another aspect of the present invention, there is provided a method for manufacturing a display panel, including:

[0051] Patterning the epitaxial structure layers of a plurality of wafers in a reconstructed wafer to form a plurality of light-emitting structures; wherein, the reconstructed wafer is obtained by using the wafer reconstruction method of any embodiment of the present invention;

[0052] Forming a conductive connection structure on one side of the light-emitting structure;

[0053] Bonding the conductive connection structure to a driving substrate.

[0054] Optionally, in the reconstructed wafer, the wafer includes a third substrate, and a first semiconductor layer, a light-emitting layer, and a second semiconductor layer stacked on one side of the third substrate; the conductive connection structure is formed on the side of the second semiconductor layer away from the first semiconductor layer;

[0055] After bonding the conductive connection structure to the driving substrate, it further includes:

[0056] Removing the third substrate;

[0057] Performing rewiring on the side of the first semiconductor layer away from the second semiconductor layer.

[0058] In the reconstructed wafer, wafer reconstruction method, and display panel manufacturing method according to the embodiments of the present invention, by removing the first substrate on one side of the epitaxial structure layer of the wafer to be divided to obtain a first intermediate structure, dividing the first intermediate structure corresponding to the smaller-sized wafer to be divided into a plurality of wafers, and bonding the wafers to a larger-sized carrier to obtain a reconstructed wafer, it is possible to reconstruct a small-sized wafer to be divided into a large-sized reconstructed wafer, so that the size of the reconstructed wafer can meet the requirements of advanced process technologies. In addition, removing the first substrate first can reduce the defects of the wafers obtained by wafer division in subsequent steps, and reduce ion contamination in the subsequent reconstructed wafer process and the display panel manufacturing process after obtaining the reconstructed wafer, which is beneficial to improving the yield of the reconstructed wafer and the display panel. And when cutting, the first substrate containing gallium arsenide is likely to generate toxic gases. Removing the first substrate in advance is beneficial to improving production safety.

[0059] It should be understood that the content described in this part is not intended to identify the key or important features of the embodiments of the present invention, nor is it used to limit the scope of the present invention. Other features of the present invention will become easily understood through the following description. Description of the Drawings

[0060] To more clearly illustrate the technical solutions in the embodiments of the present invention, the following will briefly introduce the drawings required for the description of the embodiments. Obviously, the drawings in the following description are only some embodiments of the present invention. For those of ordinary skill in the art, without creative efforts, other drawings can also be obtained based on these drawings.

[0061] Figure 1 It is a flowchart of a wafer reconstruction method provided by an embodiment of the present invention;

[0062] Figure 2 It is a schematic structural diagram of a wafer to be divided;

[0063] Figure 3 is Figure 2 A further refined schematic structural diagram of the wafer to be divided in;

[0064] Figure 4 It is a flowchart of another wafer reconstruction method provided by an embodiment of the present invention;

[0065] Figure 5 It is a schematic structural diagram after bonding the wafer to be divided with a second substrate;

[0066] Figure 6 It is a schematic structural diagram after removing the first substrate;

[0067] Figure 7 It is a schematic structural diagram of forming a plurality of ohmic contact structures on the side of the first semiconductor layer away from the beam splitting layer;

[0068] Figure 8 It is a flowchart of another wafer reconstruction method provided by an embodiment of the present invention;

[0069] Figure 9 It is a schematic structural diagram after forming isolation grooves;

[0070] Figure 10 It is a top view of the first intermediate structure divided into a plurality of wafers;

[0071] Figure 11 is Figure 10 A cross-sectional view obtained by cutting along AA';

[0072] Figure 12 It is a top view of the second intermediate structure obtained by bonding the second substrate of the wafer to the carrier;

[0073] Figure 13 is Figure 12 A cross-sectional view obtained by cutting along BB';

[0074] Figure 14It is a schematic structural diagram after bonding the side of the first semiconductor layer of the second intermediate structure away from the second substrate to the third substrate;

[0075] Figure 15 It is a schematic structural diagram after removing the carrier and the second bonding layer;

[0076] Figure 16 It is a schematic structural diagram after removing the second substrate and the second bonding layer;

[0077] Figure 17 It is a flowchart of another wafer reconstruction method provided by an embodiment of the present invention;

[0078] Figure 18 It is a schematic structural diagram after bonding one side of the first semiconductor layer in the epitaxial structure layer of the wafer to the carrier;

[0079] Figure 19 It is a flowchart of a method for manufacturing a display panel provided by an embodiment of the present invention;

[0080] Figure 20 It is a schematic structural diagram after forming the light-emitting structure;

[0081] Figure 21 It is a schematic structural diagram after bonding the conductive connection structure to the driving substrate;

[0082] Figure 22 It is a flowchart of another method for manufacturing a display panel provided by an embodiment of the present invention;

[0083] Figure 23 It is a schematic structural diagram after removing the third substrate;

[0084] Figure 24 It is a schematic structural diagram after re-wiring on the side of the first semiconductor layer away from the second semiconductor layer. Detailed implementation manners

[0085] In order to enable those skilled in the art to better understand the solution of the present invention, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present invention.

[0086] It should be noted that the terms "first", "second", etc. in the description, claims and the above drawings of the present invention are used to distinguish similar objects and do not necessarily describe a specific order or sequence. It should be understood that the data used in this way can be interchanged under appropriate circumstances so that the embodiments of the present invention described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "comprising" and "having" and any variations thereof are intended to cover non-exclusive inclusion. For example, a process, method, system, product or device comprising a series of steps or units does not necessarily limit to those steps or units clearly listed, but may include other steps or units not clearly listed or inherent to these processes, methods, products or devices.

[0087] Figure 1 is a flowchart of a wafer reconstruction method provided by an embodiment of the present invention. Refer to Figure 1 and the wafer reconstruction method includes:

[0088] S110. Remove the first substrate on one side of the epitaxial structure layer of the wafer to be divided to obtain a first intermediate structure.

[0089] Figure 2 is a schematic structural diagram of the wafer to be divided. Figure 3 is Figure 2 a further refined schematic structural diagram of the wafer to be divided in Figure 2 and Figure 3 . Refer to Figure 3 Figure 3As shown, the first semiconductor layer 21 may include an N-GaInP layer 211, an N-GaAs layer 212, and an N-AlInP layer 213 stacked from the first substrate 10 toward the light-emitting layer 22; the second semiconductor layer 23 includes a P-AlInP layer 231 and a P-GaP layer 232 stacked from one side of the light-emitting layer 22. In an alternative embodiment, the thicknesses of the first substrate 10, the N-GaInP layer 211, the N-GaAs layer 212, the N-AlInP layer 213, the light-emitting layer 22, the P-AlInP layer 231, and the P-GaP layer 232 are 250 μm, 0.2 μm, 0.08 μm, 0.26 μm, 0.2 μm, 0.17 μm, and 0.1 μm in sequence. Of course, the thicknesses of the respective structural layers of the wafer to be divided can be adjusted according to actual needs, and the embodiments of the present invention do not make specific limitations here.

[0090] Specifically, the size of the wafer to be divided meets the requirements for epitaxial growth, and the wafer to be divided can be obtained by epitaxial growth. Since the technology of epitaxial growth is mature at a smaller size, in this embodiment, the wafer to be divided can be a wafer of a smaller size, such as a 4-inch wafer or a 6-inch wafer. Among them, the first substrate 10 can be removed by wet etching. For example, the first substrate 10 can be removed using an ammonia solution, or the first substrate 10 can also be removed using a mixed solution of a hydrochloric acid solution and a phosphoric acid solution. The first intermediate structure obtained after removing the first substrate 10 from the wafer to be divided includes the epitaxial structure layer 20 but does not include the first substrate.

[0091] In some alternative embodiments, the material of the first substrate 10 of the wafer to be divided may only include gallium arsenide. In other alternative embodiments, the material of the first substrate 10 of the wafer to be divided includes other materials in addition to gallium arsenide. Since gallium arsenide is fragile, during wafer dicing in subsequent steps, it is likely to cause defects in the wafers, and gallium arsenide is prone to ion contamination. In this step, first removing the first substrate 10 can reduce the defects of the wafers obtained by wafer dicing in subsequent steps and reduce the ion contamination during the subsequent reconstruction of the wafer and the preparation of the display panel after obtaining the reconstructed wafer. Since in the process of large-sized wafers, the requirements for the chamber are relatively high, removing the first substrate 10 in advance and reducing the ion contamination in the chamber are beneficial to improving the yield of the reconstructed wafer and the display panel. In addition, when cutting, the first substrate 10 containing gallium arsenide is likely to generate toxic gases. Removing the first substrate 10 in advance is beneficial to improving production safety.

[0092] S120. Divide the first intermediate structure into a plurality of wafers.

[0093] In this step, the wafer to be diced is diced into multiple chips. A chip can be a part of the wafer to be diced, also known as a die, which is an unpackaged semiconductor chip obtained by dicing the wafer to be diced. When dicing the wafer to be diced, an etching process and / or a cutting process can be used. The cutting process can be a laser stealth dicing process or a plasma cutting process.

[0094] S130. Bond the chips to a carrier to obtain a reconstructed wafer.

[0095] Among them, the area of the carrier is larger than the area of the wafer to be diced.

[0096] In this step, the multiple chips obtained by dicing the first intermediate structure are bonded to the carrier. The area of the carrier is larger than the area of the wafer to be diced, so as to realize the reconstruction of the wafer to be diced with a smaller size into a reconstructed wafer with a larger size, so that the size of the reconstructed wafer can meet the requirements of advanced process technologies. Exemplarily, the reconstructed wafer is a 12-inch wafer. Optionally, multiple red light emitting devices can be formed on the reconstructed wafer in subsequent processes.

[0097] In some alternative embodiments, the above S130 includes removing defective chips among the multiple chips; bonding multiple non-defective chips to a carrier to obtain a reconstructed wafer. In this way, each chip on the reconstructed wafer obtained by reconstruction can be a non-defective chip, improving the yield of the display panel prepared from the reconstructed wafer.

[0098] Among them, a defective chip is a chip including at least one of particle defects, scratch defects, bubble defects, crack and fracture defects, and lattice defects. A non-defective chip is a chip that does not include particle defects, scratch defects, bubble defects, crack and fracture defects, and lattice defects. The method for determining whether a chip is a defective chip or a non-defective chip can include optical detection, electron beam detection, light scattering detection, etc.

[0099] In some alternative embodiments, the above S130 may further include selecting chips with similar uniformity and consistency among the multiple chips; bonding multiple chips with similar uniformity and consistency to a carrier to obtain a reconstructed wafer.

[0100] Among them, wafers with close uniformity and consistency refer to wafers with a wavelength uniformity of less than 1 nm within a single wafer and a wavelength uniformity of less than 3 nm between different wafers; and the number of particles included in the wafers is less than or equal to 20 ea, where the diameter of the particles is greater than or equal to 15 μm. In addition, when bonding the side of the epitaxial structure layer of multiple wafers with close uniformity and consistency away from the first substrate to the carrier to obtain a reconstructed wafer, it is necessary to ensure that when the reconstructed wafer is a blue light wafer, the blue light wavelength range is 455 nm - 465 nm, when the reconstructed wafer is a green light wafer, the green light wavelength range is 520 - 540 nm, and when the reconstructed wafer is a red light wafer, the red light wavelength range is 615 nm - 635 nm, so as to improve the uniformity and consistency of the display panel prepared from the reconstructed wafer. In this way, the optoelectronic parameters (such as wavelength, brightness, typical parameters, etc.) of each wafer on the reconstructed wafer obtained after reconstruction can be uniform and consistent. For example, the average wavelength fluctuation range of each wafer is controlled within 1 nm, improving the uniformity and consistency of the display panel prepared from the reconstructed wafer.

[0101] The wafer reconstruction method of this embodiment can realize reconstructing a small-sized wafer to be divided into a large-sized reconstructed wafer by removing the first substrate on one side of the epitaxial structure layer of the wafer to be divided to obtain a first intermediate structure, dividing the first intermediate structure corresponding to the smaller-sized wafer to be divided into multiple wafers, and bonding the wafers to a larger-sized carrier to obtain a reconstructed wafer, so that the size of the reconstructed wafer can meet the requirements of advanced process technology. In addition, removing the first substrate first can reduce the defects of the wafers obtained by wafer dicing in subsequent steps and reduce the ion contamination during the subsequent reconstructed wafer process and the display panel preparation process after obtaining the reconstructed wafer, which is beneficial to improving the yield of the reconstructed wafer and the display panel. And when cutting the first substrate containing gallium arsenide, toxic gases are likely to be generated. Removing the first substrate in advance is beneficial to improving production safety.

[0102] Figure 4 is a flowchart of another wafer reconstruction method provided by an embodiment of the present invention. Refer to Figure 4 , this wafer reconstruction method includes:

[0103] S210: Bond the side of the epitaxial structure layer of the wafer to be divided away from the first substrate to the second substrate; the material of the second substrate is different from that of the first substrate.

[0104] Figure 5It is a schematic diagram of the structure after the wafer to be divided is bonded to the second substrate. Optionally, when the side of the epitaxial structure layer 20 of the wafer to be divided away from the first substrate 10 is bonded to the second substrate 30: when the side of the epitaxial structure layer 20 of the wafer to be divided away from the first substrate 10 does not include other structural layers, the epitaxial structure layer 20 can be bonded to the second substrate 30. When the side of the epitaxial structure layer 20 of the wafer to be divided away from the first substrate 10 includes other structural layers, the other structural layers of the epitaxial structure layer 20 away from the first substrate 10 can be bonded to the second substrate 30. Reference Figure 2 、 Figure 3 and Figure 5 , optionally, before S210, it further includes: forming a current spreading layer 40 on a side of the second semiconductor layer 23 away from the first semiconductor layer 21. Accordingly, the above S210 includes: bonding the current spreading layer 40 to the second substrate 30 using the first bonding layer 50. That is, refer to Figure 2 、 Figure 3 and Figure 5 , the other structural layer on the side of the epitaxial structure layer 20 of the wafer to be divided away from the first substrate 10 can be a current spreading layer 40. Optionally, the material of the current spreading layer 40 can be indium tin oxide ITO. When forming the current spreading layer 40, it can be achieved by plating an ITO film on the side of the second semiconductor layer 23 away from the first semiconductor layer 21. Exemplarily, the thickness of the ITO film is less than 100nm, that is, the thickness of the current spreading layer 40 can be 30nm, 50nm, 80nm, 100nm. The provision of the current spreading layer 40 can make the second semiconductor layer 23 form a reliable electrical connection with the circuit in the driving substrate after the display panel is subsequently formed and / or make the current better spread on the surface of the second semiconductor layer 23.

[0105] Optionally, the second substrate 30 is a silicon substrate, and the material of the first bonding layer 50 is silicon dioxide. When bonding the wafer to be separated to the second substrate 30, silicon melt bonding or thermal bonding can be used.

[0106] S220, removing the first substrate.

[0107] Figure 6It is a schematic structural diagram after removing the first substrate. Specifically, after bonding the epitaxial structure layer 20 of the wafer to be divided on the side away from the first substrate to the second substrate 30, the first substrate is removed. When removing the first substrate, the surface where the second substrate 30 is located is placed at the corresponding process station position, that is, it can be achieved by contacting the second substrate 30 with the carrier structure of the station, and the current spreading layer 40 will not contact the carrier structure of the process station, avoiding the surface of the current spreading layer 40 from being corroded or introducing dirt during the removal of the first substrate and some subsequent process steps, thereby ensuring that the current spreading layer 40 has a good current spreading effect. In addition, the material of the second substrate 30 is silicon, which is not easily broken compared to gallium arsenide, and will not generate ionic contamination and toxic gases during cutting, which can reduce ionic contamination and toxic gases during subsequent wafer dicing, extend the service life of the wafer reconstruction equipment, and improve production safety. In some alternative embodiments, Figure 6 The structure shown can be used as the first intermediate structure.

[0108] In another alternative embodiment of the present invention, after S220 described above, the following S230 is further included, and the structure after S230 is used as the first intermediate structure.

[0109] S230, forming a plurality of ohmic contact structures on the side of the first semiconductor layer away from the light-emitting layer to obtain the first intermediate structure, and the material of the ohmic contact structure is a metal material.

[0110] Figure 7 It is a schematic structural diagram of forming a plurality of ohmic contact structures on the side of the first semiconductor layer away from the light-splitting layer. Specifically, for a gallium arsenide-based wafer, it is relatively difficult to form an ohmic contact on the first semiconductor layer 21. In this step, by forming a plurality of metal material ohmic contact structures 60 on the side of the first semiconductor layer 21 away from the dividing layer, in the display panel structure prepared from the reconstructed wafer, the first semiconductor layer 21 can form a good ohmic contact with the conductive structure in the display panel through the ohmic contact structure 60, improving the yield and display effect of the display panel. Optionally, the material of the ohmic contact structure 60 is a gold-germanium-gold three-layer structure, with the outer two layers being gold and the middle layer being germanium. Specifically, annealing can be carried out with gold-germanium-gold at 400 °C to form the ohmic contact structure 60.

[0111] S240, dividing the first intermediate structure into a plurality of wafers.

[0112] S250, bonding the wafers to a carrier to obtain a reconstructed wafer.

[0113] Figure 8 It is a flowchart of another wafer reconstruction method provided by an embodiment of the present invention. Refer to Figure 8 , this wafer reconstruction method includes:

[0114] S310. Bond the side of the epitaxial structure layer of the wafer to be divided, which is away from the first substrate, to the second substrate (see Figure 5 ).

[0115] S320. Remove the first substrate (see Figure 6 ).

[0116] As Figure 7 shown, after removing the first substrate, it may further include forming a plurality of ohmic contact structures 60 on the side of the first semiconductor layer 21 away from the light-emitting layer 22 to obtain a first intermediate structure.

[0117] S330. Use a patterning process to open isolation on one side of the first semiconductor layer to form isolation grooves that at least penetrate the epitaxial structure layer.

[0118] Figure 9 is a schematic structural diagram after forming the isolation grooves. Figure 9 Schematically shows the situation where the isolation grooves 70 penetrate the epitaxial structure layer 20. The isolation grooves 70 can be formed by photolithography and etching processes. Since the thickness of the second substrate 30 itself is relatively thick, it is not easy to etch through the second substrate 30 using photolithography and etching processes. In this step, it is only necessary to ensure that the formed isolation grooves 70 at least penetrate the epitaxial structure layer 20. In this way, when the wafer to be divided is cut subsequently, there is no need to use a cutting process to divide the epitaxial structure layer 20. The epitaxial structure layer 20 contains gallium arsenide material, and not using a cutting process for the epitaxial structure layer 20 can avoid the generation of toxic gases due to cutting the epitaxial structure layer 20.

[0119] S340. Form an insulating dielectric layer on the side of the first semiconductor layer away from the light-emitting layer and on the sidewalls of the isolation grooves.

[0120] Continue to refer to Figure 9 , the insulating dielectric layer 80 can be located on the side of the ohmic contact structure 60 away from the light-emitting layer 22, on the side of the first semiconductor layer 21 away from the light-emitting layer 22, and on the side and bottom surfaces of the isolation grooves 70. By forming the insulating dielectric layer 80 on the sidewalls of the isolation grooves 70, the insulating dielectric layer 80 can protect the sidewalls of the isolation grooves 70 formed in the epitaxial structure layer 20, so that in some process steps, the epitaxial structure layer 20 will not be damaged, thereby reducing the generation of defective wafers. Optionally, the material of the insulating dielectric layer 80 is silicon nitride.

[0121] S350. On the side of the second substrate away from the epitaxial structure layer, cut along the scribe lanes to divide the first intermediate structure into a plurality of wafers; wherein, the scribe lanes correspond to the positions of the isolation grooves.

[0122] Figure 10 is a top view after dividing the first intermediate structure into a plurality of wafers. Figure 11Yes Figure 10 A cross-sectional view obtained by cutting along AA', refer to Figure 10 and Figure 11 Optionally, the cutting process for cutting the first intermediate structure can be a laser cutting process or a plasma cutting process. In the thickness direction of the wafer to be divided, the position of the cutting channel corresponds to that of the isolation groove 70, so that after cutting the first intermediate structure from the side of the second substrate 30 away from the epitaxial structure layer 20, the cutting gap 90 formed by cutting communicates with the isolation groove 70, and then the first intermediate structure is divided into multiple wafers 01. The wafer 01 can be a part of the wafer to be divided, also called a die, which is an unpackaged semiconductor chip obtained by dividing the wafer to be divided. In this step, the structure layer in the first intermediate structure includes the structure layer that was not etched away when opening the isolation in S320, so that after cutting, the gap 90 formed by cutting can communicate with the isolation groove 70.

[0123] Optionally, the width of the cutting channel is smaller than the width of the corresponding isolation groove 70. In this way, even if there is a certain error during cutting, the cutting gap 90 formed after cutting from the side of the second substrate 30 away from the epitaxial structure layer 20 can also communicate with the isolation groove 70, so that the adjacent wafers 01 are completely divided, ensuring that the size of the divided wafers 01 meets the requirements.

[0124] In some optional embodiments of the present invention, S330 includes forming an isolation groove 70 that penetrates the epitaxial structure layer 20 and the first bonding layer 50 between the epitaxial structure layer 20 and the second substrate 30 by using a patterning process on one side of the first semiconductor layer 21; correspondingly, S350 includes: cutting the second substrate 30 along the cutting channel on the side of the second substrate 30 away from the epitaxial structure layer 20 to divide the first intermediate structure into multiple wafers 01. In this way, it can be ensured that when there is a current spreading layer 40 on the side of the second semiconductor layer 23 away from the light-emitting layer 22, the current spreading layer 40 will also be penetrated by the isolation groove 70, and correspondingly, the insulating dielectric layer 80 will also protect the current spreading layer 40, further avoiding the generation of defective wafers 01.

[0125] S360. Bond the second substrate of the wafer to the carrier to obtain a second intermediate structure.

[0126] Figure 12 is a top view of the second intermediate structure obtained by bonding the second substrate of the wafer to the carrier, Figure 13 Yes Figure 12 A cross-sectional view obtained by cutting along BB', refer to Figure 12 and Figure 13, in this step, the total area of the second intermediate structure obtained by bonding the second substrate 30 of the wafer 01 to the carrier 100 is larger than the area of the wafer to be divided, so as to realize the reconstruction of the small-sized wafer to be divided into a larger-sized reconstructed wafer. Optionally, S360 includes bonding the second substrate 30 of the wafer 01 to the carrier 100 through the second bonding layer 101 to obtain the second intermediate structure; the second bonding layer 101 includes a colloid, and the cost of the colloid material is relatively low. Using the colloid to bond the wafer 01 and the carrier 100 is beneficial to cost saving. Since the epitaxial structure layer 20 includes gallium arsenide material, the epitaxial structure layer 20 is fragile, and using the colloid for bonding is likely to cause problems such as deformation and warping. In this embodiment, by bonding the second substrate 30 of the wafer 01 to the carrier 100 through the colloid, even if the bonding causes deformation and / or warping, the influence on the epitaxial structure layer 20 will be relatively small, so as to ensure the yield of the formed reconstructed wafer, and further ensure the yield of the display panel prepared from the reconstructed wafer. Since in the subsequent steps, both the carrier 100 and the second substrate 30 will be removed, the deformation or warping of the carrier 100 and the second substrate 30 has little influence on the reconstructed wafer.

[0127] Since after wafer reconstruction, subsequent advanced process manufacturing needs to be performed on the obtained reconstructed wafer, the spacing between the wafers 01 needs to meet the corresponding process requirements. Therefore, optionally, when bonding the wafers 01 to the carrier 100, the subsequent process requirements of multiple wafers 01 can be rearranged. Optionally, the distance between adjacent wafers 01 on the carrier 100 is greater than the width of the scribe lane, and the distance between adjacent wafers 01 on the carrier 100 is greater than the width of the isolation groove 70 to meet the requirements of subsequent advanced process manufacturing.

[0128] S370: Bond the side of the first semiconductor layer of the second intermediate structure away from the second substrate to the third substrate.

[0129] Figure 14 is a schematic structural diagram after bonding the side of the first semiconductor layer of the second intermediate structure away from the second substrate to the third substrate. Refer to Figure 14 , optionally, bond the side of the first semiconductor layer 21 of the second intermediate structure away from the second substrate 30 to the third substrate 102 through the third bonding layer 103. In the case where the insulating dielectric layer 80 is included on the side of the first semiconductor layer 21 away from the light-emitting layer 22, the insulating dielectric layer 80 on the second intermediate structure can be bonded to the third substrate 102 through the third bonding layer 103. Among them, the material of the third substrate 102 can be silicon, and the material of the third bonding layer 103 can be silicon dioxide. In this step, silicon fusion bonding or thermal bonding method can be used to bond the second intermediate structure and the third substrate 102.

[0130] S380: Remove the carrier and the second substrate.

[0131] Optionally, S380 includes removing the carrier 100 and the second bonding layer 101; removing the second substrate 30 and the first bonding layer 50 between the second substrate 30 and the epitaxial structure layer 20.

[0132] Figure 15 is a schematic structural diagram after removing the carrier and the second bonding layer, Figure 16 is a schematic structural diagram after removing the second substrate and the second bonding layer. Among them, the second substrate can be removed by chemical mechanical polishing and / or wet etching processes. Since S340 forms an insulating dielectric layer 80 on the sidewalls of the isolation trenches 70, during the process of removing the second substrate and the second bonding layer, the insulating dielectric layer 80 can protect the epitaxial structure layer 20, improving the yield of the fabricated reconstructed wafer and display panel.

[0133] In this embodiment, a reconstructed wafer is obtained after S310 - S380.

[0134] Figure 17 is a flowchart of another wafer reconstruction method provided by an embodiment of the present invention. Refer to Figure 17 , this wafer reconstruction method includes:

[0135] S410, bond the side of the epitaxial structure layer of the wafer to be divided away from the first substrate to the second substrate (see Figure 5 ).

[0136] S420, remove the first substrate (see Figure 6 );

[0137] S430, use a patterning process to open isolation on one side of the first semiconductor layer, forming at least isolation trenches penetrating the epitaxial structure layer (see Figure 9 ).

[0138] S440, form an insulating dielectric layer on the side of the first semiconductor layer away from the light-emitting layer and on the sidewalls of the isolation trenches.

[0139] S450, on the side of the second substrate away from the epitaxial structure layer, perform cutting along the scribe lanes to divide the first intermediate structure into multiple wafers; wherein, the scribe lanes correspond to the positions of the isolation trenches (see Figure 10 ).

[0140] S460, bond the side of the first semiconductor layer in the epitaxial structure layer of the wafer to the carrier to obtain a third intermediate structure.

[0141] Figure 18It is a schematic structural diagram after bonding one side of the first semiconductor layer in the epitaxial structure layer of the wafer to the carrier. In this step, by bonding one side of the first semiconductor layer 21 in the epitaxial structure layer 20 of the wafer to the carrier 100, before the subsequent step of removing the second substrate 30, there is no need to pour the epitaxial structure layer 20 of the wafer onto the third substrate again. When removing the second substrate 30, the carrier 100 can be used as the substrate on the side of the first semiconductor layer, so that process steps can be saved, and thus the efficiency of the wafer reconstruction process can be improved.

[0142] S470. Remove the second substrate.

[0143] Specifically, in this step, the second substrate and the first bonding layer between the second substrate and the epitaxial structure layer can be removed together.

[0144] In this embodiment, a reconstructed wafer is obtained after S410 - S470.

[0145] The embodiment of the present invention also provides a reconstructed wafer, which is reconstructed by using the wafer reconstruction method of any of the above embodiments of the present invention.

[0146] The embodiment of the present invention also provides a method for manufacturing a display panel. Figure 19 It is a flowchart of a method for manufacturing a display panel provided by the embodiment of the present invention. Refer to Figure 19 , and the method for manufacturing the display panel includes:

[0147] S510. Pattern the epitaxial structure layers of multiple wafers in the reconstructed wafer to form multiple light-emitting structures.

[0148] Among them, the reconstructed wafer is obtained by using the wafer reconstruction method of any of the above embodiments of the present invention.

[0149] Figure 20 It is a schematic structural diagram after forming the light-emitting structures. Among them, after patterning the epitaxial structure layer 20 of the wafer of the reconstructed wafer, multiple light-emitting structures 02 can be formed. Optionally, after patterning, the epitaxial structure layer 20 of each wafer is patterned into multiple light-emitting structures 02. Optionally, the cross-section of the light-emitting structure 02 can be Figure 20 the trapezoid shown. Among them, the light-emitting structure 02 can be a micro light-emitting device Micro-LED. An insulating layer can be provided between the light-emitting structures 02.

[0150] S520. Form a conductive connection structure on one side of the light-emitting structure.

[0151] Continue to refer to Figure 20, a positive projection of a partial conductive connection structure 104 on the driving substrate overlaps with a positive projection of a light-emitting structure 02 on the driving substrate. This partial conductive connection structure 104 is electrically connected to the light-emitting structure 02, and the positive projection of the partial conductive connection structure 104 on the driving substrate is between positive projections of adjacent light-emitting structures 02 on the driving substrate. When bonding the light-emitting structure 02 to the driving substrate, the conductive connection structure 104 can serve as a bonding structure.

[0152] S530: Bond the conductive connection structure to the driving substrate.

[0153] Figure 21 is a schematic structural diagram after bonding the conductive connection structure to the driving substrate. Refer to Figure 21 , after bonding the conductive connection structure 104 to the conductive bonding structure 106 of the driving substrate 105, the light-emitting structure 02 and the driving circuit in the driving substrate 105 form an electrical connection through the conductive connection structure 104 and the conductive bonding structure 106, enabling the driving substrate 105 to drive the light-emitting structure 02. Among them, when bonding the conductive connection structure to the driving substrate, a hybrid bonding method can be adopted.

[0154] For the manufacturing method of the display panel in this embodiment, a reconstructed wafer obtained by using the wafer reconstruction method of any of the above embodiments of the present invention is used to manufacture the display panel, which has the beneficial effects of the wafer reconstruction method of any of the above embodiments of the present invention. Moreover, since the reconstructed wafer obtained by using the wafer reconstruction method has a relatively large size, it can meet the requirements of the display panel manufacturing process for the wafer size.

[0155] Based on the above embodiments, optionally, continue to refer to Figure 20 and Figure 21 , in the reconstructed wafer, the wafer includes a third substrate 102 and a first semiconductor layer 21, a light-emitting layer 22, and a second semiconductor layer 23 stacked on one side of the third substrate 102; the conductive connection structure 104 is formed on the side of the second semiconductor layer 23 away from the first semiconductor layer 21. Among them, the side of the second semiconductor layer 23 away from the light-emitting layer 22 may further include a current spreading layer 40, and the conductive connection structure 104 may be located on the side of the current spreading layer 40 away from the first semiconductor layer 21.

[0156] Figure 22 is a flowchart of another manufacturing method of the display panel provided by an embodiment of the present invention. Refer to Figure 22 , optionally, the manufacturing method of the display panel includes:

[0157] S610: Pattern the epitaxial structure layers of multiple wafers in the reconstructed wafer to form multiple light-emitting structures.

[0158] S620. Form a conductive connection structure on one side of the light-emitting structure.

[0159] Specifically, form a conductive connection structure on the side of the second semiconductor layer away from the first semiconductor layer. In the structure shown in Figure 20 and Figure 21 , when the side of the second semiconductor layer 23 away from the first semiconductor layer 21 includes the current spreading layer 40, form a conductive connection structure 104 on the side of the current spreading layer 40 away from the first semiconductor layer 21.

[0160] S630. Bond the conductive connection structure to the driving substrate.

[0161] S640. Remove the third substrate.

[0162] Figure 23 FIG. is a schematic structural diagram after removing the third substrate. When removing the third substrate, the bonding layer between the third substrate and the wafer (i.e., the third bonding layer 103 in Figure 21 ) can also be removed. Optionally, the material of the third substrate is silicon, and the material of the bonding layer between the third substrate and the wafer can be silicon dioxide. The third substrate and the bonding layer between the third substrate and the wafer can be removed by a chemical mechanical polishing process.

[0163] S650. Perform redistribution on the side of the first semiconductor layer away from the second semiconductor layer.

[0164] Figure 24 FIG. is a schematic structural diagram after performing redistribution on the side of the first semiconductor layer away from the second semiconductor layer. Referring to Figure 24 , after removing the third substrate, a via hole 107 can be formed from the conductive connection structure 104 located between the light-emitting structures 02 to the side of the first semiconductor layer 21 away from the second semiconductor layer 23, and a conductive material is filled in the via hole 107. Then, redistribution is performed on the side of the first semiconductor layer 21 away from the second semiconductor layer 23, so that the first semiconductor layers 21 of the respective light-emitting structures 02 are interconnected to form a common electrode structure. During the redistribution process, connection pads in the display panel can also be formed.

[0165] Optionally, in the above embodiments of the present invention, each wafer can be used to form at least one display panel. In some alternative embodiments, each wafer can be used to form at least two display panels. Subsequently, steps of dividing the display panels corresponding to different wafers or dividing different display panels corresponding to the same wafer can also be performed.

[0166] It should be understood that the various forms of processes shown above can be used, with steps reordered, added, or deleted. For example, the steps described in the present invention can be executed in parallel, sequentially, or in different orders, as long as the desired results of the technical solution of the present invention can be achieved, and no limitation is imposed herein.

[0167] The above specific embodiments do not constitute a limitation on the protection scope of the present invention. Those skilled in the art should understand that various modifications, combinations, sub - combinations, and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principle of the present invention shall be included within the protection scope of the present invention.

Claims

1. A wafer reconstruction method, characterized in that: include: Removing the first substrate on one side of the epitaxial structure layer of the wafer to be split to obtain a first intermediate structure; The epitaxial structure layer comprises a first semiconductor layer, a light emitting layer and a second semiconductor layer which are stacked, wherein the first semiconductor layer is located between the light emitting layer and the first substrate; and the material of the first substrate comprises gallium arsenide; dividing the first intermediate structure into a plurality of wafers; Bonding the wafer to a carrier to obtain a reconstructed wafer; wherein the area of ​​the carrier is larger than the area of ​​the wafer to be divided; The epitaxial structure layer of the chip of the reconstructed wafer is used to form a plurality of light-emitting structures after being patterned.

2. The wafer reconstruction method according to claim 1, characterized in that: The step of removing the first substrate on one side of the epitaxial structure layer of the wafer to be divided to obtain a first intermediate structure includes: Bonding a side of the epitaxial structure layer of the wafer to be divided away from the first substrate to a second substrate; the second substrate is made of a different material from the first substrate; The first substrate is removed.

3. The wafer reconstruction method according to claim 2, characterized in that: Before removing the first substrate on one side of the epitaxial structure layer of the wafer to be divided to obtain the first intermediate structure, the method further includes: forming a current spreading layer on a side of the second semiconductor layer away from the first semiconductor layer; The step of bonding the epitaxial structure layer of the wafer to be divided away from the first substrate to the second substrate comprises: The current spreading layer and the second substrate are bonded by using a first bonding layer.

4. The wafer reconstruction method according to claim 3, characterized in that: The material of the second substrate is silicon, and the material of the first bonding layer is silicon dioxide.

5. The wafer reconstruction method according to any one of claims 1 to 4, characterized in that: The step of removing the first substrate on one side of the epitaxial structure layer of the wafer to be divided to obtain a first intermediate structure includes: removing the first substrate; A plurality of ohmic contact structures are formed on a side of the first semiconductor layer away from the light-emitting layer to obtain the first intermediate structure, and the material of the ohmic contact structure is a metal material.

6. The wafer reconstruction method according to claim 2, characterized in that: The step of dividing the first intermediate structure into a plurality of wafers comprises: Using a patterning process to open an isolation groove on one side of the first semiconductor layer to form an isolation groove that at least penetrates the epitaxial structure layer; forming an insulating dielectric layer on a side of the first semiconductor layer away from the light emitting layer and on a sidewall of the isolation trench; On a side of the second substrate away from the epitaxial structure layer, cutting is performed along a cutting line to divide the first intermediate structure into a plurality of wafers; wherein the cutting line corresponds to a position of the isolation groove.

7. The wafer reconstruction method according to claim 6, characterized in that: The width of the scribe line is smaller than the width of the corresponding isolation groove.

8. The wafer reconstruction method according to claim 6, characterized in that: The distance between adjacent wafers on the carrier is greater than the width of the dicing road, and the distance between adjacent wafers on the carrier is greater than the width of the isolation groove.

9. The wafer reconstruction method according to claim 6, characterized in that: The method of using a patterning process to open an isolation groove on one side of the first semiconductor layer to form an isolation groove that at least penetrates the epitaxial structure layer includes: Using a patterning process to open an isolation on one side of the first semiconductor layer to form an isolation groove that penetrates the epitaxial structure layer and the first bonding layer between the epitaxial structure layer and the second substrate; Cutting along a cutting path on a side of the second substrate away from the epitaxial structure layer to divide the first intermediate structure into a plurality of wafers includes: The second substrate is cut along a cutting line on a side of the second substrate away from the epitaxial structure layer to divide the first intermediate structure into a plurality of wafers.

10. The wafer reconstruction method according to claim 2, characterized in that: The step of bonding the wafer to a carrier to obtain a reconstructed wafer comprises: Bonding the second substrate of the wafer to the carrier to obtain a second intermediate structure; bonding a side of the first semiconductor layer of the second intermediate structure away from the second substrate to a third substrate; The carrier and the second substrate are removed.

11. The wafer reconstruction method according to claim 10, characterized in that: The step of bonding the second substrate of the wafer to the carrier to obtain a second intermediate structure comprises: Bonding the second substrate of the wafer to the carrier via a second bonding layer to obtain the second intermediate structure; the second bonding layer includes a colloid; The removing the carrier and the second substrate comprises: removing the carrier and the second bonding layer; The second substrate and the first bonding layer between the second substrate and the epitaxial structure layer are removed.

12. The wafer reconstruction method according to claim 2, characterized in that: The step of bonding the wafer to a carrier to obtain a reconstructed wafer comprises: Bonding one side of the first semiconductor layer in the epitaxial structure layer of the wafer to the carrier to obtain a third intermediate structure; The second substrate is removed.

13. The wafer reconstruction method according to claim 1, characterized in that: The step of bonding the wafer to a carrier to obtain a reconstructed wafer comprises: Removing defective wafers from the plurality of wafers; bonding a plurality of non-defective wafers to the carrier to obtain a reconstructed wafer; and / or Selecting a wafer with similar uniformity and consistency among multiple wafers; The side of the epitaxial structure layer of a wafer with similar uniformity and consistency among the multiple wafers, which is away from the first substrate, is bonded to a carrier to obtain a reconstructed wafer.

14. The wafer reconstruction method according to claim 1, characterized in that: The first semiconductor layer is an N-type semiconductor layer, and the second semiconductor layer is a P-type semiconductor layer.

15. A reconstructed wafer, characterized in that: The wafer is reconstructed by using the wafer reconstruction method described in any one of claims 1 to 14.

16. A method for preparing a display panel, characterized in that: include: The epitaxial structure layers of the plurality of wafers in the reconstructed wafer are patterned to form a plurality of light-emitting structures; wherein the reconstructed wafer is obtained by the wafer reconstruction method according to any one of claims 1 to 13; forming a conductive connection structure on one side of the light emitting structure; The conductive connection structure is bonded to the driving substrate.

17. The preparation method according to claim 16, characterized in that: In the reconstructed wafer, the wafer includes a third substrate and the first semiconductor layer, the light emitting layer and the second semiconductor layer stacked on one side of the third substrate; The conductive connection structure is formed on a side of the second semiconductor layer away from the first semiconductor layer; After bonding the conductive connection structure to the drive substrate, the method further includes: removing the third substrate; Rewiring is performed on a side of the first semiconductor layer away from the second semiconductor layer.

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