Processor system and method for operating the same

Abstract

Disclosed herein is a processor system (1) comprising a plurality of processor cores and a message exchange network, the processor system (1) configured to execute a neural network having at least a first neural network layer and a second neural network layer. A first of the processor cores is configured to transmit the plurality of activation event data in a packed message that includes a common indication for sources of the plurality of activation event data in the first neural network layer. Thus, the load of the message exchange network can be significantly reduced. And the access times of the memory can be reduced.

Description

Background Art

[0001] The present disclosure relates to a processor system including a plurality of processor cores and a message switching network, the processor system being configured to execute a neural network.

[0002] The present disclosure also relates to methods of operating such a processor system.

[0003] In a processor system as disclosed herein, respective processor cores are assigned to respective neural network layers or portions thereof. That is, during execution, the processor cores assigned to the neural network layer or portion thereof perform the calculations and operations defined by the neural network elements (also represented as neurons) in the neural network layer or portion thereof. The word "assigned processor core" of a neuron will be used herein to refer to the processor core assigned to the neural network layer or portion thereof that includes the neuron.

[0004] In a processor system executing a neural network, a computation in a processor core is triggered by the arrival of an event containing an output value as a result of the activation of a neuron of the neural network executed by the processor core. Typically, the event is sent from the processor core that computes the activation to all processor cores that are to process the successors of the activated neuron. In each of those processor cores, the event is typically received in an event queue and then processed by accessing the neuron states of all successors of the activated neuron and updating them. In the literature in this technical field, neuron states are also referred to as neuron or membrane potentials. This known process has the following inefficiencies:

[0005] For each activation event, the coordinate values ​​of the event and the identifier of the target neural network layer or its part must be sent.

[0006] For each activation event received by a receiving processor core, the receiving processor core must read the neuron state from memory, recompute the neuron state, and write the recomputed neuron state back to memory for each neuron to be updated. Neuron state reading and writing is responsible for a large proportion of the energy consumption when updating neuron state, and consumes a large proportion of the available memory bandwidth. Summary of the invention

[0007] The goal is to mitigate at least some of these inefficiencies.

[0008] According to this, an improved processor system as defined in claim 1 is proposed.

[0009] An improved method of operating a processor system as defined in claim 10 is also proposed.

[0010] The improved processor system as defined in claim 1 comprises a plurality of processor cores and a message exchange network, wherein the processor cores are configured to exchange messages between each other using the message exchange network. In an example, the plurality of processor cores are arranged on a single integrated circuit and the message exchange network is arranged as a network on chip (NoC). It is also conceivable that the improved processor system comprises a plurality of such integrated circuits coupled to each other via a further message exchange network. The processor cores are arranged as dedicated hardware configured to perform neural network operations such as neuron state evaluation, or as programmable processor units having an instruction set including dedicated instructions for such operations.

[0011] The claimed processor system is configured to execute a neural network having at least a first neural network layer and a second neural network layer. In practice, the neural network may have tens or hundreds of layers, but for the subsequent description, it is assumed that there are at least two neural network layers.

[0012] The first neural network layer has a corresponding first feature map, and the second neural network layer has a corresponding second feature map. The feature map corresponding to the neural network layer includes a plurality of feature map data elements, each of which indicates a neural state of a corresponding neuron of the neural network layer. The feature map data can be addressed by a group consisting of two or more coordinates, the group consisting of two or more coordinates including at least a position coordinate indicating a position in the feature map and a channel coordinate indicating an element of a feature channel at the indicated position. A simple example of a feature map is an image of a matrix with image values. A pixel in the image has a plane coordinate x, y, and may have a pixel value for each of three color channels. The color channel may be considered a feature channel. Thus, in this example, the feature map data may be represented by the value of each of the color channels at each position in the feature map. In another example, the feature map is a two-dimensional space having one dimension t indicating time and another dimension specifying a sound channel. Similarly, in a convolutional neural network, a neural network layer generates a feature map defined by the value of each of the feature channels at each position in the feature map. At this point, it is assumed that the feature map is defined by two spatial coordinate (position coordinate) pairs and channel coordinates specifying a channel. However, other embodiments can be envisaged, in which the feature map has more than two spatial coordinates, such as, for example, in a three-dimensional image.

[0013] The processor system is configured to execute a neural network because, in operation, it performs all operations involved in the execution of the neural network. Herein, a first processor core in the processor core executes at least a portion of a first neural network layer. This includes the option that the first processor core in the processor core executes the entire first neural network layer. In operation, the first processor core in the processor core evaluates the neuron state in the first feature map or a corresponding portion thereof. The processor core evaluates the neuron state, for example, by calculating an autonomous state change, for example, by calculating a state change based on a leakage model or by performing an integration process. In addition, the processor core can change the neuron state during the evaluation in response to an event message. Based on the evaluation, the processor core generates activation event data to be transmitted to a second processor core in the processor core that executes at least a portion of a second neural network layer. Typically, the neuron state is considered to be a membrane potential. If the processor core has determined that the membrane potential of the neuron exceeds a threshold as a result of the evaluation, the activation event data is transmitted. In an embodiment, the processor core is configured to perform these two operations in mutually different operation phases. In the first phase, the processor core performs a state evaluation of all neurons of the neural network layer or a portion thereof, and in a subsequent phase, the processor core performs the operations required for generating the activation event data. In an alternative embodiment, the processor core is configured to immediately perform operations for generating activation event data for a neuron when it determines that an activation condition is met (eg, a threshold level is exceeded).

[0014] It is assumed that the processor core receiving the activation event message stores the neural state of the neurons executed by it in a dedicated state memory. The neural network executed by the processor system may additionally include stateless neurons. The processor core executing the neural network layer with stateless neurons calculates the state data from scratch each time. This may be different for each layer. That is, some neural network layers may have reserved storage space accessible to the executing processor core for storing feature maps of the neural network layer, and other neural network layers may have volatile neural state data.

[0015] If a processor core assigned to a first neural network layer generates activation event data, the activation event data is addressed to a specific neuron of a second neural network layer. Then, a second processor core executing a second neural network layer or a portion thereof including the specific neuron updates the neural state of the specific neuron upon receiving the activation event data.

[0016] The improved processor system is characterized in that a first processor core of the processor cores is configured to transmit in a packed message a plurality of activation event data emitted by a plurality of neurons in the first neural network layer having a common value for at least one of their coordinates, wherein the packed message comprises the at least one common coordinate value. In this way, a load reduction of the message exchange network is achieved, since the total amount of source coordinate data to be transmitted is less than if corresponding source coordinate data were transmitted for each activation event. Furthermore, less cache space needs to be reserved by the receiving processor core to store the packed messages than would be the case without the claimed measures.

[0017] In some embodiments, the common value of at least one of the coordinates includes a corresponding common value of each of the position coordinates of neurons in the first neural network layer for which the events bundled in the packaged message are generated, and the packaged message includes a corresponding indication of the channel coordinates of the neuron and the corresponding activation event value for each of the plurality of activation event data. Thus, the message is packaged such that all activation events originate from neurons of the first neural network layer having the same feature map position coordinate value. Thus, the value of the feature map position coordinate needs to be transmitted only once.

[0018] In an example of this embodiment, the indication of the channel coordinates (Z) for each of the multiple activation event data includes an absolute value of the channel coordinates for a first neuron among the neurons for which the activation event data is transmitted and one or more relative values, each of which indicates the difference between the absolute value of the channel coordinates of the neuron for which the activation event data is transmitted and the absolute value of the channel coordinates of the previous neuron for which the activation event data is transmitted.

[0019] The inventors have recognized that, in practice, the differences in channel coordinate values ​​of neurons having a common position in the first neural network layer generating the event are relatively small compared to the available channel coordinate address range. Thus, the relative value can be encoded with a substantially smaller number of bits than the number of bits required to encode the absolute channel coordinate value. Thus, the event message can be encoded even more compactly in the packed message. For example, only each of the four channel coordinate values ​​is provided as an absolute address. The remaining three channel coordinate values ​​are provided as relative addresses (i.e., relative to the previous address) having fewer bits. For example, the relative channel coordinate values ​​are encoded with at most half the number of bits used to encode the absolute channel coordinate value.

[0020] At this point, it is observed that, instead of packing activation event data with common channel coordinate values ​​or a common set of position coordinate values ​​in the first neural network layer, it is alternatively conceivable to pack activation event data with common channel coordinate values. In the case of packing event data with common channel coordinate values, the packing message includes a corresponding indication for each position of the neuron for which event data is emitted. Moreover, in this case, additional compaction is possible by encoding the absolute coordinate values ​​of only one of those neurons and by encoding the relative coordinate values ​​of the other event data in a similar manner as specified for encoding the relative channel coordinate values.

[0021] However, it is considered more efficient to pack activation event data with common source feature map position coordinate values.

[0022] In some embodiments, the second processor core performs all neuron state updates for the neuron in the second neural network layer or portion thereof that includes the neuron before it proceeds to perform neuron state updates for subsequent neurons in the second neural network layer or portion thereof. Thus, the processor core executing (portion of) the second neural network layer that includes the neuron only needs to access the storage space for neural state data once to obtain the current state, and access the storage space for neural state data once to write back the new state after the processor core has performed updates based on the plurality of event data in the packed message.

[0023] In some embodiments of the processor system, the first processor core in the processor core is configured to temporarily cache the activation event data generated when evaluating the neuron state of the first feature map. This makes it possible to more efficiently bind the activation event data in the packaged message. For example, in the case of sparse activation, activation event data of positions with specific position coordinate values ​​can be collected in the cache area until a sufficient number of activation events with relatively small channel coordinate value differences can be packaged so that a small number of bit values ​​are sufficient to indicate the difference. In an example thereof, the first processor core in the processor core is configured to transmit a packaged message for a predetermined number of cached activation event data. In this way, the message exchange network load can be controlled. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] These and other aspects are described in more detail with reference to the accompanying drawings, in which:

[0025] Figure 1 Schematically illustrates an embodiment of an improved processor system including a plurality of processor cores and a message switching network;

[0026] Figure 2 An example of allocating processor cores to two neural network layers of a neural network is shown;

[0027] Figure 3 Schematically showing the feature maps of two neural network layers;

[0028] Figure 4 Components of an exemplary processor core are shown;

[0029] Figure 5 schematically illustrating aspects of an improved method for operating an improved processor system;

[0030] Fig. 6A , Figure 6B shows the head phit and body phit emitted in the first operating mode;

[0031] Fig. 7A , Figure 7B shows the head phit and body phit emitted in the second operating mode in the first case;

[0032] Fig. 8A shows the header phit issued in the second case in the second operating mode;

[0033] Figure 8B shows the volume phit emitted for every four events in the second operating mode in the second case;

[0034] Figure 8C shows the additional volume phit emitted for every two events in the second case in the second operating mode;

[0035] Fig. 9 The operational steps performed by the receiving processor core are shown;

[0036] Fig.10 An exemplary process for updating a single destination neuron based on multiple events in a packet is shown. DETAILED DESCRIPTION

[0037] Throughout the application, like reference numerals in the various drawings indicate like elements unless otherwise indicated.

[0038] Figure 1 Schematically illustrated is a processor system 1 including a plurality of processor cores 100 and a message exchange network 20. In the illustrated embodiment, the message exchange network 20 includes a network node 21 for each processor core 100, and mutually adjacent network nodes 21 are coupled by a network link 22. The processor cores 100 are configured to exchange messages between each other using the message exchange network 20. In the illustrated example, the multi-processor system includes additional components, such as an arithmetic processor core 200 specifically adapted for arithmetic calculations. The processor system 1 is also coupled to a main processor 300.

[0039] The processor system is configured to execute a neural network having at least a first neural network layer and a second neural network layer. Figure 2 In the example shown in , the network has n layers. By way of example, for subsequent layers L k , L k+1 (defined herein as at least a first neural network layer and a second neural network layer) for specific reference.

[0040] like Figure 2 As schematically shown in the figure, the first neural network layer L k With the first feature map F k , and the second neural network layer L k+1 With the corresponding second feature map F k+1 The feature map of the neural network layer includes a plurality of feature map data elements each indicating a neural state of a corresponding neuron of the neural network layer, and the feature map data can be addressed by a group consisting of at least two coordinates, the group consisting of at least two coordinates including at least a position coordinate (here a position coordinate (x, y) pair) for indicating a position in the feature map and a channel coordinate (i, z) for indicating an element of a feature channel at the indicated position. For example, Figure 3 As shown in the figure, the neural network layer L k , L k+1 The feature map F k 、F k+1 It has a width D in the x-coordinate direction. x , and has a value of D in the y-coordinate direction y In the example shown, the first feature map F k With D i channels, and the second feature map F k+1 With D z channels. Thus, the first feature map F k The feature map data elements of can be uniquely addressed using a first coordinate triplet, and a second feature map F k+1 The feature map data elements can be uniquely addressed using the second coordinate triplet.

[0041] like Figure 2 As schematically shown in FIG. 1 , the first processor core (specifically denoted as 100_k_1) in the processor core 100 executes the first neural network layer L k This means that the processor core 100_k_1 is configured to evaluate the first feature map F corresponding to at least a part of the first neural network layer to which it is assigned. k and is configured to generate activation event data based on the evaluation. Figure 2As shown in the example of FIG. 1 , each of the processor cores 100_k_1, 100_k_2, 100_k_3 executes a first neural network layer L k Partitioning implies that each of the processor cores performs computations for a subset of neurons (e.g., a subset defined by a spatial region in a coordinate space defined by position coordinates x, y or a subset defined by a subset of channels). Similarly, a second processor core in the processor core 100 (specifically denoted as 100_k+1_1, 100_k+1_2, and 100_k+1_3) performs computations for a second neural network layer L k+1 corresponding part of .

[0042] The activation event data generated by a first processor core of the processor cores, such as core 100_k_1, is addressed to specific neurons of the second neural network layer. Upon receiving the activation event data, a second processor core, such as 100_k+1_1, executing the second neural network layer or portion thereof including the specific neurons, updates the neural states of these specific neurons.

[0043] In the improved processor system 1, a first processor core among the processor cores, for example core 100_k_1, is configured to transmit in a packed message a plurality of activation event data emitted by a plurality of neurons in a first neural network layer having a common value for at least one of their coordinates, wherein the packed message includes the at least one common coordinate value.

[0044] Figure 4 Schematic diagram showing the execution of the first neural network layer L k 1. As shown therein, the core includes a processor 110 configured to execute a process for evaluating a first feature map F. k The processor 110 provides the generated activation event data to the event queue 120. The processor core 100 also includes an event message generation module 130, which is configured to transmit multiple activation event data in a packaged message.

[0045] In the illustrated embodiment, the event message generation module 130 is capable of operating in an operating mode selected from a plurality of potential operating modes. The plurality of potential operating modes include a deep neural network operating mode represented as a DNN mode. As specified below, the DNN mode of the event message generation module 130 is the most relevant operating mode for the purposes of the present application, because the DNN mode of the event message generation module 130 utilizes the regularity of the interconnection of neurons in a deep neural network to effectively use the message exchange network. However, in the illustrated embodiment, the plurality of potential operating modes also include a data flow graph mode represented as a DFG mode. If there is no regularity of interconnection, the DFG mode is particularly suitable. This may be the case if the processor core executes a data flow graph in which the computational units that exchange messages are actors rather than neurons. In another exemplary embodiment, the event message generation module 130 always operates in the DNN mode. In other other embodiments, in addition to the DNN mode, the event message generation module 130 also has two or more alternative potential operating modes.

[0046] Also refer to Figure 5 An exemplary operation of the event message generation module 130 is described. In this section, the amount of data transmitted in a single cycle across a NoC link is referred to as a phit (physical unit). A flow control unit is denoted as a flit and represents a group of phits that are routed together. A flit is the smallest routable unit. A single phit does not necessarily contain routing information and can therefore be routed only in the context of the flit to which it belongs. A flit may require several cycles (= phit) to traverse a link.

[0047] In process block S1, the same initialization process is performed for both operating modes. During the initialization process, the following is created: Fig. 6A , Fig. 7A , Fig. 8AThe message header "HDR" shown in one of the above includes routing information for the remaining part of the flit. The router is used to establish a connection and route all phits belonging to the same flit (atomically) through the connection. In this example, the field "Channel" indicates the (physical) channel used to route across the flit, and the values ​​"CLY", "CLX" encode the relative y hops and x hops towards the destination core. In addition, the field "Queue" specifies which event queue is to be used by the receiving processor core. Therefore, the selection of the receiving queue is separated from the selection of the physical channel. Thus, the value of the field queue has no additional effect on the routing and switching strategy. Near this routing information, the header phit HDR includes a field "L" which is used to specify the length of the flit measured in the remaining phit, that is, the total number of phits minus 1. Since each header phit is always followed by at least one additional phit, the length is encoded as the total number of remaining phits in the flit minus 1. That is, when the length is zero, exactly one phit will be behind the header. Finally, the header phit HDR contains a field "Mode" which is used to indicate one of the operating modes {DFG, DNN}. In DFG mode, the message encodes a single activation event. In DNN mode, the message may include multiple activation event data. The header phit HDR also contains a content field "Content" which will be filled in a further processing step, as specified below.

[0048] The header Phit HDR is input as the first item of the list to be included in the message. Therefore, the list "lst" is initialized as:

[0049] Lst=[HDR]

[0050] As a further initialization operation in process block S1, an activation event is obtained from the event queue 120, which is symbolically represented as:

[0051] e = EvtQ.pop()

[0052] The item counter "i" is also initialized.

[0053] i=0

[0054] Subsequently, in process block S2 it is determined whether the event message generation module 130 is operating in DFG mode or DNN mode. This is indicated in the mode field of the header phit HDR.

[0055] If the event message generation module 130 is in DFG mode, then proceed to process block S3. Fig. 6AAs shown in , the address of the destination neuron within the destination neural network layer or part thereof executed by the destination core is specified in the content field of the header Phit HDR. The destination neuron is specified as e.nid in the event message obtained from the queue 120.

[0056] like Figure 6B As shown in , the list is further extended with body phit B1, in which the value e.value of event e is assigned to the value field. Figure 6B The abbreviation "RSV" is used in the and other figures to indicate a reserved field. It will be appreciated that a reserved field may be used, such as in this case, to specify a value to be transferred with greater precision or for other purposes.

[0057] The operation then ends with process block S4, where the length of the message is specified in field L of the header Phit HDR. As described above, in order to use the fields efficiently, the length is specified as the length of the list [HDR, B1] minus 2, i.e., here L = 0. The list is then sent out.

[0058] If it is determined in process block S2 that the event message generation module 130 is operating in DNN mode, then in process block S5, this is done at the head of the list Phit HDR (see Fig. 7A ) is indicated in the mode field mode (mode = DNN).

[0059] Subsequently, in process block S6, it is determined whether the event queue 120 is empty. If this is the case, the process continues with process block S7, where, if Figure 7B As shown in , the body Phit B2 is added to the list. The value field therein is assigned the value e. value of the activation event. In addition, the channel coordinate value indicating the neuron addressed by the event and the indicated PID of the weight set to be used by the receiving processor core are specified therein.

[0060] After process block S7, the operation ends with process block S4 as specified above. That is, the list lst[HDR, B2] is sent.

[0061] If it is determined in process block S6 that the event queue 120 is not empty, then in process block S8 it is determined whether the value counter i modulo 4 is equal to 0. If this is the case, the next process block is S9. Otherwise, the next process block is S10. Fig. 8A The header HDR shown in indicates the total number of blocks in the list with a field L. The value of L is the number of blocks (phit) minus 2.

[0062] In process block S9, if Figure 8BThe body phit B3 shown in is appended to the list. The field PID is assigned the value B3.PID=e.PID in body phit B3, which is the channel coordinate value of the neuron that is the source of event e. This determines the first set of weights to be used by the receiving processor core. The event message generation module 130 temporarily stores this channel coordinate value as the variable "base", i.e. base=e.PID.

[0063] In process block S10, a field Δk (where k=1, 2 or 3 in this case) is assigned a value indicating the difference between the value of the PID of the current event and the value stored in the variable base. That is, field B3.Δk=e.PID-base, where k=i modulo 4.

[0064] Then, the variable base is assigned the value of the PID of the current event, that is, base = e.PID.

[0065] In special cases, it may happen that the value e.PID-base exceeds the maximum value that can be encoded in field B3.Δk. In this case, other procedural steps may be performed to deliver the event data. For example, in this case, it may be possible to use e.PID-base to Figure 7B The phit transmission event data of type B2 shown in FIG.

[0066] After executing either process block S9 or S10, the process executes process block S11, in which it is determined whether the value counter i is a multiple of 2. If this is the case, then in process block S12, Figure 8C The new body phit B4 shown in is appended to the list. Process block S12 is followed by process block S13, in which the field Valuek (here, k=1 or 2) is assigned the value of the current active event e (i.e., the latest event retrieved from the event queue 120). Therefore, B4.value_k=e.value, where k=i modulo 2.

[0067] If it is determined in process block S11 that the value i is not a multiple of 2, the process skips process block S12 and instead proceeds directly to process block S13.

[0068] Process block S13 is followed by process block S14 to determine whether a stop condition is met. The stop condition is met in any of the following situations:

[0069] a) The event queue is empty

[0070] b) The event counter has a predetermined maximum value, for example 7.

[0071] If the stop condition is met, the operation ends with process block S4 as specified above.

[0072] If the stop condition is not met, the operation continues to process block S15 where the next event e is popped from the event queue and the event counter i is incremented by 1. Process block S15 is followed by process block S8 as described above.

[0073] Thus, in the illustrated embodiment, the event message generation module 130, when operating in the DFG mode, will transmit a message including Fig. 6A Head HDR and Figure 6B When operating in DNN mode, if there is only one activation event in the event queue 120, the event message generation module 130 will transmit a message including Fig. 7A Head HDR and Figure 7B If the event message generation module 130 operates in DNN mode and the event queue 120 contains more than one activation event, the event message generation module 130 will send a packaged message including the following: Fig. 8A The head HDR shown in the figure, followed by the body phit of type B3 ( Figure 8B ) and type B4 body phit( Figure 8C ). The packed message then includes a message having the format specified as: HDR[B3, B4, B4] n1 [B3, B4] n2 A list of phit.

[0074] Note that in the above examples, it is assumed that the maximum number of activation events that are packaged is 8. In alternative embodiments, a smaller or larger number of events are packaged. In addition, other phit types for transmitting packaged messages can be envisioned. For example, a phit of type B3 can be replaced with a phit having more or fewer address fields, or a phit of type B4 can be replaced with a phit having more or fewer value fields. In addition, phit types having both address and value fields can be envisioned.

[0075] As described above, processor core 100 includes processor 110, which is configured to perform operations for evaluating a feature map, such as a neuron state in feature map Fk, and operations for generating activation event data based on the evaluation. According to one option, processor 110 performs neuron state evaluation and activation event data generation in mutually independent operation phases. According to another option, this is more common in neuromorphic and other event-based AI machines where there is no separate readout phase. According to this option for each update of the neuron's neural state caused by an event, the assigned processor core evaluates the neuron's activation function, and if the assigned processor core determines that the neuron's state meets the excitation condition, an output event is generated.

[0076] In the example, the processor 110 updates the neural states of neurons in a Z-first order. That is, the processor core updates the neural states in a sequence of feature map elements with predetermined position coordinate values ​​x, y pairs arranged along the z-axis before continuing with the next sequence of feature map elements with another x, y coordinate value pair arranged along the z-axis. If all updates of the current input event are evaluated in a target Z-first order, the activation events caused by the updates can be effectively bound for transmission as packaged messages. It should be noted that activation events can be bound in other ways. For example, it is conceivable to bind event messages obtained by evaluating neurons in an area in the XY plane or even on the entire XY plane while keeping the Z coordinate value constant. This method enables the reuse of a portion of the state information and weights, however, due to sparsity, not all state information can be retained.

[0077] If the assigned processor cores perform the neuron state evaluation and the generation of activation event data in mutually independent operating phases, it is sufficient for the assigned processor cores to generate activation events only in a certain order.

[0078] exist Figure 5 In an embodiment, the common indication in the packaged message includes a corresponding value for each of the first position coordinates and the second position coordinates (X, Y), and an indication of the channel coordinate value (Z) and the corresponding activation event value for each of the multiple activation event data.

[0079] Fig. 9 The operations performed by the processor core are shown. The processor core receives the Figure 5 The message transmitted during the process.

[0080] In process block S21, the receiving processor core receives the header HDR of the message.

[0081] In process block S22, the receiving processor core identifies the mode indicated in the header HDR.

[0082] If the mode is indicated as DFG, the receiving processor core proceeds to process block S23, where the receiving processor core also receives the following Figure 6B and then updates the individual neurons identified in the head HDR based on the transmission values ​​included in the body phit B1.

[0083] If the mode is indicated as DNN, the receiving processor core proceeds to process block S24 where the receiving processor core determines whether the value L is different from zero.

[0084] If the value L is equal to 0, the receiving processor core proceeds to process block S25, wherein the receiving processor core also receives Figure 7Band then updates the data in the header HDR ( Fig. 7A ) and body phit B2( Figure 7B ) of individual neurons identified in .

[0085] If the value L is greater than 0, the receiving processor core initializes the data element counter i at 0 and proceeds to process block S26, where the receiving processor core also receives the data element counter i at 0. Figure 8B The body phit of type B3 shown in . The body phit B3 includes an absolute channel coordinate value of a first neuron addressed by an event in the packed message, and relative channel coordinate values ​​of one or more other neurons addressed by other events in the packed message. Each of the relative channel coordinate values ​​indicates the difference between the z coordinate of the associated source neuron and the z coordinate of the source neuron associated with the previous event in the packed message. The relative channel coordinate values ​​are specified with a smaller number of bits than the absolute channel coordinate values. For example, the number of bits reserved for each relative channel coordinate value is at most half the number of bits reserved for the absolute channel coordinate value.

[0086] The receiving processor core then proceeds to process block S27, wherein the receiving processor core also receives Figure 8C The body of type B4 shown in phit contains data value information.

[0087] In subsequent process block S28, the receiving processor core inputs data elements from the data received in process blocks S26, S27. The receiving cluster may directly perform a neural network update operation based on the received data elements, but alternatively, it may cache the received data elements before performing an update operation.

[0088] In a subsequent process block S29, the receiving processor core increments the data element counter by one.

[0089] If it is determined in process block S30 that the counter has reached a maximum value, then the process stops in process block S31. At this point, the receiving processor core will expect a new header block.

[0090] If the maximum value has not been reached, the receiving processor core checks whether the data element counter is a multiple of 2. If this is not the case (No), the receiving processor core continues with the execution of process block S28. If the receiving processor core determines that the data element counter is indeed a multiple of 2 (Yes), the receiving processor core further checks whether the data element counter is a multiple of 4. If this is not the case (No), the receiving processor core continues with the execution of process block S27. Otherwise (Yes), the receiving processor core continues with the execution of process block S26.

[0091] If it is determined in process block S30 that the maximum value is reached, then the operation proceeds to process block S31. At this point, the receiving core has received a list of event data to update the state value of the neuron with the neuron coordinate value [z][y'][x']. Each item j in the list includes the event value Vj of the source neuron and the corresponding pattern index j of the weight to be used. The event value is the element {source [j 1 ][y][x], source[j 2 ][y][x],……,source[j N ][y][x]}.

[0092] Pattern index j 1 , j 2 , ..., J N It can be a direct succession of values, but this is not necessary, especially if the activation is sparse. As discussed above, the mode index is transmitted in coded form. That is, the absolute value of the first mode index is transmitted in the field PID of the phit block B3, and the three differences between the subsequent mode index values ​​are transmitted in the fields Δ1, Δ2, Δ3. In process block S31, the absolute mode index value is calculated. That is,

[0093] j 1 =PID,j 2 =j 1 +Δ1,j 3 =j 2 +Δ2,j 4 =j 3 +Δ3

[0094] Similarly, according to the information of the subsequent phit block B3

[0095] j 5 =PID,j 6 =j 5 +Δ1,j 7 =j 6 +Δ2,j 8 =j 7 +Δ3

[0096] Fig.10 It shows how the receiving processor core uses the data obtained from the packed message to efficiently update the state value of a neuron having neuron coordinate values ​​[z][y'][x'].

[0097] exist Fig.10 In process block S41 of the process, the receiving processor core assigns the state value of the neuron having the neuron coordinate value [z][y'][x'] to the temporary variable.

[0098] Tmp = destination [z] [y'] [x']

[0099] In process block S43 it is verified whether the counter m has reached a maximum value. The maximum value is indicated in the header block HDR.

[0100] If this is not the case, the receiving processor core proceeds to process block S43 to update the value stored in the temporary value to:

[0101] Tmp+=source[m]*W[z][j m ][y'-y][x'-x], where

[0102] W[z][j m ][l][k] is the weight value.

[0103] From the array with index [z][j m ][y'-y][x'-x], where z is the z coordinate value of the destination neuron and j m It is the schema index rebuilt from the packaged message.

[0104] The receiving processor core then increments the counter m in process block S44 and continues with verification in block S42.

[0105] If it is determined in block S42 that the counter m has reached the maximum value, the process ends with process block S45, in which the receiving processor core writes the value of the temporary variable tmp to the neuron with the neuron coordinate value [z][y'][x']. Otherwise, the process continues with block S43.

[0106] Due to the fact that the event message generation module 130 of the sending processor core 100 has packaged the message to transmit multiple activation event data with the same destination neuron, the receiving processor core only needs to access the memory location of the neuron - only once for a read operation, and only once for a write operation, to perform all updates.

[0107] In the appended claims, the word "comprising" does not exclude other elements or steps, and the indefinite article "a" or "an" does not exclude a plurality. A single component or other unit may fulfill the functions of several items recited in the claims. The mere fact that certain measures are recited in mutually different claims does not indicate that a combination of these measures cannot be used to advantage. Any reference signs in the claims should not be construed as limiting the scope.

Claims

1. A processor system (1), comprising a plurality of processor cores (100, 200) and a message exchange network (20), wherein: The processor cores are configured to exchange messages between each other using the message exchange network, The processor system is configured to execute a neural network having at least a first layer (L k ) and the second neural network layer (L k+1 ) of a neural network, the first neural network layer (L k ) has the corresponding first feature map (F k ), the second neural network layer (L k+1 ) has a corresponding second feature map (F k+1 ), a feature map corresponding to a neural network layer comprises a plurality of feature map data elements, each of the plurality of feature map data elements indicating a neural state of a corresponding neuron of the neural network layer, and wherein the feature map data is addressable by a group consisting of at least two coordinates, the group consisting of at least two coordinates comprising at least a position coordinate (X, Y) indicating a position in the feature map and a channel coordinate (Z) indicating an element of a feature channel at the indicated position, Wherein, the processor core in which the first neural network layer (L k ) is configured to evaluate the first feature map (F k ) in the processor core, and, based on the evaluation, generating a second neural network layer (L k+1 ), the activation event data being addressed to a specific neuron of the second neural network layer, the second of the processor cores being configured to update the neural state of the specific neuron upon receiving the activation event data, It is characterized in that the first processor core among the processor cores is configured to transmit a plurality of activation event data emitted by a plurality of neurons in the first neural network layer having a common value for at least one of their coordinates in a packed message, wherein the packed message includes an indication of the at least one common coordinate value.

2. The processor system according to claim 1, wherein: The indication in the packaged message includes a corresponding value for each position coordinate (X, Y) of a neuron in the first neural network layer for which activation event data is transmitted, and an indication of the channel coordinate (Z) and the corresponding activation event value of the neuron for each of the multiple activation event data.

3. The processor system according to claim 2, wherein: The indication of the channel coordinate (Z) for each of the multiple activation event data in the packaged message includes an absolute value of the channel coordinate of a first neuron in the first neural network layer for which the activation event data is transmitted and one or more relative values, each of which indicates the difference between the absolute value of the channel coordinate of the neuron in the first neural network layer for which the activation event data is transmitted and the absolute value of the channel coordinate of a previous neuron in the first neural network layer for which the activation event data is transmitted.

4. The processor system according to claim 1 or 2, wherein: The plurality of activation event data in the packaged message is directed to a single neuron in the second neural network layer.

5. The processor system according to one of the preceding claims, wherein: The first of the processor cores is configured to temporarily cache activation event data generated when evaluating neuron states of the first feature map.

6. The processor system according to claim 5, wherein: The first of the processor cores is configured to transmit the packetized message for a predetermined number of buffered activation event data.

7. The processor system according to claim 5 or 6, wherein: The first of the processor cores is configured to transmit the packaged message for cached activation event data associated with a single position in the first feature map as it continues to evaluate a next position in the first feature map, the single position in the first feature map being specified by one or more position coordinates (X, Y) in the feature map.

8. The processor system according to claim 5 or 6, wherein: The first of the processor cores is configured to transmit the packaged message for cached activation event data associated with a narrow range corresponding to a location in the first feature map as it continues to evaluate a next location in the first feature map, the location in the first feature map being specified by the location coordinates (X, Y) in the feature map, wherein the cached activation event data have a common destination range in corresponding neurons in the second feature map.

9. The processor system according to one of the preceding claims, wherein: The second processor core, upon receiving the packaged message, performs all updates of the neuron state of a neuron in the second neural network layer that is a destination of the activation event data based on each of the activation event data in the packaged message before continuing to update the neuron state of other neurons in the second neural network layer.

10. A method for operating a processor system (1) comprising a plurality of processor cores (100, 200) and a message switching network (20), the method comprising: The processor system is configured to execute a neural network having at least a first layer (L k ) and the second neural network layer (L k+1 ) neural network, The first neural network layer (L k ) has the corresponding first feature map (F k ), The second neural network layer (L k+1 ) has a corresponding second feature map (F k+1 ), a feature map corresponding to a neural network layer comprising a plurality of feature map data elements, each of the plurality of feature map data elements indicating a neural state of a corresponding neuron of the neural network layer, and wherein the feature map data is addressable by a group consisting of at least two coordinates, the group consisting of at least two coordinates comprising at least a position coordinate (X, Y) indicating a position in the feature map and a channel coordinate (Z) indicating an element of a feature channel at the indicated position, The first processor core in the processor core executes the first neural network layer (L k ), and a second processor core in the processor core executes the second neural network layer (L k+1 ), Wherein, a first processor core among the processor cores evaluates the first feature map (F k ) and, based on said evaluation, generating activation event data, transmitting the activation event data to a second processor core among the processor cores, the activation event data being addressed to a specific neuron of the second neural network layer, wherein a second processor core among the processor cores updates a neural state of the specific neuron based on the received activation event data, It is characterized in that the first processor core among the processor cores transmits a plurality of activation event data emitted by a plurality of neurons in the first neural network layer having a common value for at least one of their coordinates in a packed message, and the packed message includes an indication of the common value.

Images