Protective causeway for power modules with spacers

Abstract

The protective bank (114) can release stresses in a chip assembly (104) of a high power semiconductor device module (100) used in electric vehicle or industrial applications. Some chip assemblies (104) incorporating copper spacers (110b) for heat dissipation may cause the device module (100) to become easily cracked. Addition of the protective dike (114) may absorb stress to prevent damage to material around the chip assembly (104). Various types of protective causeways (114) are presented, including a high profile flexible protective causeway (114a), a low profile flexible protective causeway (114b), a metal protective causeway (114c), and an integrated protective causeway (114d). The protective bank (114) may be incorporated into the high power semiconductor device module (100) having one-side or two-side cooling via a direct bond metal structure.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This patent application claims the benefit of U.S. non-provisional patent application No. 18 / 172,904, filed on February 22, 2023, and entitled “Protection Dam for a Power Module with Spacers,” which is incorporated herein by reference in its entirety. Technical Field

[0003] The present description relates to assembling and packaging semiconductor device modules, such as semiconductor device assemblies, semiconductor device module assemblies, etc. More particularly, the present description relates to semiconductor device modules having improved thermal performance and reduced mechanical stress. Background Art

[0004] Semiconductor device modules (such as modules including power semiconductor devices) can be implemented using multiple semiconductor dies, multiple substrates (e.g., direct bond metal (DBM) substrates, die attach pads (DAPs)), electrical interconnects, and molding compounds. Power transistors can include, for example, insulated gate bipolar transistors (IGBTs) or power metal oxide semiconductor field effect transistors (MOSFETs). Electrical interconnects within a high power semiconductor device module can include, for example, bonding wires, conductive spacers, and conductive clips. Polymer molding compounds can be used as encapsulants to protect components of device assemblies. Such power transistor devices can be used in a variety of applications, including automotive and / or industrial applications. Summary of the invention

[0005] In some aspects, the technology described herein relates to a device comprising: a substrate; a chip assembly coupled to the substrate, wherein the chip assembly comprises: a semiconductor die, a heat sink, and a molding material coupled to the heat sink; and a protective dam surrounding at least a portion of a periphery of the chip assembly.

[0006] In some aspects, an apparatus includes a protective dam configured to absorb mechanical stress resulting from expansion of a heat sink.

[0007] In some aspects, an apparatus includes a protective dike made of a flexible material.

[0008] In some aspects, an apparatus includes a protective dam having a barrier configured to block solder flow.

[0009] In some aspects, an apparatus includes a protective dam forming a seal against a substrate.

[0010] In some aspects, an apparatus includes a protective dam made of copper.

[0011] In some aspects, a device includes a direct bonded metal (DBM) substrate having a first metal layer, a second metal layer, and an insulating layer disposed between the first metal layer and the second metal layer, and the protection dam is a recessed copper layer integrated in the first metal layer.

[0012] In some aspects, an apparatus includes a first chip assembly and a second chip assembly coupled to a substrate, with a protective dam surrounding the two chip assemblies.

[0013] In some aspects, an apparatus includes a first chip assembly and a second chip assembly coupled to a substrate, the second chip assembly disposed outside a protective dike.

[0014] In some aspects, an apparatus includes a semiconductor die coupled to a copper heat spreader through a layer of sintered silver (Ag).

[0015] In some aspects, an apparatus includes a chip assembly that is a component of a high-power module configured for use in an automotive system.

[0016] In some aspects, an apparatus includes a substrate; a die assembly coupled to the substrate, the die assembly including a copper feature in contact with a polymer layer; and a protective dam disposed around the die assembly.

[0017] In some aspects, an apparatus includes a protective dam attached to a substrate.

[0018] In some aspects, an apparatus includes a protective dam integrated into a substrate.

[0019] In some aspects, an apparatus includes a protection dam comprising a recessed region of a substrate.

[0020] In some aspects, an apparatus includes a protective dam having an extension configured as a solder barrier.

[0021] In some aspects, the technology described herein relates to a method comprising: forming a chip assembly having a semiconductor die and a copper spacer; forming a protective dam around the chip assembly; coupling a substrate to a lead frame; coupling the chip assembly to the substrate; forming a direct bond metal (DBM) layer over the chip assembly; forming wire bonds to leads of the lead frame; and filling the remaining space around the chip assembly with a molding compound.

[0022] In some aspects, forming a protective dam around the chip assembly includes attaching the protective dam to the substrate.

[0023] In some aspects, the protective dam is flexible and attaching the protective dam to the substrate includes applying pressure to the protective dam.

[0024] In some aspects, attaching the protective dam to the substrate includes applying an adhesive.

[0025] In some aspects, the protective dam is metallic and attaching the protective dam to the substrate includes welding.

[0026] In some aspects, forming the protective dam includes forming a solder barrier integral with the protective dam.

[0027] In some aspects, the technology described herein relates to a method comprising: manufacturing a chip assembly including a semiconductor die and a copper spacer; etching a recessed area in a surface metal layer of a substrate to form a protective dam; coupling the chip assembly to the substrate, located within the protective dam; forming a direct bond metal (DBM) layer above the chip assembly; and filling the remaining space around the chip assembly with a molding compound.

[0028] In some aspects, a method further includes coupling additional chip assemblies to a substrate, wherein etching the recessed region forms a protective dam around at least one of the additional chip assemblies. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] Figure 1 is a high-level simplified block diagram, shown in cross-section, illustrating a high power semiconductor device module according to an embodiment of the present disclosure.

[0030] Figure 2 According to the embodiments of the present disclosure Figure 1 Detailed cross-sectional view of a high-power semiconductor device module shown in FIG.

[0031] Figure 3 is a top plan view of a high power semiconductor device module attached to a lead frame according to an embodiment of the present disclosure.

[0032] Figure 4A , Figure 4B and Figure 4C A top plan view, an enlarged view, and a cross-sectional view are respectively shown of a high power semiconductor device module configured with a high profile flexible protection dam according to an embodiment of the present disclosure.

[0033] Figure 5A , Figure 5B and Figure 5C A top side plan view, an enlarged view, and a cross-sectional view are respectively shown of a high power semiconductor device module configured with a low profile flexible protection dam according to an embodiment of the present disclosure.

[0034] Fig. 6A, Figure 6B and Figure 6C A top plan view, an enlarged view, and a cross-sectional view are respectively shown of a high-power semiconductor device module configured with a metal protection dam according to an embodiment of the present disclosure.

[0035] Fig. 7A , Figure 7B and Figure 7C A top plan view, an enlarged view, and a cross-sectional view are respectively shown of a high-power semiconductor device module configured with an integrated protection dam according to an embodiment of the present disclosure.

[0036] Fig. 8A , Figure 8B and Figure 8C A top plan view, an enlarged view, and a cross-sectional view are respectively shown of a high-power semiconductor device module configured with an integrated protection dam according to an embodiment of the present disclosure.

[0037] Fig. 9 is a flow chart of a method for manufacturing a high-power semiconductor device module configured with a protection dam according to an embodiment of the present disclosure.

[0038] Fig.10 is a graph of computer simulation data illustrating the benefits of implementing various types of protective dikes in accordance with an embodiment of the present disclosure.

[0039] In the drawings that are not necessarily drawn to scale, similar reference symbols may indicate similar and / or similar parts (elements, structures, etc.) in different views. The drawings generally illustrate various embodiments discussed in the present disclosure by way of example and not limitation. Reference symbols shown in one drawing may not be repeated for the same and / or similar elements in the related views. Reference symbols repeated in multiple figures may not be specifically discussed with respect to each of the figures in these figures, but are provided for context between the related views. In addition, not all similar elements in the drawings are specifically referenced with reference symbols when multiple instances of the element are shown. DETAILED DESCRIPTION

[0040] The present disclosure relates to embodiments of high power semiconductor device assemblies and modules having improved thermal performance and reduced mechanical stress.

[0041] In the assembly process of a semiconductor device module, a semiconductor die assembly (e.g., a chip assembly) including a semiconductor die containing one or more electronic devices is first attached to a substrate. The contact pads or bonding pads of the semiconductor die can then be attached to the contact pads at the ends of the leads of the lead frame by wire bonding. In some embodiments, double-sided cooling can be applied to the semiconductor die, in which case wire bonding may not be required. After attaching the semiconductor die assembly, the lead frame is placed in a mold. The mold is provided with a container for accommodating a certain amount of insulating molding compound. The molding compound is then injected into the mold to encapsulate the die attachment pads and the semiconductor die.

[0042] In some applications, power transistor devices can be used to implement electronic circuits used in automotive systems such as electric vehicles (EVs) and / or hybrid electric vehicles (HEVs), such as inverters or power amplifiers. Such applications require reliable heat dissipation. Current implementations of semiconductor device assemblies including such power transistors (e.g., in combination with fast recovery diodes (FRDs)) have certain disadvantages in terms of thermal management. For example, some assemblies include heat sinks that change the thermal distribution of the assembly. In addition, or alternatively, some embodiments may allow cooling of the assembly only on a single side of the assembly (e.g., by attaching a heat sink). Such thermal imbalances may cause and / or exacerbate stresses between components within such assemblies, such as tensile stresses and strain energy on the included semiconductor die, which may damage components of the assembly. As the power requirements and associated operating temperatures of such devices increase, the incidence of such damage may also increase.

[0043] In some embodiments, the power transistor assembly may include a spacer that acts as a heat sink near the semiconductor die. In this case, the spacer dissipates the heat generated by the components on the die operating at high voltage. Such spacers can be made of various materials, including ceramics, metals, etc. Spacers are a way to improve the thermal performance of high-power semiconductor dies. When copper components are used as heat sinks to dissipate heat within a chip assembly or die assembly, the rapid expansion of copper can cause tensile stresses in adjacent materials. Depending on the relative size and material properties near the heat sink, the increased stress may cause damage, such as cracks, dislocations, or fractures in the surrounding structure. Such damage may cause premature failure of devices within the chip assembly, poor thermal performance, or poor reliability.

[0044] The present disclosure relates to embodiments of high power semiconductor device assemblies and modules with improved thermal performance and reduced mechanical stress that address the above-mentioned problems. At least one solution is to introduce a protective element to relieve tensile stress in the structure around the copper spacer. Various types of protective elements are proposed herein in the form of flexible protective dams, metal protective dams, and integrated protective dams that are designed to surround one or more chip components that experience high heat dissipation within a power module. In some embodiments, the protective dam can be in contact with the lower surface of the chip component, and the protective dam can have walls that extend partially along the sides of the chip component. In some embodiments, the protective dam can be slightly spaced apart from the chip component.

[0045] Figure 1 is a simplified example of a high power semiconductor device module 100 according to some embodiments of the present disclosure. Figure 2 A more detailed description of the high-power semiconductor device module 100 is provided in . In some embodiments, the high-power semiconductor device module 100 includes a substrate 102 as a basic element, one or more chip components 104 (one chip component is shown), and an upper direct bonded metal (DBM) structure 106. In some embodiments, the substrate 102 may also include a lower DBM structure. In some embodiments, the DBM structure is a direct bonded copper (DBC) type structure or a direct bonded aluminum (DBA) or a direct plated copper (DPC) type structure. The DBM structure 106 can be designed as a three-layer structure, which includes a large thermal mass body, such as a dielectric, disposed between two outer metal layers to absorb and absorb heat. In some embodiments, the thermal mass body can provide electrical insulation. The use of the upper DBM structure and the lower DBM structure provides double-sided cooling for the chip component 104.

[0046] The chip assembly 104 includes at least one semiconductor die 108 and a spacer 110 in contact with the semiconductor die 108 to dissipate (e.g., quickly dissipate) heat generated therein. The chip assembly 104 is coupled to (e.g., mounted on) the substrate 102. In some embodiments, the upper DBM structure 106 is a multi-layer structure formed on the spacer 110. In some embodiments, the upper DBM structure 106 is larger than the spacer 110, which is larger than the semiconductor die 108, thereby creating an inverted pyramid shape (e.g., Figure 1 After the chip assembly 104 and the DBM structure 106 are constructed on the substrate 102 , the remaining space around the chip assembly 104 can be filled with the molding compound 112 .

[0047] The spacer 110 used as a heat sink is made of a material with high thermal conductivity (e.g., copper or its alloy). One such copper alloy that can be used as the spacer 110 is a copper-molybdenum (CuMo) alloy. Whether to use pure copper or, for example, CuMo can be selected based on the heat dissipation requirements of the type of chip assembly 104 coupled to the spacer 110. For example, the FRD chip assembly designated as 104b below can operate at a higher voltage or current than the IGBT chip assembly designated as 104a below, and therefore can generate more heat and may require more effective heat dissipation provided by the spacer 110 made of pure copper. Cost may also be a factor. Pure copper can be cheaper than copper alloys such as CuMo while providing faster heat dissipation. However, when the spacer 110 is made of pure copper, it may be easier to cause stress damage to the surrounding materials. In particular, the mold compound 112 (e.g., polymer) that is in direct contact with the spacer 110 (e.g., a pure copper spacer) is easily damaged by the rapid expansion of the spacer 110, especially at the corner C where the spacer 110 is exposed.

[0048] One way to relieve stress on the mold compound 112 is to replace a portion of the mold compound 112 with a material that can absorb stress (e.g., a flexible material that can conform to the chip assembly 104b, such as a polymer or elastomer). Alternatively, a material that can provide further heat dissipation, such as additional copper, can be used. In some embodiments, the replacement material can form a protective dam 114 around (e.g., in contact with) the chip assembly 104 (and / or a portion thereof). In some embodiments, the replacement material can form a protective dam 114 around the lower corner C of the spacer 110, which would otherwise be surrounded by the mold compound 112. The formation of the protective dam 114 can occur after the chip assembly 104 is attached to the substrate 102 and before the upper DBM structure 106 is manufactured on top of the chip assembly 104. In some embodiments, the protective dam 114 can be L-shaped so as to wrap around the lower corner C. The protective dam 114 can extend below the lower corner C to abut the semiconductor die 108. As described below, the height of the protective dike 114 relative to the spacer 110 may vary.

[0049] After the upper DBM structure 106 is formed on the chip assembly 104, with the protective dam 114 in place, the mold compound 112 can be injected to be disposed in (e.g., occupy) the remaining space around the chip assembly 104. In some embodiments, the mold compound 112 fills all the remaining space around the chip assembly. In some embodiments, there may be space (e.g., air pockets) around the chip assembly that is not completely filled with the mold compound 112. Because the protective dam 114 already occupies the space around the chip assembly 104, there will be less remaining space to be filled with the mold compound 112. With the addition of the protective dam 114, the injected mold compound 112 will occupy the open space around the upper portion of the chip assembly 104, which does not include the exposed corner C. Therefore, cracks are less likely to form in this area than in the area around the lower portion of the chip assembly 104 surrounded by the protective dam 114.

[0050] like Figure 1 As shown, the protective dam 114 may have a first portion close to and in contact with the semiconductor die 108, and a second portion away from the semiconductor die 108 and in contact with the sidewall of the spacer 110. The first portion may have a first thickness t1 that is less than a second thickness t2 of the second portion. The first thickness t1 of the first portion may be disposed between the bottom surface of the spacer 110 and the top surface of the substrate 102. The second thickness t2 of the second portion may be disposed between the bottom surface of the mold compound 112 and the top surface of the substrate 102.

[0051] Figure 2 Detailed cross-sectional view of a high power semiconductor device module 100 according to some embodiments of the present disclosure is shown. Figure 1 In addition to the basic components shown, Figure 2 Also includes the middle layer. Figure 2 1, the protective dike 114 is shown in dashed lines. In the example shown, the substrate 102 includes a lower DBM structure. In some embodiments, the lower DBM structure can be substantially the same or similar to the upper DBM structure 106. For example, the two DBM structures can be three-layer structures, where the inner layers 102b and 106b that provide the thermal mass of the DBM structure are made of an electrically insulating but thermally conductive ceramic material (e.g., aluminum oxide (Al2O3)). 2 O 3) or another ceramic), and the top and bottom outer metal layers 102a, c and 106a, c are made of copper or another highly conductive metal. In some embodiments, the ceramic inner layers 102b and 106b can be attached to the outer metal layers 102a, 102c and 106a, 106c using an adhesive material (not shown) (e.g., a thermally conductive epoxy adhesive or an electrically conductive epoxy adhesive (such as, silver-filled epoxy)). In some embodiments, the ceramic inner layers 102b, 106b can each have a thickness in the range of about 0.3mm to about 0.35mm. In some embodiments, the outer metal layers 102a, 102c and 106a, 106c can have a thickness between about 0.2mm and about 0.8mm.

[0052] In some embodiments, the chip assembly 104 can be attached to the upper DBM structure 106 and to the substrate 102 by a solder layer 116. When the solder layer 116 is formed on the top surface of the substrate 102, the solder resist material 118 can be patterned to contain the solder to the desired area of ​​the substrate 102. In some embodiments, the solder resist material 118 can have a thickness in the range of about 0.01 mm to about 0.03 mm. Each chip assembly 104 (including the semiconductor die 108 and the spacer 110) can be held together by a bonding layer 120. In some embodiments, the bonding layer 120 can be made of a layer of sintered silver (Ag) inserted between the semiconductor die 108 and the spacer 110.

[0053] Figure 2 Also shown are cracks that tend to form in the mold compound 112 surrounding the above layers when the protective dam 114 is not included. In particular, without the protective dam 114, the mold compound 112 located near the lower corner C of the spacer 110 may be susceptible to cracking. Figure 2In the example shown, the distance d1 of the mold compound between the upper DBM structure 106 and the substrate 102 can be in the range of about 2.0 mm to about 3.0 mm, and the distance d2 between the lower corner C of the spacer 110 and the lower DBM structure of the substrate 102 can be in the range of about 0.1 mm to about 0.5 mm. Without the protective dam 114 in place, strain on the spacer 110 can accumulate due to radial forces R1 and R2 located at the upper and lower corners of the spacer 110, respectively. In some embodiments, the radial force R2 can be particularly problematic at the lower corner C, which can extend laterally beyond the semiconductor die 108. The stress in the mold compound 112 generated by this strain on the spacer 110 caused by the various surrounding material layers may result in the formation of a corner crack 122 extending downward from the lower corner C toward the substrate 102 , and a vertical crack 124 extending through the region of the mold compound 112 between the upper and lower DBM structures.

[0054] Figure 3 A top view of a packaged high power semiconductor device module 100 attached to a lead frame is shown according to some embodiments of the present disclosure. The lead frame includes leads 304 and mounting brackets 306. The leads 304 (six leads are shown on each side of the lead frame) provide signal paths to and from each semiconductor die 108 in the chip assembly 104. The lead frame can be cut or stamped from a thin sheet of metal (e.g., copper).

[0055] In the example shown, the high-power semiconductor device module 100 includes a total of four chip assemblies attached to a substrate 102 (e.g., attached to the top outer metal layer 102a of the lower DBM structure). The four chip assemblies shown are of two types: a transistor chip assembly 104a (two transistor chip assemblies are shown) and a diode chip assembly 104b (two diode chip assemblies are shown). In some embodiments, the larger transistor chip assembly 104a contains a die 108a, wherein a power transistor (e.g., an IGBT) is coupled to a CuMo copper alloy spacer 110a. In some embodiments, the smaller diode chip assembly 104b contains a die 108b, wherein a diode (e.g., an FRD) is coupled to a copper spacer 110b. In the example shown, the chip assembly 104 is attached to a common substrate 102.

[0056] exist Figure 3, the protective levee 114 is represented as a dashed rectangle. In some embodiments, the protective levee may have rounded corners. In some embodiments, the protective levee 114 may be square, circular, or irregularly shaped, depending on the shape of the chip assembly 104. In the example shown, the protective levee 114 is applied to diode chip assemblies 104b equipped with copper spacers 110b, which are more prone to cracking than transistor chip assemblies 104a equipped with copper alloy spacers 110a. In some embodiments, the protective levee 114 may surround more than one chip.

[0057] FIG. 4A to FIG. 4C , FIG. 5A to FIG. 5C , FIG. 6A to FIG. 6C , 7A to 7C and FIG. 8A to FIG. 8C Each of the figures shows a top view, an enlarged view, and a cross-sectional view of a packaged high-power semiconductor device module 100 with a protective dike 114 added according to various embodiments of the present disclosure. Each set of figures shows a different example of a protective dike 114 applied to a high-power diode chip assembly 104b that includes a copper spacer 110b as a heat sink. Note that for clarity, the Figure 4A , Figure 5A , Fig. 6A , Fig. 7A and Fig. 8A The upper DBM structure 106 is omitted from the top perspective view shown.

[0058] FIG. 4A to FIG. 4C and FIG. 5A to FIG. 5C The packaged high-power semiconductor device module 100 implemented with two types of flexible protection dams 114a and 114b are shown respectively; FIG. 6A to FIG. 6C shows a packaged high power semiconductor device module 100 implemented with a metal protection dam 114c; 7A to 7C and FIG. 8A to FIG. 8C The packaged high power semiconductor device module 100 implemented with two types of integrated protection dams 114d and 114e are shown respectively.

[0059] Note that although each group FIG. 4A to FIG. 4C , FIG. 5A to FIG. 5C , FIG. 6A to FIG. 6C , 7A to 7C and FIG. 8A to FIG. 8CThe protective dam 114 is shown to be applied to a high-power semiconductor device module 100 implemented with double-sided cooling provided by an upper three-layer DBM structure and a lower three-layer DBM structure, but the same protective dam 114 can be applied to a similar high-power semiconductor device module 100 that is implemented with single-sided cooling provided by an upper DBM structure or a lower DBM structure. Alternatively, the same protective dam 114 can be applied to a high-power semiconductor device module 100 that is implemented without any DBM structure.

[0060] Figure 4A , Figure 4B and Figure 4C A high power semiconductor device module 100 configured with a high profile flexible protection dam 114 a according to some embodiments of the present disclosure is shown. Figure 4A A top plan view of a high power semiconductor device module 100 during its manufacture is shown. A high profile flexible protective dam 114a has been added to an FRD chip assembly 104b having a copper spacer 110b. A high profile flexible protective dam 114a is not added to an IGBT transistor chip assembly 104a having a copper alloy spacer 110a (e.g., a CuMo spacer). This is because the cracking problem described above preferentially affects the mold compound 112 around the corners of the copper spacer 110b due to the higher thermal conductivity of copper.

[0061] In the example shown, the high profile flexible protective dam 114a is in the form of a rectangular housing with walls. In some embodiments, the high profile flexible protective dam 114a is made of an elastic polymer material similar to a gasket. In some embodiments, the high profile flexible protective dam 114a is made of an epoxy resin material. The high profile flexible protective dam 114a can wrap around (e.g., conform to) the periphery of each chip assembly in the chip assembly 104b and / or fit tightly, so that the high profile flexible protective dam 114a is in physical contact with the lower corner C of the copper spacer 110b.

[0062] Figure 4B An enlarged view of an example of a high-profile flexible protective dam 114a according to some embodiments of the present disclosure is shown. In the example shown, the dimensions of the high-profile flexible protective dam 114a are as follows: the inner length dimension L and the width dimension W of the high-profile flexible protective dam 114a can be approximately 0.5 mm larger than the dimensions of the spacer 110b; the wall thickness t of the high-profile flexible protective dam 114a can be about 0.4 mm to about 1.0 mm; the height h of the high-profile flexible protective dam 114a can be in the range of about 1.0 mm to about 2.0 mm, so that the high-profile flexible protective dam 114a at least covers the lower portion of the side of the copper spacer 110b, as shown in FIG. Figure 4C as shown in .

[0063] Figure 4C A cross-sectional view of the high-power semiconductor device module 100 along the cut line 4C-4C is shown to further illustrate the multi-layer DBM structure and external connections to the chip assembly 104 in detail. In some embodiments, both the lower DBM structure and the upper DBM structure 106 of the substrate 102 are included as additional heat sinks to dissipate heat from both the chip assemblies 104a and 104b, thereby providing double-sided cooling of the high-power semiconductor device module 100. Alternatively, one of the DBM structures (e.g., DBM structure 106) can be used to provide single-sided cooling of the high-power semiconductor device module 100. Figure 4C In the example shown, both the upper DBM structure and the lower DBM structure are shared by a pair of chip assemblies 104a and 104b. In some embodiments, the common upper DBM structure and the lower DBM structure can be shared by all four chip assemblies included in the packaged high-power semiconductor device module 100. Alternatively, each chip assembly 104 can be attached to one or more separate dedicated DBM structures.

[0064] Still reference Figure 4C , leads 304 provide electrical connections to chip components 104a and 104b via the top outer metal layer 102a of the lower DBM in substrate 102. Some connections can be made directly to the top outer metal layer 102a. Other connections can be made via wire bonds 404 that couple leads 304 to the top outer metal layer 102a of the lower DBM structure in substrate 102. In some embodiments, the top outer metal layer 102a can be patterned, while the bottom outer metal layer 102c can be continuous.

[0065] Figure 4C Also shown is a vertical profile of the high profile flexible protective dam 114a relative to the sides and corners of the copper spacer 110b. In the example shown, the wall of the high profile flexible protective dam 114a surrounds the lower corner C and extends upward to about half of the side of the copper spacer 110b. In some embodiments, the wall of the high profile flexible protective dam 114a may surround a larger portion or all of the side of the copper spacer 110b. In some embodiments, the wall of the high profile flexible protective dam 114a may surround a smaller portion of the side of the copper spacer 110b or not surround the side of the copper spacer. When the wall of the high profile flexible protective dam 114a surrounds at least some portions of the side of the copper spacer 110b, the high profile flexible protective dam 114a forms an L-shaped profile around the lower corner C of the copper spacer 110b.

[0066] Figure 5A , Figure 5B and Figure 5CA high power semiconductor device module 100 configured with a low profile flexible protection dam 114 b is shown according to some embodiments of the present disclosure. Figure 5A , Figure 5B and Figure 5C Similar to Figure 4A , Figure 4B and Figure 4C , except that a low-profile flexible protective dam 114b replaces the high-profile flexible protective dam 114a on the FRD chip assembly 104b. In the example shown, the low-profile flexible protective dam 114b wraps around the lower perimeter of the chip assembly 104b, under the spacer 110b, and between the spacer 110b and the top outer metal layer 102a of the lower DBM structure in the substrate 102.

[0067] In some embodiments, the outer length dimension L and width dimension W of the low-profile flexible protective dam 114b can be approximately equal to the dimensions of the spacer 110b, so that the low-profile flexible protective dam 114b is flush with the sides of the spacer 110b and extends outward to the lower corner C of the spacer 110b but does not extend around the lower corner C. In some embodiments, the low-profile flexible protective dam 114b can have a thickness T1 in the range of about 0.2 mm to about 0.3 mm, leaving a small gap in the range of about 0.1 mm to about 0.2 mm between the bottom of the low-profile flexible protective dam 114b and the top outer metal layer 102a. In some embodiments, the low-profile flexible protective dam 114b can include an extension, such as an inner flange 500 integral with the flexible protective dam 114b. The inner flange 500 can extend inward and extend below the edge of the semiconductor die 108b attached to the underside of the spacer 110b. In some embodiments, the inner flange 500 may have a thickness T in a range of about 0.09 mm to about 0.1 mm.

[0068] In some embodiments, the low-profile flexible protective dam 114b can be made of an elastic material similar to the high-profile flexible protective dam 114a described above. Depending on its elasticity, the inner flange 500 can form a seal against the top surface of the substrate 102 (e.g., against the die attach pad area of ​​the substrate 102). In some embodiments, such a sealed inner flange 500 can act as a barrier to block the flow of liquids (e.g., the flow of molten solder used in the assembly process). The inner flange 500 can be used together with the solder resist material 118 as additional protection to control the flow of solder.

[0069] Fig. 6A , Figure 6B and Figure 6C A high power semiconductor device module 100 configured with a metal protection dam 114 c according to some embodiments of the present disclosure is shown. Fig. 6A , Figure 6B and Figure 6C Similar to the above Figure 4A , Figure 4B and Figure 4C , except that the metal protection dam 114c replaces the high profile flexible protection dam 114a on the FRD chip assembly 104b. In some embodiments, the metal protection dam 114c can be in the form of a rectangular frame around the lower perimeter of the chip assembly 104b. In some embodiments, the metal protection dam 114c can be slightly spaced from the spacer 110b to allow the metal to expand during heating and contract when the metal protection dam 114c relaxes. The metal protection dam 114c can be soldered to the top outer metal layer 102a of the lower DBC structure in the substrate 102 using a solder layer 600 applied to the underside of the metal protection dam 114c. In some embodiments, the metal protection dam 114c can be made of copper or another highly conductive metal, which can provide additional heat dissipation to draw heat away from the copper spacer 110b and conduct the heat through the solder layer 600 into the thermal mass of the lower DBM. The metal protection dam 114c may also be elastic to relieve mechanical stress around the lower corner C of the copper spacer 110b and prevent cracking in a similar manner as the flexible protection dam 114a provides stress relief.

[0070] Figure 6B An enlarged view of an example of a metal protection dam 114c according to some embodiments of the present disclosure is shown. In the example shown, the dimensions of the metal protection dam 114c can be as follows: the inner length dimension L and the width dimension W of the metal protection dam 114c can be approximately 0.5 mm larger than the dimensions of the spacer 110b; the wall thickness t of the metal protection dam 114c can be in the range of about 0.7 mm to about 0.8 mm; the thickness of the solder layer 600 can be in the range of about 0.2 mm to about 0.3 mm; and the height h of the metal protection dam 114c can be in the range of about 1.2 mm to about 1.3 mm, so that the metal protection dam 114c covers at least the lower portion of the side of the copper spacer 110b, as shown in FIG. Figure 6C In some embodiments, the metal protection dam 114c can surround a larger portion or all of the sides of the copper spacer 110b.

[0071] Figure 6C A cross-sectional view of a metal protection dam 114 c applied to a high power semiconductor device module 100 according to some embodiments of the present disclosure is shown. Figure 6C The profile of the metal protection dam 114c is shown to be vertical, not L-shaped, and therefore it does not extend below the lower surface of the copper spacer 110b.

[0072] Fig. 7A , Figure 7B and Figure 7C A high power semiconductor device module 100 configured with an integrated protection dam 114 d according to some embodiments of the present disclosure is shown. Fig. 7A , Figure 7B and Figure 7C Similar to the corresponding views shown above, the difference is that the integrated protective dam 114 replaces the previous type of protective dam 114 around each FRD chip component 104b. In some embodiments, the integrated protective dam 114d can be in the form of a rectangular frame around the lower periphery of the chip component 104b and can be slightly laterally spaced apart from the spacer 110b. The integrated protective dam 114d can be integrated with the top outer metal layer 102a of the lower DBC structure in the substrate 102. The integrated protective dam 114d can be adjacent to the die attach pad (DAP) on which the adjacent chip component 104a is placed. In some embodiments, the integrated protective dam 114d can be formed by etching the top outer metal layer 102a before attaching the chip component 104a, so that the integrated protective dam 114d extends vertically upward in the z direction above the plane of the top outer metal layer 102a. Because the integrated protection dam 114d is made of the same material (e.g., copper or another highly conductive metal) as the top outer metal layer 102a that forms the integrated protection dam, the integrated protection dam 114d provides additional heat dissipation to draw heat away from the copper spacer 110b and conduct the heat directly into the thermal mass of the lower DBM. The integrated protection dam 114d can also be elastic to relieve mechanical stress around the lower corner C of the copper spacer 110b and prevent cracking in a manner similar to the stress relief provided by the flexible protection dams 114a and 114b and / or the metal protection dam 114c.

[0073] Figure 7B An enlarged view of an example of an integrated protective dam 114d according to some embodiments of the present disclosure is shown. In the example shown, the dimensions of the integrated protective dam 114d can be as follows: the inner length dimension L and the width dimension W of the integrated protective dam 114d can be approximately 0.5 mm larger than the dimensions of the spacer 110b; the wall thickness t of the integrated protective dam 114d can be in the range of about 0.5 mm to about 1.0 mm; and the height h of the integrated protective dam 114d can be in the range of about 1.0 mm to about 2.0 mm, so that the integrated protective dam 114d covers at least the lower portion of the side of the copper spacer 110b, as shown in FIG. Figure 7C In some embodiments, the integrated protection dam 114d can surround a larger portion or all of the sides of the copper spacer 110b.

[0074] Figure 7C A cross-sectional view of an integrated protection dam 114 d applied to a high power semiconductor device module 100 according to some embodiments of the present disclosure is shown. Figure 7C The profile of the integral protective dam 114d is shown to be a vertical extension of the top outer metal layer 102a beneath the lower DBM structure. Figure 7C It is also shown that the chip assembly 104b is disposed within the integrated protective dam 114d, while the chip assembly 104a is disposed outside the integrated protective dam 114d. The profile of the integrated protective dam 114d is not L-shaped, so it does not extend below the lower surface of the copper spacer 110b.

[0075] Fig. 8A , Figure 8B and Figure 8C A high power semiconductor device module 100 configured with an integrated protection dam 114 e according to some embodiments of the present disclosure is shown. Fig. 8A , Figure 8B and Figure 8C Similar to the corresponding view shown above, except that an integrated protective dam 114e replaces the previous type of protective dam 114 around the FRD chip assembly 104b. In some embodiments, the integrated protective dam 114e can be in the form of a partial wall around a portion of the lower perimeter of the chip assembly 104b, and can be slightly laterally spaced apart from the copper spacer 110b. The integrated protective dam 114e can be integral with the top outer metal layer 102a of the lower DBC structure in the substrate, formed by etching a recess in the top outer metal layer 102a before attaching the chip assembly 104a, so that the integrated protective dam 114e extends vertically upward in the z-direction above the plane of the top outer metal layer 102a. Because the integrated protection dam 114e is made of the same material (e.g., copper or another highly conductive metal) as the top outer metal layer 102a that forms the integrated protection dam, the integrated protection dam 114e provides additional heat dissipation to draw heat away from the copper spacer 110b and conduct the heat directly into the thermal mass of the lower DBM. The integrated protection dam 114e can also be elastic to relieve mechanical stress around the lower corner C of the copper spacer 110b and prevent cracking in a manner similar to the stress relief provided by the flexible protection dams 114a and 114b and / or the metal protection dam 114c.

[0076] Figure 8BAn enlarged view of an example of an integrated protective dam 114e according to some embodiments of the present disclosure is shown. In the example shown, the dimensions of the integrated protective dam 114e can be as follows: the inner length dimension L and the width dimension W of the recess forming the integrated protective dam 114e can be approximately 0.5 mm larger than the dimensions of the spacer 110b; the recess depth d of the recess forming the integrated protective dam 114e can be in the range of about 0.5 mm to about 1.0 mm; and the total height h of the copper top outer metal layer 102a can be in the range of about 1.0 mm to about 1.5 mm, so that the integrated protective dam 114e at least covers the bottom corner C of the copper spacer 110b, as also shown in FIG. Figure 8C In some embodiments, a deeper recess may be etched in the copper top outer metal layer 102a so that the integrated protective dam 114e may surround a larger portion or all of the sides of the copper spacer 110b.

[0077] Figure 8C A cross-sectional view of an integrated protection dam 114 e applied to a high power semiconductor device module 100 according to some embodiments of the present disclosure is shown. Figure 8C The profile of the integral protection dam 114e is shown to be an asymmetric vertical extension of the top outer metal layer 102a below the lower DBM structure. That is, unlike the integral protection dam 114d, the integral protection dam 114e does not necessarily surround the copper spacer 110b on all sides. For example, Figure 8B As shown, the integrated protection levee 114e surrounds the copper spacer 110b on three sides. However, in some embodiments, the recess formed in the top outer metal layer 102a can be symmetrical so that the integrated protection levee 114e does surround the copper spacer 110b on all sides. In addition, unlike the above-mentioned embodiments, the recess formed in the upper layer 102a that defines the integrated protection levee 114e surrounds both chip components 104a and 104b, rather than just surrounding the diode chip component 104b. The profile of the integrated protection levee 114e is not L-shaped, so it does not extend below the lower surface of the copper spacer 110b.

[0078] Fig. 9is a flow chart illustrating a method 900 for manufacturing a high-power semiconductor device module 100 according to some embodiments of the present disclosure. The operations of method 900 may be performed in a different order, or not performed, depending on the specific application. It should be noted that method 900 may not produce a complete high-power semiconductor device module 100. Therefore, it should be understood that additional processes may be provided before, during, or after method 900, and some of these additional processes may be briefly described herein. According to the above embodiments, operations 902 to 910 may be performed to form a high-power semiconductor device module 100 and apply protective dikes 114a, 114b, 114c, 114d, or 114e.

[0079] At 902, method 900 includes forming chip assemblies 104 by coupling semiconductor dies to a heat sink of each chip assembly 104. For example, transistor chip assembly 104a may be fabricated by coupling copper alloy spacers 110a to each IGBT semiconductor die 108a; and diode chip assembly 104b may be fabricated by coupling copper spacers 110b to each FRD semiconductor die 108b.

[0080] At 904, method 900 includes forming a protective dam 114. When using flexible protective dams 114a or 114b, operation 904 may include separately manufacturing the flexible protective dam 114 and then stretching the flexible protective dam 114 around the diode chip assembly 104b. When using a metal protective dam 114c, operation 904 may include soldering the metal dam 114c to the substrate 102. When using an integral protective dam 114d, operation 904 may include etching the top surface of the substrate 102 (e.g., the thick top outer metal layer 102a) to remove a layer of metal, thereby leaving the wall structure of the integral protective dam 114d. When using an integral protective dam 114e, operation 904 may include etching a recess in the top surface of the substrate 102 (e.g., the top outer metal layer 102a) to produce a recessed copper layer, thereby leaving the structure of the integral protective dam 114d.

[0081] At 906 , method 900 includes coupling substrate 102 to a leadframe. In some embodiments, substrate 102 may be a three-layer DBM, and top outer metal layer 102a may be coupled to leads 304 and mounting bracket 306 .

[0082] At 908, method 900 includes coupling chip assemblies 104a and 104b to substrate 102. In some embodiments, chip assembly 104 can be coupled to substrate 102 via solder layer 116 using a solder reflow process, a sintering process, or other suitable process. In some embodiments, attaching chip assembly 104 to substrate 102 can be achieved by, for example, mounting or bonding chip assembly 104 to substrate 102 using a bonding adhesive (e.g., a conductive bonding adhesive) instead of solder layer 116. In some embodiments, attaching chip assembly 104b with flexible protective dam 114b to substrate 102 includes applying pressure to form a seal between flange 500 and substrate 102.

[0083] At 910, method 900 includes forming upper DBM 106 on chip assembly 104. In some embodiments, upper DBM 106 is formed separately and attached to chip assembly 104 with solder layer 116 using a solder reflow process, a sintering process, or other suitable process. In some embodiments, attaching upper DBM 106 to chip assembly 104 can be achieved by, for example, mounting or bonding upper DBM 106 to chip assembly 104 using a bonding adhesive (e.g., a conductive bonding adhesive) instead of solder layer 116. Operation 910 can be omitted when single-sided cooling is used.

[0084] At 912, method 900 includes forming wire bonds 404 to connect substrate 102 to leads 304. The lower end of wire bonds 404 can be soldered to a bonding pad formed in substrate 102 (e.g., in top outer metal layer 102a). The upper end of wire bonds 404 can be soldered to a selected one of leads 304 according to a specified circuit design. While wire bonds 404 are being connected, bracket 306 can be attached to substrate 102 at structural connection point 800.

[0085] At 914, method 900 includes encapsulating the high power semiconductor device module 100 with a mold compound 112 using, for example, an injection molding process. Encapsulation introduces the mold compound 112 into the remaining space between and around the chip components 104 that is not occupied by electronic components, connectors, or protective dams 114. In some embodiments, the upper DBM and the lower DBM define the top and bottom surfaces of the package, so that the mold compound 112 does not surround the upper DBM and the lower DBM. External connections can then be made to the top outer metal layers 106a and 102a.

[0086] Fig.10 Computer simulation results 1000 of tensile stress reduction in the mold compound 112 according to some embodiments of the present invention are shown. When the protection dam 114 is applied to the high power semiconductor device module 100, a tensile stress reduction is observed.

[0087] Computer simulations were run on a model of a high power semiconductor device module 100 to compare the calculated stresses at different representative locations of the mold compound 112 for different embodiments of the protection dam 114. The results were compared to a high power semiconductor device module 100 implemented without the protection dam 114. A first data set 1002 was calculated as a general representation of the stress in the mold compound 112; a second data set 1004 was calculated at a representative location near the FRD diode chip assembly 104b; a third data set 1006 was calculated at a representative location near the edge of the spacer 110b of the FRD diode chip assembly 104b; and the different embodiments of the protection dam 114 simulated included flexible protection dams 114a, 114b in the form of soft epoxy, closed copper protection dams 114c, 114d, and a copper protection dam 114e formed by etching a recess in the top outer metal layer 102a.

[0088] Still reference Fig.10 , computer simulations of tensile stress or "EMC tensile stress" within the mold compound 112 indicate that performance is improved by using each simulated protection dam 114. The best overall protection indicated by the first data set 1002 is shown to be associated with the flexible protection dam 114a / 114b. In particular, when the flexible protection dams 114a and 114b are made of a soft epoxy material, the EMC tensile stress can be reduced by about 33.5% for the flexible protection dams having the above dimensions. The computer simulations further indicate that the use of closed copper protection dams 114c / 114d can reduce the EMC tensile stress by about 22.4%, regardless of whether the copper protection dam is soldered in place or formed by etching a wall in the copper top outer metal layer 102a. The computer simulations further indicate that the use of an integral protection dam 114e formed by etching a recess having a recess depth in the range of about 0.5mm to about 1.0mm in the copper top outer metal layer 102a, the EMC tensile stress can be reduced by about 4.2%. The results for the second data set 1004 are similar to the results for the first data set 1002 .

[0089] Referring to the third data set 1006, near the edge of the FRD spacer, as predicted by the model, the best protection can be achieved by using copper dikes 114c / 114d, which show a reduction in EMC stress of about 22.7%, compared to an increase in stress of about 10.7% using flexible protection dikes 114a / 114b, and a reduction in stress of about 2.8% using recess-etched integral protection dikes 114e. In these cases, the EMC stress does not exceed the EMC strength near the edge of the FRD spacer.

[0090] It should be understood that in the foregoing description, when an element such as a layer, a region or a substrate is mentioned as being on another element, connected to another element, electrically connected to another element, coupled to another element, or electrically coupled to another element, the element may be directly on another element, connected or coupled to another element, or one or more intermediate elements may be present. On the contrary, when an element is mentioned as being directly on another element or layer, directly connected to another element or layer, or directly coupled to another element or layer, there is no intermediate element or layer. Although the term directly on, directly connected to, or directly coupled to may not be used throughout the specific embodiments, an element that is shown as being directly on an element, directly connected, or directly coupled can be mentioned in this manner. The claims of the present application may be revised to narrate the exemplary relationships described in the specification or shown in the drawings.

[0091] As used in this specification, unless the context clearly indicates a particular case, the singular form may include the plural form. In addition to the orientation shown in the drawings, spatial relative terms (e.g., above, above, above, below, below, below, below, at the top, at the bottom, etc.) are intended to cover different orientations of the device in use or operation. In some embodiments, the relative terms above and below may include vertically above and vertically below, respectively. In some embodiments, the term adjacent may include lateral adjacent or horizontal adjacent.

[0092] Although certain features of the described embodiments have been illustrated as described herein, those skilled in the art will now recognize many modifications, alternatives, variations, and equivalents. For example, features shown with respect to one embodiment may also be included in other embodiments where appropriate. Therefore, it should be understood that the appended claims are intended to cover all such modifications and variations that fall within the scope of the embodiments. It should be understood that these modifications and variations are presented only by way of example and not limitation, and that various changes in form and detail may be made. In addition to mutually exclusive combinations, any part of the apparatus and / or method described herein may be combined in any combination. The embodiments described herein may include various combinations and / or sub-combinations of the functions, components, and / or features of the different embodiments described.

Claims

1. A device, comprising: A substrate (102); A chip assembly (104), the chip assembly being coupled to the substrate (102), the chip assembly (104) comprising: a semiconductor die (108), Radiator, and a molding material (112) coupled to the heat sink; and A protective dam (114) surrounds at least a portion of a perimeter of the chip assembly (104).

2. The device according to claim 1, wherein the protective dike (114) is configured to absorb mechanical stress from expansion of the heat sink.

3. The device according to claim 1, wherein the protective dike (114) comprises a flexible material. The apparatus of claim 3 , wherein the protective dam comprises a barrier configured to block solder flow.

5. The device of claim 3, wherein the protective dam (114) forms a seal against the substrate (102).

6. The apparatus of claim 1, wherein the protective dam (114) comprises copper.

7. The device according to claim 6, wherein the substrate (102) is a direct bonded metal (DBM) substrate, comprising a first metal layer (102a), a second metal layer (102c), and an insulating layer (102b) arranged between the first metal layer (102a) and the second metal layer (102c), and the protective dam (114) is a recessed copper layer integrated in the first metal layer (102a).

8. The device according to claim 6, wherein the chip component (104) is a first chip component (104a), and the device also includes a second chip component (104b) coupled to the substrate (102), wherein the protective embankment (114) surrounds the two chip components (104a, 104b).

9. The device according to claim 1, wherein the chip component (104) is a first chip component (104a), and the device further comprises a second chip component (104b) coupled to the substrate (102), and the second chip component (104b) is arranged outside the protective embankment (114).

10. The apparatus of claim 1, wherein the semiconductor die (108) is coupled to the heat sink through a sintered silver (Ag) layer (120).

11. The apparatus of claim 1, wherein the chip assembly (104) is a component of a high power module (100) configured for use in an automotive system.

12. A device, comprising: A substrate (102); a die assembly (104) coupled to the substrate (102), the die assembly (104) comprising a copper feature in contact with the polymer layer (112); and A protective dike (114) is disposed around the die assembly (104).

13. The device of claim 12, wherein the protective dam (114) is attached to the substrate (102).

14. The device of claim 12, wherein the protective dam (114) is integrated into the substrate (102).

15. The apparatus of claim 12, wherein the protective dam (114) comprises a recessed region of the substrate (102).

16. The apparatus of claim 12, wherein the protective dam (114) includes an extension configured as a solder barrier (116).

17. A method comprising: forming a chip assembly (104) including a semiconductor die (108) and a copper spacer (110b); forming a protective embankment (114) around the chip assembly (104); coupling a substrate (102) to a lead frame; coupling the chip assembly (104) to the substrate (102); forming a direct bonding metal (DBM) layer above the chip component (104); forming wire bonds (404) to the leads (304) of the lead frame; and The remaining space around the chip assembly (104) is filled with a molding compound (112).

18. The method of claim 17, wherein forming the protective dam (114) around the chip assembly (104) comprises attaching the protective dam (114) to the substrate (102).

19. The method of claim 18, wherein the protective dam (114) is flexible and attaching the protective dam (114) to the substrate (102) comprises applying pressure to the protective dam (114).

20. The method of claim 17, wherein attaching the protective dam (114) to the substrate (102) comprises applying an adhesive.

21. The method of claim 17, wherein the protective dam (114) is metallic and attaching the protective dam (114) to the substrate (102) comprises welding.

22. The method of claim 21, wherein forming the protective dam (114) comprises forming a solder barrier (116) integral with the protective dam (114).

23. A method comprising: manufacturing a chip assembly (104) including a semiconductor die (108) and a copper spacer (110b); Etching a recessed area in a surface metal layer of the substrate (102) to form a protective dam (114); coupling the chip assembly (104) to the substrate (102) within the protective dike (114); forming a direct bonding metal (DBM) layer (106a) above the chip component (104); and The remaining space around the chip assembly (104) is filled with a molding compound (112).

24. The method according to claim 23, further comprising: Additional chip assemblies (104) are coupled to the substrate (102), and wherein etching the recessed region forms a protective dam (114) around at least one of the additional chip assemblies (104).

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