Charging circuit for bootstrap capacitor

Abstract

A power converter circuit including a self-timing bootstrap capacitor power supply and a method. Added to a power converter having a diode stack for charging a bootstrap capacitor is three types of supplemental circuit blocks: a trigger block, a trigger bypass block, and a bypass block. In operation, adjacent supplemental circuit blocks operate in pairs. An upper block in a pair, when triggered, is used to charge its associated bootstrap capacitor by connecting a top plate of the associated bootstrap capacitor to a top plate of a bootstrap capacitor associated with a lower block of the pair, substantially bypassing a diode associated with the upper block. In addition, the lower blocks in pairs are used to activate (trigger) the bypass function of the upper block. When the connected bootstrap capacitors are disconnected and their respective voltages are "fly" on, the bypass function of the upper block is automatically terminated, or controllably terminated.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to U.S. non-provisional patent application No. 17 / 752,492, "CHARGING CIRCUIT FOR BOOTSTRAP CAPACITORS," filed on May 24, 2022, the contents of which are incorporated herein by reference in their entirety. Technical Field

[0003] The present invention relates to electronic circuits and, more particularly, to power converter circuits, including DC to DC power converter circuits. Background Art

[0004] Many electronic products, especially mobile computing and / or communication products and components (e.g., cell phones, laptops, ultrabooks, tablet devices, LCD and LED displays) require multiple voltage levels. For example, a radio frequency (RF) transmitter power amplifier may require a relatively high voltage (e.g., 12V or higher), while logic circuitry may require a low voltage level (e.g., 1V to 3V). Still other circuitry may require an intermediate voltage level (e.g., 5V to 10V).

[0005] DC power converters are commonly used to generate lower or higher voltages from common power sources such as batteries, solar cells, fuel cells, and rectified AC sources. Power converters that generate lower output voltage levels from higher input voltage sources are often called buck converters because the output voltage V OUT Less than the input voltage V IN , so the converter "steps down" the input voltage. Power converters that generate higher output voltage levels from lower input voltage supplies are often referred to as boost converters because V OUT Greater than V IN Some power converters can be either buck converters or boost converters, depending on which terminals are used for input and output. Some power converters can provide inverting outputs. Some power converters, known as multilevel converters, use charge transfer capacitors, often called "fly capacitors" or "pump capacitors."

[0006] 1 is a block diagram of a circuit including a prior art power converter 100. In the example shown, the power converter 100 includes a converter unit 102 and a controller 104. The converter unit 102 is configured to receive an input voltage V across terminals V1+, V1- (common) from a voltage source 106 (e.g., a battery). IN , and the input voltage V INTransformed into an output voltage V across terminals V2+, V2- (common) OUT . Output voltage V OUT Usually coupled to the output capacitor C OUT The output capacitor C OUT The two ends of the resistor can be connected to a load represented by an equivalent resistance R.

[0007] The controller 104 receives a set of input signals and generates a set of output signals. Some of these input signals arrive along a signal path 110 connected to the converter unit 102. Some of the input signals carry information indicating the operating state of the converter unit 102. The controller 104 also typically receives one or more external input / output signals I / O and a clock / timing signal CLK, which may be analog, digital (encoded or direct signal line), or a combination of both (although some controllers may be configured for asynchronous operation, e.g., a hysteresis controller or a constant on-time controller). Based on the received input signals, the controller 104 generates a set of control signals that are returned to the converter unit 102 on the signal path 110, which control the internal components of the converter unit 102 (e.g., internal switches, such as FETs, particularly MOSFETs) to cause the converter unit 102 to switch V IN Convert to V OUT In some embodiments, auxiliary circuits (not shown) may provide various signals to controller 104 (and optionally directly to converter unit 102), such as clock signal CLK, input / output signal I / O, and various voltages such as a universal power supply voltage V DD and transistor bias voltage V BIAS .

[0008] In some power converter designs, such as multi-level converters, the converter circuit 102 uses an inductor as an energy storage element. For example, FIG. 2 is a schematic diagram of a prior art 4-level DC to DC buck converter unit 200 that can be used as the converter circuit 102 of FIG. 1 . A set of FET power switches M1 to M6 (generally Mn) are coupled in series at V IN with respect to a reference potential (e.g., circuit ground or V IN The inductor L is coupled to the output capacitor C OUT and coupled to a node L between FET power switches M3 and M4. X . Coupled at node L X The FET power switches M1 to M3 between the circuit ground are "low-side" switches, and the FET power switches M1 to M3 ... X With V IN The FET power switches M4 to M6 are "high-side" switches.

[0009] The multi-level converter unit 200 converts the input voltage V IN Converted to output voltage V OUT The state transition pattern of the power switch determines the operating area and the corresponding V OUT In the example of FIG. 2 , the inductor L is surrounded by two groups of FET power switches M1 to M3 and M4 to M6 connected in series. Each adjacent pair of power switches in the first group of FET power switches and the second group of FET power switches are separated by a corresponding node. The node between each adjacent pair of FET power switches in a group is connected by a corresponding flying capacitor C. Fx is coupled to the corresponding node between each pair of FET power switches in another group. For example, in FIG2 , the node T1 between the FET power switches M4 and M5 is connected via the flying capacitor C F1 is coupled to the node B1 between the FET power switches M2 and M3. Similarly, the node T2 between the FET power switches M5 and M6 is connected to the node B1 between the FET power switches M2 and M3 through the flying capacitor C F2 Coupled to node B2 between FET power switches M1 and M2. The control clock signals for each set of power switches are complementary and provided by a control circuit (not shown).

[0010] Voltage detectors 202a, 202b (eg, simple comparator type circuits) may be used to sense a voltage relative to a reference voltage V REF The corresponding flying capacitor C Fx The voltage across the flying capacitor C Fx The output of each voltage detector 202a, 202b can be a simple voltage high / low state signal C Fx _ H / L , the voltage detectors 202a, 202b may be coupled to a control circuit (not shown).

[0011] In the example shown, the control gate of each FET power switch Mn is coupled to a corresponding level shifter / driver (LS / D) circuit 204 (although in some cases, level shifting circuitry is not required). A clock signal coupled as an input to each LS / D circuit 204 The on or off state of the corresponding FET power switch Mn is controlled. The clock signal may be generated, for example, by the controller 104 shown in FIG.

[0012] Powering LS / D circuit 204 effectively, efficiently, and with minimal circuitry is a desirable design goal. Summary of the invention

[0013] The present invention includes a power converter circuit and method including a self-timed bootstrap capacitor power supply.

[0014] Added to a power converter having a diode stack for charging a bootstrap capacitor are three types of supplemental circuit blocks: a trigger block, a trigger bypass block, and a bypass block (in some embodiments, a trigger bypass block may be used in place of a bypass block or a trigger block). In operation, adjacent supplemental circuit blocks work in pairs. The upper block in the pair, when triggered, is used to charge its associated bootstrap capacitor by connecting the top plate of the associated bootstrap capacitor to the top plate of the bootstrap capacitor associated with the lower block of the pair, essentially bypassing the diode associated with the upper block. In addition, the lower block in the pair is used to start (trigger) the bypass function of the upper block. When the connected bootstrap capacitors are disconnected and their respective voltages "fly" away, the bypass function of the upper block is automatically terminated, or controllably terminated. In some applications, the diode stack includes an explicit Schottky diode, while in other applications, the diode stack includes an intrinsic diode of a PFET switch within the supplemental circuit block.

[0015] It is noteworthy that the timing of the bypass function switching on and then off is simply a matter of the charging behavior of the bootstrap capacitors and the internal signal propagation timing between the complementary circuit blocks. The only control signals passed between any two bootstrap capacitor stacks are independent - no external inputs and / or synchronization control logic are required.

[0016] Generally, the present invention includes providing a circuit and method for transferring charge among multiple bootstrap capacitors of a power converter having multiple power switches, each bootstrap capacitor having a top plate and a bottom plate, wherein the top plates of each adjacent pair of bootstrap capacitors are coupled via corresponding diodes within a diode stack, the circuit and method being configured to perform one or both of the following functions: providing a trigger signal after an associated one of the multiple power switches is switched to an on state and thereby connects the bottom plates of the adjacent pair of bootstrap capacitors; and / or in response to receiving the trigger signal, initiating a bypass function with respect to the corresponding diodes coupling the adjacent pairs of bootstrap capacitors.

[0017] The details of one or more embodiments of the invention are set forth in the following drawings and description. Other features, objects, and advantages of the invention will be apparent from the description and drawings, and from the claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] FIG. 1 is a block diagram of a circuit including a prior art power converter.

[0019] FIG. 2 is a schematic diagram of a prior art 4-level DC to DC buck converter circuit that may be used as the converter circuit of FIG. 1 .

[0020] Figure 3Schematic diagram of a 3-level multi-level power converter implemented using NFET power switches.

[0021] Figure 4A is a schematic diagram of a portion of a 3-level multi-level power converter including a self-timed set / reset latch embodiment of the present invention.

[0022] Figure 4B is a schematic diagram of a portion of a 3-level multilevel power converter including a self-timed set / reset latch embodiment of the present invention, which advantageously utilizes the intrinsic body diode.

[0023] Figure 5 is a schematic diagram of a portion of a 3-level multilevel power converter including a self-timed set / controlled reset latch embodiment of the present invention.

[0024] Fig. 6A is a block diagram of a 4-level multilevel power converter including a supplementary circuit according to the present invention.

[0025] Figure 6B is a block diagram of a series capacitor buck power converter including a supplementary circuit according to the present invention.

[0026] Figure 6C is a block diagram of a conventional charge pump power converter.

[0027] Figure 7 is used to couple to the inductor L and the output capacitor C OUT 00140] A block diagram of one embodiment of the control circuitry of an M-level converter unit of an output block of FIG.

[0028] Figure 8 is a top view of a substrate which may be, for example, a printed circuit board or a chip module substrate (eg, a thin film assembly).

[0029] Fig. 9 is a process flow diagram illustrating a method for transferring charge among multiple bootstrap capacitors of a multi-level power converter having multiple power switches, each bootstrap capacitor having a top plate and a bottom plate, wherein the top plates of each adjacent pair of bootstrap capacitors are coupled through corresponding diodes within a diode stack.

[0030] Like reference numbers and designations in the various drawings indicate like elements. DETAILED DESCRIPTION

[0031] The present invention includes a power converter circuit and method including a self-timed bootstrap capacitor power supply. More specifically, the present invention includes providing a circuit and method for transferring charge among a plurality of bootstrap capacitors of a power converter having a plurality of power switches, each bootstrap capacitor having a top plate and a bottom plate, wherein the top plates of each adjacent pair of bootstrap capacitors are coupled through a corresponding diode within a diode stack, the circuit and method being configured to perform one or both of the following functions: providing a trigger signal after an associated one of the plurality of power switches is switched to a conductive state and thereby connects the bottom plates of the adjacent pairs of bootstrap capacitors; and / or in response to receiving the trigger signal, initiating a bypass function with respect to the corresponding diodes coupling the adjacent pairs of bootstrap capacitors.

[0032] Diode charges the bootstrap capacitor

[0033] In many power converters, especially multi-level power converters, N-type MOSFETs (NFETs) are often used for FET power switches because NFETs are characterized by much lower (better) R compared to P-type MOSFETs (PFETs). ON ×Q G Quality factor, where Q G is to turn on the FET to achieve a specified R ON The total gate charge required. For example, Figure 3 FIG. 3 is a schematic diagram of a 3-level multilevel power converter 300 implemented using NFET power switches. In this example, the clock signal and The voltage is applied to the control gates of a group 302 of series-coupled NFET power switches MN1 to MN4 via non-inverting driver circuits 302a, 302b or inverting driver circuits 304a, 304b. In some embodiments, the number of component inverters (or buffers) within driver circuits 302x, 304x can be increased to accommodate signal delay requirements. Level shifter circuitry is omitted in this example, but may be required in some embodiments, depending on V IN and the number of layers in the multilevel power converter.

[0034] The output VG1 to VG4 of each driver circuit 302x, 304x is coupled to the control gate of the corresponding NFET power switch MN1 to MN4. F1 The inductor L is coupled to the node between the adjacent low-side NFET power switches MN1 and MN2 and between the adjacent high-side NFET power switches MN3 and MN4. The inductor L is coupled to the output capacitor C OUT and coupled to a node L between the NFET power switches MN2 and MN3. X .

[0035] A disadvantage of using NFETs in switching power converters is that the NFETs are referenced to their source, which is the low voltage side of the power converter. One way to provide appropriate gate bias for each NFET power switch MNn and power the associated driver circuitry (and level shifter circuitry, if present) is to couple a bootstrap capacitor to the source of the associated NFET power switch and charge each bootstrap capacitor to a voltage sufficient to effect switching of the gate of the associated power switch NFET.

[0036] Refer again Figure 3 , power to each driver circuit 302x, 304x is provided by the charge stored on a corresponding bootstrap capacitor Cn (in this example, n=1...4) coupled to the voltage input of the driver circuit 302x, 304x. Each bootstrap capacitor Cn should be sized to provide at least enough charge with minimal voltage drop to allow the driver circuit 302x, 304x to switch the state of the associated NFET power switch Mn (whose control gate is a relatively large capacitive structure). Typically, all bootstrap capacitors Cn lose charge when switching the gate of the associated NFET power switch. In addition, the bootstrap capacitors Cn lose charge even when not switching the associated power switch, such as through DC current consumption from other connected circuit systems (e.g., bias current of analog circuits). Therefore, the bootstrap capacitors Cn need to be periodically recharged during startup and during normal operation to replenish the lost charge.

[0037] In a conventional 2-level DC-to-DC converter (which is not considered a "multi-level" converter), there are only two NFET power switches and no flying capacitor C F1 Low-side NFET power switches are typically referenced to circuit ground, so their gate driver supply can be directly connected to a fixed supply (for example, V DD ). The source reference node L of the high-side NFET power switch X , hence a floating gate driver supply is required, which can be provided by an associated bootstrap capacitor. The high side bootstrap capacitor needs to be recharged periodically to replenish the lost charge. This can be achieved by providing a diode with its anode connected to the fixed supply and its cathode connected to the top plate of the high side bootstrap capacitor. When node L X (which is coupled to both the bottom plate of the high-side bootstrap capacitor and the source of the high-side NFET power switch) is at a 0V level, the high-side bootstrap capacitor is charged to the voltage level of the fixed power supply, minus the forward bias voltage drop of the diode. This works well because when the low-side NFET power switch is turned on (conducting), node L X (Source of the high-side switch) is forced to 0V.

[0038] In a true multi-level converter including series capacitor buck, charge pump and resonant charge pump circuits, there are usually more than two NFET power switches connected in series. Therefore, the source of some NFET power switches will not be at 0V level during operation, so the associated bootstrap capacitor cannot be charged from the fixed voltage supply connected to the bootstrap capacitor that powers the lowest NFET power switch. However, the diode-only charging technique applicable to 2-level DC to DC converters has limitations for true multi-level power converters (e.g., 3-level, 4-level and higher level power converters). For example, again referring to Figure 3 , each diode D1 to D3 is coupled so that its anode is connected to the top plate of the lower bootstrap capacitor and its cathode is connected to the top plate of the next higher bootstrap capacitor (“higher” means closer to V IN terminals, and "lower" means closer to the ground terminal). Therefore, diode D1 is coupled between the top plates of bootstrap capacitors C1 and C2; diode D2 is coupled between the top plates of bootstrap capacitors C2 and C3; and diode D3 is coupled between the top plates of bootstrap capacitors C3 and C4. In addition, the anode of the lowest diode D1 is coupled to V DD .

[0039] Whenever the NFET power switch is turned on (conducting), it connects the bottom plate of the next higher bootstrap capacitor to the bottom plate on its associated bootstrap capacitor, so in a sense, the two bootstrap capacitors "fly" together to the same voltage level. In contrast, whenever the NFET power switch is turned off (not conducting or blocking), the bottom plates of the two adjacent bootstrap capacitors will be disconnected and therefore "fly" apart to different voltage levels. Figure 3 As an example, if V IN =12V, then any NFET power switch MNx that is turned off will have approximately 6V separating the bottom plates of two adjacent bootstrap capacitors, and any NFET power switch that is turned on will have 0V separating the bottom plates of two adjacent bootstrap capacitors.

[0040] Therefore, the minimum bootstrap capacitor C1 is V DD Continuously charge; when MN1 is closed (on), the bootstrap capacitor C2 is charged by V through diode D1 DD when MN2 is closed, the bootstrap capacitor C3 is charged by the bootstrap capacitor C2 through the diode D2; and when MN2 is closed, the bootstrap capacitor C4 is charged by the bootstrap capacitor C3 through the diode D3.

[0041] The problem that arises is that each successive higher diode causes a forward bias voltage drop, which reduces the available charge voltage. For example, bootstrap capacitor C4 will see 3 diode voltage drops across diodes D1 to D3, plus the capacitor charge redistribution voltage drop. Assuming V DD =5V, the diode forward bias voltage drop is about 0.7V, and the charge redistribution voltage drop is about 0.3V, then the bootstrap capacitor C2 will be charged at a maximum of about 4V, C3 will be charged at a maximum of about 3V, and C4 will only be charged at a maximum of about 2V, which may not be enough to cause the corresponding driver circuit 302a to switch the associated NFET power switch MN4. The lower voltage available for the higher-level bootstrap capacitors also results in larger switching delays for the associated buffer circuits, which may increase the generation of the clock signal and (or equivalent timing signal), limiting the switching rate of the power converter. The lower voltage available for the upper layer bootstrap capacitor also makes the resistance of the power switch FET larger, and thus the switching rate of the power converter is limited by the dead time in the clock circuitry of the FET (or equivalent timing signal). GS And the efficiency is lower.

[0042] In addition to the voltage lost due to charge redistribution, the penalty of one diode forward bias voltage drop per charge transfer becomes worse as the number of layers in the stack of NFET power switches increases. For example, a 5-level multilevel converter would have a stack of 8 NFET power switches with associated bootstrap capacitors. If the bottom bootstrap capacitor is directly connected to a fixed supply (e.g., V DD ), there is still a stack of 7 higher bootstrap capacitors, each seeing a cumulative diode voltage drop due to all the bootstrap capacitors below. For example, the topmost bootstrap capacitor will see a cumulative 7 diode forward bias voltage drop. Even if Figure 3 The diodes in the circuit are replaced by Schottky diodes, which have a smaller forward bias voltage drop than conventional diodes. The accumulation of diode forward bias voltage drops can also effectively "consume" most or all of the available voltage from the fixed power supply.

[0043] The additional circuitry encompassed by the present invention overcomes the shortcomings of diode-only charging techniques for multi-level converters.

[0044] Self-Timed Set / Reset Complement Circuit for Diode Stacks

[0045] Figure 4A FIG. 4 is a schematic diagram 400 of a portion of a 3-level multilevel power converter including a self-timed set / reset latch embodiment of the present invention. The circuit shown is similar in many respects to Figure 3, but omitting the driver circuits 302x, 304x and the output circuit system (inductor L, capacitor C OUT ) to avoid clutter. In addition, the diodes D1' to D3' are preferably Schottky diodes, which have a smaller forward bias voltage drop than conventional diodes (note that in some embodiments, the explicit circuit components diodes D1' to D3' are not required, as described in detail below). Although a 3-level multilevel power converter is shown by way of example, the concepts of the present invention can be easily extended to higher-order multilevel power converters. The level shifter circuit system is omitted in this example, but the level shifter circuit system may be required in some embodiments, depending on V IN and the number of layers in the multilevel power converter.

[0046] Added to the circuit are three types of supplemental circuit blocks: trigger block 402, trigger bypass blocks 404a, 404b, and bypass block 406 (in some embodiments, trigger bypass block 404x may be used in place of trigger block 402 and / or bypass block 406, as further described below).

[0047] The bypass block 406 shown includes a pair of cross-coupled PFETs MP4a, MP4b. The drain-source conductive channel of MP4a is coupled in parallel with the associated diode D3' (i.e., the source of MP4a is coupled to the cathode of D3', and the drain of MP4a is coupled to the anode of D3'). The drain of MP4a is also coupled to the gate of MP4b. The drain-source conductive channel of MP4b is coupled between the cathode of D3' and the gate of MP4a. The drain of MP4b is also coupled to the trigger signal line from the adjacent lower-level supplementary circuit block 404a. Therefore, the sources of MP4a and MP4b are also coupled to the top plate of the bootstrap capacitor C4.

[0048] The illustrated trigger bypass blocks 404a, 404b include a pair of cross-coupled PFETs MP3a, PFET MP3b and PFETs MP2a, PFET MP2b, respectively, which are configured similarly to the illustrated pair of cross-coupled PFETs MP4a, PFET MP4b of the bypass block 406. Thus, the conductive channel of MP3a is coupled in parallel with the associated diode D2', and the conductive channel of MP2a is coupled in parallel with the associated diode D1'. Similarly, the conductive channel of MP3b is coupled between the cathode of D2' and the gate of MP3a, and is coupled to the trigger signal line from the adjacent lower-level supplementary circuit block 404b, while the conductive channel of MP2b is coupled between the cathode of D1' and the gate of MP2a, and is coupled to the trigger signal line from the adjacent lower-level supplementary circuit block 402.

[0049] In each trigger bypass block 404a, 404b, a corresponding inverter I3, I2 is also included, and the inverter I3, I2 has an input terminal coupled to the drain of the corresponding NFET power switch MN3, MN2 and an output terminal coupled to the gate of the corresponding trigger NFET MNt3, NFETMNt2. The conductive channel of the trigger NFET MNt3 is coupled between the gate of MP4a and the source of the NFET power switch MN3, and selectively provides a trigger signal to MP4a. The conductive channel of the trigger NFET MNt2 is coupled between the gate of MP3a and the source of the NFET power switch MN2, and selectively provides a trigger signal to MP3a. Note that a level shifter (not shown) may be required to convert the maximum V of each MNtx DS and the levels between the corresponding inverter inputs (I1, I2 and I3 in this example). In addition, the voltage supply for inverters I1, I2 and I3 comes from the corresponding bootstrap capacitors C1, C2 and C3, and if the bootstrap capacitor voltage exceeds the maximum supply voltage tolerated by the inverter, a corresponding voltage reduction circuit may be required.

[0050] As should be clear, bypass block 406 is similar to trigger bypass block 404x, but the inverter NFET and trigger NFET are omitted. Therefore, trigger bypass block 404x can be used in place of bypass block 406.

[0051] The trigger block 402 includes an inverter I1 having an input terminal coupled to the drain of the NFET power switch MN1 and an output terminal coupled to the gate of the trigger NFET MNt1. The conductive channel of the trigger NFET MNt1 is coupled between the gate of MP2a and the source of the NFET power switch MN1, and selectively provides a trigger signal to MP2a.

[0052] In operation, adjacent supplementary circuit blocks 402, 404x, 406 work in pairs. The upper block in the pair, when triggered, is used to charge its associated bootstrap capacitor by connecting the top plate of the associated bootstrap capacitor to the top plate of the bootstrap capacitor associated with the lower block of the pair, essentially bypassing the diode associated with the upper block. In addition, the lower block in the pair is used to start (trigger) the bypass function of the upper block. When the connected bootstrap capacitors are disconnected and their respective voltages "fly" apart, the bypass function of the upper block is automatically terminated.

[0053] It is noteworthy that in this embodiment, the timing of the bypass function switching on and then off is simply a matter of the charging behavior of the bootstrap capacitors and the internal signal propagation timing between the complementary circuit blocks. The only control signals passed between any two bootstrap capacitor stacks are independent - no external inputs and / or synchronization control logic are required.

[0054] Taking adjacent trigger bypass blocks 404a and 404b as an example of operation, when gate control voltage VG2 is applied to NFET power switch MN2, then MN2 will turn on, thereby connecting the bottom plate of bootstrap capacitor C2 to the bottom plate of bootstrap capacitor C3. As a result, charge begins to transfer from the top plate of C2 to the top plate of C3 through diode D2'. At the same time, the on-state of MN2 causes the input of inverter I2 to be low, causing the output of inverter I2 to be high, thereby causing trigger NFET MNt2 to turn on (conduct). The on-state of triggering NFET MNt2 connects the gate of MP3a to a relatively low voltage (circuit ground in the case of MNt1) relative to the voltage at the source of MP3a, and thus acts as a trigger signal, which causes the gate voltage on PFET MP3a to be negative and allows MP3a to turn on with a delay of a period of time after MN2 is turned on. When MP3a is on, it effectively bypasses diode D2' and connects the top plate of C3 directly to the top plate of C2, causing essentially no voltage drop losses with respect to charge transfer from C2 to C3 (especially compared to Figure 3 In this state, MP3b is open (blocked).

[0055] When gate control voltage VG2 turns NFET power switch MN2 off, MN2 stops conducting, which allows the voltage across previously parallel-connected bootstrap capacitors C2 and C3 to move apart, with the top plate of C2 being more negative than the top plate of C3. A sufficient voltage difference causes MP3b to turn on, thereby applying essentially zero V to the gate of PFET MP3a. GS , disconnecting MP3a, thus preventing the charge on C3 from flowing back to C2 through MP3a.

[0056] There may be a short delay in turning MP3a off while the voltages on the bootstrap capacitors C3 and C2 move apart, but the cross-coupled PFET pair MP3a / MP3b is typically very fast so the delay is typically very small (believed to be on the order of 1ns or less), which provides very little time for any reverse transfer of charge from the higher bootstrap capacitor C3 back to the lower bootstrap capacitor C2.

[0057] When MN2 is disconnected, the trigger signal generated by MNt2 also stops being generated after some delay time (i.e., MNt2 returns to the blocking state). Note that due to signal delays through inverter I2 and MNt2 itself, MNt2 may not have been disconnected when MP3b is turned on, and technically still shunts the gate of MP3a to a relatively low voltage. However, by sizing MP3b to be significantly larger than MNt2 (e.g., 10 times wider with the same channel length), MP3b overwhelms the shunting effect of MNt2 to quickly disconnect the cross-coupled MP3a. It can also be noted that MP3b does not need to be particularly large relative to MP3a, as MP3b only controls the gate voltage. For example, MP3b can be significantly smaller than MP3a (e.g., reduced to 1 / 10 times in width with the same channel length).

[0058] The bypass block 406 works in the same manner as the adjacent lower level trigger bypass block 404x, however, as a top supplementary circuit block, the bypass block 406 does not need to generate a trigger signal.

[0059] Trigger block 402 operates in a similar manner to provide a trigger signal to an adjacent higher level trigger bypass block 404x. However, as a bottom complementary circuit block for bootstrap capacitor C1 coupled to a fixed voltage supply, the cross-coupled PFET circuitry of trigger bypass block 404x may be omitted.

[0060] Self-Timed Set / Reset Complementary Circuit Using Intrinsic Body Diode

[0061] Figure 4A The embodiments utilize explicit circuit components diodes D1' to D3'. However, in some applications, explicit diodes D1' to D3' may be omitted, relying instead on the intrinsic body diodes of the MOSFET devices to perform substantially the same function. For example, Figure 4B 450 is a schematic diagram of a portion of a 3-level multilevel power converter including a self-timed set / reset latch embodiment of the present invention that advantageously utilizes an intrinsic body diode. It is common practice to omit the schematic representation of the intrinsic body diode from the symbol of an NFET or PFET. However, in Figure 4B In FIG. 1 , the symbols of PFET MP2a to PFET MP4a have been expanded to include their respective intrinsic body diodes Di1 to Di3. Figure 4B and Figure 4A As shown in the comparison, Figure 4B The circuit system is essentially the same as Figure 4AThe circuitry of the 2000 diodes is identical to that of the 2000 diodes and operates in substantially the same manner (note that the body diode is a conventional pn junction diode with a larger forward bias voltage drop than a Schottky diode). Also, the level shifter circuitry is omitted in this example, but may be required in some implementations, depending on V IN and the number of layers in the multilevel power converter.

[0062] Self-Timed Set / Controlled Reset Complementary Circuit for Diode Stacks

[0063] As mentioned above, Figure 4A and Figure 4B The operation of the embodiment of is entirely dependent on the charging behavior of the bootstrap capacitors and the internal signal propagation timing between the supplementary circuit blocks. However, in some applications, when the capacitors begin to "fly" apart to different voltages, transient voltage swings may occur within the power converter, which will disrupt the pattern of charging of adjacent bootstrap capacitors after their bottom plates are disconnected from the common potential. For example, although the bottom plates of the bootstrap capacitors C2 and C3 are connected together when the trigger NFET MNt2 is turned on, there is no problem of transient effects because the on-resistance of MNt2 is very low, so the bottom plates are forced together. When MNt2 is disconnected, the voltages on C2 and C3 begin to fly apart, but due to certain transient conditions, the bottom plates of C2 and C3 may be momentarily together, which causes the PFET MP3a to be inadvertently turned on. Therefore, such transient voltage swings may cause the diode bypass function of the bypass block 404x and the bypass block 406 supplementary circuit to remain turned on (conducting) for too long, or to be triggered, thereby discharging its associated bootstrap capacitor.

[0064] To accommodate the possibility of such transient voltage swings and / or to mitigate any concern that the diode bypass functions of PFET MP2a to PFET MP4a may be inadvertently activated or remain activated for too long, the hybrid circuit provides a self-timed set but controlled reset of the diode bypass functions of PFET MP2a to PFET MP4a. More specifically, the hybrid circuit utilizes internal signal propagation timing between complementary circuit blocks to initiate the diode bypass functions of trigger bypass blocks 404x and bypass blocks 406, but uses logic signals derived from the associated gate control voltage signals of the NFET power switches to force PFET MP2a to PFET MP4a into an off state, thereby terminating their diode bypass functions.

[0065] Figure 5 5 is a schematic diagram of a portion of a 3-level multilevel power converter including a "controlled set / self-timed reset" latch embodiment of the present invention. Level shifter circuitry is omitted in this example, but may be required in some embodiments, depending on VIN and the number of layers in the multilevel power converter.

[0066] Similar in many ways to Figure 4A In the embodiment shown in Figure 5 The embodiment shown in FIG. 5 includes three types of supplementary circuit blocks: a trigger block 502, a trigger bypass block 504a, 504b, and a bypass block 506. In some embodiments, the trigger bypass block 504 can be used in place of the bypass block 506 by leaving the inverter unconnected. In some embodiments, the trigger bypass block 504 can be used in place of the trigger block 502 by leaving the latch and the PFET unconnected. Therefore, the trigger bypass block 504 can be considered a "universal" block that can be used as any of the three types of supplementary circuit blocks.

[0067] Figure 5 The embodiment shown in replaces the trigger bypass blocks 404a, 404b and the bypass block 406 with modified trigger bypass blocks 504a, 504b and modified bypass block 506. In essence, Figure 4A The cross-coupled PFETs M2Pb through PFETMP4b shown in FIG. 5 are replaced by circuits that essentially function as active-low set / reset (SR) latches 501a through 501c.

[0068] The SR latch 501x ​​of each modified trigger bypass block 504x and modified bypass block 506 has an output terminal Q coupled to the gate of the corresponding PFET MP2a to PFET MP4a. The (low reset) input terminal is coupled to the corresponding trigger signal line from the adjacent lower layer supplementary circuit block. For example, in the modified bypass block 506, the SR latch 501c coupled to MP4a The input terminal is coupled to the trigger signal line from the trigger NFET MNt3 in the modified trigger bypass block 504a. The input terminal is also connected through a pull-up resistor R P Coupled to the top plate of the corresponding bootstrap capacitors C2 to C4.

[0069] Each of the modified trigger bypass blocks 504x and the modified bypass block 506 has a SR latch 501x. The (low Set) input terminals are coupled to respective control signals VG1' to VG3', which correspond to respective gate control signals VG1 to VG3 applied to the adjacent lower NFET power switches. The control signals VG1' to VG3' are synchronized with the gate control signals VG1 to VG3, but are different in phase from the gate control signals VG1 to VG3 and may be level shifted. Preferably, the control signals VG1' to VG3' are earlier in phase than the gate control signals VG1 to VG3 so as to switch the output Q of their respective SR latches 501x ​​(so as to turn off the respective PFET MP2a to PFET MP4a) before the respective NFET power switches MN1 to MN3 are turned off. The delay of the gate control signals VG1 to VG3 relative to the control signals VG1' to VG3' may be provided, for example, by a signal delay inherent in the driver circuit of the corresponding NFET power switch MNx.

[0070] In operation, adjacent supplementary circuit blocks 502, 504x, 506 work in pairs. The upper block in the pair, when triggered, is used to charge its associated bootstrap capacitor by connecting the top plate of the associated bootstrap capacitor to the top plate of the bootstrap capacitor associated with the lower block of the pair, essentially bypassing the diode associated with the upper block. In addition, the lower block in the pair is used to enable (trigger) the bypass function of the upper block.

[0071] Thus, for example, when gate control voltage VG2 is applied to NFET power switch MN2, MN2 is turned on, thereby connecting the bottom plate of bootstrap capacitor C2 to the bottom plate of bootstrap capacitor C3. As a result, charge begins to transfer from the top plate of C2 to the top plate of C3 through diode D2'. At the same time, the on-state of MN2 causes the input of inverter I2 to be low, thereby causing the output of inverter I2 to be high, thereby causing trigger NFET MNt2 to turn on. The on-state of trigger NFET MNt2 turns the SR latch 501b on. The input is connected to a low potential and thus acts as a trigger signal, which causes the Q output of SR latch 501b to be low (negative relative to the source of PFET MP3a). Therefore, MP3a turns on with a delay of some time after MN2 turns on. When MP3a turns on, it effectively bypasses diode D2' and connects the top plate of C3 directly to the top plate of C2, causing substantially no voltage drop losses with respect to the charge transfer from C2 to C3.

[0072] exist Figure 4A and Figure 4BIn the embodiment of , when two previously connected bootstrap capacitors "fly" apart (due to the associated NFET power switch MNx switching to the off state), the difference in the top plate voltages of the two previously connected bootstrap capacitors is used to terminate the triggering of the bypass function of the bypass block 404x or the bypass block 406. In contrast, in Figure 5 In the embodiment of the present invention, the corresponding "early" control signals VG1' to VG3' are applied to the associated SR latch 501x. Input, causing the Q output of SR latch 501b to be high, thereby turning off the associated PFET MP2a to PFET MP4a and terminating the bypass function of the modified trigger bypass block 504x or the modified bypass block 506. Since the high-to-low state change of the control signal VG1' to VG3' preferably occurs earlier in time than (but otherwise synchronously with) the corresponding high-to-low state change of the gate control signal VG1 to VG3, the initiated bypass function is terminated before the voltage of the associated bootstrap capacitor (e.g., C2 and C3) can "fly" away. Therefore, the diode bypass function of PFET MP2a to PFET MP4a is terminated early enough to avoid the possibility that PFET MP2a to PFET MP4a may be inadvertently activated or remain activated for too long.

[0073] Self-Timed Set / Controlled Reset Complementary Circuit Using Intrinsic Body Diode

[0074] Similar to Figure 4A implementation method, Figure 5 The embodiments utilize explicit circuit components diodes D1' to D3'. However, in some applications, the explicit diodes D1' to D3' may be omitted, relying instead on the intrinsic body diodes of the MOSFET devices to perform substantially the same function, such as in Figure 4B Therefore, we can use Figure 5 In the embodiment of the present invention, the intrinsic body diodes of PFET MP2a to PFET MP4a are used to replace the explicit diodes D1' to D3'. Also, the level shifter circuit system is omitted in this example, but the level shifter circuit system may be required in some embodiments, depending on V IN and the number of layers in the multilevel power converter.

[0075] Extensions to other multilevel power converters

[0076] Although Figure 4A , Figure 4B and Figure 5 An example 3-level multilevel power converter is shown, but the concepts of the present invention can be easily extended to higher order multilevel power converters and other types of power converters. For example, Fig. 6Ais a block diagram 600 of a 4-level multilevel power converter including a supplementary circuit according to the present invention. Figure 4A , Figure 4B and Figure 5 In the embodiment of FIG. 2 , the supplementary circuit blocks 402, 502, 404x, 504x and 406, 406 of these figures have been summarized as a trigger block 602, trigger bypass blocks 604a to 604d, and a bypass block 606. The number of NFET power switches MNx totals 6 (as in the 4-level multilevel power converter of FIG. 2 ). Fig. 6A middle, Figure 4A and Figure 5 The diode stack shown in is considered to be part of a supplementary circuit block, as the explicit circuit component diodes are optional.

[0077] Additional circuitry may be added as needed for a particular application. For example, the voltage detectors 202a, 202b shown in FIG. 2 may be included in Figure 4A , Figure 4B , Figure 5 and the embodiment shown in Figure 6 and in higher order multi-level power converters. As another example, the bootstrap capacitor Cx may need to be pre-charged during a start-up period before normal switching operation of the power converter can properly begin. Fig. 6A An example of a precharge circuit 610 that can be used during the startup period is shown in FIG. PC1 and the associated series resistor R PC1 coupled between the bottom plates of the bootstrap capacitors C3 and C5; the second NFET M PC2 and the associated series resistor R PC2 coupled between the bottom plates of the bootstrap capacitors C5 and C6; and a third NFET M PC3 and the associated series resistor R PC3 The bottom plate of the bootstrap capacitor C6 is coupled to V IN between.

[0078] In a startup process, at the beginning of the startup period, the bottom two NFET power switches MN1, MN2 are forced on (ie, VG1 and VG2 are high) to connect the two flying capacitors C F1 , C F2 The bottom plate is connected to circuit ground, and V DD is applied to the bootstrap capacitor C1. The switches MN3 to MN6 remain open. If the flying capacitors CF1, CF2 are initially in a discharged state and the flying capacitor C F1 , C F2If the capacitance of the bypass block 604a and 604b is much larger than the capacitance of the bootstrap capacitor Cx, the diodes (explicit or inherent) in the bypass blocks 604a and 604b and the corresponding bypass PFET MPna are triggered to charge the bottom three bootstrap capacitors C1 to C3 when turned on, while only the diodes in the bypass blocks 604c, 604d and the bypass block 606 are triggered to charge the top three bootstrap capacitors C4 to C6.

[0079] Then, using NFET M PC1 To NFET M PC3 Combined with its corresponding series resistor R PC1 To R PC3 , by making the three NFETs M PC1 To NFET M PC3 The flying capacitor C may be switched on or off until a corresponding target voltage is reached (eg, as determined by the voltage detectors 202a, 202b). F1 , C F2 precharged to the corresponding target voltage. For example, if C F1 If the voltage is higher than the target, M PC1 should be connected. If C F1 voltage is lower than the target or C F2 If the voltage is higher than the target, M PC2 should be connected. If C F2 If the voltage is lower than the target, M PC3 In this example, the corresponding target voltage for the flying capacitor C F1 Yes V IN / 3, and for the flying capacitor C F2 is 2×V IN / 3 (the denominator is one less than the number of orders or stages of the multilevel power converter: in this example 3 = stage 4-1). Once the flying capacitor C F1 , C F2 Once their target voltages are reached, normal switching of the power converter can begin at the target switching frequency.

[0080] With the flying capacitor C F1 , C F2 The voltage on MN3 rises, triggering the diodes within bypass blocks 604c and 604d and within bypass block 606 to stop charging the top three bootstrap capacitors C4 to C6. Leakage current from the circuits connected to the top three bootstrap capacitors C4 to C6 may cause those capacitors to discharge, in which case the capacitor charge can be replenished by periodically turning on NFET power switches MN3, MN4, and MN5 for a short time (e.g., 100ns), which forces a small current through inductor L to the output of the power converter.

[0081] It will be appreciated that other circuitry may be used to pre-charge the flying capacitors and the bootstrap capacitors of the multi-level power converter.

[0082] As another example of the use of the charging circuit for the bootstrap capacitor of the present invention with other types of power converters, Figure 6B 6 is a block diagram 650 of a series capacitor buck power converter 652 including a supplemental circuit according to the present invention. The series capacitor buck power converter 652 includes a first group of series-coupled NFET power switches MN1 to MN4 and a second group of series-coupled NFET power switches MN5 to MN8. Each NFET power switch MN1 to MN8 has a control gate coupled to a corresponding driver circuit 654-1...654-8 (e.g., a buffer circuit), which in turn is coupled to a corresponding control signal S1 to S8. In the example shown, the drains and sources of the three pairs of corresponding NFET power switches from the two groups are coupled through capacitors; therefore, the flying capacitors C F1 The source of MN4 is coupled to the drain of MN5, and the flying capacitor C F2 The source of MN3 is coupled to the drain of MN6, and the flying capacitor C F3 The source of MN2 is coupled to the drain of MN7. The respective drain of each of the second set of NFET power switches MN5 to MN8 is coupled to V through corresponding inductors L1 to L4. OUT terminals and output capacitor C OUT .

[0083] In the example shown, a second set of series-coupled NFET power switches MN5 to MN8 is connected by V DD Power is supplied by the first group of series-coupled NFET power switches MN5 to MN1 to MN4, while the first group of series-coupled NFET power switches MN5 to MN1 to MN4 are powered by corresponding bootstrap capacitors C1 to C4. In a conventional configuration, diodes D1" to D4" are coupled to V as shown. DD and the top plate of C1 (in the case of D1"), or coupled between the top plate of the associated bootstrap capacitor and the top plate of the bootstrap capacitor associated with the next lower block bootstrap capacitor. Thus, D2" couples the top plates of C2 and C1, D3" couples the top plates of C3 and C2, and D5" couples the top plates of C4 and C3. The series capacitor step-down power converter 652 operates in a known manner.

[0084] Conventional series capacitor buck power converter 652 presents the above-mentioned problems with charging bootstrap capacitors C1 to C4 effectively, efficiently, and with minimal circuitry. Figure 6BIn the example shown, trigger block 602 is coupled across NFET power switch MN8, trigger bypass blocks 604a, 604b, 604c are coupled to bootstrap capacitors C1, C2, C3, respectively, and bypass block 606 is coupled to bootstrap capacitor C4 (note that in Figure 6B , the diode stacks D1" to D4" are shown as part of a supplementary circuit block because the explicit circuit component diodes are optional). Thus, the conventional series capacitor buck power converter 652 benefits from the use of supplementary blocks encompassed by the present invention.

[0085] As yet another example of the use of the charging circuit for the bootstrap capacitor of the present invention with other types of power converters, Figure 6C is a block diagram of a conventional charge pump power converter 670. In the example shown, the clock phase During this period, the capacitor C B The capacitor C is charged A In contrast, in the clock phase During this period, the capacitor C B Discharge while capacitor C A To advantageously use the supplementary circuit according to the invention to charge from V DD The upward ripple charge to charge each bootstrap capacitor C, diode Dx will be triggered by the trigger block (for the bottom-most diode D T ), bypass block (for the top diode D B ) or trigger bypass block (for middle diode D TB ) instead.

[0086] Conventional charge pump power converter 670 may also include pre-charge circuits 672a, 672b, which are similar to Fig. 6A The pre-charge circuit 610 functions in a manner to pre-charge the bootstrap capacitor C during a startup period before normal switching operation of the power converter can properly begin.

[0087] Example Control Circuitry for an M-Level Shifter Cell

[0088] It will be appreciated that the power converter may require complex control circuitry which may include feedback loops to control the switching of the power FETs and monitor the current and / or voltage at one or more nodes of the power converter to achieve a desired conversion ratio and maintain a desired output voltage level.

[0089] For example, Figure 7 is used to couple to the inductor L and the output capacitor C OUT4. A block diagram of one embodiment of a control circuit system 700 for an M-level converter unit 702 of an output block 704 of FIG. 4 (conceptually, the inductor L may also be considered to be included within the M-level converter unit 400). The example control circuit system 700 is adapted from the teachings set forth in U.S. patent application serial number 63 / 276,923, entitled “Controlling Charge-Balance and Transients in a Multi-Level Power Converter,” filed on November 8, 2021, which is assigned to the assignee of the present invention and the contents of which are incorporated by reference. However, the present invention may be used in conjunction with other types of control circuit systems for the M-level converter unit 702.

[0090] The control circuit system 700 is used as a control loop coupled to the output of the M-level converter unit 702 and to the switch control input of the M-level converter unit 702. Generally, the control circuit system 700 is configured to monitor the output (e.g., voltage and / or current) of the M-level converter unit 702 and take into account V IN The control circuit system 700 dynamically generates a set of switch control inputs to the M-level converter unit 702 according to the change of the output load, which attempts to stabilize the output voltage and / or current at a specified value. In an alternative embodiment, the control circuit system 700 can be configured to monitor the input (e.g., voltage and / or current) of the M-level converter unit 702 and / or the internal nodes of the M-level converter unit 702 (e.g., the voltage across one or more flying capacitors or the current through one or more power switches). Therefore, most generally, the control circuit system 700 can be configured to monitor the voltage and / or current of the nodes (e.g., input terminals, internal nodes, or output terminals) of the M-level converter unit 702. The control circuit system 700 can be incorporated into the overall controller 104 of the power converter 100 for implementing the M-level converter unit 702 or can be separated from the overall controller 104.

[0091] The first block includes a feedback controller 706, which can be a conventional controller such as a fixed frequency voltage mode or current mode controller, a constant on-time controller, a hysteresis controller, or any other variation. The feedback controller 706 is shown coupled to V from the M level converter unit 702. OUT In an alternative embodiment, the feedback controller 706 may be configured to monitor the input of the M-level converter unit 702 and / or the internal nodes of the M-level converter unit 702. The feedback controller 706 generates a signal directly or indirectly indicating V OUT The voltage at V is a signal that, in general, determines what needs to be done in the M-level converter unit 702 to maintain V OUTThe expected value of: charging, discharging, or tri-state (i.e., open circuit, no current flowing).

[0092] In the example shown, the feedback controller 706 includes a feedback circuit 708, a compensation circuit 710, and a PWM generator 712. The feedback circuit 708 may, for example, include a feedback loop voltage detector that converts V OUT (or V OUT The attenuated version of V OUT The target voltage (which can be dynamic) is compared with a reference voltage and a control signal is output to indicate V OUT Is it above or below the target voltage. The feedback loop voltage detector can be implemented with a comparison device, such as an operational amplifier (op-amp) or a transconductance amplifier (gm amplifier).

[0093] The compensation circuit 710 is configured to stabilize the closed-loop response of the feedback controller 706 by avoiding unintentional creation of positive feedback that could cause oscillations, and controlling overshoot and ringing in the step response of the feedback controller 706. The compensation circuit 710 may be implemented in a known manner and may include LC and / or RC circuits.

[0094] The PWM generator 712 generates the actual PWM control signal that ultimately sets the duty cycle of the switches of the M-level converter unit 702. In some embodiments, the PWM generator 712 can pass an additional optional control signal CTRL that indicates, for example, V OUT The magnitude of the difference from the reference voltage (thus indicating that certain levels of the M-level converter unit 702 should be bypassed to reach a higher or lower level) and the direction of the difference (e.g., V OUT In other embodiments, the optional control signal CTRL may be output from the output of the compensation circuit 710 or from the output of the feedback circuit 708 or from a voltage coupled to, for example, V OUT A separate comparator (not shown) is used to obtain the selectable control signal CTRL. One purpose of the selectable control signal CTRL is to OUT How close to the target output voltage is that this may be useful for advanced control algorithms, allowing OUT In severe under regulated conditions, the inductor L is charged faster.

[0095] The second block includes an M-level controller 714, the main function of which is to select the desired V OUT The switch states of the charge balance state on the flying capacitors within the M-level converter unit 702 are simultaneously maintained regardless of which switch state or switch states were used in the past.

[0096] The M-level controller 714 includes a voltage level selector 716 that receives the PWM control signal and an additional control signal CTRL (if available). In addition, the voltage level selector 716 may be coupled to V OUT and / or V IN , and in some embodiments, coupled to a corresponding flying capacitor C from within the M level converter unit 702 Fx The high / low state signal of the voltage detector C Fx_H / L The function of the voltage level selector 716 is to convert the received signal to a target output voltage level (eg, on a cycle-by-cycle basis). The voltage level selector 716 typically considers at least V OUT and V IN to determine which target level should charge or discharge the output of the M-level converter unit 702 at a desired rate.

[0097] The output of the voltage level selector 716 is coupled to an M-level switch state selector 718, which typically couples the output of the flying capacitor C Fx The capacitor voltage detector status signal C Fx H / L . Taking into account the target level generated by the voltage level selector 716, the M-level switch state selector 718 determines which switch state for the desired output level should be most suitable for capacitor charge balancing. The M-level switch state selector 718 can be implemented, for example, as a lookup table (LUT) or comparison circuitry and combinational logic or more general processor circuitry. The output of the M-level switch state selector 718 is coupled to the switches of the M-level converter unit 702 (through appropriate level shifter circuits and driver circuits, as may be required for a particular converter unit) and includes a switch state setting determined by the M-level switch state selector 718 (which selects the configuration of the switches within the M-level converter unit 702 corresponding to the selected target level).

[0098] Typically (but not always), the voltage level selector 716 and the M-level switch state selector 718 only change their states when the PWM signal changes. For example, when the PWM signal goes high, the voltage level selector 716 selects which level causes the charging of the inductor L, and the M-level switch state selector 718 sets which version of this level is used. Then, when the PWM signal goes low, the voltage level selector 716 selects which level should discharge the inductor L, and the M-level switch state selector 718 sets which version of this level is to be used. Therefore, the PWM signal is actually a clock signal for the voltage level selector 716 and the M-level switch state selector 718. However, there may be the following situation or event: the CTRL signal is expected to change the state of the voltage level selector 716. In addition, there may be the following situation or event: it is expected that the flying capacitor C coupled to the M-level converter unit 702 Fx The voltage detector C Fx_H / L The state signal causes the M-level switch state selector 718 to select a particular configuration of the power switch settings, such as when a severe mid-cycle imbalance occurs. In some embodiments, it may be useful to include a timing function that forces the M-level switch state selector 718 to periodically re-evaluate the best version of the state, for example, to avoid being "stuck" at one level for a long time, which may cause a charge imbalance.

[0099] In an implementation utilizing the teachings set forth in the above-referenced patent application entitled “Controlling Charge-Balance and Transients in a Multi-Level Power Converter,” M-level controller 714 implements a control method for M-level converter unit 702 that selects L each time. X The voltage level at the node is selected so that the flying capacitor C Fx The multi-level converter circuit thus freely selects different switching states or L in each switching cycle. X voltage level without keeping track of any previous switch state or sequence of switch states.

[0100] Figure 7 One significant benefit of the control circuitry shown in is that it enables the generation of voltages in boundary regions between voltage levels that represent output voltages that are not obtainable with conventional multi-level DC to DC converter circuits.

[0101] In an alternative unregulated charge pump implementation, the feedback controller 706 and the voltage level selector 716 may be omitted and the clock signal CLK may instead be applied to an M-level switch state selector 718. The M-level switch state selector 718 will generate a pattern of switch state settings that periodically turns the flying capacitor C Fx Charge balancing is performed regardless of which switch state or states were used in the past (rather than cycling through a predefined sequence of states). This ensures that if V IN Changes or abnormal events occur, the system is usually always flying capacitor C Fx Seek charge balance.

[0102] In some embodiments, the M-level switch state selector 718 can take into account the current I flowing through the inductor L by way of an optional current measurement input 720. L , which can be achieved in a conventional manner.

[0103] Although Figure 7 A specific embodiment of control circuitry for an M-level converter cell modified in accordance with the present invention is shown, but it will be appreciated that other control circuits may be adapted or designed to provide appropriate switching signals for switches within the converter cell.

[0104] Circuit Implementation

[0105] In power converters, especially multi-level power converters, power switches can be implemented with FETs, especially MOSFETs. For each power FET, a driver circuit is usually required. In addition, for some power FETs, a level shifter may be required to convert a low voltage logic on / off signal referenced to ground from an analog or digital controller to a signal with the same voltage swing but referenced to the source voltage of the power FET, which drives the power FET to charge or discharge the gate of the power FET, thereby controlling the on or blocking state of the power FET. In some applications, the functions of the level shifter and the driver circuit can be incorporated into one circuit.

[0106] Circuits and devices according to the present invention can be used alone or in combination with other components, circuits and devices. Embodiments of the present invention can be manufactured as integrated circuits (ICs), which can be packaged in IC packages and / or modules to facilitate processing, manufacturing and / or improve performance. In particular, IC embodiments of the present invention are generally used in such ICs where one or more ICs are combined with other circuit components or blocks (e.g., filters, amplifiers, passive components and possible additional ICs) into a packaged module. Then, ICs and / or modules are generally combined with other components, usually on a printed circuit board, to form a part of a final product such as a cellular phone, a laptop computer or an electronic tablet, or to form a higher-level module that can be used in various products such as vehicles, test equipment, medical devices, etc. Through various configurations of modules and components, such ICs generally enable communication modes that are usually wireless communications.

[0107] As an example of further integration of embodiments of the present invention with other components, Figure 8 800, which may be, for example, a printed circuit board or a chip module substrate (e.g., a thin film assembly). In the example shown, substrate 800 includes a plurality of ICs 802a to 802d having terminal pads 804 that are interconnected by conductive vias and / or traces on and / or within substrate 800 or on an opposing (back) surface of substrate 800 (to avoid clutter, surface conductive traces are not shown and not all terminal pads are labeled). For example, ICs 802a to 802d may include signal switches, active filters, amplifiers (including one or more LNAs), and other circuitry. For example, IC 802b may include one or more instances of a power converter circuit including Figure 4A , Figure 4B , Figure 5 and / or an implementation of the circuit shown in FIG. 6 .

[0108] The substrate 800 may also include one or more passive devices 806 embedded in, formed on, and / or secured to the substrate 800. Although shown as generally rectangular, the passive devices 806 may be, for example, filters, capacitors, inductors, transmission lines, resistors, planar antenna elements, transducers (including, for example, MEMS-based transducers such as accelerometers, gyroscopes, microphones, pressure sensors, etc.), batteries, etc., interconnected with other passive devices 806 and / or individual ICs 802a to 802d via conductive traces on or in the substrate 800. The front or back surface of the substrate 800 may be used as a location to form other structures.

[0109] Additional Control and Operational Considerations

[0110] It may be desirable to provide additional control and operating circuitry (or one or more shutdown procedures) that enables reliable and efficient operation of a power converter utilizing a multilevel converter unit designed according to the present disclosure. For example, in a step-down power converter, the output voltage of the converter unit is less than the input voltage of the converter unit. Shutting down or disabling (e.g., due to a fault event, such as a short circuit) a converter unit that has a built-in inductor connected to the output when the output load current is non-zero generally requires some means of releasing the inductor current. In some embodiments, a bypass switch may be connected in parallel to the built-in inductor connected to the output of the converter unit, and the bypass switch may be controlled to be disconnected during normal operation and closed when the converter unit is shut down or in the event of a fault. Ideally, in order to prevent transient ringing and provide a safe discharge of the inductor current, the bypass switch may be closed before disabling the converter unit switching. In an alternative embodiment where a MOSFET is used for the main switch of the converter, an inherent body diode connected between the body and drain terminal of each MOSFET may also release the inductor current. Details of these solutions and alternative shutdown solutions are taught in U.S. Patent No. 10,686,367, entitled “Apparatus and Method for Efficient Shutdown of Adiabatic Charge Pumps,” which issued on June 16, 2020, is assigned to the assignee of the present invention and is incorporated by reference.

[0111] Another consideration when combining converter units in parallel is to control multiple parallel power converters to avoid inrush current (e.g., during a soft start period of the power converter) and / or switch overstress when all power converters are not fully operational, such as during startup or when a fault condition occurs. Conditional control can be achieved by monitoring voltage and / or current using node state detectors coupled to selected nodes within the parallel connected power converters. In some embodiments, such node state detectors can be configured to work in parallel with output state detectors that measure the output voltage of the associated power converter during startup. The node state detector ensures that the voltage across important components (e.g., flying capacitors and / or switches) within the converter unit of the power converter is within a desired range before achieving full power steady-state operation of the parallel power converter, otherwise full power steady-state operation will be prevented. The node state detector can be coupled to a master controller that uses one or more common control signals to control one or more of the parallel power converters. In the advancement of the master controller configuration, the parallel power converters can each report a power good signal (Pgood) when preparing to leave the startup phase for full power steady-state operation. The master controller may substantially "AND" all such Pgood signals, and possibly along with one or more status signals from other circuits, such that the master controller does not enable full power steady-state operation of any parallel power converter unless all parallel power converters are ready for that state. In essence, the Pgood signals from each parallel power converter are all tied together such that the parallel power converters may not transition out of the startup phase until all Pgood signals indicate that they are ready to transition to stable operation. In addition, if the Pgood signal changes due to a fault condition in one or more of the parallel power converters, the parallel power converters may transition from steady-state operation to automatic restart or shutdown operation. Details of these solutions and alternative shutdown solutions are taught in U.S. Patent No. 10,992,226, entitled "Startup Detection for Parallel Power Converters," published on April 27, 2021, which has been assigned to the assignee of the present invention, and the contents of which are incorporated by reference.

[0112] Another consideration in operating a multi-level converter unit is to obtain (i.e., pre-charge) and maintain substantially fully proportionally balanced flying capacitor voltages so that all switches are subject to similar voltage stresses, because unbalanced flying capacitors may cause switches (particularly FET switches) to break down due to exposure to high voltages. One solution to both pre-charging capacitor voltages and operating balance of capacitor voltages in a multi-level DC to DC converter circuit is to provide parallel "shadow" circuits that conditionally couple a flying capacitor to a voltage source or other circuit to pre-charge the capacitor, or conditionally couple two or more flying capacitors together to transfer charge from a higher voltage capacitor to a lower voltage capacitor, or conditionally couple a flying capacitor to a voltage sink to discharge the capacitor, all under the control of real-time capacitor voltage measurements. Each parallel "shadow" circuit may include a switch and a resistor coupled in parallel with a main switch that is part of a multi-level converter unit (in some cases, one switch-resistor pair may span two series-connected switches). This particular solution for precharging and / or balancing the charge on the flying capacitor is very fast, provides a slow precharging of the flying capacitor during the precharging period, protects the switches from inrush current, and provides a stable voltage for the converter cell switches. Details of this solution and alternative precharging and charge balancing solutions are taught in U.S. Patent No. 10,720,843, entitled “Multi-Level DC-DC Converter with Lossy Voltage Balancing,” issued on July 21, 2020, which is assigned to the assignee of the present invention and is incorporated by reference.

[0113] Another solution to balancing capacitor voltages in a multi-level DC-to-DC converter circuit is to provide a lossless voltage balancing solution in which disordered state transitions of the multi-level DC-to-DC converter units are allowed to occur during normal operation. The net effect of the disordered state transitions is to increase or decrease the voltage across a particular flying capacitor, thereby preventing voltage overstress on the main switch of the DC-to-DC converter. In some embodiments, the overall sequence of state transitions is restricted to reduce or avoid transition state switching, thereby allowing each capacitor the opportunity to have its voltage manipulated as needed, rather than allowing voltage balancing of one capacitor and then another capacitor. Details of this solution and alternative charge balancing solutions are taught in U.S. Patent No. 10,770,974, entitled “Multi-Level DC-DC Converter with Lossless Voltage Balancing,” published on September 8, 2020, which is assigned to the assignee of the present invention and the contents of which are incorporated by reference.

[0114] An additional consideration of some embodiments is to implement the operation of the multi-level converter unit so that a voltage can be generated in the boundary region between the voltage levels. "Boundary region" means an output voltage that cannot be obtained by a conventional multi-level DC to DC converter circuit. In order to generate an output voltage in the boundary region, some embodiments substantially alternate (switch) between adjacent (or even nearby) regions by setting the state of the converter unit switch in the boundary region transition mode. For example, a 3-level DC to DC converter circuit can operate in region 1 for a selected time and in adjacent region 2 for a selected time. Therefore, region 1 and region 2 are considered as a single "super region". More generally, in some cases, it may be useful to create a super region using non-adjacent regions or using more than two regions (adjacent and / or non-adjacent). The details of this solution are taught in U.S. Patent No. 10,720,842, entitled "Multi-Level DC-DC Converter with Boundary Transition Control", published on July 21, 2020, which is assigned to the assignee of the present invention and its contents are incorporated by reference.

[0115] Yet another consideration of some embodiments is to protect the main power switches and other components within the power converter from stress conditions, particularly from voltages exceeding the breakdown voltage of such switches, particularly FET switches. A method for protecting a multi-level power converter uses at least one high voltage FET switch while allowing all or most other main power switches to be low voltage FET switches.

[0116] It should be clear that the multi-level power converter embodiments described in this disclosure may be synergistically combined with the teachings of one or more of the additional control and operating circuits and methods described in this section.

[0117] General Benefits and Advantages of Multilevel Power Converters

[0118] Embodiments of the present invention improve power density and / or power efficiency of combined circuits and circuit modules or blocks. As will be appreciated by those skilled in the art, utilizing embodiments of the present invention beneficially impacts system architecture in key ways, including lower power and / or longer battery life. Thus, the present invention specifically includes system-level embodiments that are creatively implemented through inclusion in large system designs and applications.

[0119] More specifically, multilevel power converters provide or achieve many benefits and advantages, including:

[0120] - Adaptability to applications where the input and / or output voltages may have a wide dynamic range (e.g., different battery input voltage levels, different output voltages);

[0121] - Improved efficiency of the operating time of devices running on portable electrical energy sources (batteries, generators or fuel cells using liquid or gaseous fuels, solar cells, etc.);

[0122] - Efficiency improvement where efficiency is important for thermal management, especially protecting other components (e.g., display, nearby ICs) from overheating;

[0123] -Enable design optimization of power efficiency, power density, and form factor of power converters - for example, smaller size multi-level power converters may allow the power converter to be placed closer to the load, thereby improving efficiency and / or reducing the overall bill of materials;

[0124] -The ability to exploit the performance of smaller, low-voltage transistors;

[0125] - Adaptability to applications where the power source can vary widely, such as batteries, other power converters, generators, or fuel cells using liquid or gaseous fuels, solar cells, line voltage (AC), and DC voltage sources (e.g., USB, USB-C, Power over Ethernet, etc.);

[0126] - Adaptability to applications where the loads can vary widely, such as general ICs (including microprocessors and memory ICs), motors and actuators, transducers, sensors, and displays (e.g., all types of LCDs and LEDs);

[0127] - Capability to be implemented in multiple IC technologies (e.g., MOSFET, GaN, GaAs, and bulk silicon) and packaging technologies (e.g., flip chip, ball grid array, wafer-level chip packaging, wide fan-out packaging, and embedded packaging).

[0128] The advantages and benefits of multi-level power converters enable use in a wide range of applications. For example, applications of multi-level power converters include portable and mobile computing and / or communication products and components (e.g., notebook computers, ultrabook computers, tablet devices and mobile phones), displays (e.g., LCD, LED), radio-based devices and systems (e.g., cellular systems, WiFi, Bluetooth, Zigbee, Z-Wave and GPS-based devices), wired network devices and systems, data centers (e.g., for battery backup systems and / or power conversion for processing systems and / or electronic / optical networking systems), Internet of Things (IOT) devices (e.g., smart switches and lights, security sensors and security cameras), home appliances and electronic products (e.g., set-top boxes, battery-powered vacuum cleaners, appliances with built-in radio transceivers, such as washing machines, dryers and refrigerators), AC / DC power converters, all types of electric vehicles (e.g., for drivetrains, control systems and / or infotainment systems), and other devices and systems that use portable power generation sources and / or require power conversion.

[0129] Radio system uses include wireless RF systems (including base stations, relay stations, and handheld transceivers) using various technologies and protocols, including various types of orthogonal frequency division multiplexing ("OFDM"), quadrature amplitude modulation ("QAM"), code division multiple access ("CDMA"), time division multiple access ("TDMA"), wideband code division multiple access ("W-CDMA"), Global System for Mobile communications ("GSM"), Long Term Evolution ("LTE"), 5G and WiFi (e.g., 802.11a, 802.11b, 802.11g, 802.11ac, 802.11ax), and other radio communication standards and protocols.

[0130] method

[0131] Another aspect of the present invention includes a method for transferring charge among multiple bootstrap capacitors of a multi-level power converter. For example, Fig. 9900 is a process flow diagram illustrating a method for transferring charge among a plurality of bootstrap capacitors of a multilevel power converter having a plurality of power switches, each bootstrap capacitor having a top plate and a bottom plate, wherein the top plates of each adjacent pair of bootstrap capacitors are coupled through respective diodes within a diode stack. The method includes: providing a trigger signal after an associated one of the plurality of power switches is switched to an on state and thereby connecting the bottom plates of the adjacent pairs of bootstrap capacitors (block 902); and in response to receiving the trigger signal, initiating a bypass function with respect to the respective diodes coupling the adjacent pairs of bootstrap capacitors (block 904).

[0132] Additional aspects of the above method may include one or more of the following: automatically terminating the bypass function after the bottom plates of the bootstrap capacitors of adjacent pairs are disconnected; automatically terminating the bypass after an associated one of the multiple power switches is switched to a non-conducting state and thereby disconnects the bottom plates of the bootstrap capacitors of the adjacent pairs; and synchronously terminating the bypass function before an associated one of the multiple power switches is switched to a non-conducting state and thereby disconnects the bottom plates of the bootstrap capacitors of the adjacent pairs.

[0133] Manufacturing Techniques and Options

[0134] In various embodiments of multi-level power converters, it may be beneficial to use a specific type of capacitor, especially a flying capacitor. For example, such a capacitor is generally useful with low equivalent series resistance (ESR), low DC bias degradation, high capacitance and small volume. Low ESR is particularly important for multi-level power converters that include additional switches and flying capacitors to increase the number of voltage levels. A specific capacitor should be selected after considering the specifications of power level, efficiency, size, etc. Various types of capacitor technologies can be used, including ceramics (including multilayer ceramic capacitors), electrolytic capacitors, film capacitors (including power film capacitors) and IC-based capacitors. The capacitor dielectric can vary according to the needs of a specific application and can include paraelectric dielectrics, such as silicon dioxide (SiO2), hafnium dioxide (HFO2) or aluminum oxide Al2O3. In addition, the multi-level power converter design can advantageously utilize inherent parasitic capacitance (e.g., inherent to power FETs) in combination with or instead of the designed capacitor to reduce circuit size and / or improve circuit performance. The selection of capacitors for a multilevel power converter may also consider factors such as capacitor component variations, reduced effective capacitance with DC bias, and ceramic capacitor temperature coefficients (minimum and maximum temperature operating limits, and capacitance variation with temperature).

[0135] Similarly, in various embodiments of a multi-level power converter, it may be beneficial to use a particular type of inductor. For example, it is generally useful for an inductor to have low DC equivalent resistance, high inductance, and small size.

[0136] The controller for controlling startup and operation of the multilevel power converter may be implemented as a microprocessor, a microcontroller, a digital signal processor (DSP), register transfer level (RTL) circuitry, and / or combinatorial logic.

[0137] As used in this disclosure, the term "MOSFET" includes any field effect transistor (FET) having an insulated gate whose voltage determines the conductivity of the transistor and includes insulated gates having metal or metalloid, insulator and / or semiconductor structures. The terms "metal" or "metalloid" include at least one conductive material (e.g., aluminum, copper or other metal or heavily doped polysilicon, graphene or other electrical conductors), "insulator" includes at least one insulating material (e.g., silicon oxide or other dielectric material), and "semiconductor" includes at least one semiconductor material.

[0138] As used in this disclosure, the term "radio frequency" (RF) refers to an oscillation rate in the range of about 3 kHz to about 300 GHz. The term also includes frequencies used in wireless communication systems. RF frequencies can be the frequency of electromagnetic waves or the frequency of an alternating voltage or current in an electrical circuit.

[0139] With respect to the drawings cited in this disclosure, the dimensions of the various elements are not drawn to scale; some dimensions may be significantly exaggerated vertically and / or horizontally for clarity or emphasis. In addition, references to orientations and directions (e.g., "top," "bottom," "above," "below," "lateral," "vertical," "horizontal," etc.) are relative to the example drawings and are not necessarily absolute orientations or directions.

[0140] Various embodiments of the present invention can be implemented to meet various specifications. Unless otherwise specified above, the selection of suitable component values ​​is a matter of design choice. Various embodiments of the present invention can be implemented in any suitable integrated circuit (IC) technology (including but not limited to MOSFET structure) or in a hybrid circuit form or a discrete circuit form. Any suitable substrate and process (including but not limited to standard bulk silicon, high resistance body CMOS, silicon on insulator (SOI) and silicon on sapphire (SOS)) can be used to manufacture integrated circuit embodiments. Unless otherwise specified above, embodiments of the present invention can be implemented in other transistor technologies such as bipolar, BiCMOS, LDMOS, BCD, GaAs HBT, GaN HEMT, GaAs pHEMT and MESFET technology. However, embodiments of the present invention are particularly useful when using SOI or SOS-based process manufacturing or when using processes with similar characteristics. The manufacture of SOI or SOS processes in CMOS enables circuits to have low power consumption, the ability to withstand high power signals during operation due to FET stacking, good linearity, and high frequency operation (i.e., up to and exceeding 300GHz radio frequency). Since parasitic capacitance and inductance can usually be kept low (or minimal, or uniform across all cells, thereby allowing compensation for parasitic capacitance) by careful design, a monolithic IC implementation is particularly useful.

[0141] Depending on the particular specification and / or implementation technology (e.g., NMOS, PMOS, or CMOS and enhancement mode or depletion mode transistor devices), voltage levels may be adjusted and / or voltage and / or logic signal polarity may be inverted. Component voltage, current, and power handling capabilities may be adjusted as needed, for example, by adjusting device size, "stacking" components (particularly FETs) in series to withstand greater voltages, and / or using multiple components in parallel to handle greater currents. Additional circuit components may be added to enhance the capabilities of the disclosed circuits and / or to provide additional functionality without significantly changing the functionality of the disclosed circuits.

[0142] in conclusion

[0143] A number of embodiments of the present invention have been described. It should be understood that various modifications may be made without departing from the spirit and scope of the present invention. For example, some of the steps described above may be order-independent and therefore may be performed in an order different from that described. In addition, some of the steps described above may be optional. The various activities described with respect to the methods identified above may be performed in a repetitive, serial and / or parallel manner.

[0144] It should be understood that the foregoing description is intended to illustrate rather than limit the scope of the invention, which is defined by the scope of the appended claims, and other embodiments are also within the scope of the claims. In particular, the scope of the invention includes any and all feasible combinations of one or more of the processes, machines, manufactures, or compositions of matter set forth in the appended claims. (Note that parenthetical markings used for claim elements are for convenience of reference to such elements and do not, by themselves, indicate a specific required order or enumeration of elements; furthermore, such markings may be reused in dependent claims as references to additional elements without being considered as starting a conflicting marking sequence).

Claims

1. A charging circuit configured to provide charge transfer among a plurality of bootstrap capacitors of a power converter having a plurality of power switches, each bootstrap capacitor having a top plate and a bottom plate, wherein: The top plates of the bootstrap capacitors of each adjacent pair are coupled via corresponding diodes within the diode stack, the charging circuit comprises two or more trigger bypass circuits, each trigger bypass circuit is coupled to a corresponding diode within the diode stack, and each trigger bypass circuit is configured to: initiate a bypass function with respect to the corresponding diode in response to receiving an associated trigger signal, and provide a trigger signal after an associated one of the plurality of power switches is switched to a conducting state and thereby connects the bottom plates of the bootstrap capacitors of the adjacent pair.

2. The invention according to claim 1, wherein: The diodes within the diode stack comprise explicit circuit components.

3. The invention according to claim 1, wherein: The diodes within the diode stack include intrinsic diodes of PFET switches within the trigger bypass circuit.

4. The invention according to claim 1, wherein: After the bottom plates of the bootstrap capacitors of the adjacent pairs are disconnected, each triggered bypass circuit automatically terminates the bypass function after a sufficient voltage difference is reached between the bootstrap capacitors of the adjacent pairs.

5. The invention according to claim 1, wherein: Each triggered bypass circuit automatically terminates the bypass function after an associated one of the plurality of power switches is switched to a non-conducting state thereby disconnecting the bottom plates of the adjacent pair of bootstrap capacitors.

6. The invention according to claim 1, wherein: Each triggered bypass circuit synchronously terminates a bypass function before an associated one of the plurality of power switches is switched to a non-conducting state and thereby disconnects the bottom plates of the adjacent pair of bootstrap capacitors.

7. The invention according to claim 1, wherein: Each trigger bypass circuit includes: (a) a first PFET having a conductive channel coupled between a cathode and an anode of a corresponding diode and a gate coupled to an associated trigger signal; and (b) a second PFET having a conductive channel coupled between a cathode of a corresponding diode and a gate of the first PFET and a gate coupled to an anode of the corresponding diode.

8. The invention according to claim 1, wherein: Each trigger bypass circuit includes: (a) a set-reset latch having a first input coupled to an associated trigger signal and a second input coupled to an associated control signal; and (b) A PFET having a conductive channel coupled between a cathode and an anode of a corresponding diode and a gate coupled to an output of the set-reset latch.

9. The invention according to claim 8, wherein: The associated control signal is synchronized with a gate control signal for an associated one of the plurality of power switches, but is earlier in phase.

10. The invention according to claim 8, wherein: The trigger signal causes the PFET to initiate a bypass function, and the associated control signal causes the PFET to terminate the bypass function.

11. The invention according to claim 1, wherein: At least one trigger bypass circuit comprises: (a) an inverter having an input terminal coupled to a drain of an associated one of the plurality of power switches, and an output terminal; (b) an NFET having a gate coupled to the output terminal of the inverter and a conductive channel coupled between a first potential and an adjacent trigger bypass circuit, wherein the NFET is configured to provide a trigger signal to the adjacent trigger bypass circuit after an associated one of the plurality of power switches is switched to an on state.

12. The invention according to claim 1 further includes a bypass circuit, which is coupled to the corresponding diode within the diode stack and is configured to: initiate a bypass function with respect to the corresponding diode in response to receiving an associated trigger signal from an adjacent trigger bypass circuit.

13. The invention according to claim 12, wherein: The diodes within the diode stack include intrinsic diodes of PFET switches within the bypass circuit.

14. The invention according to claim 12, wherein: The bypass circuit comprises: (a) a first PFET having a conductive channel coupled between a cathode and an anode of a corresponding diode and a gate coupled to a trigger signal from an adjacent trigger bypass circuit; and (b) a second PFET having a conductive channel coupled between a cathode of a corresponding diode and a gate of the first PFET and a gate coupled to an anode of the corresponding diode.

15. The invention according to claim 12, wherein: The bypass circuit comprises: (a) a set-reset latch having a first input coupled to an associated trigger signal and a second input coupled to an associated control signal; and (b) A PFET having a conductive channel coupled between a cathode and an anode of a corresponding diode and a gate coupled to an output of the set-reset latch.

16. The invention according to claim 15, wherein: The associated control signal is synchronized with a gate control signal for an associated one of the plurality of power switches, but is earlier in phase.

17. The invention according to claim 15, wherein: The trigger signal causes the PFET to initiate a bypass function, and the associated control signal causes the PFET to terminate the bypass function.

18. The invention according to claim 1 further includes a trigger circuit, which is configured to provide a trigger signal to an adjacent trigger bypass circuit after an associated one of the multiple power switches is switched to an on state and thereby connects the bottom plates of the adjacent pairs of bootstrap capacitors.

19. The invention according to claim 18, wherein: The trigger circuit comprises: (a) an inverter having an input terminal coupled to a drain of an associated one of the plurality of power switches, and an output terminal; (b) an NFET having a gate coupled to the output terminal of the inverter and a conductive channel coupled between a first potential and an adjacent trigger bypass circuit, wherein the NFET is configured to provide a trigger signal to the adjacent trigger bypass circuit after an associated one of the plurality of power switches is switched to an on state.

20. The invention according to claim 1, wherein: The power converter is a multi-level power converter.

21. The invention according to claim 1, wherein: The power converter is a charge pump.

22. The invention according to claim 1, wherein: The power converter is a series capacitor buck converter.

23. A charging circuit configured to provide charge transfer among a plurality of bootstrap capacitors of a power converter having a plurality of power switches, each bootstrap capacitor having a top plate and a bottom plate, wherein: The top plates of the bootstrap capacitors of each adjacent pair are coupled through respective diodes within the diode stack, the charging circuit comprising: (a) a plurality of supplementary circuit blocks, the plurality of supplementary circuit blocks comprising: (1) a trigger block configured to: provide a trigger signal after an associated one of the plurality of power switches is switched to an on state and thereby connects the bottom plates of the adjacent pair of bootstrap capacitors; (2) two or more trigger bypass blocks, each trigger bypass block coupled to a corresponding diode within the diode stack and configured to: initiate a bypass function with respect to the corresponding diode in response to receiving an associated trigger signal from an adjacent trigger block or an adjacent trigger bypass block, and provide the trigger signal after an associated one of the plurality of power switches is switched to a conducting state and thereby connects the bottom plates of the adjacent pair of bootstrap capacitors; and (3) A bypass block coupled to a corresponding diode in the diode stack and configured to activate a bypass function with respect to the corresponding diode in response to receiving an associated trigger signal from an adjacent trigger bypass block.

24. The invention according to claim 23, wherein: The diodes within the diode stack comprise explicit circuit components.

25. The invention according to claim 23, wherein: The diodes within the diode stack include the trigger bypass block and intrinsic diodes of the PFET switches within the bypass block.

26. The invention according to claim 23, wherein: After the bottom plates of the bootstrap capacitors of adjacent pairs are disconnected, each triggered bypass block automatically terminates the bypass function after a sufficient voltage difference is reached between the bootstrap capacitors of the adjacent pairs.

27. The invention according to claim 23, wherein: Each triggered bypass block automatically terminates the bypass function after an associated one of the plurality of power switches is switched to a non-conducting state and thereby disconnects the bottom plates of the adjacent pair of bootstrap capacitors.

28. The invention according to claim 23, wherein: Each triggered bypass block synchronously terminates a bypass function before an associated one of the plurality of power switches is switched to a non-conducting state and thereby disconnects the bottom plates of the adjacent pair of bootstrap capacitors.

29. The invention according to claim 23, wherein: Each trigger bypass block consists of: (a) a first PFET having a conductive channel coupled between a cathode and an anode of a corresponding diode and a gate coupled to an associated trigger signal; and (b) a second PFET having a conductive channel coupled between a cathode of a corresponding diode and a gate of the first PFET and a gate coupled to an anode of the corresponding diode.

30. The invention according to claim 23, wherein: Each trigger bypass block consists of: (a) a set-reset latch having a first input coupled to an associated trigger signal and a second input coupled to an associated control signal; and (b) A PFET having a conductive channel coupled between a cathode and an anode of a corresponding diode and a gate coupled to an output of the set-reset latch.

31. The invention according to claim 30, wherein: The associated control signal is synchronized with a gate control signal for an associated one of the plurality of power switches, but is earlier in phase.

32. The invention according to claim 30, wherein: The trigger signal causes the PFET to initiate a bypass function, and the associated control signal causes the PFET to terminate the bypass function.

33. The invention according to claim 23, wherein: Each trigger bypass block consists of: (a) an inverter having an input terminal coupled to a drain of an associated one of the plurality of power switches, and an output terminal; (b) an NFET having a gate coupled to the output terminal of the inverter and a conductive channel coupled between a first potential and an adjacent trigger bypass block or an adjacent bypass block, wherein the NFET is configured to provide a trigger signal to the adjacent trigger bypass block or the adjacent bypass block after an associated one of the plurality of power switches is switched to an on state.

34. The invention according to claim 23, wherein: The bypass block comprises: (a) a first PFET having a conductive channel coupled between a cathode and an anode of a corresponding diode and a gate coupled to a trigger signal from an adjacent trigger bypass block; and (b) a second PFET having a conductive channel coupled between a cathode of a corresponding diode and a gate of the first PFET and a gate coupled to an anode of the corresponding diode.

35. The invention of claim 23, wherein: The bypass block comprises: (a) a set-reset latch having a first input coupled to an associated trigger signal and a second input coupled to an associated control signal; and (b) A PFET having a conductive channel coupled between a cathode and an anode of a corresponding diode and a gate coupled to an output of the set-reset latch.

36. The invention according to claim 35, wherein: The associated control signal is synchronized with a gate control signal for an associated one of the plurality of power switches, but is earlier in phase.

37. The invention according to claim 35, wherein: The trigger signal causes the PFET to initiate a bypass function, and the associated control signal causes the PFET to terminate the bypass function.

38. The invention of claim 23, wherein: The trigger block comprises: (a) an inverter having an input terminal coupled to a drain of an associated one of the plurality of power switches, and an output terminal; (b) an NFET having a gate coupled to the output terminal of the inverter and a conductive channel coupled between the first potential and an adjacent trigger bypass block, wherein the NFET is configured to provide a trigger signal to the adjacent trigger bypass block after an associated one of the plurality of power switches is switched to an on state.

39. The invention of claim 23, wherein: The power converter is a multi-level power converter.

40. The invention of claim 23, wherein: The power converter is a charge pump.

41. The invention according to claim 23, wherein: The power converter is a series capacitor buck converter.

42. The invention of claim 23, further comprising a multilevel power converter, in which the plurality of power switches comprise a plurality of NFETs coupled in series and configured to be coupled between an input voltage and a reference potential, wherein: The capacitor is coupled between a first pair of NFETs in the plurality of NFETs and a second pair of NFETs in the plurality of NFETs.

43. The invention according to claim 42, wherein: Each of the plurality of NFETs includes a control gate, and further includes a plurality of gate drivers, each gate driver coupled to the control gate of a corresponding one of the plurality of NFETs.

44. A method for transferring charge among a plurality of bootstrap capacitors of a power converter having a plurality of power switches, each bootstrap capacitor having a top plate and a bottom plate, wherein: The top plates of each adjacent pair of bootstrap capacitors are coupled through respective diodes within a diode stack, the method comprising: (a) providing a trigger signal after an associated one of the plurality of power switches is switched to an on state and thereby connects the bottom plates of the adjacent pair of bootstrap capacitors; and (b) in response to receiving the trigger signal, enabling a bypass function with respect to respective diodes coupling the bootstrap capacitors of adjacent pairs.

45. The method of claim 44, further comprising: After the bottom plates of the bootstrap capacitors of the adjacent pair are disconnected, the bypass function is automatically terminated.

46. ​​The method of claim 44, further comprising: The bypassing is automatically terminated after an associated one of the plurality of power switches is switched to a non-conducting state and thereby disconnects the bottom plates of the adjacent pair of bootstrap capacitors.

47. The method of claim 44, further comprising: The bypass function is synchronously terminated before an associated one of the plurality of power switches is switched to a non-conducting state and thereby disconnects the bottom plates of the bootstrap capacitors of the adjacent pair.

48. The method of claim 44, wherein: The power converter is a multi-level power converter.

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