Graded superlattice structure for gate all-around devices

Abstract

Silicon germanium (SiGe) / silicon-containing superlattice structures and methods of forming the same are provided. Various embodiments utilize SiGe layers in SiGe / Si superlattice structures that include different concentrations of germanium throughout the layers to achieve reduced dislocation or dislocation-free superlattices. For example, in some embodiments, for each SiGe layer, there is a core SiGe film having a low Ge content and two thinner SiGe layers or cladding layers on opposite sides of the core SiGe film, where each SiGe cladding layer has a Ge content higher than that of the core SiGe film. Various embodiments provide a SiGe layer with a germanium depth profile, enabling strained SiGe superlattice deposition on a Si {110} substrate.

Description

Technical Field

[0001] The present disclosure relates to transistor devices and methods for manufacturing transistor devices. More particularly, the present disclosure relates to superlattice structures that can be used in gate-all-around (GAA) transistor devices and methods for manufacturing the same. Background Art

[0002] The electronics industry is experiencing a growing demand for smaller and faster electronic devices that are simultaneously capable of supporting a greater number of increasingly complex and sophisticated functions. As a result, there is a continuing trend in the semiconductor industry to manufacture low-cost, high-performance, and low-power integrated circuits (ICs). To date, these goals have been achieved in large part by scaling down semiconductor IC sizes (e.g., minimum feature sizes) and thereby increasing production efficiency and reducing associated costs. However, such miniaturization has introduced greater complexity into the semiconductor manufacturing process. Therefore, achieving continued advancements in semiconductor ICs and devices requires similar advancements in semiconductor manufacturing processes and technologies.

[0003] Recently, multi-gate devices have been introduced to improve gate control by increasing gate-channel coupling, reducing off-state current, and reducing short-channel effect (SCE). One such multi-gate device that has been introduced is the gate-all around transistor (GAA). In a GAA device, all side surfaces of the channel region are surrounded by gate electrodes, which allows for more complete depletion in the channel region and results in less short-channel effect due to steeper subthreshold current swing and smaller drain induced barrier lowering (DIBL).

[0004] As transistor dimensions scale to smaller technology nodes, further improvements in GAA design and manufacturing are needed. Summary of the invention

[0005] The present disclosure relates to transistor devices and methods for manufacturing transistor devices. More particularly, the present disclosure relates to superlattice structures that can be used in GAA transistor devices and methods for manufacturing the same.

[0006] In one aspect, a device structure is provided. The device structure includes a substrate. The device structure further includes a superlattice structure formed on the substrate. The superlattice structure includes one or more superlattice stacks. The one or more superlattice stacks include a silicon material layer, a first silicon germanium cladding layer having a first germanium concentration and a first thickness, a silicon germanium core layer having a second germanium concentration and a second thickness, and a second silicon germanium cladding layer having a third germanium concentration and a third thickness. The silicon material layer, the first silicon germanium cladding layer, the silicon germanium core layer and the second silicon germanium cladding layer are arranged in a stacked arrangement. The silicon germanium core layer is located between the first silicon germanium cladding layer and the second silicon germanium cladding layer. The first germanium concentration and the third germanium concentration are greater than the second germanium concentration and the first thickness and the third thickness are less than the second thickness.

[0007] Embodiments may include one or more of the following. The surface of the first silicon germanium cladding layer contacts the surface of the substrate, and the surface of the second silicon germanium cladding layer contacts the surface of the silicon material layer. At least one of the first silicon germanium cladding layer, the silicon germanium core layer, and the second silicon germanium cladding layer further comprises carbon or boron. The first germanium concentration is in the range of about 10% to about 50%. The first germanium concentration is in the range of about 20% to about 50%. The first germanium concentration is in the range of about 20% to about 40%. The first germanium concentration is in the range of about 30% to about 40%. The first thickness and the third thickness are each independently in the range of about 1 nanometer to about 10 nanometers. The first thickness and the third thickness are each independently greater than 0 nanometers and less than or equal to 3 nanometers. The total thickness of the first thickness, the second thickness, and the third thickness is in the range of about 5 nanometers to about 20 nanometers. The total thickness of the first thickness, the second thickness, and the third thickness is about 10 nanometers or less. The thickness of the silicon material is in the range of about 5 nanometers to about 20 nanometers. The thickness of the silicon material layer is about 10 nanometers or less. The superlattice structure includes superlattice stacks between 2 and 5. The substrate comprises silicon {110}.

[0008] In another aspect, a method of forming a device structure is provided. The method includes forming a superlattice structure on a substrate. Forming the superlattice structure includes forming a first superlattice stack on the substrate. Forming the first superlattice stack includes forming a first silicon germanium structure using a first deposition process with a first precursor material and a second precursor material. Forming the first silicon germanium structure includes forming a first silicon germanium cladding layer having a first germanium concentration and a first thickness; forming a silicon germanium core layer on the first silicon germanium cladding layer, the silicon germanium core layer having a second germanium concentration and a second thickness; and forming a second silicon germanium cladding layer on the silicon germanium core layer, the second silicon germanium cladding layer having a third germanium concentration and a third thickness. Forming the first superlattice stack further includes forming a first silicon layer using a second deposition process with a third precursor material. The first germanium concentration and the third germanium concentration are greater than the second germanium concentration and the first thickness and the third thickness are less than the second thickness.

[0009] Embodiments may include one or more of the following. The first deposition process and the second deposition process are epitaxial deposition processes. The first deposition process and the second deposition process are performed in the same process chamber. The first deposition process is performed at a temperature in the range of about 400 degrees Celsius to about 850 degrees Celsius and a pressure in the range of about ultra-high vacuum (e.g., <1 Torr) to about atmospheric pressure. The first deposition process is performed at a temperature in the range of about 600 degrees Celsius to about 680 degrees Celsius and a pressure in the range of about 1 Torr to about 10 Torr. The first precursor material is dichlorosilane, the second precursor material is germane, and the third precursor material is disilane. The first deposition process is performed with a fourth precursor material, which is a carbon-containing precursor material. Forming a silicon germanium core layer on the first silicon germanium cladding layer includes reducing the flow rate of the second precursor material, and then increasing the flow rate of the second precursor material to produce a germanium concentration gradient in the silicon germanium core layer. The germanium concentration gradient decreases as the distance from the different materials increases.

[0010] In yet another aspect, a method of forming a device structure is provided. Forming the device structure includes forming a superlattice structure on a substrate. The substrate includes <110> The invention relates to a method for forming a superlattice structure of a silicon-germanium structure and a substrate comprising a first silicon-containing precursor material and a second germanium-containing precursor material. The method comprises forming a first silicon-germanium structure and a second silicon-germanium structure. The method comprises forming a first silicon-germanium cladding layer having a first thickness; forming a silicon-germanium core layer on the first silicon-germanium cladding layer, the silicon-germanium core layer having a second thickness; and forming a second silicon-germanium cladding layer on the silicon-germanium core layer. The second silicon-germanium cladding layer has a third thickness. The silicon-germanium stack has a germanium concentration gradient, and the germanium concentration gradient decreases with increasing distance from different materials. The method further comprises forming a first silicon layer on the first silicon-germanium structure using a second deposition process with a second silicon-containing precursor material. The first thickness and the third thickness are less than the second thickness.

[0011] Implementations may include one or more of the following. Forming the device structure further includes forming a gate-all-around transistor from the substrate and the superlattice structure.

[0012] In another aspect, a non-transitory computer-readable medium has stored thereon instructions that, when executed by a processor, cause a process to perform the operations of the apparatus and / or method described above.

[0013] BRIEF DESCRIPTION OF THE DRAWINGS

[0014] In order to be able to understand the above-mentioned features of the present disclosure in detail, the aspects briefly summarized above may be more particularly described with reference to the embodiments, some of which are illustrated in the accompanying drawings. However, it should be noted that the accompanying drawings illustrate only typical embodiments of the present disclosure and are therefore not to be considered as limiting the scope thereof, as the present disclosure may allow for other equally effective embodiments.

[0015] Figure 1 A flow chart of a method for fabricating a superlattice structure according to one or more embodiments of the present disclosure is illustrated.

[0016] FIG. 2A to FIG. 2B Illustrated are cross-sectional views of various stages in the fabrication of a superlattice structure according to one or more embodiments of the present disclosure.

[0017] Figure 3 Illustrated is a cross-sectional view of a portion of a superlattice structure according to one or more embodiments of the present disclosure.

[0018] FIG. 4A to FIG. 4B A graph of germanium concentration of a portion of a superlattice structure according to one or more embodiments of the present disclosure is shown.

[0019] Figure 5 A flow chart of a method for fabricating a transistor device structure incorporating a superlattice structure according to one or more embodiments of the present disclosure is illustrated.

[0020] 6A to 6F Illustrated are cross-sectional views of various stages in the fabrication of a transistor device structure incorporating a superlattice structure in accordance with one or more embodiments of the present disclosure.

[0021] To facilitate understanding, identical reference numerals have been used, where possible, to designate identical elements that are common to the figures. It is contemplated that elements and features of one embodiment may be beneficially incorporated in other embodiments without further recitation. DETAILED DESCRIPTION

[0022] Interface discontinuities and uniformity in heterostructures are key to controlling electronic and optical properties. It is also desirable to use materials with increased hole mobility to speed up devices.

[0023] The scaling down of silicon metal oxide semiconductor (MOS) devices has become a major challenge in the semiconductor industry. One problem with scaling conventional planar devices is the short channel effect, which begins to dominate device performance. One solution to this problem is to introduce multi-gate devices with a three-dimensional architecture, such as fin-based semiconductor devices or FINFETs and all-around gate (GAA) devices. Due to its three-dimensional architecture, whether the gate for FINFET is wrapped around a thin semiconductor fin, or the gate electrode for GAA is wrapped around all side surfaces of the channel region, improved gate control on the channel (and thereby reducing the short channel effect) can be achieved by using multiple gates.

[0024] However, the introduction of these multi-gate devices has led to additional challenges. For example, one problem is the insufficient mobility of carriers in the device. The development of high mobility semiconductors is expected to further improve the device performance of electronic devices. Therefore, it is necessary to develop multi-gate devices with improved hole mobility to achieve faster electronic devices. Crystalline silicon, such as Si{110} substrates, is a crystalline silicon substrate that provides improved hole mobility.

[0025] Superlattice structures can be used to make devices that form integrated circuits. These superlattice structures incorporate films, such as silicon films and silicon germanium films, that have different properties, depending on the specific application for which the deposited film is used. Film stress is a key property to control for certain applications. For example, in some applications, it is desirable to form a silicon germanium film with higher stress (compared to the underlying silicon substrate) to increase the electron mobility through the silicon. This improved electron mobility increases the speed of the device structure.

[0026] In other applications, it is desirable to form a silicon germanium film with lower stress (compared to the underlying silicon substrate) in order to minimize dislocation of the layer from, for example, the underlying substrate or to minimize the formation of dislocations in the substrate itself. Such dislocations are detrimental to device function because they can scatter electron / hole motion and / or enhance diffusion, which is undesirable.

[0027] Various embodiments provide improved SiGe / Si superlattice structures that can be used with, for example, silicon substrates that exhibit improved hole mobility (e.g., Si{110} substrates). A SiGe layer of a SiGe / Si superlattice structure can be formed using a chlorosilane gas source. These chlorosilane gas sources provide high growth rates and chlorine surface termination, which results in excellent interface steepness. Such interface steepness provides improved etch selectivity between SiGe and Si layers in the superlattice structure. Various embodiments also provide improved SiGe / Si superlattice structures that have lower stress (compared to an underlying silicon substrate) in order to minimize the formation of SiGe layers from, for example, dislocations of an underlying substrate or dislocations in the substrate itself. These dislocations can be detrimental to device function because they can scatter electron / hole motion and / or enhance diffusion, which is undesirable.

[0028] Various embodiments utilize SiGe layers in SiGe / Si superlattice structures that contain different concentrations of germanium throughout the layer to achieve reduced dislocations or dislocation-free superlattices. For example, in some embodiments, for each SiGe layer, there is a core SiGe film with a low Ge content and two thinner SiGe layers or cladding layers located on opposite sides of the core SiGe film, wherein each SiGe cladding layer has a Ge content higher than the core SiGe film. Various embodiments provide SiGe layers with a depth profile of germanium, thereby enabling strained SiGe superlattice deposition on Si{110} substrates. The SiGe layers can be doped with atoms having smaller atomic radii. For example, in some embodiments, the SiGe layers can be doped with carbon and / or boron to further reduce strain. Therefore, superlattice structures on crystalline silicon, such as Si / SiGe:C / Si{110} structures, are less prone to misfit dislocations than previous superlattice designs.

[0029] Figure 1 A flow chart of a method 100 for fabricating a superlattice structure according to one or more embodiments of the present disclosure is illustrated. The method 100 may be part of a multi-operation fabrication process for a semiconductor device, such as a GAA transistor.

[0030] At operation 110, a substrate is provided. In some embodiments, the substrate is a bulk semiconductor substrate. The term bulk semiconductor substrate refers to a substrate in which the entire substrate is composed of semiconductor material. Bulk semiconductor substrates include any suitable semiconductor material and / or semiconductor material combination for forming a semiconductor structure. For example, the semiconductor layer may include one or more materials, such as crystalline silicon (e.g., Si{100}, Si{110}, or Si{111}), silicon oxide, strained silicon, silicon germanium, doped or undoped polysilicon, doped or undoped silicon substrate, patterned or unpatterned substrate, doped silicon, germanium, gallium arsenide, or other suitable semiconductor materials. In some embodiments, the semiconductor material is silicon. In other embodiments, the semiconductor material is a doped material, such as n-doped silicon (n-Si) or p-doped silicon (p-Si). In a specific embodiment, the semiconductor material is Si{110}. Si{110} has an improved hole mobility, which can lead to an increase in the overall device speed.

[0031] At operation 120 of method 100, in some embodiments, the substrate is exposed to an optional pre-cleaning or surface treatment process. The substrate is surface treated to improve mobility and bias temperature instability (BTI). In some embodiments, the surface treatment includes rinsing the substrate in hydrogen (H 2 ) atmosphere. The annealing process can be any suitable annealing process known to the skilled person. In some embodiments, the annealing is a rapid thermal process (RTP) annealing. In some embodiments, the annealing process is performed at a temperature in the range of about 500 degrees Celsius to about 900 degrees Celsius, or in the range of about 600 degrees Celsius to about 900 degrees Celsius, or in the range of about 600 degrees Celsius to about 800 degrees Celsius. In some embodiments, the annealing process is performed at a pressure in the range of about 5 torr to about 20 torr.

[0032] At operation 130 of method 100, a superlattice structure is formed on a substrate. As used herein, the term superlattice generally refers to a stack of material layers that are closely lattice matched materials but are sufficiently different in composition that a selective removal process can be performed on the superlattice structure. More generally, the composition of the various material layers in the stack may be unique to one or more of the material layers in the stack. In one example, the superlattice structure includes one or more layers of a silicon-containing material (e.g., Si) and a silicon-germanium-containing material (e.g., SiGe). In some embodiments, the superlattice structure includes a first material layer and a second material layer. In some embodiments, the superlattice structure includes a first material layer, a second material layer, a third material layer, and a fourth material layer. In this embodiment, the second material layer, the third material layer, and the fourth material layer are formed of the same compound material, but may have different material properties.

[0033] Forming a superlattice structure at operation 130 includes forming a first material layer at operation 140 and forming a second material layer on the first material layer at operation 150. Operations 140 and 150 may be repeated until the superlattice structure reaches a desired thickness and / or number of layers. The first material layer and the second material layer may be alternately arranged in stacked pairs. The superlattice structure may include a plurality of first material layers and a corresponding plurality of second material layers, the plurality of first material layers and the plurality of second material layers being alternately arranged in a plurality of stacked pairs. In one embodiment, the plurality of first layers are formed of a silicon-containing material and the plurality of second layers are formed of at least a silicon-containing material and a germanium-containing material. Therefore, the first material layer and the second material layer are different materials. In some embodiments, the plurality of first layers and the corresponding plurality of second layers are lattice-matched materials having sufficient composition differences so that selective layer removal can be subsequently performed.

[0034] In some embodiments, the plurality of first layers include Group IV materials, such as silicon (e.g., Si). The plurality of second layers include Group IV materials, such as silicon and germanium (e.g., SiGe). In some embodiments, the concentration (atomic percentage) of germanium in the silicon germanium layer can be gradient. For example, the concentration of germanium can be highest near the interface (e.g., the top and bottom surfaces of the silicon germanium layer) and decrease from the interface toward the center of the silicon germanium layer.

[0035] In some embodiments, the silicon germanium layer has a silicon:germanium molar ratio between about 1:1 and about 5:1. In some embodiments, the silicon germanium layer has a germanium content in the range of about 10% to about 50%, or in the range of about 20% to about 50%, or in the range of about 20% to about 40%, or in the range of about 30% to about 40%. The silicon content may be in the range of about 50% to about 90%, or in the range of about 50% to about 80%, or in the range of about 60% to about 80%, or in the range of about 60% to about 70%. In other embodiments, the silicon germanium layer has a germanium content in the range of about 20% to about 90%, or in the range of about 50% to about 80%. The silicon content may be in the range of about 10% to about 80%, or in the range of about 20% to about 50%.

[0036] In some embodiments, the silicon germanium layer includes a plurality of layers of different concentrations. For example, in some embodiments, the silicon germanium layer includes a first silicon germanium layer or cladding layer having a first germanium concentration, a second silicon germanium layer or core layer having a second germanium concentration, and a third silicon germanium layer or cladding layer having a third germanium concentration. The second silicon germanium layer may be located or sandwiched between the first silicon germanium layer and the third silicon germanium layer. The first germanium concentration and the third germanium concentration may be greater than the second germanium concentration. In some embodiments, the first germanium concentration and the third germanium concentration are each independently greater than or equal to 10% germanium, such as in the range of about 10% to about 80%, or in the range of about 20% to about 50%, or in the range of about 30% to about 40%, and the second germanium concentration is less than or equal to the first germanium concentration and the third germanium concentration. For example, the second germanium concentration is less than or equal to 20% germanium, such as in the range of about 1% to about 20%, or in the range of about 5% to about 15%, or in the range of about 5% to about 10%. In some embodiments, the second germanium concentration is less than or equal to 50%, or less than or equal to 40%, or less than or equal to 30%, or less than or equal to 20%, or less than or equal to 10%, for example, in the range of about 1% to about 50%, or in the range of about 1% to about 40%, or in the range of about 1% to about 30%, or in the range of about 1% to about 20%, or in the range of about 1% to about 10%, or in the range of about 1% to about 5%, or in the range of about 5% to about 10%.

[0037] In some embodiments, at least one of the plurality of first material layers and the plurality of second material layers is doped with carbon, such as Si:C or SiGe:C.

[0038] In some embodiments, the first material layer and the second material layer are formed via an epitaxial chemical vapor deposition process. Therefore, the interface between different atomic species can be controlled, which provides favorable control of the superlattice structure during subsequent selective etching or modification processes. In some embodiments, the epitaxial deposition process includes loading the substrate into a process chamber and adjusting the conditions in the process chamber to a target temperature and pressure. Then, a deposition process is started to form one or more epitaxial layers on the single crystal surface of the substrate. The deposition process is then terminated. The thickness of the epitaxial layer is then determined. If a predetermined epitaxial layer thickness is reached, the epitaxial process is terminated. However, if the predetermined thickness is not reached, the steps of deposition and purification are repeated cyclically until the predetermined thickness is reached. Further details of this exemplary process are described below.

[0039] After the substrate is loaded into the process chamber, the conditions in the process chamber are adjusted to a predetermined temperature and pressure. The temperature is customized according to a specific process. The appropriate temperature for performing the epitaxial process may depend on the specific precursors used to deposit the silicon-containing material and the silicon-germanium-containing material. In some embodiments, the process chamber is maintained at a temperature within a range of about 450 degrees Celsius to about 750 degrees Celsius, or within a range of about 550 degrees Celsius to about 650 degrees Celsius, or within a range of about 500 degrees Celsius to about 650 degrees Celsius during the epitaxial deposition process. In some embodiments, the pressure of the process chamber is maintained within a range of about 0.1 torr to about 50 torr, or within a range of about 1 torr to about 20 torr, or within a range of about 5 torr to about 10 torr during the epitaxial deposition process. The pressure may fluctuate during and between process steps, but is generally maintained constant.

[0040] During the epitaxial deposition process, the substrate is exposed to a deposition gas to form a first material layer and a second material layer. In some embodiments, the substrate is exposed to the deposition gas for a period ranging from about 0.5 seconds to about 30 seconds, or from about 1 second to about 20 seconds, or from about 5 seconds to about 10 seconds. In a specific embodiment, the deposition step lasts for about 10 seconds to 11 seconds. The specific exposure time during the epitaxial deposition process is generally related to the specific precursor and temperature used in the epitaxial deposition process. Typically, the substrate is exposed to the deposition gas for a sufficient time to form an epitaxial layer of a target thickness in the superlattice structure.

[0041] In some embodiments, the deposition gas contains at least a silicon source, and may contain a carrier gas and / or at least one secondary element source, such as a germanium source and / or a carbon source.

[0042] In some embodiments, the silicon source is generally provided to the process chamber at a rate in the range of about 5 sccm to about 500 sccm, or in the range of about 10 sccm to about 300 sccm, or in the range of about 50 sccm to about 200 sccm, such as about 100 sccm. Useful silicon sources in the deposition gas for depositing the silicon-containing compound include silanes, halosilanes, and organosilanes. Silanes include silane (SiH 4 ) and higher silanes of the empirical formula SixH(2x+2), such as disilane (Si 2 H 6 ), trisilane (Si 3 H 8 ), tetrasilane (Si 4 H 10 ) and neopentasilane, etc. Halosilanes include compounds with the empirical formula X'ySixH(2x+2-y), where X'=F, Cl, Br or I, such as hexachlorodisilane (Si 2 Cl 6 ), tetrachlorosilane (SiCl 4 ), dichlorosilane (Cl 2 S H 2 ) and trichlorosilane (Cl 3 Organosilanes include compounds of the empirical formula RySixH(2x+2-y) where R = methyl, ethyl, propyl or butyl, such as methylsilane ((CH 3 )SiH 3 ), dimethylsilane ((CH 3 ) 2 S H 2 ), ethylsilane ((CH 3 CH 2 )SiH 3 ), methyl disilane ((CH 3 )Si 2 H 5 ), dimethyldisilane ((CH 3 ) 2 Si 2 H 4 ) and hexamethyldisilane ((CH 3 ) 6 Si 2 ). Organosilane compounds have been found to be advantageous sources of silicon and carbon in embodiments where carbon is incorporated into the deposited silicon-containing compound.

[0043] In some embodiments where the silicon source is provided with a carrier gas, the flow rate of the carrier gas is in the range of about 1 slm (standard liters per minute) to about 100 slm, or in the range of about 5 slm to about 75 slm, or in the range of about 10 slm to about 50 slm, or in the range of about 10 slm to about 20 slm. The carrier gas may include nitrogen (N 2 ), hydrogen (H 2 ), argon, helium, or a combination thereof. In some embodiments, an inert carrier gas is preferred and is selected from nitrogen, argon, helium, or a combination thereof. The carrier gas may be selected based on the precursors and / or process temperature used during the epitaxial process.

[0044] In a specific embodiment, where the epitaxial layer is a silicon layer, the deposition gas comprises disilane.

[0045] In some embodiments, the deposition gas used also contains at least one secondary element source, such as a germanium source and / or a carbon source. A germanium source may be added to the process chamber along with a silicon source and an optional carrier gas to form a silicon-containing compound, such as a silicon germanium material layer. In some embodiments, the germanium source is provided to the process chamber at a rate in the range of about 0.1 sccm to about 20 sccm, such as in the range of about 0.5 sccm to about 10 sccm, or in the range of about 1 sccm to about 5 sccm. Germanium sources that can be used to deposit silicon-containing compounds include germanium (GeH 4 ), higher germanes and organogermanes. Higher germanes include compounds with the empirical formula GexH(2x+2), such as digermane (Ge 2 H 6 ), trigermane (Ge 3 H 8 ) and tetragermane (Ge 4 H 10 ) etc. Organic germanes include methylgermane ((CH 3 )Ge 3 ), dimethylgermane ((CH 3 ) 2 HkDJ 2 ), ethylgermane ((CH 3 CH 2 )Ge 3 ), methyldigermane ((CH 3 ) 2 H 5 ), dimethyldigermane ((CH 3 ) 2 Ge 2 H 4 ) and hexamethyldigermane ((CH 3 ) 6 Ge 2) compounds. It has been found that when germanium and carbon are incorporated into deposited silicon-containing compounds, i.e., SiGe and SiGe:C compounds, germanane and organogermanium compounds are advantageous germanium and carbon sources in embodiments. In some embodiments, the germanium concentration in the epitaxial layer is in the range of about 1 atomic % to about 30 atomic %, such as about 20 atomic %. In some embodiments, the germanium concentration can be graded within the epitaxial layer, as discussed herein.

[0046] A carbon source may be added to the process chamber during deposition along with a silicon source and / or a germanium source and an optional carrier gas to form a silicon-containing compound, such as a silicon-carbon material (e.g., Si:C) or a silicon-germanium-carbon material (e.g., SiGe:C). In some embodiments, the carbon source is provided to the process chamber at a rate in the range of about 0.1 sccm to about 40 sccm, or in the range of about 3 sccm to about 25 sccm, or in the range of about 5 sccm to about 25 sccm. The carbon source may be diluted 5% in argon or nitrogen and flowed at a rate of 750 sccm. Carbon sources that can be used to deposit silicon-containing compounds include organosilanes, alkyl compounds, olefins, and alkynes having ethyl, propyl, and butyl groups. Such carbon sources include methylsilane (CH 3 S H 3 ), dimethylsilane ((CH 3 ) 2 S H 2 ), ethylsilane (CH 3 CH 2 S H 3 ), methane (CH 4 ), ethylene (C 2 H 4 ), acetylene (C 2 H 2 ), propane (C 3 H 8 ), propylene (C 3 H 6 ), butyne (C 4 H 6 ), etc. In some embodiments, the carbon concentration of the epitaxial layer is in the range of about 200 ppm to about 5 atomic %, or in the range of about 1 atomic % to about 3 atomic %. In some embodiments, the carbon concentration can be graded within the epitaxial layer, preferably graded so that the carbon concentration in the initial portion of the epitaxial layer is lower than the carbon concentration in the final portion of the epitaxial layer. Alternatively, both the germanium source and the carbon source can be added to the process chamber during deposition along with the silicon source and the carrier gas to form a silicon-containing compound, such as silicon-carbon or silicon-germanium-carbon material.

[0047] In a specific embodiment, the first epitaxial layer, which is a silicon layer, is formed using disilane, and the second epitaxial layer, which is a silicon germanium layer, is formed using dichlorosilane and germane. The use of dichlorosilane provides a high growth rate process with chlorine surface termination, which results in excellent interface steepness. This interface steepness helps to improve the etch selectivity of the silicon and germanium containing layer relative to the silicon layer.

[0048] In some embodiments, after the deposition process is terminated, the process chamber can be flushed with a purge gas or a carrier gas and / or the process chamber can be evacuated with a vacuum pump. The purging and / or evacuation process removes excess deposition gas, reaction byproducts, and other contaminants. In some embodiments, the process chamber can be purged between the deposition of the first layer and the second layer. In one embodiment, the process chamber can be purged for about 10 seconds by flowing a carrier gas at about 5 slm. The cycle of deposition and purging can be repeated many times.

[0049] refer to FIG. 2A to FIG. 2B and Figure 3 , cross-sectional views of some embodiments of device structures of semiconductor devices at various stages of fabrication are provided to illustrate Figure 1 Although FIG. 2A to FIG. 2B and Figure 3 is described with respect to method 100, but it should be understood that FIG. 2A to FIG. 2B and Figure 3 The structure disclosed in is not limited to the method 100, but can be used as a structure independent of the method 100. Similarly, although the method 100 is about FIG. 2A to FIG. 2B and Figure 3 However, it should be understood that method 100 is not limited to FIG. 2A to FIG. 2B and Figure 3 The structure disclosed in FIG. 2A to FIG. 2B and Figure 3 The disclosed structure.

[0050] Figure 2A A cross-sectional view of a semiconductor device structure 200 during an intermediate manufacturing stage corresponding to operations 110 and 120 of method 100 is illustrated according to some embodiments. The semiconductor device structure 200 includes a substrate 210. The substrate 210 may be a substrate as described in operation 110. The substrate 210 has a front side 210f (also referred to as a front surface) and a back side 210b (also referred to as a back surface) opposite the front side 210f. As described in operation 120, the substrate 210 may be exposed to a pre-cleaning process. Next, as described in operation 120, Figure 2B As shown, a superlattice structure 220 as described herein is formed over the front side 210 f of the substrate 210 .

[0051] Figure 2BA cross-sectional view of a semiconductor device structure 200 during an intermediate manufacturing stage corresponding to operation 130 according to some embodiments is illustrated. The superlattice structure 220 includes a plurality of first material layers 224a to 224c and a corresponding plurality of second material layers 226a to 226c, the plurality of first material layers and the plurality of second material layers being alternately arranged into a plurality of stacked pairs. In one embodiment, the plurality of first material layers 224a to 224c are formed of at least a silicon-containing material and a germanium-containing material. In one embodiment, the plurality of second material layers 226a to 226c are formed of at least a silicon-containing material. Accordingly, the first material layers 224a to 224c and the second material layers 226a to 226c are different materials. In some embodiments, the plurality of first material layers 224 and the corresponding plurality of second material layers 226 are lattice-matched materials having sufficient compositional differences so that selective layer removal or layer modification can be subsequently performed.

[0052] In some embodiments, the plurality of first material layers 224a to 224c and the corresponding plurality of second material layers 226a to 226c may be any number of lattice-matched material pairs suitable for forming the superlattice structure 220. For example, the plurality of first material layers 224a to 224c and the corresponding plurality of second material layers 226a to 226c include about 2 pairs to about 5 pairs of lattice-matched materials, such as Figure 2B Three pairs of lattice-matched materials are shown.

[0053] The material layers of the superlattice structure 220 may have controlled thicknesses to provide substantially defect-free crystallographic profiles of various materials. In some embodiments, the total thickness of the layers of the superlattice structure 220 is in the range of about 3 nm to about 50 nm, or in the range of about 5 nm to about 40 nm, or in the range of about 5 nm to about 30 nm, or in the range of about 5 nm to about 20 nm. In some embodiments, the thickness of the layers of the superlattice structure 220 is in the range of about 3 nm to about 50 nm. For example, the thickness 225 of the plurality of first material layers 224a to 224c may be in the range of about 1 nm to about 20 nm, or in the range of about 1 nm to about 10 nm, or in the range of about 3 nm to about 10 nm, or in the range of about 5 nm to about 7 nm, for example, about 6 nm. The thickness 227 of the plurality of second material layers 226a to 226c may be in the range of about 1 nm to about 20 nm, or in the range of about 5 nm to about 15 nm, or in the range of about 7 nm to about 10 nm, for example, about 8 nm.

[0054] Figure 3 A cross-sectional view of a portion of a semiconductor device structure 200 during an intermediate manufacturing stage corresponding to operation 130 is illustrated in accordance with some embodiments. In some embodiments, the first material layer 224 is Figure 3The multilayer structure 230 shown. The multilayer structure 230 may include a first silicon germanium layer 232 or a first silicon germanium cladding layer having a backside interface 232b and a frontside interface 232f; and a second silicon germanium layer 234 or a core layer having a backside interface 234b and a frontside interface 234f; and a third silicon germanium layer 236 or a second silicon germanium cladding layer having a backside interface 236b and a frontside interface 236f. ​​The first silicon germanium layer 232 has a first germanium concentration and a first thickness 233, the second silicon germanium layer 234 has a second germanium concentration and a second thickness 235, and the third silicon germanium layer 236 has a third germanium concentration and a third thickness 237. Figure 3 As depicted, in some embodiments, the second silicon germanium layer 234 can be located or sandwiched between the first silicon germanium layer 232 and the third silicon germanium layer 236. In some embodiments, the first germanium concentration and the third germanium concentration can be greater than the second germanium concentration and the first thickness and the third thickness can be less than the second thickness.

[0055] In some embodiments, a concentration gradient of germanium is formed within the first material layer 224. The concentration gradient of germanium can be continuous or stepped. The concentration gradient of germanium can be formed in a direction perpendicular to the front side interface 236f of the third silicon germanium layer 236. The concentration gradient of germanium can vary from a high concentration to a low concentration in one direction, or vice versa. In some embodiments, the concentration gradient of germanium can vary from a high concentration to a low concentration in one direction and then return to a high concentration, or vice versa. In some embodiments described herein, one or more regions of the first material layer may include a more complex germanium gradient, such as high / low / high or low / high / low germanium. In some embodiments, the concentration gradient is configured so that the germanium concentration decreases as the distance from the different materials (e.g., the different materials in the second material layer 226 or the substrate 210) increases. In some embodiments, reference Figure 3 , for example, the germanium concentration may be highest at the front side interface 236f and the back side interface 232b. Having the highest germanium concentration at the interface of material layers contacting different materials provides improved etching selectivity between the first material layer 224 and the second material layers 226a to 226c. For example, having a higher germanium concentration at the front side interface 236f that may contact one of the second material layers 226a to 226c, and having a higher germanium concentration at the back side interface 232b of any of the second material layers 226a to 226c contacting the front side 210f of the substrate 210, provides improved etching selectivity when removing the first material layers 224a to 224c.

[0056] In some embodiments, a concentration gradient of germanium is formed in at least one of the first silicon germanium layer 232, the second silicon germanium layer 234, and the third silicon germanium layer 236. Figure 3In some embodiments, the first silicon germanium layer 232 and the third silicon germanium layer 236 always have a uniform germanium concentration and the second silicon germanium layer has a germanium concentration gradient. The germanium concentration gradient in the second silicon germanium layer 234 can decrease from the backside interface 234b toward the central region of the second silicon germanium layer 234, and then increase again from the central region of the second silicon germanium layer 234 to the frontside interface 234f.

[0057] Figure 4A A germanium concentration graph 400 for fabricating a superlattice structure according to one or more embodiments of the present disclosure is illustrated. The x-axis of the germanium concentration graph 400 represents time, and the y-axis represents the germanium concentration in the deposited layer. In some embodiments, as Figure 4A As depicted, the first material layers 224a-224c are silicon germanium layers and the second material layers 226a-226c are silicon layers. The germanium concentration graph 400 illustrates an example where the germanium concentration varies within the first material layers 224a-224c but is highest at the interface between the first material layers 224a-224c and the second material layers 226a-226c.

[0058] Figure 4B Another germanium concentration graph 410 for fabricating a superlattice structure according to one or more embodiments of the present disclosure is illustrated. The germanium concentration graph 410 is similar to Figure 4A The germanium concentration diagram 400 shown is different in that the germanium concentration variation shown in the germanium concentration diagram 410 varies within the second silicon germanium layer 234 in the following manner: it decreases from the interface between the front side interface 232f and the back side interface 234b into the second silicon germanium layer 234, but then increases toward the interface between the front side interface 234f and the back side interface 236b.

[0059] Figure 5 A flow chart of a method 500 for fabricating a transistor device incorporating a superlattice structure according to one or more embodiments of the present disclosure is illustrated. 6A to 6F 1 shows cross-sectional views of various stages of fabricating a transistor device incorporating a superlattice structure according to one or more embodiments of the present disclosure. The transistor device may be a GAA device. 6A to 6F is described with respect to method 500, but it should be understood that 6A to 6F The structure disclosed in is not limited to method 500, but can instead be a structure independent of method 500. Similarly, although method 500 is about 6A to 6F However, it should be understood that method 500 is not limited to 6A to 6F The structure disclosed in the above, but can instead be independent of 6A to 6F The structure disclosed in .

[0060] At operation 510 of method 500, a superlattice structure is formed on a substrate, e.g., Figure 2B As shown, a superlattice structure 220 is formed on a substrate 210 .

[0061] Fig. 6A A cross-sectional view of a portion of a semiconductor device structure 600 during an intermediate manufacturing stage corresponding to operation 520 is illustrated in accordance with some embodiments. At operation 520, after a hard mask layer 614 is deposited on a top surface of the superlattice structure 220, a patterning and etching process 610 is performed to form trenches 612a-612c in the superlattice structure 220. In some embodiments, the hard mask layer 614 is patterned using photolithography techniques. Typically, a photoresist material (not shown) is deposited over the hard mask layer 614. The photoresist material is irradiated (exposed) with radiation (e.g., light) through a patterned master mask to induce a reaction in portions of the photoresist material exposed to the energy. The photoresist material is developed to remove a portion of the photoresist material, wherein the remaining photoresist material protects the underlying material from subsequent processing steps (such as etching).

[0062] like Fig. 6A As shown, after the etching process is performed on the superlattice structure 220, the remaining area of ​​the superlattice structure 220 and the underlying substrate 210 form fins, such as the first fin 616a and the second fin 616b (collectively referred to as fin 616). Fig. 6A As seen in FIG. 6 , the fin 616 includes a portion of the superlattice structure 220 (eg, a portion of the first material layer 224 ′ (eg, SiGe layer) and a portion of the second material layer 226 ′ (eg, silicon layer)), and a portion of the substrate 210. Fig. 6A Two fins are illustrated, namely a first fin 616a and a second fin 616b, but it should be understood that any suitable number and type of fins may be utilized.

[0063] Figure 6BA cross-sectional view of a portion of a semiconductor device structure 600 during an intermediate manufacturing stage corresponding to operation 530 is illustrated in accordance with some embodiments. In accordance with some embodiments, at operation 530, shallow trench isolations (STIs) 622a-622c are formed. At operation 530, a deposition process 620 may be performed to deposit dielectric insulating materials in the trenches 612a-612c between adjacent fins 616 to form the STIs 622a-622c. The STIs 622a-622c may be made of a suitable dielectric material such as silicon oxide, silicon nitride, silicon oxynitride, fluoride-doped silicate glass (FSG), a low dielectric constant dielectric such as carbon-doped oxide, an extremely low dielectric constant dielectric such as porous carbon-doped silicon dioxide, a polymer such as polyimide, combinations thereof, and the like. In some embodiments, the deposition process 620 is a process such as CVD, flowable CVD (FCVD), or a spin-on glass process, but any acceptable process may be used. Subsequently, the STIs 622a to 622c may be subjected to one or more of a hard mask removal process and a process for removing portions of the STIs 622a to 622c extending above the top surfaces of the fins 616a to 616b using, for example, an etching process, chemical mechanical polishing (CMP), etc.

[0064] Figure 6C A cross-sectional view of a portion of a semiconductor device structure 600 during an intermediate manufacturing stage corresponding to operation 540 according to some embodiments is illustrated. At operation 540, the sidewalls of the fins 616a-616b can be exposed by recessing the STIs 622a-622c to form recessed STIs 622a'-622c'. In some embodiments, the STIs 622a-622c are recessed using one or more selective etching processes 630 using the fins 616a-616b as etching masks. For example, the STIs 622a-622c are recessed using one or more etching processes. The depth of the recessed STIs 622a'-622c' can be determined by the height of the superlattice structure 220. In some embodiments, the recess extends to a depth that exposes the bottommost first material layer 224a'. Alternatively, the bottommost first material layer 224 a ′ (eg, SiGe layer) may remain below the upper surfaces of the recessed STIs 622 a ′ to 622 c ′.

[0065] Fig.6DA cross-sectional view of a portion of a semiconductor device structure 600 during an intermediate manufacturing stage corresponding to operation 550 is illustrated according to some embodiments. At operation 550, a dummy gate oxide layer 642 is formed over the exposed fins 616a-616b. In some embodiments, the dummy gate oxide layer 642 can be formed by a deposition process 640, such as thermal oxidation, CVD, sputtering, or any other method known and used in the art for forming a dummy gate oxide layer 642. In some embodiments, the dummy gate oxide layer 642 can be formed of the same material as the STI 622a-622c. In other embodiments, the dummy gate oxide layer 642 can be made of one or more suitable dielectric materials, such as silicon oxide, silicon nitride, low dielectric constant dielectrics (such as carbon-doped oxides), very low dielectric constant dielectrics (such as porous carbon-doped silicon dioxide), polymers (such as polyimide), etc., or combinations thereof. In other embodiments, the dummy gate oxide layer 642 includes a dielectric material having a high dielectric constant (k value), for example, greater than 3.9. These materials may include silicon nitride, oxynitride, metal oxides (such as HfO2, HfZrOx, HfSiOx, HfTiOx, HfAlOx), combinations thereof, multilayers thereof, etc.

[0066] Fig. 6E A view of a portion of a semiconductor device structure 600 during an intermediate manufacturing stage corresponding to operation 560 is illustrated in accordance with some embodiments. At operation 560, a dummy metal layer 652 may be deposited over the dummy gate oxide layer 642 (at Fig.6D 652). In one embodiment, the dummy metal layer 652 is a conductive material and may be selected from the group consisting of polycrystalline silicon (poly-Si), polycrystalline silicon germanium (poly-SiGe), metal nitrides, metal silicides, metal oxides, and metals. In one embodiment, the dummy metal layer 652 may be deposited by a deposition process 650 (e.g., PVD, CVD, sputtering deposition, or other techniques known and used in the art for depositing conductive materials). Other conductive and non-conductive materials may be used. The top surface of the dummy metal layer 652 may be planarized after deposition.

[0067] In some embodiments, the first hard mask layer 654 is deposited on the dummy metal layer 652 via a deposition process such as CVD or a spin-on-glass process, but any acceptable process may be used. In a particular embodiment, the first hard mask layer 654 may be an oxide layer (e.g., silicon oxide) and may have a thickness of about to about A second hard mask layer 656 may then be deposited on the first hard mask layer 654 via a process such as CVD or a spin-on-glass process, but any acceptable process may be used. In a particular embodiment, the second hard mask layer 656 may be a nitride (e.g., silicon nitride). The second hard mask layer 656 may have a thickness of about to about The first hard mask layer 654 and the second hard mask layer 656 may be patterned to form a virtual gate hard mask layer stack (not shown) above the virtual metal layer 652. In a particular embodiment, a polysilicon etch and a virtual oxide removal process are performed using the virtual gate hard mask stack to pattern the virtual metal layer 652 and the virtual gate oxide layer 642. During patterning, portions of the virtual metal layer 652 and portions of the virtual gate oxide layer 642 are removed from the source / drain regions of the fins 616a to 616b, and portions of the virtual metal layer 652 and portions of the virtual gate oxide layer 642 are retained above the channel regions of the fins 616a to 616b to form a virtual metal gate electrode (not shown). The virtual metal gate electrode may include a patterned virtual metal layer and a patterned virtual gate oxide layer disposed below the patterned virtual metal layer. The virtual metal gate electrode and the virtual gate hard mask layer stack together form a virtual metal gate stack (not shown).

[0068] A dummy metal gate stack may then be used to define and form source / drain regions from the exposed portions of the fins 616a-616b. The dummy metal gate stack may then be removed to allow processing to be performed to define and form channel regions (not shown) from the central portions of the fins 616a-616b.

[0069] Fig. 6F A cross-sectional view of a portion of a semiconductor device structure 600 during an intermediate manufacturing stage corresponding to operation 570 according to some embodiments is illustrated. At operation 570, a removal process of the first material layers 224a-224c (e.g., SiGe layers) is performed. Fig. 6F After the first material layers 224a to 224c are formed of silicon germanium (SiGe) and the second material layers 226a to 226c are formed of silicon (Si), the first material layers 224a to 224c can be removed, for example, by a removal process 660. In some embodiments, the removal process 660 can use an etchant that etches silicon germanium at a higher rate than silicon, such as NH 4 OH:H 2 O 2 :H 2 O (ammonia peroxide mixture, APM), H2 SO 4 +H 2 O 2 (sulfuric acid peroxide mixture, SPM), etc. Other suitable processes and materials may be used. This etching process removes the first material layer 224a to 224c. Thus, a first nanowire 662a to 662c or nanosheet for an n-type device is formed by the fins 616a to 616b. In some embodiments, after etching, the bottommost first layer 224a (e.g., SiGe layer) may remain below the upper surface of the recessed STI 622a' to 622c' as a stress layer within the first fin 616a and the second fin 616b to provide some strain or relaxation of the fin material.

[0070] After operation 570 , the semiconductor device structure 600 may undergo additional processing at operation 580 to form a final device structure, such as a GAA device.

[0071] In the Summary and Detailed Description, the claims and the drawings, reference is made to specific features (including method operations) of the disclosure. It should be understood that the disclosure in this specification includes all possible combinations of such specific features. For example, where a specific feature is disclosed in the context of a particular aspect, embodiment or example of the disclosure or a particular claim, that feature may also be combined with and / or within the context of other specific aspects and embodiments of the disclosure, and generally in the disclosure, to the extent possible.

[0072] The embodiments and all functional operations described in this specification can be implemented in digital electronic circuit systems or in computer software, firmware or hardware (including the structural devices disclosed in this specification and their structural equivalents) or a combination thereof. The embodiments described herein can be implemented as one or more non-transitory computer program products, that is, one or more computer programs tangibly embodied in a machine-readable storage device for execution by a data processing device (e.g., a programmable processor, a computer, or multiple processors or computers) or to control the operation of the data processing device.

[0073] The processes and logic flows described in this specification may be performed by one or more programmable processors executing one or more computer programs to perform functions by operating on input data and generating output. The processes and logic flows may also be performed by, and the apparatus may also be implemented as, a special purpose logic circuit system, such as an FPGA (field programmable gate array) or an ASIC (application specific integrated circuit).

[0074] The term "data processing apparatus" includes all devices, means and machines for processing data, including, for example, a programmable processor, a computer, or multiple processors or computers. In addition to hardware, the apparatus may also include code that creates an execution environment for the computer program in question, for example, code constituting processor firmware, a protocol stack, a database management system, an operating system, or a combination of one or more of them. For example, processors suitable for executing a computer program include both general and special purpose microprocessors, and any one or more processors of any kind of digital computer.

[0075] Computer readable media suitable for storing computer program instructions and data include all forms of nonvolatile memory, media, and memory devices, including, for example, semiconductor memory devices, such as EPROM, EEPROM, and flash memory devices; magnetic disks, such as internal hard disks or removable disks; magneto-optical disks; and CD ROM and DVD-ROM disks. The processor and memory may be supplemented by, or incorporated in, special purpose logic circuitry.

[0076] The term "comprising" and its grammatical equivalents are used herein to mean that other components, ingredients, operations, etc. may be optionally present. For example, an article "comprising" (or "including") components A, B, and C may consist of (that is, only contain) components A, B, and C, or may contain not only components A, B, and C, but also one or more other components. In addition, whenever a composition, an element, or a group of elements is preceded by the transition phrase "comprising" or its grammatical equivalent, it is to be understood that we also contemplate that the same composition or group of elements may be preceded by the transition phrases "consisting essentially of," "consisting of," "selected from the group consisting of," or "is," and vice versa.

[0077] When introducing elements of the present disclosure or exemplary aspects or embodiments thereof, the articles "a," "an," "the," and "said" are intended to mean that there are one or more of the elements.

[0078] While the foregoing is directed to embodiments of the present disclosure, other and further embodiments of the disclosure may be devised without departing from the basic scope thereof, and the scope of the disclosure is determined by the claims that follow.

Claims

1. A device structure, comprising: substrate; A superlattice structure is formed on the substrate, and the superlattice structure includes: One or more superlattice stacks comprising: Silicon material layer; a first silicon germanium cladding layer having a first germanium concentration and a first thickness; a silicon germanium core layer having a second germanium concentration and a second thickness; and a second silicon germanium cladding layer having a third germanium concentration and a third thickness, wherein the silicon material layer, the first silicon germanium cladding layer, the silicon germanium core layer and the second silicon germanium cladding layer are arranged in a stacked manner, wherein the silicon germanium core layer is located between the first silicon germanium cladding layer and the second silicon germanium cladding layer; and The first germanium concentration and the third germanium concentration are greater than the second germanium concentration and the first thickness and the third thickness are less than the second thickness. 2 . The device structure of claim 1 , wherein a surface of the first silicon germanium cladding layer contacts a surface of the substrate, and a surface of the second silicon germanium cladding layer contacts a surface of the silicon material layer. 3 . The device structure of claim 1 , wherein at least one of the first silicon germanium cladding layer, the silicon germanium core layer, and the second silicon germanium cladding layer further comprises carbon or boron.

4. The device structure of claim 1, wherein the first germanium concentration is in a range from about 10% to about 50%.

5. The device structure of claim 1, wherein the first germanium concentration is in a range from about 20% to about 40%. 6 . The device structure of claim 1 , wherein the first thickness and the third thickness are each independently in a range from about 1 nm to about 10 nm. 7 . The device structure of claim 6 , the first thickness, the second thickness, and the third thickness having a total thickness in a range of about 5 nm to about 20 nm.

8. The device structure of claim 7, wherein the silicon material layer has a thickness in a range of about 5 nm to about 20 nm.

9. The device structure of claim 1, wherein the superlattice structure comprises between 2 and 5 of the superlattice stacks.

10. The device structure of claim 1, wherein the substrate comprises silicon {110}.

11. A method of forming a device structure, comprising: A superlattice structure is formed on a substrate, comprising: Forming a first superlattice stack on the substrate, comprising: Forming a first silicon germanium structure using a first deposition process with a first precursor material and a second precursor material includes: forming a first silicon germanium cladding layer having a first germanium concentration and a first thickness; forming a silicon germanium core layer on the first silicon germanium cladding layer, the silicon germanium core layer having a second germanium concentration and a second thickness; and forming a second silicon germanium cladding layer on the silicon germanium core layer, wherein the second silicon germanium cladding layer has a third germanium concentration and a third thickness, forming a first silicon layer using a second deposition process with a third precursor material, The first germanium concentration and the third germanium concentration are greater than the second germanium concentration and the first thickness and the third thickness are less than the second thickness.

12. The method of claim 11, wherein the first deposition process and the second deposition process are epitaxial deposition processes. 13 . The method of claim 12 , wherein the first deposition process and the second deposition process are performed in a same process chamber.

14. The method of claim 12, wherein the first deposition process is performed at a temperature in a range of about 600 degrees Celsius to about 680 degrees Celsius and a pressure in a range of about 1 Torr to about 10 Torr.

15. The method of claim 11, wherein the first precursor material is dichlorosilane, the second precursor material is germane, and the third precursor material is disilane.

16. The method of claim 11, wherein the first deposition process is performed using a fourth precursor material, the fourth precursor material being a carbon-containing precursor material.

17. The method according to claim 11, wherein the step of forming the silicon germanium core layer on the first silicon germanium cladding layer comprises: The flow rate of the second precursor material is reduced and then increased to produce a germanium concentration gradient in the silicon germanium core layer.

18. The method of claim 17, wherein the germanium concentration gradient decreases with increasing distance from the different materials.

19. A method of forming a device structure, comprising: A superlattice structure is formed on a substrate, wherein the substrate comprises silicon {110}, and the steps of forming the superlattice structure include: A plurality of superlattice stacks are formed on the substrate, comprising: The method comprises forming a first silicon-germanium structure by using a first deposition process with a first silicon-containing precursor material and a second germanium-containing precursor material, comprising: forming a first silicon germanium cladding layer having a first thickness; forming a silicon germanium core layer on the first silicon germanium cladding layer, wherein the silicon germanium core layer has a second thickness; and forming a second silicon germanium cladding layer on the silicon germanium core layer, the second silicon germanium cladding layer having a third thickness, wherein the silicon germanium stack has a germanium concentration gradient that decreases with increasing distance from the different materials; and A first silicon layer is formed on the first silicon germanium structure using a second deposition process with a second silicon-containing precursor material, wherein the first thickness and the third thickness are less than the second thickness.

20. The method of claim 19, further comprising: A gate-all-around transistor is formed by the substrate and the superlattice structure.

Images