Power conversion device, deterioration determination device, and deterioration determination method

Abstract

The invention provides a power conversion device, a deterioration determination device, and a deterioration determination method, which can improve the accuracy of deterioration determination of a semiconductor device. This power conversion device is provided with: a semiconductor device having a semiconductor element having a first main electrode, a second main electrode, and a control electrode, a first main terminal electrically connected to the first main electrode, a second main terminal electrically connected to the second main electrode, an auxiliary terminal electrically connected to the second main electrode, and a control terminal electrically connected to the control electrode; a command unit that generates a command for switching the semiconductor element; a drive unit that applies a drive voltage to the control electrode in accordance with a command; a voltage detection unit that detects a voltage between the auxiliary terminal and the second main terminal; a trigger unit that generates a trigger signal when the detected voltage is equal to or greater than a threshold voltage; and a deterioration determination unit that determines deterioration of the semiconductor device using a determination value corresponding to a current flowing between the main terminals between the first main terminal and the second main terminal when the trigger signal is input.

Description

Technical Field

[0001] The present disclosure relates to a power conversion device, a degradation determination device, and a degradation determination method. Background Art

[0002] Conventionally, there is known a degradation detection circuit that detects degradation of a joint of a semiconductor element based on a gate voltage between a main electrode terminal and a gate electrode terminal of the semiconductor element and a voltage between the main electrode terminal and other main electrode terminals and outputs an alarm signal (for example, refer to Patent Document 1).

[0003] [Prior art literature]

[0004] [Patent Literature]

[0005] [Patent Document 1] Japanese Patent Application Publication No. 2022-36633 Summary of the invention

[0006] [Problems to be solved by the invention]

[0007] However, in the conventional degradation detection circuit, there is room for improving the accuracy of determining the degradation of the semiconductor device.

[0008] The present disclosure provides a power conversion device, a degradation determination device, and a degradation determination method capable of determining degradation of a semiconductor device with high accuracy.

[0009]

Methods to solve the problem

[0010] In one embodiment of the present disclosure, there is provided a power conversion device comprising:

[0011] A semiconductor device comprising: a semiconductor element having a first main electrode, a second main electrode and a control electrode, a first main terminal electrically connected to the first main electrode, a second main terminal electrically connected to the second main electrode, an auxiliary terminal electrically connected to the second main electrode, and a control terminal electrically connected to the control electrode;

[0012] An instruction unit that generates an instruction to switch the semiconductor element;

[0013] a driving unit, applying a driving voltage to the control electrode according to the instruction;

[0014] a voltage detection unit for detecting a voltage between the auxiliary terminal and the second main terminal;

[0015] a trigger unit that generates a trigger signal when the voltage detected by the voltage detection unit is equal to or greater than a threshold voltage; and

[0016] The degradation determination unit determines degradation of the semiconductor device using a determination value corresponding to a current flowing between main terminals between the first main terminal and the second main terminal when the trigger signal is input.

[0017] In another aspect of the present disclosure, there is provided a degradation determination device comprising:

[0018] A semiconductor device comprising: a semiconductor element having a first main electrode and a second main electrode, a first main terminal electrically connected to the first main electrode, a second main terminal electrically connected to the second main electrode, and an auxiliary terminal electrically connected to the second main electrode;

[0019] a voltage detection unit configured to detect a voltage between the auxiliary terminal and the second main terminal or a voltage between the first main terminal and the second main terminal;

[0020] a trigger unit that generates a trigger signal when the voltage detected by the voltage detection unit is equal to or greater than a threshold voltage; and

[0021] The degradation determination unit determines degradation of the semiconductor device using a determination value corresponding to a current flowing between main terminals between the first main terminal and the second main terminal when the trigger signal is input.

[0022] In another embodiment of the present disclosure, there is provided a degradation determination method for determining degradation of a semiconductor device, the semiconductor device comprising: a semiconductor element having a first main electrode and a second main electrode, a first main terminal electrically connected to the first main electrode, a second main terminal electrically connected to the second main electrode, and an auxiliary terminal electrically connected to the second main electrode, wherein:

[0023] detecting a voltage between the auxiliary terminal and the second main terminal, or a voltage between the first main terminal and the second main terminal,

[0024] When the detected voltage is above the threshold voltage, a trigger signal is generated.

[0025] Deterioration of the semiconductor device is determined using a determination value corresponding to a current flowing between the main terminals between the first main terminal and the second main terminal when the trigger signal is input.

[0026] [Effects of the Invention]

[0027] According to the present disclosure, degradation of a semiconductor device can be determined with high accuracy. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] Figure 1 It is a diagram showing a configuration example of a power conversion device according to the present embodiment.

[0029] Figure 2 It is a plan view showing a structural example of a semiconductor device according to this embodiment.

[0030] Figure 3 It is a diagram showing a configuration example of a degradation determination device according to the first embodiment.

[0031] Figure 4 This is a timing chart illustrating waveforms of various parts accompanying a detection operation of the current Ic in a state where power is supplied between two main terminals of a semiconductor device.

[0032] Figure 5 This is a timing chart illustrating the operation of the degradation determination device according to the first embodiment.

[0033] Figure 6 This is a diagram illustrating changes in the estimated value of the resistance component Ree recorded in the memory in accordance with the operation time.

[0034] Figure 7 It is a diagram showing a configuration example of a degradation determination device according to the second embodiment.

[0035] Figure 8 This is a timing chart illustrating the operation of the degradation determination device according to the second embodiment.

[0036] Fig. 9 This is a timing chart illustrating the operation of the degradation determination device according to the third embodiment.

[0037]

Explanation of symbols

[0038] 5 Insulation substrate

[0039] 8 Surface

[0040] 9 Back

[0041] 10 Main circuit

[0042] 11a Anode electrode

[0043] 11c Collector electrode

[0044] 11e Emitter electrode

[0045] 11g Gate electrode

[0046] 11k Cathode Electrode

[0047] 12 Surface

[0048] 13 Back

[0049] 14 Load

[0050] 15~19 leads

[0051] 20 Control device

[0052] 21 Control Department

[0053] 22 Command Department

[0054] 23 Current estimation unit

[0055] 24 Deterioration determination unit

[0056] 30 Current detection unit

[0057] 33 Power Supply

[0058] 40 Gate drive unit

[0059] 51 Voltage detection unit

[0060] 61 Presumption

[0061] 62 Judgment Department

[0062] 70 Trigger

[0063] 101 Semiconductor Devices

[0064] 111~116 Power semiconductor modules

[0065] 200 Power conversion device

[0066] 301,302,303 Deterioration determination device

[0067] C Collector terminal

[0068] E Emitter terminal

[0069] Es Auxiliary emitter terminal

[0070] G Gate terminal DETAILED DESCRIPTION

[0071] Hereinafter, embodiments will be described.

[0072] In recent years, power converters have been used in applications that require high reliability (power systems or mobile objects such as trains and cars), and as a result, the demand for high reliability of power converters has increased. In response to this demand, the expectation for predicting failures and taking measures in advance to achieve predictive maintenance has increased.

[0073] One of the main causes of failure in power conversion devices is semiconductor devices such as power semiconductor modules. Semiconductor devices include semiconductor elements such as power semiconductor chips. The main failure of semiconductor devices is caused by the deterioration of leads or solder due to repeated thermal stress caused by current conduction or switching of semiconductor elements.

[0074] If a semiconductor device installed in a power electronic device such as a power converter continues to operate in a degraded state, the semiconductor device or the power electronic device may fail. Therefore, it is necessary to detect degradation with high accuracy and implement CBM (Condition Based Maintenance).

[0075] According to the power conversion device, degradation determination device, and degradation determination method of the present embodiment, degradation of the semiconductor device can be determined with high accuracy. Hereinafter, the power conversion device, degradation determination device, and degradation determination method according to the present embodiment will be described.

[0076] <Power conversion device>

[0077] Figure 1 It is a diagram showing a configuration example of a power conversion device according to the present embodiment. Figure 1 The illustrated power conversion device 200 includes a main circuit unit 10 that converts DC power supplied from a DC power source 33 into AC power supplied to a load 14 , and a control device 20 that controls the power conversion operation of the main circuit unit 10 . Figure 1 The embodiment in which the main circuit unit 10 converts DC power into three-phase AC power is illustrated.

[0078] The main circuit unit 10 includes a plurality of power semiconductor modules 111 to 116, a plurality of voltage detection units VD1 to VD6, a plurality of gate drive units PD1 to PD6, and a current detection unit 30. The power semiconductor modules 111 to 116 are examples of semiconductor devices for power conversion.

[0079] exist Figure 1 In the figure, as a power semiconductor module, a 1in1 packaged IGBT module is illustrated, which is assembled with an IGBT chip of one arm of an inverter and a diode chip (FWD chip) connected in anti-parallel thereto. IGBT is the abbreviation of Insulated Gate Bipolar Transistor, the IGBT chip is an example of a power semiconductor element, and the FWD chip is an example of a rectifier element. However, the packaging structure of the power semiconductor module can be other types of packaging structures such as 6in1, and the power semiconductor element constituted in the power semiconductor module can also be other types of power semiconductor elements such as MOSFET. MOSFET is the abbreviation of Metal Oxide Semiconductor Field Effect Transistor.

[0080] The plurality of power semiconductor modules 111 to 116 may have the same structure, the plurality of voltage detection units VD1 to VD6 may have the same structure, and the plurality of gate driving units PD1 to PD6 may have the same structure.

[0081] The power semiconductor module 111 of the upper arm of the u-phase includes an IGBT chip Q1 and a FWD chip D1. In addition, the power semiconductor module 111 has a collector terminal C, an emitter terminal E, a gate terminal G, and an auxiliary emitter terminal Es. The collector terminal C is an example of a first main terminal, the emitter terminal E is an example of a second main terminal, the gate terminal G is an example of a control terminal, and the auxiliary emitter terminal Es is an example of an auxiliary terminal.

[0082] The IGBT chip Q1 is an example of a switching element (semiconductor element) having a collector electrode 11c, an emitter electrode 11e, and a gate electrode 11g. The collector electrode 11c is an example of a first main electrode, the emitter electrode 11e is an example of a second main electrode, and the gate electrode 11g is an example of a control electrode.

[0083] The FWD chip D1 is an example of a rectifying element (semiconductor element) having an anode electrode 11 a and a cathode electrode 11 k .

[0084] The collector terminal C is electrically connected to the collector electrode 11c and the cathode electrode 11k. The emitter terminal E is electrically connected to the emitter electrode 11e and the anode electrode 11a. The gate terminal G is electrically connected to the gate electrode 11g. The auxiliary emitter terminal Es is electrically connected to the emitter electrode 11e and the anode electrode 11a.

[0085] The power semiconductor module 112 of the lower arm of the u phase includes an IGBT chip Q2 and a FWD chip D2. The power semiconductor module 113 of the upper arm of the v phase includes an IGBT chip Q3 and a FWD chip D3. The power semiconductor module 114 of the lower arm of the v phase includes an IGBT chip Q4 and a FWD chip D4. The power semiconductor module 115 of the upper arm of the w phase includes an IGBT chip Q5 and a FWD chip D5. The power semiconductor module 116 of the lower arm of the w phase includes an IGBT chip Q6 and a FWD chip D6. The power semiconductor modules 112 to 116 have the same structure as the above-mentioned power semiconductor module 111.

[0086] The gate driver PD1 is a circuit that drives the gate electrode 11g of the IGBT chip Q1 according to the on or off switching command S1 provided from the control device 20. Similarly, the gate drivers PD2 to PD6 are circuits that drive the gate electrodes 11g of the IGBT chips Q2 to Q6 according to the on or off switching commands S2 to S6 provided from the control device 20, respectively. The gate drivers PD1 to PD6 are driver units that apply a driving voltage between the gate terminal G and the auxiliary emitter terminal Es to switch the IGBT chips Q1 to Q6 of the power semiconductor modules 111 to 116 according to the switching commands S1 to S6 from the control device 20.

[0087] The voltage detection unit VD1 is a circuit that detects the voltage Vee1 between the auxiliary emitter terminal Es and the emitter terminal E of the power semiconductor module 111, and sends the detection value of Vee1 to the control device 20. Similarly, the voltage detection units VD2 to VD6 are circuits that detect the voltages Vee2 to Vee6 between the auxiliary emitter terminal Es and the emitter terminal E of the power semiconductor modules 112 to 116, and send the detection values ​​of Vee2 to Vee6 to the control device 20.

[0088] The current detection unit 30 detects the three-phase AC currents iu, iv, iw flowing between the power semiconductor modules 111 to 116 and the load 14, and sends the detected values ​​of the AC currents iu, iv, iw to the control device 20. The current detection unit 30 includes, for example, a current sensor for detecting the three-phase AC currents iu, iv, iw. The AC currents iu, iv, iw are load currents flowing through the load 14.

[0089] The control device 20 is, for example, a control unit having a processor such as a CPU (Central Processing Unit) and a memory. The functions of the control device 20 are realized by causing the processor to operate according to a program stored in the memory. The functions of the control device 20 can be realized by an FPGA (Field-Programmable Gate Array) or an ASIC (Application Specific Integrated Circuit).

[0090] The main circuit unit 10 may also include a heat sink temperature detection unit 80. The heat sink temperature detection unit 80 detects the temperature of a heat sink (e.g., fins, etc.) for cooling the power semiconductor modules 111 to 116, and sends a temperature detection value Th of the heat sink to the control device 20. The heat sink temperature detection unit 80 includes, for example, a temperature sensor that detects the temperature of the heat sink.

[0091] <Semiconductor devices>

[0092] Figure 2 It is a plan view showing a structural example of a semiconductor device according to this embodiment. Figure 2 For example, the circuit structure of one arm of the inverter is shown. In the case of the circuit structure of the upper arm of the u-phase, the semiconductor device 101 is equivalent to the above-mentioned power semiconductor module 111. Since the circuit structures of the arms are the same, the upper arm of the u-phase is used as an example for explanation below unless otherwise specified.

[0093] Figure 2 The semiconductor device 101 shown includes an insulating substrate 5 , a collector terminal C, an emitter terminal E, an auxiliary emitter terminal Es, a gate terminal G, an IGBT chip Q1 , a FWD chip D1 , and leads 15 , 16 , 17 , 18 , and 19 .

[0094] The insulating substrate 5 is a substrate on which the IGBT chip Q1 and the FWD chip D1 are mounted, and may be, for example, a DCB (Direct Copper Bonding) substrate, an AMB (Active Metal Blazing) substrate, etc. The insulating substrate 5 is fixed to a base substrate (not shown) via a bonding material such as solder.

[0095] The insulating substrate 5 includes an insulating layer 5a and a wiring layer 5c. The insulating layer 5a is, for example, a ceramic plate. The wiring layer 5c is provided on the upper surface of the insulating layer 5a and is, for example, a conductor layer formed of a conductive metal such as copper. The wiring layer 5c includes at least one conductor pattern.

[0096] The IGBT chip Q1 is a semiconductor element incorporated in the semiconductor device 101, and is a semiconductor switching element having electrodes on the front surface 12 and the back surface 13. The IGBT chip Q1 may be a Si semiconductor element or a SiC semiconductor element.

[0097] The IGBT chip Q1 has a surface 12 on which an emitter electrode 11e and a gate electrode 11g are formed, and a back surface 13 on which a collector electrode 11c is formed. The collector electrode 11c is an example of a first main electrode of the IGBT chip Q1. The emitter electrode 11e is an example of a second main electrode of the IGBT chip Q1. The gate electrode 11g is an example of a control electrode of the IGBT chip Q1. The IGBT chip Q1 is fixed to the insulating substrate 5 on the back surface 13 by bonding the collector electrode 11c to the conductor pattern of the wiring layer 5c using a bonding material such as solder.

[0098] The FWD chip D1 is a semiconductor element incorporated in the semiconductor device 101, and is a semiconductor diode element having electrodes on the front surface 8 and the back surface 9. The FWD chip D1 may be a Si semiconductor element or a SiC semiconductor element.

[0099] The FWD chip D1 has a surface 8 on which an anode electrode 11a is formed and a back surface 9 on which a cathode electrode 11k is formed. The FWD chip D1 is fixed to the insulating substrate 5 on the back surface 9 by bonding the cathode electrode 11k to the conductor pattern of the wiring layer 5c using a bonding material such as solder. The cathode electrode 11k is electrically connected to the collector electrode 11c through the conductor pattern of the wiring layer 5c.

[0100] The collector terminal C, the emitter terminal E, the gate terminal G, and the auxiliary emitter terminal Es are external terminals for connecting to the outside of the semiconductor device 101. Each of these external terminals is formed into a cylindrical or flat plate shape using conductive metal such as copper or aluminum.

[0101] The collector terminal C is electrically connected to the collector electrode 11 c and the cathode electrode 11 k via a lead wire 19 .

[0102] The emitter terminal E is electrically connected to the emitter electrode 11 e via the lead 15 , and is electrically connected to the anode electrode 11 a via the lead 18 .

[0103] The gate terminal G is electrically connected to the gate electrode 11 g via a wire 17 .

[0104] The auxiliary emitter terminal Es is electrically connected to the emitter electrode 11 e via the lead wire 16 .

[0105] Leads 15 to 19 are, for example, bonding leads formed using conductive metals such as copper and aluminum or conductive alloys such as iron-aluminum alloys. Lead 15 is one or more (for example, three) linear components that connect the emitter electrode 11e, which is the surface electrode of the IGBT chip Q1, to the conductor pattern of the wiring layer provided with the emitter terminal E. Lead 16 is one or more (for example, one) linear components that connect the emitter electrode 11e, which is the surface electrode of the IGBT chip Q1, to the conductor pattern of the wiring layer provided with the auxiliary emitter terminal Es. Lead 17 is one or more (for example, one) linear components that connect the gate electrode 11g, which is the surface electrode of the IGBT chip Q1, to the conductor pattern of the wiring layer provided with the gate terminal G. Lead 18 is one or more (for example, three) linear components that connect the emitter electrode 11e, which is the surface electrode of the IGBT chip Q1, and the anode electrode 11a, which is the surface electrode of the FWD chip D1. Lead 19 is one or more (for example, three) linear components that connect the conductor pattern of the wiring layer 5c and the conductor pattern of the wiring layer provided with the collector terminal C. The lead 15 is an example of a first lead or a main lead, and the lead 16 is an example of a second lead or an auxiliary lead.

[0106] The current Ic flowing through the semiconductor device 101 flows to the leads 15, 18, and 19 but not to the leads 16 and 17. The current Ic flowing into the semiconductor device 101 from the collector terminal C flows to the collector electrode 11c via the conductor pattern and bonding material of the wiring layer 5c, and passes through the IGBT chip Q1. Then, the current Ic output from the emitter electrode 11e flows to the emitter terminal E via the lead 15 and the conductor pattern. On the contrary, the current Ic flowing into the semiconductor device 101 from the emitter terminal E flows to the anode electrode 11a via the conductor pattern and the leads 15 and 18, and passes through the FWD chip D1. Furthermore, the current Ic output from the cathode electrode 11k or the collector electrode 11c flows to the collector terminal C via the bonding material, the conductor pattern of the wiring layer 5c, and the lead 19.

[0107] The IGBT chip Q1 and the FWD chip D1 are thermally connected on the path of the bonding material, the insulating substrate 5, the bonding material, the base substrate, the thermal grease and the heat sink. Each chip is cooled by being released from the heat sink to the outside air.

[0108] As is known to all, the semiconductor device 101 degrades due to the current flowing in each chip or the repeated heat generated by the switch. The main deterioration sites include the wire bonding portion between the lead and the chip or wiring pattern, the solder and other bonding materials under the chip, etc. If the wire bonding portion degrades, the resistance mainly increases, and if the solder and other bonding materials under the chip degrade, the thermal resistance mainly increases. Thermal grease degrades as the temperature of the semiconductor device 101 or the heat sink changes. When the thermal grease ages, the thermal resistance increases. For the heat sink, the thermal resistance increases due to clogging of the fins and failure of the fan, etc.

[0109] <Degradation determination device according to first embodiment>

[0110] Figure 3 It is a diagram showing a configuration example of a degradation determination device according to the first embodiment. Figure 3 The degradation determination device 301 shown determines degradation of the semiconductor device 101 . Figure 3 For example, the circuit structure of one arm of the inverter is shown. In the case of the circuit structure of the upper arm of the u-phase, the semiconductor device 101 is equivalent to the above-mentioned power semiconductor module 111. Since the circuit structures of the arms are the same, the upper arm of the u-phase is used as an example for explanation unless otherwise specified. Figure 3 , the bonding material and the lead wire 19 between the collector terminal C and the collector electrode 11c are shown (see Figure 2 ) and the lead wire 15 (see Figure 2 )’s resistance component Ree.

[0111] When degradation of the electrical connection portion between the emitter electrode 11 e and the emitter terminal E progresses, the resistance component Ree increases. Figure 3 The degradation determination device 301 shown determines degradation of the semiconductor device 101 by detecting an increase in the resistance component Ree.

[0112] Next, the configuration of the degradation determination device 301 will be described. The degradation determination device 301 includes the semiconductor device 101, the gate driving unit 40, the voltage detection unit 51, the current detection unit 30, the trigger unit 70, and the control unit 21.

[0113] The gate drive unit 40 is a gate drive circuit that applies a drive voltage for switching the IGBT chip Q1 of the semiconductor device 101 between the gate terminal G and the auxiliary emitter terminal Es of the semiconductor device 101 according to the switching command Sg from the control unit 21. The gate drive unit 40 corresponds to the gate drive unit PD1 described above, for example. The switching command Sg corresponds to the switching command S1 described above that instructs the switching timing (on timing and off timing) of the IGBT chip Q1.

[0114] The voltage detection unit 51 is a circuit that detects a voltage Vee between the auxiliary emitter terminal Es and the emitter terminal E of the semiconductor device 101 and outputs the detected voltage Vee to the trigger unit 70 .

[0115] The current detection unit 30 detects the alternating current iu output from the collector terminal C or the emitter terminal E, and outputs the detected value of the alternating current iu to the control unit 21 .

[0116] The trigger unit 70 is a circuit that generates a trigger signal Str when the voltage Vee detected by the voltage detection unit 51 is greater than the threshold voltage Veeth. The trigger signal Str indicates that the voltage Vee detected by the voltage detection unit 51 is greater than the threshold voltage Veeth. The trigger signal Str is also called a timing signal. The trigger unit 70 outputs the trigger signal Str when the voltage Vee detected by the voltage detection unit 51 is greater than the threshold voltage Veeth.

[0117] In addition, the trigger unit 70 may also be provided in the control unit 21 .

[0118] In this example, the trigger unit 70 is composed of a comparator 71 and an isolator 72 .

[0119] The comparator 71 compares the voltage Vee detected by the voltage detection unit 51 with a predetermined threshold voltage Veeth. When the detected voltage Vee is higher than the threshold voltage Veeth, the comparator 71 enables the trigger signal Str (in this example, the logic level of the trigger signal Str is set to a high level). On the other hand, when the detected voltage Vee is lower than the threshold voltage Veeth, the comparator 71 disables the trigger signal Str (in this example, the logic level of the trigger signal Str is set to a low level).

[0120] The isolator 72 transmits the trigger signal Str output from the comparator 71 to the control unit 21 while ensuring electrical insulation between the comparator 71 and the control unit 21. A specific example of the isolator 72 is a photocoupler or the like.

[0121] The control unit 21 is a controller that controls the switching of the semiconductor device 101. The control unit 21 corresponds to the control device 20 ( Figure 1 ), but may also be a controller different from the control device 20. The control unit 21 includes an instruction unit 22, a current estimation unit 23, and a degradation determination unit 24.

[0122] The command unit 22 generates a switching command Sg for switching the IGBT chip Q1 based on the detection values ​​of the AC currents iu, iv, and iw obtained from the current detection unit 30 and the like.

[0123] A current Ic flows through the semiconductor device 101. The sign of the current Ic is set as positive, for example, in the direction from the collector terminal C to the emitter terminal E via the IGBT chip Q1, and set as negative in the direction from the emitter terminal E to the collector terminal C via the FWD chip D1. In the case of an inverter, the current estimation unit 23 of the control unit 21 can determine in which direction the current Ic flows based on the state of the AC currents iu, iv, iw obtained from the current detection unit 30 and the on command or off command of the switch command Sg obtained from the command unit 22.

[0124] Figure 4 It is a timing diagram illustrating the waveforms of various parts of the detection action of the current Ic in the power-on state between the two main terminals of the semiconductor device. In the example of the figure, the AC current iu is a sinusoidal load current, and the U-phase voltage command is a sinusoidal voltage. The on-state and off-state of the upper and lower arms of the U-phase depend on the magnitude relationship between the U-phase voltage command and the carrier. In the example of the figure, the control device 20 outputs a switching command S1 that turns on the IGBT chip Q1 and turns off the IGBT chip Q2 during the period when the U-phase voltage command is larger than the carrier. On the other hand, the control device 20 outputs a switching command S1 that turns off the IGBT chip Q1 and turns on the IGBT chip Q2 during the period when the U-phase voltage command is smaller than the carrier.

[0125] When the IGBT chip Q1 is turned on and the AC current iu is positive, the same current as the AC current iu flows through the IGBT chip Q1. When the IGBT chip Q2 is turned off and the AC current iu is negative, the same current as the AC current iu flows through the FWD chip D1.

[0126] When the trigger signal Str is input (valid), the current estimation unit 23 ( Figure 3 ) obtains the detection value of the current iu from the current detection unit 30. When the detected voltage Vee is higher than the positive threshold voltage Veeth, the trigger signal Str is enabled.

[0127] The current estimation unit 23 samples the detection value of the current iu detected by the current detection unit 30 at the timing corresponding to the trigger signal Str. Thus, the current estimation unit 23 can estimate the value of the current Ic flowing at the timing corresponding to the trigger signal Str in the state (power-on state A) where the current Ic flows from the collector terminal C via the IGBT chip Q1 and the resistance component Ree to the emitter terminal E.

[0128] The method for detecting the current Ic between the main terminals when the IGBT chip is in the on state (energized state) is not limited to this. For example, the current Ic between the main terminals can be measured by a current measuring mechanism such as a Rogowski coil.

[0129] In this way, Figure 3 When the semiconductor device 101 shown is turned on, a main current (in this example, current Ic) flows between the collector terminal C and the emitter terminal E (between the main terminals). When the current Ic flows between the main terminals, the voltage drop generated between the main terminals of the semiconductor device 101 includes the voltage drop between the collector terminal C and the emitter electrode 11e, and the voltage drop between the emitter electrode 11e and the emitter terminal E.

[0130] The voltage drop between the collector terminal C and the emitter electrode 11e mainly includes the voltage drop of the IGBT chip Q1 and the voltage drop caused by the resistance component Rs of the bonding material including the solder under the chip. The voltage drop between the emitter electrode 11e and the emitter terminal E mainly includes the voltage drop caused by the resistance component Ree, which includes the lead 15 electrically connecting the emitter electrode 11e and the emitter terminal E.

[0131] Degradation determination unit 24 calculates an estimated value of resistance component Ree by dividing threshold voltage Veeth by current estimated by current estimation unit 23 (current Ic flowing at a timing corresponding to trigger signal Str). Degradation determination unit 24 uses the estimated value of resistance component Ree as a determination value for determining degradation of semiconductor device 101.

[0132] The degradation determination unit 24 may also determine the degradation of the semiconductor device 101 by comparing the estimated value of the resistance component Ree with a predetermined determination level. For example, when the estimated value of the resistance component Ree is detected to exceed the predetermined determination level, the degradation determination unit 24 determines that the degradation of the semiconductor device 101 (the electrical connection portion between the emitter electrode 11e and the emitter terminal E) has deteriorated, and issues an alarm notifying the degradation.

[0133] In this way, the degradation determination device 301 of the present embodiment uses the determination value corresponding to the current estimated by the current estimation unit 23 (the current Ic flowing at the timing corresponding to the trigger signal Str) to determine the degradation of the semiconductor device 101. As a result, the current Ic flowing at a specific timing synchronized with the timing when the voltage Vee detected by the voltage detection unit 51 is equal to or greater than the threshold voltage Veeth is added to the determination value, so the accuracy of the degradation determination is improved. In addition, the specific timing synchronized with the timing when the voltage Vee detected by the voltage detection unit 51 is equal to or greater than the threshold voltage Veeth is not limited to the same timing as the instant (timing) when the voltage Vee is equal to or greater than the threshold voltage Veeth.

[0134] For example, the judgment value corresponding to the current Ic flowing at the same timing as the timing when the voltage Vee detected by the voltage detection unit 51 reaches or exceeds the threshold voltage Veeth just after the IGBT chip Q1 is turned on may not be used as the judgment value for determining the degradation of the semiconductor device 101. This is because there is a high possibility that an excessively large current Ic will flow compared to a steady state due to a surge current or the like during the period just after the IGBT chip Q1 is turned on. Therefore, by determining the degradation of the semiconductor device 101 using the judgment value corresponding to the current Ic flowing in a steady state other than just after the IGBT chip Q1 is turned on, the possibility that the degradation determination device 301 erroneously determines the degradation of the semiconductor device 101 can be suppressed at a stage where the degradation of the semiconductor device 101 is not progressing.

[0135] In addition, the degradation determination device 301 determines the degradation of the semiconductor device 101 by measuring the current Ic flowing at the timing corresponding to the trigger signal Str. That is, in order to perform degradation measurement, it is sufficient to input the trigger signal Str to the control unit 21, so the electrical insulation from the semiconductor device 101, which will become the high potential part, is only the output of the comparator 71. That is, it is not necessary to increase the voltage (at Figure 3 The voltage Vee) is input to the AD converter having a withstand voltage performance of the control unit 21. Therefore, the degradation determination device 301 can determine the degradation of the semiconductor device 101 with a simple structure.

[0136] Next, a more detailed structure and operation of the degradation determination device 301 will be described.

[0137] Figure 5 1 is a timing chart illustrating the operation of the degradation determination device according to the first embodiment. The voltage detection unit 51 detects the voltage Vee, and the trigger unit 70 uses the comparator 71 to compare the detected voltage Vee with a predetermined threshold voltage Veeth.

[0138] The threshold voltage Veeth is set, for example, to the voltage Vee of the semiconductor device 101 or the power conversion device at half load before the degradation of the semiconductor device 101 progresses. The half load of the semiconductor device 101 or the power conversion device can also be defined as a state where the power output is 40% or more and 60% or less of the rated power of the semiconductor device 101 or the power conversion device. Since the frequency of occurrence of heavy loads where the output power is close to the rated power is not very high, if the threshold voltage Veeth is set to the voltage Vee at heavy load, the degradation judgment interval may become longer. On the other hand, since the voltage Vee at light load where the output power is close to zero is small, if the threshold voltage Veeth is set to the voltage Vee at light load, there is a possibility that the noise resistance becomes weak. Therefore, considering these possibilities, it is preferred to set the threshold voltage Veeth to the voltage Vee at half load. In addition, the threshold voltage Veeth can also be set to a voltage Vee with a lower or higher voltage value than that at half load.

[0139] The trigger unit 70 generates a trigger signal Str that becomes a high level (H) state when the voltage Vee is higher than the threshold voltage Veeth, and becomes a low level (L) state when the voltage Vee is lower than the threshold voltage Veeth. The trigger signal Str is transmitted to the control unit 21 via the isolator 72. The current estimation unit 23 of the control unit 21 reads the trigger signal Str at a specific time during the period when the IGBT chip Q1 is in the on state, and sets the value of the read trigger signal Str to Str′. In addition, Str′ is an example of the timing corresponding to the trigger signal Str. The current estimation unit 23 estimates the current Ic at the timing when Str′ changes from a low level to a high level or from a high level to a low level. The current estimation unit 23 estimates the current Ic using the switch command Sg generated by the command unit 22 and the load current (AC current iu) detected by the current detection unit 30.

[0140] The specific time during which the IGBT chip Q1 is in the on state refers to the time after a predetermined time has passed since the switching command Sg was switched from the off command to the on command, for example, Figure 4As shown in FIG. 1 , the carrier wave reaches a valley moment. In this way, by setting the value of the trigger signal Str to Str′ at a certain time after the IGBT chip Q1 is turned on, the voltage Vee when an excessive current Ic flows just after the IGBT chip Q1 is turned on can be excluded from the judgment value, thereby improving the accuracy of the degradation judgment.

[0141] The degradation determination unit 24 calculates the estimated value of the resistance component Ree by dividing the threshold voltage Veeth by the current estimated by the current estimation unit 23 (the current Ic flowing at the timing corresponding to the trigger signal Str). The degradation determination unit 24 records the estimated value of the resistance component Ree in the memory in association with the operation time (see Figure 6 ).

[0142] Figure 6 It is a diagram illustrating the change of the estimated value of the resistance component Ree recorded in the memory corresponding to the operation time. The degradation determination unit 24, for example, determines that the semiconductor device 101 is degraded (for example, there is a sign of failure) when the estimated value of the resistance component Ree exceeds the fault sign determination level. For example, the estimated value of the resistance component Ree can be an average value of multiple estimated values ​​of the resistance component Ree. The degradation determination unit 24 can also determine that the semiconductor device 101 is degraded (for example, there is a sign of failure) when the number of times the estimated value of the resistance component Ree exceeds the fault sign determination level is more than a specified number of times Nf within a specified operation period Tf. By considering multiple estimated values ​​in the degradation determination, the possibility of erroneous determination of degradation caused by noise, etc. can be suppressed. The degradation determination unit 24 can also determine the degradation of the semiconductor device 101 by measuring the trend of the estimated value of the resistance component Ree before exceeding a specified fixed value, and predict the degradation period (for example, failure time) of the semiconductor device 101. For example, the degradation determination unit 24 may predict the degradation period (eg, failure period) of the semiconductor device 101 by deriving the intersection of a regression curve (including a regression line) obtained by regression analysis and the failure determination level from a plurality of estimated values ​​of the resistance component Ree.

[0143] The degradation determination unit 24 may also set the fault sign determination level based on the estimated values ​​of the multiple resistance components Ree at the initial stage of the operation of the semiconductor device 101. For example, the degradation determination unit 24 averages the multiple estimated values ​​of the resistance component Ree in the initial stage of the operation time before degradation of the semiconductor device 101, and sets the fault sign determination level on the value obtained by multiplying or adding a specified value to the average value. The so-called initial stage of the operation time before degradation of the semiconductor device 101 is, for example, the initial period from the start of operation when the specified initial time has passed to the specified operation time. In this way, different fault sign determination levels can be automatically set according to the type (rated capacity, etc.) of the power semiconductor element.

[0144] The degradation determination unit 24 may set the predicted failure sign determination level to a predetermined value (for example, a value measured in advance during development or factory testing).

[0145] In addition, the degradation determination device 301 of the present embodiment uses the estimated value of the resistance component Ree as the determination value corresponding to the current estimated by the current estimation unit 23 (the current Ic flowing at the timing corresponding to the trigger signal Str). However, the determination value may also be a value related to the current Ic. In the above description, even if the resistance component Ree is replaced by the current Ic, the accuracy of the degradation determination is improved. However, when the resistance component Ree increases due to degradation, the current Ic decreases, so the degradation determination unit 24 can determine that the semiconductor device 101 is degraded (for example, there is a sign of failure) when the estimated value of the current Ic is lower than the fault sign determination level.

[0146] <Degradation determination device according to second embodiment>

[0147] Figure 7 1 is a diagram showing a configuration example of a degradation determination device according to a second embodiment. In the second embodiment, the configuration, operation, and effects similar to those of the first embodiment are omitted by citing the above description. The second embodiment differs from the first embodiment in that the trigger unit 70 permits the generation of the trigger signal Str after a predetermined time has passed since the IGBT chip Q1 was turned on.

[0148] exist Figure 7 In the example shown, the trigger section 70 has a BT generator 73 and a logic AND gate 74. The BT generator 73 is a circuit that generates a blanking time (BT). The BT generator 73 is a circuit that delays the trigger signal Str by the blanking time (BT). The logic AND gate 74 outputs a logical OR signal of the pulse signal Sbt output from the BT generator 73 and the signal See output from the comparator 71 as the trigger signal Str.

[0149] Figure 8 1 is a timing diagram illustrating the operation of the degradation determination device according to the second embodiment. The BT generation unit 73 outputs a pulse signal Sbt when a predetermined blanking time has passed after the switch instruction Sg is changed from a cut-off instruction to a conduction instruction. The logic AND gate 74 outputs a logical OR signal of the pulse signal Sbt output from the BT generation unit 73 and the signal See output from the comparator 71 as a trigger signal Str. The trigger signal Str is transmitted to the control unit 21 via the isolator 72. The current estimation unit 23 of the control unit 21 reads the trigger signal Str and estimates the current Ic at the timing of the read signal. The following operation is the same as that of the first embodiment.

[0150] In the transition period when the IGBT chip Q1 changes from off to on, a surge current is generated, and an excessive current flows relative to the current in the steady state, so there is a possibility that the voltage Vee is erroneously detected. According to the degradation determination device 302 of the second embodiment, the degradation of the semiconductor device 101 is determined using the current Ic that flows after a predetermined blanking time has passed since the switching instruction Sg changes from the off instruction to the on instruction. Therefore, by synchronizing with the switching operation of the IGBT chip Q1, but not performing degradation determination during the period when an excessive current flows in the transition period, the accuracy of the degradation determination can be improved.

[0151] In addition, Figure 8 In the embodiment, the mechanism of the trigger unit 70 that generates the trigger signal Str after a predetermined time has passed since the IGBT chip Q1 was turned on is not limited to the BT generating unit 73 and the logic AND gate 74. For example, the trigger unit 70 may also include a delay circuit between the voltage detecting unit 51 and the comparator 71 instead of the BT generating unit 73 and the logic AND gate 74. The delay circuit delays the detection signal of the voltage Vee output from the voltage detecting unit 51 for a predetermined time and then outputs it to the comparator 71. The trigger unit 70 may also generate the trigger signal Str after a predetermined time has passed since the IGBT chip Q1 was turned on by using such a delay circuit. In addition, the excessive current during the transition period is caused by the switching speed of the IGBT chip Q1. Therefore, even if the trigger unit 70 includes a low-pass filter with a cutoff frequency lower than the switching speed between the voltage detecting unit 51 and the comparator 71 instead of the BT generating unit 73 and the logic AND gate 74, the same effect can be obtained.

[0152] <Degradation determination device according to third embodiment>

[0153] Fig. 9 1 is a diagram showing a configuration example of a degradation determination device according to a third embodiment. In the third embodiment, the above description is cited, and description of the same configuration, operation, and effect as those of the above embodiment is omitted.

[0154] The resistance component Rs increases as degradation of the electrical connection portion between the collector electrode 11c and the collector terminal C progresses. The degradation determination device 303 of the third embodiment determines degradation of the semiconductor device 101 by detecting an increase in the resistance component that is a combination of the resistance component Rs and the resistance component Ree.

[0155] In the third embodiment, the voltage detection unit 51 detects the voltage Vce between the collector terminal C and the emitter terminal E of the semiconductor device 101, and outputs the detected voltage Vce to the trigger unit 70. When the voltage Vce detected by the voltage detection unit 51 exceeds the threshold voltage Vceth, the trigger unit 70 generates a trigger signal Str. Other aspects may be the same as the above embodiment.

[0156] As described above, the embodiments are described, but the above embodiments are presented as examples, and the present invention is not limited to the above embodiments. The above embodiments can be implemented in various other ways, and various combinations, omissions, substitutions, changes, etc. can be made without departing from the scope of the invention. These embodiments and their variations are included in the scope and gist of the invention, and are included in the invention described in the claims and the scope of their equivalents.

[0157] For example, the semiconductor element is not limited to a power transistor such as an IGBT or a MOSFET, and may be a diode, a thyristor, a gate turn-off thyristor, a triac, or the like.

[0158] In addition, for example, one or both of the current estimation unit 23 and the degradation determination unit 24 may be installed in an external device (for example, an information processing device such as a server having a computing unit) different from the control device 20. In this case, the external device can determine the degradation of the semiconductor device 101 by receiving the trigger signal Str or Str′ and the information of the AC current iu or the current Ic between the main terminals.

Claims

1. A power conversion device, comprising: A semiconductor device comprising: a semiconductor element having a first main electrode, a second main electrode and a control electrode, a first main terminal electrically connected to the first main electrode, a second main terminal electrically connected to the second main electrode, an auxiliary terminal electrically connected to the second main electrode, and a control terminal electrically connected to the control electrode; An instruction unit that generates an instruction to switch the semiconductor element; a driving unit, applying a driving voltage to the control electrode according to the instruction; a voltage detection unit for detecting a voltage between the auxiliary terminal and the second main terminal; a trigger unit that generates a trigger signal when the voltage detected by the voltage detection unit is equal to or greater than a threshold voltage; as well as The degradation determination unit determines degradation of the semiconductor device using a determination value corresponding to a current flowing between main terminals between the first main terminal and the second main terminal when the trigger signal is input.

2. The power conversion device according to claim 1, wherein: The degradation determination unit determines degradation of the semiconductor device by comparing the determination value with a determination level.

3. The power conversion device according to claim 2, wherein: The determination level is set based on the plurality of determination values ​​at an initial stage of operation of the semiconductor device.

4. The power conversion device according to claim 1, wherein: The degradation determination unit determines degradation of the semiconductor device based on a trend of a change in the determination value.

5. The power conversion device according to any one of claims 1 to 4, wherein: The determination value is a value related to the current flowing between the main terminals.

6. The power conversion device according to any one of claims 1 to 4, wherein: The determination value is a value obtained by dividing the threshold voltage by the current.

7. The power conversion device according to any one of claims 1 to 4, wherein: The current flowing between the main terminals is a current flowing between the main terminals at a timing corresponding to the trigger signal.

8. The power conversion device according to any one of claims 1 to 4, wherein: The current flowing between the main terminals is a value estimated by a current estimating unit that estimates the current flowing between the main terminals at a timing corresponding to the trigger signal.

9. The power conversion device according to claim 8, wherein: The current estimating unit estimates the current flowing between the main terminals using a detected value of the current output from the first main terminal or the second main terminal.

10. The power conversion device according to any one of claims 1 to 4, wherein: The trigger unit permits generation of the trigger signal after a predetermined time has elapsed since the semiconductor element was turned on.

11. A degradation determination device, comprising: A semiconductor device comprising: a semiconductor element having a first main electrode and a second main electrode, a first main terminal electrically connected to the first main electrode, a second main terminal electrically connected to the second main electrode, and an auxiliary terminal electrically connected to the second main electrode; a voltage detection unit configured to detect a voltage between the auxiliary terminal and the second main terminal or a voltage between the first main terminal and the second main terminal; a trigger unit that generates a trigger signal when the voltage detected by the voltage detection unit is equal to or greater than a threshold voltage; as well as The degradation determination unit determines degradation of the semiconductor device using a determination value corresponding to a current flowing between main terminals between the first main terminal and the second main terminal when the trigger signal is input.

12. A degradation determination method for determining degradation of a semiconductor device, the semiconductor device comprising: a semiconductor element having a first main electrode and a second main electrode, a first main terminal electrically connected to the first main electrode, a second main terminal electrically connected to the second main electrode, and an auxiliary terminal electrically connected to the second main electrode, wherein: detecting a voltage between the auxiliary terminal and the second main terminal, or a voltage between the first main terminal and the second main terminal, When the detected voltage is above the threshold voltage, a trigger signal is generated. Deterioration of the semiconductor device is determined using a determination value corresponding to a current flowing between the main terminals between the first main terminal and the second main terminal when the trigger signal is input.

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