An integrated circuit standard unit timing arc pulse delay measurement system

Abstract

The present invention discloses a timing arc pulse delay measurement system for integrated circuit standard cells, comprising: an on-chip clock generation module, which is used to generate a high-frequency clock on a chip as a reference counting clock; an on-chip standard cell timing arc generation circuit, which realizes the pulse widening of the timing arc through a multi-stage cascade circuit structure of the same timing arc, and measures a single timing arc delay through the superposition of multiple stages of the same timing arc delay; an on-chip timing arc counting circuit, which uses the on-chip high-frequency clock as a reference clock to count the widened timing arc pulse; an on-chip input and output module, which controls the selection of multiple integrated circuit standard cell types, the selection of timing arcs, and controls the output of counters; a wafer circuit tester, which uses a wafer circuit test probe to perform wafer-level electrical connection, and supplies power to the integrated circuit standard cell and inputs and outputs signals. The present invention realizes the measurement of the timing arc of the integrated circuit standard cell and the measurement of all timing arcs of all standard cells in the standard cell library.

Description

Technical Field

[0001] The invention relates to the technical field of integrated circuits, and in particular to a timing arc pulse delay measurement system for an integrated circuit standard unit. Background Art

[0002] Integrated circuit standard cells, or standard cell libraries, are essential cell components for wafer fabs to manufacture chips. Standard cell libraries contain logic gates and interconnections required to perform specific functions, such as AND gates, OR gates, triggers, etc. The design requirements for standard cell libraries for different processes are different. In the early stages of process development, wafer fabs or manufacturing providers need design teams to design corresponding standard cell libraries for different processes. After the layout design of different logical functional units of the standard cell is completed, the simulation results of the timing arc delay of the standard cell will be obtained. Generally, the simulation values ​​are obtained by simulating with spice models and spice simulators. However, there is generally a significant gap between the simulation value and the actual value after actual manufacturing. These gaps will directly affect the sign-off strategy and process robustness of chip design and manufacturing. Therefore, it is of great significance to measure the timing arc delay of integrated circuit standard cells.

[0003] The common IC standard unit timing arc delay test is generally found in the wafer acceptance test (WAT) of the wafer fab. In the later process production, the process is monitored by using the scribe groove and test probe measurement. In addition, the IC standard unit test also exists in some large chip companies.

[0004] Common integrated circuit standard unit timing arc delay test has the following shortcomings:

[0005] The cost of WAT in wafer fabs is extremely high. Test data is contacted by probes and other tools, and the output is an analog quantity that is measured on the machine, which inevitably results in errors. It is impossible to exhaust all timing arcs of integrated circuit standard cells (the number of standard cells of integrated circuit standard cells is as many as 1000+, and the timing arc combinations are more complicated).

[0006] The CP (Circuit Probing) and FT (Final Test) costs of large chip design companies are high. Due to cost and test complexity considerations, general chip companies generally do not perform detailed measurements on all timing arcs of integrated circuit standard cells. They generally use a small-scale RO (ring oscillator) oscillation ring for basic oscillation frequency measurements, which cannot meet the more accurate and detailed standard cell timing arc delay measurement requirements. Summary of the invention

[0007] The object of the present invention is to provide an integrated circuit standard unit timing arc pulse delay measurement system to solve the problems in the background technology.

[0008] In order to solve the above technical problems, the present invention provides an integrated circuit standard unit timing arc pulse delay measurement system, comprising:

[0009] An on-chip clock generation module is used to generate a high-frequency clock on the chip as a reference counting clock;

[0010] The on-chip standard unit timing arc generation circuit realizes the pulse broadening of the timing arc through the circuit structure of multi-stage cascade of the same timing arc, and measures the delay of a single timing arc by superposition of multi-stage delays of the same timing arc;

[0011] An on-chip timing arc counting circuit uses an on-chip high-frequency clock as a reference clock to count the stretched timing arc pulses;

[0012] On-chip input and output module, controls the selection of various integrated circuit standard cell types, the selection of timing arcs, and controls the output of the on-chip timing arc counting circuit;

[0013] The wafer circuit tester uses wafer circuit test probes to make wafer-level electrical connections, provide power supply and signal input and output to the integrated circuit standard units.

[0014] In one embodiment, the on-chip standard cell timing arc generation circuit traverses the timing arcs of various standard cells to obtain the input pins and output pins corresponding to the timing arc in the standard cell, as well as the value of the static pin corresponding to the timing arc; for each timing arc of each standard cell, the input and output pins of the timing arc are cascaded to form a timing arc chain, and the static values ​​of other pins are set using a circuit to form a timing arc stretching pulse generation circuit for multiple timing arcs corresponding to the integrated circuit standard cell; the timing arc stretching pulse generation circuit realizes the generation of a stretching pulse for a specific timing arc of the integrated circuit standard cell through a selection signal and an enable signal.

[0015] In one embodiment, the on-chip clock generation module generates a high-frequency clock using a phase-locked loop and an external reference crystal oscillator clock; the high-frequency clock is generated by a basic reference clock, has an accurate oscillation period, and the clock period at the phase-locked loop oscillation frequency is smaller than the pulse width widened after the integrated circuit standard unit timing arc is cascaded.

[0016] In one embodiment, the measurement steps of the integrated circuit standard unit timing arc pulse delay measurement system include: the timing arc pulse starts with a rising edge and ends with a falling edge; when detecting the arrival of the rising edge, starting counting with an on-chip timing arc counting circuit driven by a high-frequency clock; when the falling edge of the timing arc pulse arrives, the counting stops, and the count is stored in binary form for subsequent testing machine reading.

[0017] In one embodiment, the wafer circuit tester controls the input reference clock, the control signal selects the timing arc of a specific standard unit, and reads the counting result; the timing delay of the timing arc widening chain of the standard unit is calculated by the counting result and the period of the reference clock; the delay data obtained by counting the number of standard units included in the timing arc chain of the standard unit, using the delay data obtained by testing the test piece, eliminating the delay values ​​of non-standard units, and then dividing by the number of standard units in the timing arc chain to obtain the precise value of the delay result of the specific timing arc of the standard unit; wherein the test piece is a wafer test piece, which is processed by a timing arc widening pulse generating circuit.

[0018] In one embodiment, the wafer circuit tester is connected to the wafer chip via a probe card to perform chip testing; and the probe card adopts a large-pitch low-cost design to reduce the testing cost.

[0019] The present invention provides an integrated circuit standard cell timing arc pulse delay measurement system, which solves the problem of integrated circuit standard cell timing arc measurement, realizes the measurement of all timing arcs of all standard cells in the standard cell library, and is low-cost and high-precision. Compared with the wafer acceptance test of the wafer factory, signal analog output is not used, and the digital counting method of the standard reference clock is used to complete the measurement of pulse width inside the chip digital circuit, thereby avoiding various interferences and errors in the analog output process. Compared with the testing tasks of traditional chip design companies, the present invention is more detailed and accurate, can provide guidance and reference for chip timing sign-off, and provide an implementation method for detailed consistency testing of process design collaborative optimization design. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] Figure 1 It is the block diagram of the standard unit timing arc pulse delay measurement system.

[0021] Figure 2 It is a basic circuit diagram of the pulse stretching circuit of three timing arcs of an AOI21 unit.

[0022] Figure 3 It is a schematic diagram of the counter timing results of the timing arc under a high-frequency clock.

[0023] Figure 4 This is a schematic diagram of the test implementation of a test machine. DETAILED DESCRIPTION

[0024] The following is a further detailed description of an integrated circuit standard unit timing arc pulse delay measurement system proposed by the present invention in conjunction with the accompanying drawings and specific embodiments. The advantages and features of the present invention will become clearer according to the following description. It should be noted that the accompanying drawings are all in a very simplified form and are not in precise proportions, and are only used to conveniently and clearly assist in explaining the purpose of the embodiments of the present invention.

[0025] The present invention provides an integrated circuit standard unit timing arc pulse delay measurement system, the overall system block diagram is as follows Figure 1 As shown, it includes the following parts:

[0026] ① On-chip clock generation module, used to generate high-frequency clock on the chip as the reference counting clock;

[0027] ② The on-chip standard unit timing arc generation circuit realizes the pulse broadening of the timing arc through the multi-stage cascade circuit structure of the same timing arc, and the measurement of the delay of a single timing arc becomes possible through the superposition of the delay of multiple stages of the same timing arc;

[0028] ③ On-chip timing arc counting circuit, using the on-chip high-frequency clock as the reference clock to count the stretched timing arc pulses;

[0029] ④ On-chip input and output modules, controlling the selection of various integrated circuit standard unit types, the selection of timing arcs, controlling counter output, etc.;

[0030] ⑤ Wafer CP test machine, which uses CP test probes to make wafer-level electrical connections, provide power supply and signal input and output for integrated circuit standard units.

[0031] Design a timing arc stretching pulse generation circuit for integrated circuit standard cells. By traversing the timing arcs of various standard cells, the input pins and output pins corresponding to the timing arc in the standard cell, as well as the values ​​of the static pins corresponding to the timing arcs are obtained. For each timing arc of each standard cell, the input and output pins of the timing arc are cascaded to form a timing arc chain, and the circuit is used to set the static values ​​of other pins to form a timing arc stretching pulse generation circuit for multiple timing arcs corresponding to the integrated circuit standard cell. The timing arc stretching pulse generation circuit can realize the generation of stretching pulses for specific timing arcs of integrated circuit standard cells through selection signals and enable signals. Figure 2 The figure shows the basic principle diagram of the timing arc stretching pulse generation circuit of the AOI21 standard unit. The AOI21 standard unit has three timing arcs in total. By cascading different timing arcs and setting the non-timing arc pins, the basic circuits of all timing arcs of the AOI21 standard unit can be successfully obtained.

[0032] The on-chip clock generation module uses a phase-locked loop and an external reference crystal clock to generate a high-frequency clock. The high-frequency clock is generated by the basic reference clock, and the oscillation period is accurate. The clock period at the phase-locked loop oscillation frequency is smaller than the pulse width widened after the cascade of the timing arc of the integrated circuit standard unit. The accuracy of the entire test method depends on the frequency of the high-frequency clock and the length of time the overall timing arc is widened.

[0033] Measurement of the delay of the timing arc pulse of the standard unit of the integrated circuit: The timing arc pulse starts with a rising edge and ends with a falling edge. When the rising edge is detected, the on-chip timing arc counting circuit driven by the high-frequency clock starts counting. When the falling edge of the timing arc pulse arrives, the counting stops and the count is stored in binary form for easy reading by the subsequent test machine. Figure 3 The figure shows a timing diagram of a standard unit timing arc delay counter.

[0034] After all circuit designs are completed and chip tape-out is achieved, wafer processing is performed to complete the manufacture of test chips. After obtaining the chip manufacturing wafer, the wafer circuit tester is used to perform wafer-level electrical connections, provide power supply and signal input and output to the integrated circuit standard unit. Figure 4 The figure shows a test machine test implementation schematic diagram. By controlling the test machine input reference clock, the control signal selects the timing arc of a specific standard unit and reads the counting result. The timing delay of the timing arc stretching chain of the standard unit can be obtained by calculating the counting result and the period of the reference clock. By counting the number of standard units contained in the timing arc chain of the standard unit, the delay data obtained by the test piece test (excluding the delay value of non-standard units) is divided by the number of standard units in the chain, and the accurate value of the delay result of the specific timing arc of the standard unit can be obtained; the test piece is a wafer test piece, which is the carrier of the timing arc stretching pulse generating circuit. The timing arc stretching pulse generating circuit will be designed and manufactured on the wafer.

[0035] The wafer circuit tester is connected to the wafer chip through a probe card to perform chip testing. The test cost of the present invention is low, and the probe card uses a large-pitch low-cost solution to complete all timing arc measurements of integrated circuit standard units, and the accuracy only depends on the frequency of the high-frequency clock and the width of the overall timing arc widening. The more the cascaded standard unit timing arcs are counted, the smaller the timing arc delay error allocated to each standard unit, and high-precision delay measurement of any timing arc of any standard unit can be easily achieved.

[0036] The above description is only a description of the preferred embodiments of the present invention, and is not intended to limit the scope of the present invention. Any changes or modifications made by a person skilled in the art in the field of the present invention based on the above disclosure shall fall within the scope of protection of the claims.

Claims

1. An integrated circuit standard unit timing arc pulse delay measurement system, characterized in that: include: An on-chip clock generation module is used to generate a high-frequency clock on the chip as a reference counting clock; The on-chip standard unit timing arc generation circuit realizes the pulse broadening of the timing arc through the circuit structure of multi-stage cascade of the same timing arc, and measures the delay of a single timing arc by superposition of multi-stage delays of the same timing arc; An on-chip timing arc counting circuit uses an on-chip high-frequency clock as a reference counting clock to count the stretched timing arc pulses; On-chip input and output module, controls the selection of various integrated circuit standard cell types, the selection of timing arcs, and controls the output of the on-chip timing arc counting circuit; The wafer circuit tester uses wafer circuit test probes to make wafer-level electrical connections, provide power supply and signal input and output to integrated circuit standard units.

2. The integrated circuit standard unit timing arc pulse delay measurement system as claimed in claim 1, characterized in that: The on-chip standard cell timing arc generation circuit traverses the timing arcs of various standard cells to obtain the input pin and output pin corresponding to the timing arc in the standard cell, as well as the value of the static pin corresponding to the timing arc; for each timing arc of each standard cell, the input and output pins of the timing arc are cascaded to form a timing arc chain, and the static values ​​of other pins are set by using a circuit to form a timing arc stretching pulse generation circuit for multiple timing arcs corresponding to the integrated circuit standard cell; The timing arc stretching pulse generating circuit realizes the generation of the stretching pulse of the timing arc of the standard unit of the integrated circuit through the selection signal and the enable signal.

3. The integrated circuit standard unit timing arc pulse delay measurement system as claimed in claim 2, characterized in that: The on-chip clock generation module generates a high-frequency clock using a phase-locked loop and an external reference crystal oscillator clock; the high-frequency clock is generated by a basic reference clock, has an accurate oscillation period, and the clock period at the phase-locked loop oscillation frequency is smaller than the pulse width widened after the timing arc of the integrated circuit standard unit is cascaded.

4. The integrated circuit standard unit timing arc pulse delay measurement system as claimed in claim 3, characterized in that: The measuring steps of the integrated circuit standard unit timing arc pulse delay measurement system include: the timing arc pulse starts with a rising edge and ends with a falling edge; when the rising edge is detected, the on-chip timing arc counting circuit driven by a high-frequency clock starts counting; when the falling edge of the timing arc pulse arrives, the counting stops, and the count is stored in binary form for subsequent reading by a test machine.

5. The integrated circuit standard unit timing arc pulse delay measurement system as claimed in claim 4, characterized in that: The wafer circuit tester controls the input reference clock, the control signal selects the timing arc of the standard unit, and reads the counting result; the timing delay of the timing arc chain of the standard unit is calculated by the counting result and the period of the reference clock; the delay data obtained by testing the test piece is counted by counting the number of standard units included in the timing arc chain of the standard unit, and the delay values ​​of non-standard units are eliminated, and then divided by the number of standard units in the timing arc chain to obtain the accurate value of the delay result of the timing arc of the standard unit; wherein the test piece is a wafer test piece, which is processed by a timing arc stretching pulse generation circuit.

6. The integrated circuit standard unit timing arc pulse delay measurement system as claimed in claim 1, characterized in that: The wafer circuit tester is connected to the wafer chip via a probe card to perform chip testing; And the probe card adopts a large-pitch and low-cost design to reduce testing costs.

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