Radio frequency chip, chip cascading and packaging structure, radar device and electronic equipment

Abstract

The invention relates to the technical field of wireless communication, in particular to a radio frequency chip, a chip cascading and packaging structure, a radar device and electronic equipment. Wherein the radio frequency chip is integrated with a signal transmission link and comprises a cascade input end and a cascade output end; the signal transmission link is connected with the cascade input end and the cascade output end to form a first signal path; when the radio frequency chip is in a first cascade slave mode, the first signal path receives a cascade synchronization signal from the outside of the radio frequency chip, and outputs the cascade synchronization signal to the outside of the radio frequency chip through the first signal path; wherein the first cascade slave mode represents that the radio frequency chip is a non-head-and-tail-level chip in the cascade structure; more radio frequency chips can be cascaded in a cascaded chip structure formed based on the radio frequency chip, so that the number of channels in the FMCW radar is increased.

Description

Technical Field

[0001] The present disclosure relates to the field of wireless communication technology, and in particular to a radio frequency chip, a chip cascade and packaging structure, a radar device, and an electronic device. Background Art

[0002] FMCW (Frequency Modulated Continuous Wave) radar refers to a radar whose transmitting frequency is modulated by a specific signal. The FMCW radar obtains the radial velocity information of the target's distance information by comparing the difference between the echo signal frequency at any time and the transmitting signal frequency at that time.

[0003] Compared with other ranging and speed measurement radars, FMCW radar has a simpler structure. In addition, FMCW radar has rich technical experience, the required transmission power peak is low, it is easy to modulate, the cost is low, and the signal processing is simple. Therefore, it is a commonly used radar system in automotive radar.

[0004] In specific applications, the number of channels of FMCW radar has an important impact on its performance; it not only affects the angular resolution of the radar, but also affects the transmission power, and thus affects the detection distance of the radar. Therefore, increasing the number of channels of FMCW radar can effectively improve the performance of FMCW radar. Specifically, the higher the number of channels of FMCW radar, the higher the angular resolution of the radar and the longer the detection distance of the radar. Summary of the invention

[0005] The embodiments of the present disclosure provide a radio frequency chip, a chip cascade and packaging structure, a radar device, and an electronic device. A radio frequency chip structure is provided. More radio frequency chips can be cascaded in the cascade chip structure formed based on the radio frequency chip, thereby increasing the number of channels in the FMCW radar.

[0006] An embodiment of the present disclosure provides a radio frequency chip, including: the radio frequency chip is integrated with a signal transmission link, and includes a cascade input terminal and a cascade output terminal; the signal transmission link connects the cascade input terminal and the cascade output terminal to form a first signal path; when the radio frequency chip is in a first cascade slave mode, the first signal path receives a cascade synchronization signal from outside the radio frequency chip, and outputs the cascade synchronization signal to the outside of the radio frequency chip through the first signal path; wherein, the first cascade slave mode represents the radio frequency chip as a non-first and last chip in the cascade structure.

[0007] The RF chip provided in this embodiment is additionally provided with a first cascade slave mode, and the first cascade slave mode can output a cascade synchronization signal through a cascade output terminal, so that more RF chips can be connected to the cascade structure formed based on the RF chip, thereby increasing the number of channels in the FMCW radar.

[0008] In some embodiments, the RF chip also includes: an RF transceiver circuit; a signal transmission link connects the cascade input end and the RF transceiver circuit to form a second signal path; when the RF chip is in the cascade master mode, the first cascade slave mode or the second cascade slave mode, the second signal path is used for the RF chip to perform radar detection using the cascade synchronization signal; wherein, the cascade master mode represents the RF chip as the first-stage chip in the cascade structure, and the second cascade slave mode represents the RF chip as the last-stage chip in the cascade structure.

[0009] In some embodiments, the RF chip also includes: a signal generating circuit and an RF transceiver circuit, the signal generating circuit is used to generate an on-chip oscillation signal; a signal transmission link connects the cascade input terminal and the RF transceiver circuit to form a second signal path; the signal transmission link connects the signal generating circuit and the RF transceiver circuit to form a third signal path; the signal transmission link connects the signal generating circuit and the cascade output terminal to form a fourth signal path; wherein, when the RF chip is in single-chip mode, the third signal path is used for the RF chip to use the on-chip oscillation signal for radar detection, and when the RF chip is in cascade master mode, the fourth signal path is used for the RF chip to output the on-chip oscillation signal as a cascade synchronization signal to the outside of the RF chip.

[0010] In some embodiments, the signal transmission link includes multiplexed electrical devices to conduct a target signal path, where the target signal path is at least one of the first signal path, the second signal path, the third signal path, and the fourth signal path.

[0011] In some embodiments, the signal transmission link includes a gate switch to conduct a target signal path based on the gate switch, the target signal path being at least one of the first signal path, the second signal path, the third signal path, and the fourth signal path.

[0012] In some embodiments, the cascade synchronization signal includes at least one of a local oscillator signal, a clock signal of an analog-to-digital converter, or a local oscillator control signal.

[0013] In some embodiments, the local oscillator signal is a continuous frequency modulation signal.

[0014] Another embodiment of the present disclosure provides a chip cascade structure, including: a master chip and multiple slave chips; at least one of the multiple slave chips is configured as a first-class slave chip, the first-class slave chip is the radio frequency chip provided in the above embodiment, and the radio frequency chip is in a first cascade slave mode; the cascade output end of the master chip is connected to the cascade input end of the master chip; the first-class slave chip is cascaded with the master chip, and is cascaded with any other slave chip.

[0015] In some embodiments, the master chip is the radio frequency chip provided in the above embodiments, and the radio frequency chip is in a cascade master mode.

[0016] In some embodiments, at least one of the multiple slave chips is configured as a second type slave chip, the second type slave chip is the RF chip provided in the above embodiment, and the RF chip is in a second cascade slave mode; the second type slave chip is cascaded with the first type slave chip.

[0017] In some embodiments, the cascade input terminal and the cascade output terminal of the second type slave chip share the same port.

[0018] Another embodiment of the present disclosure provides a chip packaging structure, which is applied to the packaging of the RF chip provided in the above embodiment, including: multiple output solder balls, each output solder ball is connected to the cascade output end through a corresponding first transmission line, and the lengths of the first transmission lines corresponding to the multiple output solder balls are the same.

[0019] In some embodiments, the chip packaging structure further includes: a plurality of input solder balls, each of which is connected to the cascade input terminal through a corresponding second transmission line, and the second transmission lines corresponding to the plurality of input solder balls have the same length.

[0020] Yet another embodiment of the present disclosure provides a radar device, which includes the chip cascade structure provided by the above embodiment.

[0021] Yet another embodiment of the present disclosure provides an electronic device, which at least includes the radar device provided by the above embodiment. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] One or more embodiments are exemplarily illustrated by pictures in the corresponding drawings, and these exemplified descriptions do not constitute a limitation on the embodiments. Unless otherwise specified, the pictures in the drawings do not constitute a scale limitation. In order to more clearly illustrate the embodiments of the present disclosure or the technical solutions in the traditional technology, the drawings required for use in the embodiments are briefly introduced below. Obviously, the drawings described below are only some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0023] Figure 1 A schematic diagram of the structures of several radio frequency chips provided in one embodiment of the present disclosure;

[0024] Figure 2 A schematic diagram of the structure of a signal transmission link provided by an embodiment of the present disclosure;

[0025] Figure 3 An embodiment of the present disclosure provides Figure 2 The structure diagram of the signal transmission link shown is when the RF chip is in different modes;

[0026] Figure 4A schematic diagram of a structure of a signal transmission link conducted by a switch provided in an embodiment of the present disclosure;

[0027] Figure 5 An embodiment of the present disclosure provides Figure 4 The structure diagram of the signal transmission link shown is when the RF chip is in different modes;

[0028] Figure 6 A schematic diagram of a chip cascade structure provided in one embodiment of the present disclosure;

[0029] Figure 7 A schematic diagram of another chip cascade structure provided in an embodiment of the present disclosure;

[0030] Figure 8 A schematic diagram of a structure of another chip cascade structure provided in an embodiment of the present disclosure;

[0031] Fig. 9 A schematic diagram of the structure of the connection relationship between various signal conditioning circuits and signal transmission links provided in an embodiment of the present disclosure;

[0032] Fig.10 A schematic diagram of the structures of two signal conditioning circuits provided in an embodiment of the present disclosure;

[0033] Fig.11 A signal conditioning circuit provided by an embodiment of the present disclosure and Figure 2 A schematic diagram of the structure of the configuration method in an example signal transmission link;

[0034] Fig.12 Another type of signal conditioning circuit provided by an embodiment of the present disclosure is Figure 2 A schematic diagram of the structure of the configuration method in an example signal transmission link;

[0035] Fig.13 A schematic diagram of the structure of a radio frequency chip with a self-test function provided in one embodiment of the present disclosure;

[0036] Fig.14 An embodiment of the present disclosure provides Figure 2 The structural diagram of the self-test circuit in the example below;

[0037] Fig.15 A schematic diagram of the structure of a radio frequency signal under a first coupler structure provided in an embodiment of the present disclosure;

[0038] Fig.16 A schematic diagram of the structure of a radio frequency signal under a second European coupler structure provided in an embodiment of the present disclosure. DETAILED DESCRIPTION

[0039] As can be seen from the background technology, the number of channels of FMCW radar has an important influence on its performance; it not only affects the angular resolution of the radar, but also affects the transmission power, and thus affects the detection distance of the radar. Therefore, increasing the number of channels of FMCW radar can effectively improve the performance of FMCW radar; specifically, the higher the number of channels of FMCW radar, the higher the angular resolution of the radar, and the longer the detection distance of the radar.

[0040] The number of channels of FMCW radar can be directly increased inside the chip, but too many channels will complicate the design, making chip production more difficult and unable to meet differentiated needs. Therefore, the cascade chip structure consisting of multiple RF chips has become a common practice to increase the number of FMCW radar channels.

[0041] A first embodiment of the present disclosure provides a radio frequency chip. More radio frequency chips can be cascaded in a cascade chip structure formed based on the radio frequency chip, thereby increasing the number of channels in an FMCW radar.

[0042] It can be understood by those skilled in the art that in the various embodiments of the present disclosure, many technical details are provided in order to enable the reader to better understand the present disclosure. However, even without these technical details and various changes and modifications based on the following embodiments, the technical solutions claimed in the present disclosure can be implemented. The division of the following embodiments is for the convenience of description and should not constitute any limitation on the specific implementation of the present disclosure. The various embodiments can be combined with each other and referenced to each other without contradiction.

[0043] The radio frequency chip provided in this embodiment is described in detail below with reference to the accompanying drawings, as follows:

[0044] It should be noted that in each embodiment of the present disclosure, the RF chip can be exemplified as a radar chip, and the RF chip has at least a working mode and a calibration mode. Specifically, the working mode is used to enable the RF chip to operate to realize real-time collection of physical data; the working mode may include: cascade master mode, first cascade slave mode, second cascade slave mode or single chip mode, etc., to adapt to the needs of different application scenarios. Specifically, the calibration mode can be used for factory calibration of the chip in a test environment, or for self-calibration or self-detection during use; the calibration mode may include: cascade calibration mode or single chip calibration mode, etc., in order to achieve the purpose of knowing whether the RF chip can work normally, or even determining the compensation parameters of the RF chip.

[0045] The radio frequency chip provided in this embodiment integrates a signal transmission link, and the radio frequency chip includes a cascade input terminal and a cascade output terminal.

[0046] In some embodiments, reference Figure 1(A), the signal transmission link 111 connects the cascade input terminal MuxIN and the cascade output terminal MuxOUT to form a first signal path. Specifically, the first signal path refers to a signal path in which the off-chip cascade synchronization signal of the RF chip 100 is input into the RF chip 100 through the cascade input terminal MuxIN, passes through the signal transmission link 111 in the RF chip 100, and is output at the cascade output terminal MuxOUT.

[0047] More specifically, when the RF chip 100 is in the first cascade slave mode, the first signal path receives a cascade synchronization signal from outside the RF chip 100 , and outputs the cascade synchronization signal to outside the RF chip 100 through the first signal path.

[0048] The first cascade slave mode represents the non-first and last chips of the cascade structure. For example, for a three-stage cascade structure, the second-stage RF chip 100 is in the first cascade slave mode; for a multi-stage cascade structure, the first-stage RF chip 100 is the first-stage chip, and the last-stage RF chip 100 is the last-stage chip. Except for the first-stage chip and the last-stage chip, all other RF chips 100 are in the first cascade slave mode.

[0049] The RF chip provided in this embodiment is additionally provided with a first cascade slave mode, and the first cascade slave mode can output a cascade synchronization signal through the cascade output terminal MuxOUT, so that more RF chips 100 can be connected to the cascade structure formed based on the RF chip, thereby increasing the number of channels in the FMCW radar.

[0050] In some embodiments, reference Figure 1 (B), with Figure 1 (A) The difference is that the RF chip 100 also includes a RF transceiver circuit 103. The RF transceiver circuit 103 is configured to generate a RF signal based on the cascade synchronization signal transmitted by the signal transmission link 121, so as to enable the RF chip 100 to transmit and receive RF signals. In this way, the RF chip can work in coordination in a certain cascade mode of multiple chips, such as realizing the real-time collection of physical data by the RF chip in the cascade mode.

[0051] The signal transmission link 121 connects the cascade input terminal MuxIN and the RF transceiver circuit 103 to form a second signal path. Specifically, the second signal path refers to the signal path in which the RF chip 100 transmits the cascade synchronization signal to the RF transceiver circuit 103 based on the signal transmission link 121, and the RF transceiver circuit 103 performs radar detection based on the cascade synchronization signal.

[0052] When the RF chip 100 is in the first cascade slave mode or the second cascade slave mode, the second signal path is used for the RF chip 100 to perform radar detection using the cascade synchronization signal.

[0053] Taking the two-level cascade structure as an example, Figure 1 The RF chip 100 shown in (B) is in the second cascade slave mode, which uses the signal transmission link 121 to receive the cascade synchronization signal of the MuxIN interface and transmit it to the RF transceiver circuit 103. Among them, taking the cascade synchronization signal as a local oscillator signal as an example, the RF transceiver circuit 103 can convert the local oscillator signal into a radar detection signal for transmission. Taking the cascade synchronization signal as a clock synchronization signal as an example, the RF transceiver circuit 103 can use the clock synchronization signal to perform digital conversion on the received signal containing the echo signal. For example, in a three-stage cascade structure, Figure 1 The RF chip 100 shown in (B) is in the first cascade slave mode or the second cascade slave mode. Taking the RF chip 100 in the first cascade slave mode as an example, the cascade input terminal MuxIn of the RF chip 100 receives the cascade synchronization signal from the chip in the cascade master mode, and transmits it to the cascade output terminal MUXOUT interface and the RF transceiver circuit 103 through the signal transmission link 121. Taking the RF chip 100 in the second cascade slave mode as an example, the cascade input terminal MuxIn of the RF chip 100 receives the cascade synchronization signal from the chip in the cascade master mode, and transmits it to the RF transceiver circuit 103 through the signal transmission link 121.

[0054] In some embodiments, reference Figure 1 (C), with Figure 1 The difference between (A) and (B) is that the RF chip 100 further includes a signal generating circuit 102 and a RF transceiver circuit 113. The description of the RF transceiver circuit 113 is the same as Figure 1 (B), which will not be described in detail here. The signal generating circuit 102 is configured to generate an on-chip oscillation signal, which can be used as a cascade synchronization signal in any cascade mode.

[0055] The signal transmission link 131 connects the signal generating circuit 102 and the RF transceiver circuit 113 to form a third signal path. Specifically, the third signal path refers to a signal path for the RF chip 100 to perform radar detection using the internal oscillation signal generated by the signal generating circuit 102.

[0056] More specifically, when the RF chip 100 is in single-chip mode, the third signal path is used for the RF chip 100 to perform radar detection using an internal oscillation signal. The single-chip mode represents a working state in which the RF chip 100 is in a non-cascaded state and a single chip works independently.

[0057] The signal transmission link 131 connects the signal generating circuit 102 and the cascade output terminal MuxOUT to form a fourth signal path. Specifically, the fourth signal path represents a signal path for the RF chip 100 to output the internal oscillation signal as a cascade synchronization signal to the outside of the RF chip 100.

[0058] More specifically, when the RF chip 100 is in the cascade master mode, the fourth signal path is used for the RF chip 100 to output the internal oscillation signal as the cascade synchronization signal to the outside of the RF chip 100 .

[0059] For the first signal path, the second signal path, the third signal path and the fourth signal path transmitted via the signal transmission link 111 (121, 131), in some embodiments, the signal transmission link 111 can constitute the first signal path, the second signal path, the third signal path and the fourth signal path through independent circuits; in other embodiments, the signal transmission link 111 can also constitute the first signal path, the second signal path, the third signal path and the fourth signal path through partially multiplexed circuits.

[0060] The signal transmission link 111 can also form a first signal path, a second signal path, a third signal path and a fourth signal path through a partially multiplexed circuit. In some embodiments, the signal transmission link 111 includes multiplexed electrical devices to conduct the target signal path, and the target signal path is at least one of the first signal path, the second signal path, the third signal path and the fourth signal path.

[0061] In one example, refer to Figure 2 The signal transmission link 111 includes: a first amplifier A1, whose input end is connected to the signal generating circuit, and whose output end is connected to the first node A; a second amplifier A2, whose input end is connected to the first node A, and whose output end is connected to the second node B; a third amplifier A3, whose input end is connected to the second node B, and whose output end is connected to the radio frequency transceiver circuit; a fourth amplifier A4, whose input end is connected to the cascade input end MuxIN, and whose output end is connected to the second node B; a fifth amplifier A5, whose input end is connected to the second node B, and whose output end is connected to the first node A; a sixth amplifier A6, whose input end is connected to the first node A, and whose output end is connected to the cascade output end MuxOUT.

[0062] for Figure 2 The structure of the signal transmission link 111 shown in FIG. Figure 3 (A), the first amplifier A1 is connected to the second amplifier A2, and the second amplifier A2 is connected to the third amplifier A3 to form a third signal path; Figure 3 (B), the first amplifier A1 is connected to the sixth amplifier A6 to form a fourth signal path; Figure 3 (C), the fourth amplifier A4 is connected to the fifth amplifier A5, and the fifth amplifier A5 is connected to the sixth amplifier A6 to form a first signal path; Figure 3 (B) Figure 3 (C) and Figure 3 (D), the fourth amplifier A4 is connected to the third amplifier A3 to form a second signal path.

[0063] Specifically, Figure 3 (A) is a schematic diagram showing the amplifier access of the RF chip 100 in single-chip mode, Figure 3 (B) is a schematic diagram showing the amplifier access of the RF chip 100 in the cascade main mode, Figure 3 (C) is a schematic diagram showing the amplifier access of the RF chip 100 in the first cascade slave mode, Figure 3 (D) is a schematic diagram showing the amplifier access of the RF chip 100 in the second cascade slave mode.

[0064] It should be noted that in Figure 3 (A)~ Figure 3 In the example of the accompanying figure (D), the amplifier formed by the solid line represents the amplifier that is actually connected, and the amplifier formed by the dotted line represents the amplifier that is not connected. In some embodiments, whether the amplifier is connected to the circuit can be controlled by controlling whether power is provided to the amplifier. In other embodiments, the corresponding path can be turned on by a switch to control whether the amplifier is connected to the circuit.

[0065] For the solution of controlling whether the amplifier is connected to the circuit by conducting the corresponding path through the switch, in some embodiments, the signal transmission link 111 includes a gating switch to conduct the target signal path based on the gating switch, and the target signal path is at least one of the first signal path, the second signal path, the third signal path and the fourth signal path. The gating switch is exemplified by a MOS tube or any device with a high impedance state.

[0066] refer to Figure 4 The signal transmission link 111 includes: a first amplifier B1, whose input end is connected to the signal generating circuit, and whose output end is connected to the first end of the fourth selection switch S04, and whose second end is connected to the first node A; a third selection switch S03, whose first end is connected to the first node A, and whose second end is connected to the input end of the second amplifier B2, and whose output end is connected to the second node B; a third amplifier B3, whose input end is connected to the second node B, and whose output end is connected to the radio frequency transceiver circuit; a fourth amplifier B4, whose input end is connected to the cascade input end MuxIN, and whose output end is connected to the second node B; a first selection switch S01, whose first end is connected to the second node B, and whose second end is connected to the input end of the fifth amplifier B5, and whose output end is connected to the first node A; a second selection switch S02, whose first end is connected to the first node A, and whose second end is connected to the input end of the sixth amplifier B6, and whose output end is connected to the cascade output end MuxOUT.

[0067] for Figure 4 The structure of the signal transmission link 111 shown in FIG. Figure 5(A), when the first selection switch S01 and the second selection switch S02 are turned off, and the third selection switch S03 and the fourth selection switch S04 are closed, the third signal path is turned on; Figure 5 (B), when the first selection switch S01 and the third selection switch S03 are turned off, and the second selection switch S02 and the fourth selection switch S04 are closed, the second signal path and the fourth signal path are turned on; Figure 5 (C), when the first selection switch S01 and the second selection switch S02 are closed, and the third selection switch S03 and the fourth selection switch S04 are opened, the first signal path and the second signal path are connected; Figure 5 (D), when the first selection switch S01, the second selection switch S02, the third selection switch S03 and the fourth selection switch S04 are turned off, the second signal path is turned on.

[0068] Specifically, Figure 5 (A) is a schematic diagram showing the amplifier access of the RF chip 100 in single-chip mode, Figure 5 (B) is a schematic diagram showing the amplifier access of the RF chip 100 in the cascade main mode, Figure 5 (C) is a schematic diagram showing the amplifier access of the RF chip 100 in the first cascade slave mode, Figure 5 (D) is a schematic diagram showing the amplifier access of the RF chip 100 in the second cascade slave mode.

[0069] It should be noted that in Figure 5 (A)~ Figure 5 In the example of the figure (D), the amplifiers formed by solid lines represent the amplifiers that are actually connected, and the amplifiers formed by dotted lines represent the amplifiers that are not connected. Among them, for the fourth amplifier B4, when the cascade input terminal MuxIN has no input, the fourth amplifier B4 can be regarded as a state of being not connected.

[0070] It should be noted that configuring at least one amplifier on each signal path is not only beneficial for the RF chip to provide effective signal gain in different working modes, but also beneficial for providing impedance matching under different mode switching. In addition, the amplifier configured on the signal transmission link is beneficial to the arrangement range of the off-chip circuit in the cascade structure when the RF chip is configured in any cascade mode. For example, the amplifier is used to increase the swing amplitude of the cascade synchronization signal, which makes it easier for multiple RF chips in the cascade structure to be arranged on the PCB board in a more sparse manner, thereby improving the isolation effect between signals transmitted between boards.

[0071] Taking the RF chip 100 as a radar chip as an example, in the cascade mode, multiple synchronization signals in the radar chip are cascaded and synchronized. For example, the cascade synchronization signal includes at least one of: a local oscillator signal, a clock signal of an analog-to-digital converter, or a local oscillator control signal. Among them, the local oscillator control signal is used for the transceiver circuit of the cascaded multiple radar chips to start / end operation to control the transceiver circuit of the radar to work synchronously with the transceiver circuits of other cascaded radars. Using the cascaded synchronized local oscillator signal, the cascaded multiple radar chips will synchronously convert and amplify the local oscillator signal to form a radar signal (i.e., a radio frequency signal) and transmit it to free space; or use the cascaded synchronized local oscillator signal to down-convert the received reflected signal to obtain an intermediate frequency signal. The cascaded synchronized clock signal enables the ADC in the cascaded multiple radar chips to synchronously convert the intermediate frequency signal into a digital signal, thereby reducing the phase difference of the intermediate frequency signal of each chip and reducing the possibility of false target detection. In this way, a large-scale, high-precision detection purpose is achieved.

[0072] In some embodiments, the local oscillator signal is a frequency modulated continuous wave (FMCW) signal.

[0073] The RF chip provided in this embodiment is additionally provided with a first cascade slave mode, and the first cascade slave mode can output a cascade synchronization signal through a cascade output terminal, so that more RF chips can be connected to the cascade structure formed based on the RF chip, thereby increasing the number of channels in the FMCW radar.

[0074] It should be noted that the features disclosed in the radio frequency chip provided in the above embodiments can be arbitrarily combined without conflict to obtain a new radio frequency chip embodiment.

[0075] The second embodiment of the present disclosure further provides a chip cascade structure, in which more RF chips can be connected, thereby increasing the number of channels in the FMCW radar.

[0076] The chip cascade structure provided in this embodiment is described in detail below in conjunction with the accompanying drawings, as follows:

[0077] The chip cascade structure includes a master chip and multiple slave chips; wherein at least one of the multiple slave chips is configured as a first-class slave chip, the first-class slave chip is the RF chip described in the first embodiment above, and the RF chip is in a first cascade slave mode; the cascade output terminal MuxOUT of the master chip is connected to the cascade input terminal MuxIN of the master chip, the first-class slave chip is cascaded with the master chip, and is cascaded with any other slave chip.

[0078] In one example, refer to Figure 6, the RF chip (B) acts as the master chip, the cascade output terminal MuxOUT passes through the first external power divider to connect the cascade input terminal MuxIN of the master chip and the cascade input terminal MuxIN of the RF chip (C), the RF chip (C) acts as a first-class slave chip, the cascade output terminal MuxOUT of the RF chip (C) passes through the second external power divider to connect the cascade input terminals MuxIN of multiple RF chips (D), and the RF chip (D) is a slave chip other than the first-class slave chip.

[0079] Among them, the RF chip (B) transmits the cascade synchronization signal to the RF chip (B) and the RF chip (C) based on the internal oscillation signal. The RF chip (B) generates an RF signal based on the returned cascade synchronization signal. The RF chip (C) generates an RF signal based on the cascade synchronization signal, and outputs the cascade synchronization signal through the cascade output terminal to provide it to multiple RF chips (D). The multiple RF chips (D) respectively generate multiple RF signals based on the cascade synchronization signal.

[0080] It should be noted that in the subsequent figures, the off-chip power divider is no longer shown between the cascaded RF chips, and those skilled in the art can Figure 6 The off-chip power divider is set up in the same manner as shown.

[0081] In one example, refer to Figure 7 , the RF chip (B) serves as the main chip, the cascade output terminal MuxOUT is connected to the cascade input terminal MuxIN of the main chip and the cascade input terminal MuxIN of the RF chip (C), the cascade output terminal MuxOUT of the RF chip (C) is connected to the cascade input terminal MuxIN of the next-level RF chip (C) to form a series structure of multiple RF chips (C), and the cascade output terminal MuxOUT of the last-level RF chip (C) is connected to the cascade input terminal MuxIN of multiple RF chips (D).

[0082] In one example, refer to Figure 8 The RF chip (B) serves as the main chip, and the cascade output terminal MuxOUT is connected to the cascade input terminal MuxIN of the main chip and the cascade input terminals MuxIN of multiple RF chips (C) to form a parallel structure of multiple RF chips (C), and the cascade output terminal MuxOUT of each level of RF chip (C) is connected to the cascade input terminal MuxIN of multiple RF chips (D).

[0083] In one example, the RF chip (C) may be combined with Figure 7 and Figure 8 There are both serial and parallel connections to form a chip cascade structure. Figure 6 to Figure 8In the embodiment, the number of RF chips (D) connected to the RF chip (C) is two, which is only used for exemplary description; in specific applications, the number of RF chips (D) connected to the RF chip (C) can be any number.

[0084] It should be noted that in order to ensure synchronization of the cascade synchronization signals received by each chip, the lengths of the parallel signal lines are the same. Figure 6 As shown, the cascade output terminal MuxOUT of the RF chip (B) is connected to the cascade input terminal MuxIN of the RF chip (B) as the first signal line, and the cascade output terminal MuxOUT of the RF chip (B) is connected to the cascade input terminal MuxIN of the RF chip (C) as the second signal line. The first signal line and the second signal line are parallel signal lines, that is, the line lengths of the first signal line and the second signal line are equal.

[0085] In some embodiments, the master chip is the RF chip provided in the first embodiment, and the RF chip is in cascade master mode. That is, the RF chip (B) is configured based on the RF chip provided in the first embodiment, and the RF chip is in cascade master mode.

[0086] In some embodiments, at least one of the multiple slave chips is configured as a second type of slave chip, the second type of slave chip is the RF chip provided in the first embodiment, and the RF chip is in the second cascade slave mode, and the second type of slave chip is cascaded with the first type of slave chip. That is, some or all of the RF chips (D) are arranged based on the RF chip provided in the first embodiment, and the RF chip is in the second cascade slave mode.

[0087] refer to Figure 6 to Figure 8 As can be seen from the example, the RF chip (D) serves as the last-stage chip of the chip cascade structure, and its cascade output terminal MuxOUT no longer outputs the cascade synchronization signal, that is, the vacant port of the cascade output terminal MuxOUT of the second-type slave chip; in some embodiments, the cascade input terminal MuxIN and the cascade output terminal MuxOUT of the second-type slave chip share the same port to reduce the layout area of ​​the chip cascade structure.

[0088] It is not difficult to find that this embodiment can be implemented in conjunction with the RF chip provided in the first embodiment. The relevant technical details mentioned in the first embodiment are still valid in this embodiment, and in order to reduce repetition, they are not repeated here. In addition, the features disclosed in the chip cascade structure provided in the above embodiments can be arbitrarily combined without conflict, and a new chip cascade structure embodiment can be obtained.

[0089] The third embodiment of the present disclosure provides a chip packaging structure, which is applied to the packaging of the RF chip provided in the above embodiments. The chip packaging structure includes multiple output solder balls, each output solder ball is connected to the cascade output terminal MuxOUT through a corresponding first transmission line, and the lengths of the first transmission lines corresponding to the multiple output solder balls are the same.

[0090] Specifically, since the output solder balls are connected to the corresponding cascade output terminals MuxOUT, the multiple output solder balls can be regarded as multiple cascade output terminals MuxOUT of the packaged RF chip, and the output solder balls are distributed at different positions to simplify the wiring during the cascading process of the RF chip.

[0091] In some embodiments, the chip packaging structure further includes a plurality of input solder balls, each of which is connected to the cascade input terminal MuxIN via a corresponding second transmission line, and the second transmission lines corresponding to the plurality of input solder balls have the same length.

[0092] Specifically, since the input solder balls are connected to the corresponding cascade input terminals MuxIN, the multiple input solder balls can be regarded as multiple cascade input terminals MuxIN of the packaged RF chip, and the input solder balls are distributed at different positions to simplify the wiring during the cascading process of the RF chip.

[0093] In specific applications, since the input solder balls and output solder balls are set at different positions, the "turns" of the routing can be avoided as much as possible during the cascading of the RF chips to form a chip cascade structure, thereby simplifying the wiring during the cascading of the RF chips.

[0094] Based on the foregoing content, it can be seen that the higher the number of channels of the FMCW radar, the higher the angular resolution of the radar. The cascade chip structure composed of multiple stages of RF chips is conducive to detecting a long and wide range, which improves the working efficiency of the radar. The fourth embodiment of the present disclosure provides a RF chip, based on the cascade chip structure composed of the RF chip, which can ensure the amplitude and phase consistency of the cascade synchronization signal in each cascade chip.

[0095] The radio frequency chip provided in this embodiment is described in detail below with reference to the accompanying drawings, as follows:

[0096] The RF chip integrates a signal transmission link and a signal conditioning circuit, and includes a cascade input terminal and a cascade output terminal. The description of the signal transmission link can be found in the first embodiment of the present disclosure, and will not be repeated in this embodiment.

[0097] Specifically, the signal transmission link connects the cascade input terminal and the cascade output terminal. In any cascade mode of the RF chip, the signal transmission link is used to transmit the cascade synchronization signal, the cascade input terminal is used to receive the cascade synchronization signal from outside the RF chip, and the cascade output terminal is used to transmit the cascade synchronization signal to the outside of the RF chip; the signal adjustment circuit is arranged in the signal transmission link, and the signal adjustment circuit is configured to compensate for the cascade adaptation of the amplitude and phase of the cascade synchronization signal caused by the transmission between boards.

[0098] Specifically, the cascade mismatch includes: the phase of the cascade synchronization signal received by the RF chip in the cascade mode does not meet the preset cascade phase error, or the phase group delay of the cascade synchronization signal received by the RF chip in the cascade mode does not meet the preset cascade group delay deviation, or the amplitude of the cascade synchronization signal received by the RF chip in the cascade mode is lower than the preset threshold.

[0099] The RF chip provided in this embodiment adjusts the phase and amplitude / power of the cascade synchronization signal received by the cascade signal through an additional signal adjustment circuit, thereby ensuring the amplitude and phase consistency of the cascade synchronization signal in each cascade chip.

[0100] Among them, the cascade mode of the RF chip includes at least one of a cascade master mode, a first cascade slave mode and a second cascade slave mode. Among them, the first cascade slave mode represents the RF chip in the non-first and last chips in the cascade structure. The cascade master mode represents the first chip of the RF chip in the cascade structure. The second cascade slave mode represents the last chip of the RF chip in the cascade structure.

[0101] Since the signal transmission link connects the cascade input terminal MuxIN and the cascade output terminal MuxOUT, and the signal conditioning circuit is arranged in the signal transmission link, reference Fig. 9 (B) and Fig. 9 (D) The signal conditioning circuit 212 can be disposed at the input port of the signal transmission link 201 and the cascade input terminal MuxIN, and the signal conditioning circuit 232 can also be disposed at the output port of the signal transmission link 201 and the cascade output terminal MuxOUT.

[0102] Specifically, the signal adjustment circuit 212 (232) is used to adjust the amplitude and phase of the cascade synchronization signal transmitted by the radio frequency chip to ensure the consistency of the amplitude and phase of the cascade synchronization signal in each cascade chip. Fig. 9 (B), if the signal conditioning circuit 212 is provided at the input port of the signal transmission link 201 and the cascade input terminal MuxIN, the signal conditioning circuit 212 is used to adjust the consistency of the amplitude and phase of the cascade synchronization signal input into the RF chip; refer to Fig. 9 (D) If the signal adjustment circuit 232 is provided at the output port between the signal transmission link 201 and the cascade output terminal MuxOUT, the signal adjustment circuit 232 is used to adjust the consistency of the amplitude and phase of the cascade synchronization signal outputted from the RF chip to the outside of the chip.

[0103] In combination with the content of the first embodiment, it can be known that in some embodiments, the radio frequency chip further includes: a signal generating circuit and a radio frequency transceiver circuit. Among them, the signal generating circuit is connected to the signal transmission link 201, and is used to generate an internal oscillation signal and output it to the signal transmission link 201; the radio frequency transceiver circuit is connected to the signal transmission link 201, and uses the cascade synchronization signal or the internal oscillation signal output by the signal transmission link 201 to perform radar detection.

[0104] refer to Fig. 9 (A) and Fig. 9 (C) The signal conditioning circuit 202 can be arranged at an input port where the signal transmission link 201 is connected to the signal generating circuit, and the signal conditioning circuit 222 can also be arranged at an output port where the signal transmission link 201 is connected to the RF transceiver circuit.

[0105] Specifically, the signal adjustment circuit 202 (222) is used to adjust the amplitude and phase of the cascade synchronization signal transmitted by the radio frequency chip to ensure the consistency of the amplitude and phase of the cascade synchronization signal in each cascade chip. Fig. 9 (A), if the signal conditioning circuit 202 is provided at the input port where the signal transmission link 201 is connected to the signal generating circuit, the signal conditioning circuit 202 adjusts the amplitude and phase of the on-chip oscillation signal generated by the signal generating circuit to adjust the consistency of the amplitude and phase of the cascade synchronization signal; refer to Fig. 9 (C) If the signal conditioning circuit 222 is provided at the output port where the signal transmission link 201 is connected to the RF transceiver circuit, the signal conditioning circuit 222 is used to adjust the consistency of the amplitude and phase of the cascade synchronization signal used for the RF signal operation.

[0106] Since the purpose of the RF chip is to use the cascade synchronization signal for radar detection, preferably, the signal conditioning circuit is as follows Fig. 9 (C) Configuration so that the cascade synchronization signal for radar detection is synchronized and then detected.

[0107] The signal conditioning circuit 202 (212, 222, 232) is used to adjust the amplitude and phase of the cascade synchronization signal. In some embodiments, reference Fig.10 The signal conditioning circuit includes a delay circuit 205 and a variable gain amplifier circuit 206 which are arranged in series.

[0108] Specifically, in one example, reference Fig.10 (A), the input end of the variable gain amplifier circuit 206 is used as the input end of the signal conditioning circuit, the output end of the variable gain amplifier circuit 206 is connected to the input end of the delay circuit 205, and the output end of the delay circuit 205 is used as the output end of the signal conditioning circuit. Fig.10(B) The input end of the delay circuit 205 serves as the input end of the signal conditioning circuit, the output end of the delay circuit 205 is connected to the input end of the variable gain amplifier circuit 206, and the output end of the variable gain amplifier circuit 206 serves as the output end of the signal conditioning circuit.

[0109] More specifically, the delay circuit 205 is used to perform group delay on the cascade synchronization signal to adjust the phase and / or delay of the cascade synchronization signal, and the variable gain amplifier circuit 206 has an adjustable gain factor to adjust the power / amplitude of the cascade synchronization signal. In some embodiments, the delay circuit 205 can be configured as an IQ phase shifter, a transmission line phase shifter, etc. In some embodiments, the variable gain amplifier circuit 206 can change the gain factor of the variable gain amplifier circuit 206 based on adjusting the power supply voltage, or change the gain factor of the variable gain amplifier circuit 206 based on the access circuit in the adjustment circuit.

[0110] Combination Figure 2 and Fig. 9 For example, refer to Fig.11 and Fig.12 , the signal conditioning circuit 301 is at least arranged in at least one of the following paths: on the path of the signal generating circuit and the radio frequency transceiver circuit connected to the signal transmission link 201, that is, the third signal path; on the path of the signal generating circuit and the cascade output terminal MuxOUT connected to the signal transmission link 201, that is, the fourth signal path; on the path of the cascade input terminal MuxIN and the cascade output terminal MuxOUT connected to the signal transmission link 201, that is, the first signal path; on the path of the radio frequency transceiver circuit and the cascade input terminal MuxIN connected to the signal transmission link 201, that is, the second signal path.

[0111] If the signal conditioning circuit 301 is disposed in the first signal path, refer to Fig.11 (B), the signal transmission link 201 includes: a first amplifier A1, whose input end is connected to the signal generating circuit, and whose output end is connected to the first node A; a second amplifier A2, whose input end is connected to the first node A, and whose output end is connected to the second node B; a third amplifier A3, whose input end is connected to the second node B, and whose output end is connected to the RF transceiver circuit; a fourth amplifier A4, whose input end is connected to the cascade input end MuxIN, whose output end is connected to the input end of the signal conditioning circuit 301, and whose output end is connected to the second node B; a fifth amplifier A5, whose input end is connected to the second node B, and whose output end is connected to the first node A; a sixth amplifier A6, whose input end is connected to the first node A, and whose output end is connected to the cascade output end MuxOUT. Reference Fig.12(B), the signal transmission link 201 includes: a first amplifier A1, whose input end is connected to the signal generating circuit, and whose output end is connected to the first node A; a second amplifier A2, whose input end is connected to the first node A, and whose output end is connected to the second node B; a third amplifier A3, whose input end is connected to the second node B, and whose output end is connected to the RF transceiver circuit; a fourth amplifier A4, whose input end is connected to the output end of the signal conditioning circuit 301, whose input end is connected to the cascade input end MuxIN, and whose output end is connected to the second node B; a fifth amplifier A5, whose input end is connected to the second node B, and whose output end is connected to the first node A; a sixth amplifier A6, whose input end is connected to the first node A, and whose output end is connected to the cascade output end MuxOUT.

[0112] If the signal conditioning circuit 301 is disposed in the second signal path, refer to Fig.11 (C), the signal transmission link 201 includes: a first amplifier A1, whose input end is connected to the signal generating circuit, and whose output end is connected to the first node A; a second amplifier A2, whose input end is connected to the first node A, and whose output end is connected to the second node B; a third amplifier A3, whose input end is connected to the output end of the signal conditioning circuit 301, whose input end is connected to the second node B, and whose output end is connected to the RF transceiver circuit; a fourth amplifier A4, whose input end is connected to the cascade input end MuxIN, and whose output end is connected to the second node B; a fifth amplifier A5, whose input end is connected to the second node B, and whose output end is connected to the first node A; a sixth amplifier A6, whose input end is connected to the first node A, and whose output end is connected to the cascade output end MuxOUT. Reference Fig.12 (C), the signal transmission link 201 includes: a first amplifier A1, whose input end is connected to the signal generating circuit, and whose output end is connected to the first node A; a second amplifier A2, whose input end is connected to the first node A, and whose output end is connected to the second node B; a third amplifier A3, whose input end is connected to the second node B, and whose output end is connected to the input end of the signal conditioning circuit 301, and whose output end is connected to the RF transceiver circuit; a fourth amplifier A4, whose input end is connected to the cascade input end MuxIN, and whose output end is connected to the second node B; a fifth amplifier A5, whose input end is connected to the second node B, and whose output end is connected to the first node A; a sixth amplifier A6, whose input end is connected to the first node A, and whose output end is connected to the cascade output end MuxOUT.

[0113] If the signal conditioning circuit 301 is disposed in the third signal path, refer to Fig.11(A), the signal transmission link 201 includes: a first amplifier A1, whose input end is connected to the signal generating circuit, whose output end is connected to the input end of the signal conditioning circuit 301, and whose output end is connected to the first node A; a second amplifier A2, whose input end is connected to the first node A, and whose output end is connected to the second node B; a third amplifier A3, whose input end is connected to the second node B, and whose output end is connected to the RF transceiver circuit; a fourth amplifier A4, whose input end is connected to the cascade input end MuxIN, and whose output end is connected to the second node B; a fifth amplifier A5, whose input end is connected to the second node B, and whose output end is connected to the first node A; a sixth amplifier A6, whose input end is connected to the first node A, and whose output end is connected to the cascade output end MuxOUT. Reference Fig.12 (A), the signal transmission link 201 includes: a first amplifier A1, whose input end is connected to the output end of the signal conditioning circuit 301, the input end of the signal conditioning circuit 301 is connected to the signal generating circuit, and the output end of the first amplifier A1 is connected to the first node A; a second amplifier A2, whose input end is connected to the first node A, and whose output end is connected to the second node B; a third amplifier A3, whose input end is connected to the second node B, and whose output end is connected to the RF transceiver circuit; a fourth amplifier A4, whose input end is connected to the cascade input end MuxIN, and whose output end is connected to the second node B; a fifth amplifier A5, whose input end is connected to the second node B, and whose output end is connected to the first node A; a sixth amplifier A6, whose input end is connected to the first node A, and whose output end is connected to the cascade output end MuxOUT.

[0114] If the signal conditioning circuit 301 is disposed in the fourth signal path, refer to Fig.11 (D), the signal transmission link 201 includes: a first amplifier A1, whose input end is connected to the signal generating circuit, and whose output end is connected to the first node A; a second amplifier A2, whose input end is connected to the first node A, and whose output end is connected to the second node B; a third amplifier A3, whose input end is connected to the second node B, and whose output end is connected to the RF transceiver circuit; a fourth amplifier A4, whose input end is connected to the cascade input end MuxIN, and whose output end is connected to the second node B; a fifth amplifier A5, whose input end is connected to the second node B, and whose output end is connected to the first node A; a sixth amplifier A6, whose input end is connected to the output end of the signal conditioning circuit 301, whose input end is connected to the first node A, and whose output end is connected to the cascade output end MuxOUT. Reference Fig.12(D), the signal transmission link 201 includes: a first amplifier A1, whose input end is connected to the signal generating circuit, and whose output end is connected to the first node A; a second amplifier A2, whose input end is connected to the first node A, and whose output end is connected to the second node B; a third amplifier A3, whose input end is connected to the second node B, and whose output end is connected to the RF transceiver circuit; a fourth amplifier A4, whose input end is connected to the cascade input end MuxIN, and whose output end is connected to the second node B; a fifth amplifier A5, whose input end is connected to the second node B, and whose output end is connected to the first node A; a sixth amplifier A6, whose input end is connected to the first node A, and whose output end is connected to the input end of the signal conditioning circuit 301, and whose output end is connected to the cascade output end MuxOUT.

[0115] Taking the RF chip 100 as a radar chip as an example, in the cascade mode, multiple synchronization signals in the radar chip are cascaded and synchronized. For example, the cascade synchronization signal includes at least one of: a local oscillator signal, a clock signal of an analog-to-digital converter, or a local oscillator control signal. Among them, the local oscillator control signal is used for the transceiver circuit of the cascaded multiple radar chips to start / end operation to control the transceiver circuit of the radar to work synchronously with the transceiver circuits of other cascaded radars. Using the cascaded synchronized local oscillator signal, the cascaded multiple radar chips will synchronously convert and amplify the local oscillator signal to form a radar signal (i.e., a radio frequency signal) and transmit it to free space; or use the cascaded synchronized local oscillator signal to down-convert the received reflected signal to obtain an intermediate frequency signal. The cascaded synchronized clock signal enables the ADC in the cascaded multiple radar chips to synchronously convert the intermediate frequency signal into a digital signal, thereby reducing the phase difference of the intermediate frequency signal of each chip and reducing the possibility of false target detection. In this way, a large-scale, high-precision detection purpose is achieved.

[0116] In some embodiments, the local oscillator signal is a frequency modulated continuous wave (FMCW) signal.

[0117] The RF chip provided in this embodiment adjusts the phase and amplitude / power of the cascade synchronization signal received by the cascade signal through an additional signal adjustment circuit, thereby ensuring the amplitude and phase consistency of the cascade synchronization signal in each cascade chip.

[0118] It should be noted that the features disclosed in the radio frequency chip provided in the above embodiments can be arbitrarily combined without conflict to obtain a new radio frequency chip embodiment. In addition, this embodiment can be implemented in conjunction with the radio frequency chip provided in the first embodiment. The relevant technical details mentioned in the first embodiment are still valid in this embodiment, and in order to reduce repetition, they are not repeated here.

[0119] The fifth embodiment of the present disclosure also provides a chip cascade structure, in which the RF chip in the chip cascade structure adjusts the phase and amplitude / power of the cascade synchronization signal received by the cascade signal through an additional signal adjustment circuit, thereby ensuring the amplitude and phase consistency of the cascade synchronization signal in each cascade chip.

[0120] Specifically, the chip cascade structure includes at least two cascaded chips, wherein at least one chip is the radio frequency chip provided in the fourth embodiment.

[0121] More specifically, assuming that the chip cascade structure includes cascaded RF chip A and RF chip B, if RF chip A is the RF chip provided in the above embodiment, then RF chip A adjusts the phase and amplitude / power of the internal cascade synchronization signal so that the phase and amplitude / power of the cascade synchronization signal in RF chip A and RF chip B are the same.

[0122] In some embodiments, the cascade chip structure provided in this embodiment may also be applied to the second embodiment, that is, at least one master chip or slave chip in the second embodiment is the radio frequency chip provided in the fourth embodiment.

[0123] That is, on the basis of ensuring the amplitude and phase consistency of the cascade synchronization signal in each cascade chip, more RF chips can be connected in the chip cascade structure, thereby increasing the number of channels in the FMCW radar.

[0124] In addition, based on the cascading requirements of the RF chip, the sixth embodiment of the present disclosure also provides a RF chip, so that the RF chip can perform functional self-test in cascading mode in single-chip mode, thereby ensuring the accuracy of the chip cascade structure constructed based on the RF chip.

[0125] The radio frequency chip provided in this embodiment is described in detail below with reference to the accompanying drawings, as follows:

[0126] refer to Fig.13 The RF chip integrates a signal transmission link 401 and a self-test circuit 402, and includes a cascade input terminal MuxIN and a cascade output terminal MuxOUT, wherein the description of the signal transmission link 401 can be found in the first embodiment of the present disclosure, and will not be repeated in this embodiment.

[0127] The signal transmission link 401 connects the cascade input terminal MuxIN and the cascade output terminal MuxOUT to receive the cascade synchronization signal from outside the chip and / or output the cascade synchronization signal to the outside of the chip; in the self-test mode of the RF chip, the self-test circuit 402 is coupled to the signal transmission link 401, and the self-test circuit 402 is configured to collect the cascade synchronization signal transmitted in the RF chip, and detect whether the working state of the RF chip in the cascade mode is abnormal based on the cascade synchronization signal.

[0128] In one example, combining Figure 2 Examples, references Fig.14 , the self-test circuit 402 at least includes an impedance circuit 412. Specifically, the impedance circuit 412 is configured to simulate the off-chip loss of the cascade synchronization signal when the RF chip is in the cascade mode, collect the cascade synchronization signal received by the RF chip, and detect whether the working state in the cascade mode is abnormal based on the amplitude / phase of the cascade synchronization signal.

[0129] More specifically, since the impedance circuit 412 is used to simulate the off-chip transmission loss of the cascade synchronization signal in the cascade mode, if the amplitude / phase loss of the cascade synchronization signal received by the RF chip meets the expected loss in the cascade mode, it proves that the RF chip can work normally in the cascade mode; if the amplitude / phase loss of the cascade synchronization signal received by the RF chip does not meet the expected loss in the cascade mode, it proves that the RF chip cannot work normally in the cascade mode.

[0130] The RF chip provided in this embodiment simulates the off-chip transmission loss of the cascade synchronization signal of the RF chip in the cascade mode through a self-test circuit, so that the RF chip can perform functional self-test in the cascade mode in the single-chip mode, thereby ensuring the accuracy of the chip cascade structure based on the RF chip.

[0131] In some embodiments, the impedance circuit 412 is configured as an adjustable impedance circuit, that is, the self-test circuit includes an adjustable impedance circuit, wherein the input end of the adjustable impedance circuit is coupled to the cascade output end MuxOUT, the output end is coupled to the cascade input end MuxIN, and the adjustable impedance circuit 412 is configured to adjust the loss of the cascade output end MuxOUT and / or the cascade input end MuxIN to the cascade synchronization signal. The impedance of the impedance circuit 412 is adjustable, which makes it easier to achieve the matching of the loss of the cascade synchronization signal between the impedance circuit 412 and the off-chip impedance connected to the cascade output end MuxOUT and / or the cascade input end MuxIN.

[0132] In some embodiments, the adjustable impedance circuit is configured as a variable gain amplifier circuit, which changes the amplitude / power of the output cascade synchronization signal by adjusting the size of the amplification factor, that is, changes the impedance size of the impedance circuit 412 by adjusting the size of the amplification factor, thereby simulating the loss of the cascade synchronization signal caused by the off-chip impedance connected to the cascade output terminal MuxOUT and / or the cascade input terminal MuxIN.

[0133] In some embodiments, the self-test circuit 402 also includes a switching circuit, which is coupled to the signal transmission link and is configured to controllably connect the self-test circuit 402 and the signal transmission link 401 in the self-test mode; and disconnect the self-test circuit 402 and the signal transmission link 401 in the non-self-test mode.

[0134] In one example, combining Figure 2 Examples, references Fig.14 Specifically, the self-test circuit 402 including the switch circuit at least includes: a first switch K1, a first end of which is connected to the cascade output end MuxOUT, a second end of which is connected to the input end of the impedance circuit 412, an output end of the impedance circuit 412 is connected to a first end of a second switch K2, and a second end of the second switch K2 is connected to the cascade input end MuxIN. Fig.14 In the example, when the first switch K1 and the second switch K2 are both closed, the self-test circuit 402 is turned on, and the impedance circuit 412 adjusts the amplitude / power of the cascade synchronization signal to simulate the loss of the cascade synchronization signal transmitted off-chip in the cascade mode.

[0135] In some embodiments, reference Fig.15 and Fig.16 The self-test circuit includes: a signal acquisition circuit and a processor; wherein the signal acquisition circuit is coupled to the signal transmission link, and the signal acquisition circuit is configured to acquire the cascade synchronization signal in the self-test mode to output a detection signal; the processor is coupled to the signal acquisition circuit, and the processor is configured to detect the detection signal and output abnormal information when the working state of the radio frequency chip in the cascade mode is abnormal.

[0136] In some embodiments, the signal acquisition circuit includes: a coupler 403 and a power detection circuit (PDT, Power detection test) 404; wherein the coupler 403 is coupled to the signal transmission link 401 and is configured to output an acquisition signal corresponding to the cascade synchronization signal; the power detection circuit 404 is coupled to the coupler 403, and the power detection circuit 404 is configured to convert the acquisition signal into a detection signal reflecting the power of the cascade synchronization signal.

[0137] Specifically, the detection signal obtained by the power detection circuit 404 is obtained by the processor, and the processor determines whether the RF chip is working abnormally in the cascade mode based on the power of the detection signal and the power of the cascade signal required to determine whether the working state in the cascade mode is abnormal, and outputs abnormal information when the working state is abnormal.

[0138] The coupler 403 includes any of the following: (1) a series capacitor circuit with an output end, connected between the signal transmission link 401 and the signal ground, and the output end thereof outputs the collected signal. (2) an inductive component, such as a coil component or an inductive coupling line component, which inductively couples the signal transmission link and outputs the collected signal.

[0139] refer to Fig.15In some embodiments, if the coupler 403 is set based on a series capacitor circuit with an output end, the series capacitor circuit includes a first capacitor C1 and a second capacitor C2, wherein the first end of the first capacitor C1 is coupled to the cascade input end MuxIN, the second end is connected to the output end of the coupler 403, the first point of the second capacitor C2 is coupled to the second end of the first capacitor C1, and the second end is coupled to the signal ground.

[0140] refer to Fig.16 In some embodiments, if the coupler 403 is configured based on a coil assembly, the coil assembly includes four mutually coupled sub-coils, which are hereinafter referred to as a first coil, a second coil, a third coil, and a fourth coil. The first coil is connected to the cascade input terminal MuxIN, the second coil is connected to the output terminal of the coupler 403, the third coil is coupled to the signal transmission link 401, and the fourth coil is coupled to the impedance circuit 412.

[0141] Taking the RF chip 100 as a radar chip as an example, in the cascade mode, multiple synchronization signals in the radar chip are cascaded and synchronized. For example, the cascade synchronization signal includes at least one of: a local oscillator signal, a clock signal of an analog-to-digital converter, or a local oscillator control signal. Among them, the local oscillator control signal is used for the transceiver circuit of the cascaded multiple radar chips to start / end operation to control the transceiver circuit of the radar to work synchronously with the transceiver circuits of other cascaded radars. Using the cascaded synchronized local oscillator signal, the cascaded multiple radar chips will synchronously convert and amplify the local oscillator signal to form a radar signal (i.e., a radio frequency signal) and transmit it to free space; or use the cascaded synchronized local oscillator signal to down-convert the received reflected signal to obtain an intermediate frequency signal. The cascaded synchronized clock signal enables the ADC in the cascaded multiple radar chips to synchronously convert the intermediate frequency signal into a digital signal, thereby reducing the phase difference of the intermediate frequency signal of each chip and reducing the possibility of false target detection. In this way, a large-scale, high-precision detection purpose is achieved.

[0142] In some embodiments, the local oscillator signal is a frequency modulated continuous wave (FMCW) signal.

[0143] The RF chip provided in this embodiment simulates the off-chip transmission loss of the cascade synchronization signal of the RF chip in the cascade mode through a self-test circuit, so that the RF chip can perform functional self-test in the cascade mode in the single-chip mode, thereby ensuring the accuracy of the chip cascade structure based on the RF chip.

[0144] It should be noted that the features disclosed in the radio frequency chip provided in the above embodiments can be arbitrarily combined without conflict to obtain a new radio frequency chip embodiment. In addition, this embodiment can be implemented in conjunction with the radio frequency chip provided in the first embodiment and / or the fourth embodiment. The relevant technical details mentioned in the first embodiment and / or the fourth embodiment are still valid in this embodiment, and will not be repeated here to reduce repetition.

[0145] The seventh embodiment of the present disclosure also provides a chip cascade structure. The RF chip in the chip cascade structure simulates the off-chip transmission loss of the cascade synchronization signal of the RF chip in the cascade mode through a self-test circuit, so that the RF chip can perform functional self-test in the cascade mode in the single-chip mode, thereby ensuring the accuracy of the chip cascade structure based on the RF chip.

[0146] Specifically, the chip cascade structure includes a master chip and at least one slave chip, wherein at least one of the master chip and the at least one slave chip is the radio frequency chip provided in the sixth embodiment.

[0147] In some embodiments, the cascade chip structure provided in this embodiment may also be applied to the second embodiment, that is, at least one master chip or slave chip in the second embodiment is the RF chip provided in the sixth embodiment.

[0148] That is, on the basis of ensuring the chip self-test function, more RF chips can be connected in the chip cascade structure, thereby increasing the number of channels in the FMCW radar.

[0149] In some embodiments, the cascade chip structure provided in this embodiment may also be applied to the fourth embodiment, that is, at least one chip in the fourth embodiment is the radio frequency chip provided in the sixth embodiment.

[0150] That is, on the basis of ensuring the chip self-test function, the amplitude and phase consistency of the cascade synchronization signal in each cascade chip is also guaranteed.

[0151] In some embodiments, the cascade chip structure provided in this embodiment may also be implemented together with the second embodiment and the fourth embodiment to form a chip cascade structure having the functions of the three.

[0152] The eighth embodiment of the present disclosure provides a radar device. In one example, the radar device includes the chip cascade structure provided by the second embodiment. In another example, the radar device includes the chip cascade structure provided by the fifth embodiment. In another example, the radar device includes the chip cascade structure provided by the seventh embodiment.

[0153] Specifically, the radar chip includes: a signal generator, a local oscillator circuit and a power amplifier circuit connected in sequence; wherein the signal generator is used to generate a signal for radar detection, such as a pulse signal, an FMCW signal, etc.

[0154] Among them, the radar chip is a circuit built based on the Doppler effect formed between electromagnetic waves and speed, which is a detection device that converts physical quantities in physical space into electrical signals.

[0155] As for the circuit principle of radar chip, the radar chip includes transmitter, receiver, analog-to-digital converter and digital circuit. Among them, the transmitter includes signal generator, local oscillator circuit, radio frequency transmission circuit (including power amplifier circuit), and transmitting antenna, etc. The receiver includes: receiving antenna (Antenna), mixer (Mixer), analog-to-digital converter (ADC), etc. Among them, the signal generator generates a signal with continuous frequency change and outputs it to the local oscillator circuit to form the LO signal of the transmission frequency band; the radio frequency transmission circuit can drive and amplify the LO signal, and even adjust the phase control to form a chirp signal and convert it into an electromagnetic wave through the transmitting antenna. The electromagnetic wave is reflected by the object to form an echo, and the receiving antenna converts the echo into an echo signal. The mixer uses the LO signal to down-convert the echo signal into an intermediate frequency signal; the analog-to-digital converter converts the intermediate frequency signal into a digital signal. Among them, the digital signal corresponding to each chirp output by the analog-to-digital converter is also called a digital sequence.

[0156] By using the above-mentioned cascaded radar device, more independent transceiver ports can be integrated to form a MIMO channel in conjunction with the antenna array. This not only enables the antenna array to be used for detection over a larger range, but also improves detection accuracy.

[0157] In addition, by using the above-mentioned cascaded radar device, the consistency of the LO signal in each radar chip can also be ensured.

[0158] In addition, by utilizing the above-mentioned cascaded radar device, the self-test function of a single radar chip can be used to enable the radar chip to perform functional self-test in the cascade mode in the single-chip mode, thereby ensuring the accuracy of the chip cascade structure formed based on the RF chip.

[0159] The digital signal processor processes the accumulated digital sequences of each receiving port to locate the relative position of the target and the radar chip. The digital signal processor is a DSP (Digital Signal Processor) or a dedicated hardware accelerator. The digital signal processor performs at least one of the following signal processing: improving SNR, FFT-based signal processing, CFAR, MIMO-based target estimation, etc. to obtain the relative position.

[0160] The radar device also includes: an antenna array, wherein a transmitting antenna in the antenna array is connected to the output end of a radio frequency amplification circuit to radiate a millimeter wave signal into free space; and receives a reflected signal (also called an echo signal) reflected by an object to obtain a digital signal.

[0161] A ninth embodiment of the present disclosure provides an electronic device, which at least includes the radar device described in the eighth embodiment.

[0162] In one example, electronic devices include traditional computing devices such as desktop computers, laptops, smartphones, wearable devices such as smart watches, Internet services, etc. However, electronic devices also include other types of computing devices such as personal voice assistants, programmable thermostats, automotive electronics, robots, smart devices embedded in other machines such as refrigerators and industrial tools, IoT devices, etc.

[0163] Those skilled in the art will appreciate that the above-mentioned embodiments are specific examples for implementing the present application, and in actual applications, various changes may be made thereto in form and detail without departing from the spirit and scope of the present application.

Claims

1. A radio frequency chip, characterized in that: include: The radio frequency chip is integrated with a signal transmission link and includes a cascade input terminal and a cascade output terminal; The signal transmission link connects the cascade input terminal and the cascade output terminal to form a first signal path; When the RF chip is in the first cascade slave mode, the first signal path receives a cascade synchronization signal from outside the RF chip, and outputs the cascade synchronization signal to outside the RF chip through the first signal path; The first cascade slave mode represents that the RF chip is not the first or last chip in the cascade structure.

2. The radio frequency chip according to claim 1, characterized in that: Also includes: RF transceiver circuit; The signal transmission link connects the cascade input terminal and the radio frequency transceiver circuit to form a second signal path; When the RF chip is in the cascade master mode, the first cascade slave mode or the second cascade slave mode, the second signal path is used for the RF chip to perform radar detection using the cascade synchronization signal; The cascade master mode represents the first-stage chip of the RF chip in the cascade structure, and the second cascade slave mode represents the last-stage chip of the RF chip in the cascade structure.

3. The radio frequency chip according to claim 1, characterized in that: Also includes: A signal generating circuit and a radio frequency transceiver circuit, wherein the signal generating circuit is used to generate an on-chip oscillation signal; The signal transmission link connects the cascade input terminal and the radio frequency transceiver circuit to form a second signal path; The signal transmission link connects the signal generating circuit and the radio frequency transceiver circuit to form a third signal path; The signal transmission link connects the signal generating circuit and the cascade output terminal to form a fourth signal path; Among them, when the RF chip is in single-chip mode, the third signal path is used by the RF chip to use the on-chip oscillation signal for radar detection; when the RF chip is in cascade master mode, the fourth signal path is used by the RF chip to output the on-chip oscillation signal as the cascade synchronization signal to the outside of the RF chip.

4. The radio frequency chip according to claim 3, characterized in that: The signal transmission link includes multiplexed electrical components to conduct a target signal path, where the target signal path is at least one of the first signal path, the second signal path, the third signal path, and the fourth signal path.

5. The radio frequency chip according to claim 3, characterized in that: The signal transmission link includes a gate switch to conduct a target signal path based on the gate switch, the target signal path being at least one of the first signal path, the second signal path, the third signal path, and the fourth signal path.

6. The radio frequency chip according to any one of claims 1 to 5, characterized in that: The cascade synchronization signal at least includes: a local oscillator signal, a clock signal of an analog-to-digital converter, or a local oscillator control signal.

7. The radio frequency chip according to claim 6, characterized in that: The local oscillator signal is a continuous frequency modulation signal.

8. A chip cascade structure, characterized in that: include: A master chip and multiple slave chips; At least one of the plurality of slave chips is configured as a first type slave chip, the first type slave chip is the radio frequency chip according to any one of claims 1 to 7, and the radio frequency chip is in a first cascade slave mode; The cascade output terminal of the master chip is connected to the cascade input terminal of the master chip; The first type of slave chip is cascaded with the master chip and cascaded with any other slave chip.

9. The chip cascade structure according to claim 8, characterized in that: The master chip is the radio frequency chip according to any one of claims 3 to 7, and the radio frequency chip is in a cascade master mode.

10. The chip cascade structure according to claim 8, characterized in that: include: At least one of the plurality of slave chips is configured as a second type slave chip, the second type slave chip is the radio frequency chip according to any one of claims 4 to 7, and the radio frequency chip is in a second cascade slave mode; The second type of slave chip is cascaded with the first type of slave chip.

11. The chip cascade structure according to claim 10, characterized in that: The cascade input terminal and the cascade output terminal of the second type slave chip share the same port.

12. A chip packaging structure, applied to the packaging of the radio frequency chip according to any one of claims 1 to 7, characterized in that: include: A plurality of output solder balls, each of which is connected to the cascade output end through a corresponding first transmission line, and the lengths of the first transmission lines corresponding to the plurality of output solder balls are the same.

13. The chip packaging structure according to claim 12, characterized in that: Also includes: A plurality of input solder balls, each of which is connected to the cascade input terminal through a corresponding second transmission line, and the second transmission lines corresponding to the plurality of input solder balls have the same length.

14. A radar device, characterized in that: The radar device comprises the chip cascade structure according to any one of claims 8 to 10.

15. An electronic device, characterized in that: The electronic device includes at least the radar device according to claim 14.

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