Techniques for optical interpolators to mate with photonic integrated circuit dies

Abstract

Techniques for an optical interposer to mate with a photonic integrated circuit die are disclosed. In an exemplary embodiment, a mechanical adhesive and a separate index matching material are used as an underfill between a photonic integrated circuit (PIC) die and an optical interposer. The index matching material reduces coupling loss between the waveguide of the PIC die and the waveguide of the optical interposer while the mechanical adhesive secures the optical interposer in place. The mechanical adhesive can be thermally cured, has a low coefficient of thermal expansion (CTE), has a high viscosity, and has a higher optical transmission loss. The index matching material may have a low optical transmission loss, be UV cured, have a higher CTE, and have a low viscosity. The combination of the mechanical adhesive and the index matching material may improve fabrication ease and yield. Additional features, such as an array of V-slots with low stress and trenches and walls in an optical interposer and PIC die, are disclosed to control the flow of mechanical adhesive and / or index matching material.

Description

Background Art

[0001] Photonic integrated circuits (PICs) can be used for several applications such as communications. It can be a challenge to efficiently and inexpensively align the optical system to couple light into and out of the PIC. Approaches such as attaching optical fiber arrays to the PIC can be slow, incompatible with conventional semiconductor packaging processes, and can cause significant yield and throughput issues. BRIEF DESCRIPTION OF THE DRAWINGS

[0002] Figure 1 is a simplified diagram of one embodiment of a system having a photonic integrated circuit (PIC) die and an optical interposer.

[0003] Figure 2 There is no optical interposer Figure 1 A simplified diagram of the system.

[0004] Figure 3 yes Figure 1 Simplified diagram of an optical interposer.

[0005] Figure 4 yes Figure 1 Top view of the system.

[0006] Figure 5 yes Figure 2 Top view of the system.

[0007] Figure 6 yes Figure 2 Front view of the system.

[0008] Figure 7 yes Figure 2 A cross-sectional view of the system.

[0009] Figure 8 yes Figure 2 A cross-sectional view of the system.

[0010] Fig. 9 yes Figure 2 A cross-sectional view of the system.

[0011] Fig.10 yes Figure 4 A cross-sectional view of the system.

[0012] Fig.11 yes Figure 1 Top view of the system.

[0013] Fig.12 yes Figure 4 A cross-sectional view of the system.

[0014] Fig.13 yes Figure 4 A cross-sectional view of the system.

[0015] Fig.14 yes Fig.10 Cross-sectional view of a mechanical adhesive.

[0016] Fig.15 yes Fig.10 Cross-sectional view of the index-matching material.

[0017] Fig.16 yes Figure 3 Cross-sectional view of an optical interposer.

[0018] Fig.17 yes Figure 4 A cross-sectional view of the system.

[0019] Fig.18 is a simplified diagram of one embodiment of a system having a PIC die and an optical interposer.

[0020] Fig.19 is a simplified diagram of one embodiment of a system having a PIC die, an optical interposer, and an optical plug.

[0021] Fig. 20 is a simplified flow chart of at least one embodiment of a method for manufacturing a system including a PIC die and an optical interposer.

[0022] Fig.21 yes Fig. 20 A simplified diagram of one embodiment of a portion of a system at one stage of a method.

[0023] Fig. 22 yes Fig. 20 A simplified diagram of one embodiment of a portion of a system at one stage of a method.

[0024] Fig.23 yes Fig. 20 A simplified diagram of one embodiment of a portion of a system at one stage of a method.

[0025] Fig.24 is a top view of a wafer and die that can be included in a microelectronic assembly according to any of the embodiments disclosed herein.

[0026] Fig.25 is a cross-sectional side view of an integrated circuit device that can be included in a microelectronic assembly according to any of the embodiments disclosed herein.

[0027] Figures 26A-26D is a perspective view of exemplary planar transistors, gate-around transistors, and stacked gate-around transistors.

[0028] Fig. 27is a cross-sectional side view of an integrated circuit device assembly that may include a microelectronic assembly according to any of the embodiments disclosed herein.

[0029] Fig.28 is a block diagram of an exemplary electrical device that may include a microelectronic assembly according to any of the embodiments disclosed herein. DETAILED DESCRIPTION

[0030] In various embodiments disclosed herein, an optical interposer is mated with a photonic integrated circuit (PIC) die. Several waveguides are defined in the optical interposer and the PIC die, and the optical interposer is mated so that the waveguides in the optical interposer are aligned to the waveguides in the PIC die, thereby allowing light to be coupled between the optical interposer and the PIC die. As described in more detail below, various features that can improve performance, manufacturing yield, etc. can be included in various embodiments. For example, in some embodiments, a mechanical adhesive is used to adhere the optical interposer to the PIC die, while a refractive index matching material is used to improve the coupling between the PIC die and the optical interposer. Using one material to provide refractive index matching and one material to provide mechanical stability can provide several benefits, such as more flexible manufacturing options, performance improvements, and increased yields, as described in more detail below.

[0031] Additionally or alternatively, in some embodiments, an array of V-grooves on the PIC die and / or optical interposer can be designed to improve performance. Rather than V-grooves that butt at the sides of the V-grooves, the V-grooves can be designed so that the peaks of one array of V-grooves butt against the valleys of another array of V-grooves. This approach can reduce stress or distribute stress more evenly, thereby reducing the likelihood of component damage. Another feature that can be incorporated is a groove in the PIC die to prevent excess mechanical adhesive from leaking onto the substrate, potentially causing failure.

[0032] As used herein, the phrase "communicative coupling" refers to the ability of a component to send a signal to or receive a signal from another component. The signal can be any type of signal, such as an input signal, an output signal, or a power signal. A component is capable of sending a signal to or receiving a signal from another component to which it is communicatively coupled via a wired or wireless communication medium (e.g., a conductive trace, a conductive contact, air). Examples of communicatively coupled components include integrated circuit dies in the same package that communicate via an embedded bridge in a package substrate, and an integrated circuit package attached to a printed circuit board that sends or receives signals to or from other integrated circuit packages or electronic devices attached to the printed circuit board.

[0033] In the following description, specific details are set forth, however, embodiments of the technology described herein can be practiced without these specific details. Well-known circuits, structures, and techniques are not shown in detail to avoid obscuring the understanding of this description. Phrases such as "embodiment", "various embodiments", "some embodiments", etc. may include features, structures, or characteristics, but not every embodiment must include the specific features, structures, or characteristics.

[0034] Some embodiments may have some, all, or none of the features described for other embodiments. "First," "second," "third," and the like describe common objects and indicate different instances of similar objects mentioned. Such adjectives do not imply that the objects described in this manner must be in a given sequence in time or space, in order, or in any other way. "Connected" may indicate that elements are in direct physical or electrical contact, and "coupled" may indicate that elements cooperate or interact, but they may or may not be in direct physical or electrical contact. In addition, the terms "include," "comprise," "have," and the like used in connection with the embodiments of the present disclosure are synonymous. Terms modified by the word "substantially" include arrangements, orientations, spacings, or positions that vary slightly from the meaning of the unmodified terms. For example, the central axis of a magnetic plug that is substantially coaxially aligned with a through hole may be misaligned by a few degrees with the central axis of the through hole. In another example, a substrate component feature described as having substantially the listed dimensions, such as a through width, may vary within a few percent of the listed dimensions.

[0035] It should be understood that in the examples further illustrated and described below, the drawings may not be drawn to scale and may not include all possible layers and / or circuit components. In addition, it should be understood that although certain drawings illustrate transistor designs with source / drain regions, electrodes, etc. having orthogonal (e.g., vertical) boundaries, embodiments herein may implement such boundaries in a substantially orthogonal manner (e.g., within + / - 5 or 10 degrees of orthogonal) due to manufacturing methods used to produce such devices or for other reasons.

[0036] Reference is now made to the accompanying drawings, which are not necessarily drawn to scale, wherein similar or identical reference numerals may be used to indicate the same or similar parts in different drawings. The use of similar or identical reference numerals in different drawings does not mean that all figures including similar or identical reference numerals constitute a single or identical embodiment. Similar reference numerals with different letter suffixes may represent different instances of similar parts. The accompanying drawings generally illustrate various embodiments discussed herein by way of example and not limitation.

[0037] In the following description, many specific details are set forth for the purpose of explanation in order to provide a thorough understanding thereof. However, it may be apparent that novel embodiments may be practiced without these specific details. In other cases, well-known structures and devices are shown in the form of block diagrams to facilitate their description. The present invention is intended to cover all modifications, equivalents, and alternatives within the scope of the claims.

[0038] As used herein, the phrase "located on..." in the context of a first layer or component being located on a second layer or component means that the first layer or component is physically attached to the second layer or component directly (without layers or components between the first and second layers or components) or is physically attached to the second layer or component with one or more intervening layers or components.

[0039] As used herein, the term "adjacent" refers to layers or components that are in physical contact with each other. That is, there are no layers or components between the adjacent layers or components. For example, layer X adjacent to layer Y refers to a layer that is in physical contact with layer Y.

[0040] Reference now Figure 1 In one embodiment, a system includes a substrate 108, a photonic integrated circuit (PIC) die 102 mounted on the substrate 108, and an optical interposer 104 mated with the PIC die 102. The ends of one or more waveguides 106 are positioned at one end of the optical interposer 104. The waveguides 106 extend through the body of the optical interposer 104 to the other end of the optical interposer (see Figure 4 ). Waveguide 106 is aligned to waveguide 212 defined in PIC die 102 (see Figure 2 ), thereby allowing light to be coupled between the optical interposer 104 and the PIC die 102. When in use, the optical plug can be mated with the optical interposer 104, as described below in conjunction with Fig.18 and Fig.19 Described in more detail.

[0041] An exemplary optical interposer 104 is silica glass. In other embodiments, the optical interposer 104 may be made of any suitable material, which may be crystalline, amorphous, amorphous, etc., such as fused silicon, borosilicate, sapphire, yttrium aluminum garnet, etc. The optical interposer 104 may be, for example, aluminosilicate glass, borosilicate glass, aluminoborosilicate glass, silica, fused silicon. The optical interposer 104 may include one or more additives, such as Al2O3, B2O3, MgO, CaO, SrO, BaO, SnO2, Na2O, K2O, SrO, P2O3, ZrO2, Li2O, Ti, and Zn. The optical interposer 104 may include silicon and oxygen, as well as any one or more of aluminum, boron, magnesium, calcium, barium, tin, sodium, potassium, strontium, phosphorus, zirconium, lithium, titanium, and zinc. The optical interposer 104 may include at least 20-40 weight percent silicon, at least 20-40 weight percent oxygen, and at least 5 weight percent aluminum. For example, some embodiments of the optical interposer 104 may include, for example, at least 20-23 weight percent silicon, and at least 20-26 weight percent oxygen. The optical interposer 104 may have any suitable length or width, such as 10-500 millimeters. The optical interposer 104 may have any suitable thickness, such as 0.2-5 millimeters. The optical interposer 104 may also be referred to as an optical coupler, a glass interposer, a glass coupler, etc.

[0042] The optical interposer 104 can route light between the optical plug and the PIC die 102 using waveguides defined in the optical interposer 104. The waveguides can be routed in any suitable manner, including in three dimensions, allowing for flexible layout. The optical interposer 104 can include optical elements such as fan-outs, splitters, couplers, combiners, filters, etc.

[0043] The PIC die 102 may be made of any suitable material, such as silicon. In the exemplary embodiment, a waveguide 212 is defined in the PIC die 102 that interfaces with the waveguide 106 defined in the optical interposer 104 to transmit light to or from the PIC die 102. In the exemplary embodiment, the waveguide 212 in the PIC die 102 may be a silicon waveguide embedded in a silicon oxide cladding. The PIC die 102 may include any suitable number of waveguides 212, such as 1-1024.

[0044] The PIC die 102 is configured to generate, detect and / or manipulate light. The PIC die 102 may include active or passive optical components, such as optical splitters, couplers, filters, optical amplifiers, lasers, photodetectors, modulators, etc. The PIC die 102 may have electrical connections to the substrate and / or EIC die, such as for power delivery, sending and receiving data, etc.

[0045] Exemplary substrate 108 can be any suitable substrate, such as silicon, glass, ceramic, circuit board, etc. In some embodiments, substrate 108 is a circuit board made of any suitable material, such as ceramic, glass, and / or an organic-based material with fiberglass and resin, such as FR-4. Substrate 108 can have any suitable length or width, such as 10-500 mm. Substrate 108 can have any suitable thickness, such as 0.2-5 mm.

[0046] In the exemplary embodiment, system 100 is at a stage in manufacturing an integrated circuit package that will include PIC die 102 and optical interposer 104. As part of packaging the integrated circuit package, PIC die 102 may be separated from substrate 108. Fig.18 and Fig.19 One embodiment of an integrated circuit package including a PIC die 102 and an optical interposer 104 is described at various stages of manufacture. The system 100 may include at any appropriate stage of the manufacturing process. Figure 1 Additional components not shown.

[0047] Reference now Figure 2 , in one embodiment, the system 100 is shown without the optical interposer 104, which shows a view of some structures for mating the optical interposer 104 with the PIC die 102. The PIC die 102 includes two V-groove arrays 202, 205, which mate with corresponding V-groove arrays 302 in the optical interposer 104 (see Figure 3 ) are matched. The V-groove arrays 202, 205 include a series of alternating peaks 203 and valleys 204. In the exemplary embodiment, a groove 208 is defined between the V-groove arrays 202, 205, such as Figure 2 As shown. Grooves 206 are defined between waveguide 212 and the end of each V-groove in array 205. Grooves 210 are defined between V-groove array 202 and wall 214. Figure 10-13 In more detail, the grooves 206, 208, 210 can facilitate placement of the mechanical adhesive 1002 and the index matching material 1006. In the exemplary embodiment, the PIC die 102 includes the grooves 206, 208, 210. In some embodiments, the PIC die 102 can include any suitable combination of the grooves 206, 208, 210.

[0048] In the exemplary embodiment, the V-groove arrays 202, 205 have a pitch of approximately 160 microns and a depth (i.e., the vertical distance between peaks 203 and valleys 204) of approximately 110 microns. In other embodiments, the V-groove arrays 202, 205 may have any suitable pitch or depth, such as 30-500 microns.

[0049] In the illustrated embodiment, the V-groove array 202, 205, the grooves 206, 208, 210, the walls 214, etc. are etched from the substrate of the PIC die 102, for example, by using 2D and 3D photolithography. In other embodiments, some or all of the V-groove array 202, 205, the grooves 206, 208, 210, the walls 214, etc. may be formed from another material, such as a material grown on or adhered to the PIC die 102.

[0050] Reference now Figure 3 In one embodiment, the optical interposer 104 has a V-groove array 302 defined on a surface of the optical interposer 104. The V-groove array 302 includes alternating peaks 304 and valleys 306. When the optical interposer 104 is mated with the PIC die 102, the V-groove array 302 mates with the V-groove arrays 202, 205.

[0051] In the exemplary embodiment, the V-groove array 302 has a pitch of approximately 160 microns and a depth (ie, the vertical distance between the peaks 304 and valleys 306) of approximately 90 microns. In other embodiments, the V-groove array 302 may have any suitable pitch or depth, such as 30-500 microns.

[0052] In the exemplary embodiment, the optical interposer 104 includes side walls 308 that mate with the sides of the PIC die 104. The optical interposer 104 also includes side walls 310 that mate with the outside of the walls 214 of the PIC die 102. Figure 10-13 In more detail, the mechanical adhesive 1002 may be present at some or all of the interfaces between the sidewalls 308 , 310 and the PIC die 102 to improve the mechanical attachment of the optical interposer 104 to the PIC die 102 .

[0053] Reference now Figure 4-9 , various views of system 100 are given. Figure 4 A top view of system 100 including PIC die 102 and optical interposer 104 is shown. Figure 5 A top view of system 100 is shown with PIC die 102 and without optical interposer 104 . Figure 5 V-groove arrays 202, 205, grooves 206, 208, 210 and walls 214 are shown.

[0054] Figure 6 A front view of system 100 is shown with PIC die 102 and without optical interposer 104 . Figure 6 An array of V-grooves 205 is shown across the wall 214 and the groove 210 . Figure 7A cross-section through the trench 208 is shown. Figure 6 A cross-sectional view of the system 100 with the PIC die 102 and without the optical interposer 104 from the same perspective. Figure 8 A cross-section through the trench 206 is shown. Figure 6 A cross-sectional view of the system 100 with the PIC die 102 and without the optical interposer 104 from the same perspective.

[0055] Fig. 9 A cross-sectional view of system 100 is shown with PIC die 102 and without optical interposer 104 . Fig. 9 The perspective is taken at a plane passing through one of the valleys 204 parallel to one of the V-grooves of array 202 . Fig. 9 Grooves 206, 208, 210 are shown.

[0056] Reference now Figure 10-11 In one embodiment, the system 100 includes a mechanical adhesive 1002 and an index matching material 1006. The mechanical adhesive 1002 secures the optical interposer 104 in place relative to the PIC die 102, and the index matching material improves coupling between the waveguides 106, 212 by reducing reflections at the ends of the waveguides 106, 212.

[0057] In the exemplary embodiment, the mechanical adhesive 1002 is disposed between the V-groove arrays 202, 205 of the PIC die 102 and the V-groove array 302 of the optical interposer 104, and between the wall 214 and the optical interposer 104. Fig.11 As shown, the mechanical adhesive 1002 may also be placed between the optical interposer 104 and the wings of the PIC die 102 to the sides of the area where the waveguide 106 is located. The grooves 206, 208, 210 allow space for the mechanical adhesive 1002 and / or the index matching material 1006 to flow in, thereby preventing the mechanical adhesive 1002 and / or the index matching material 1006 from spreading to undesired locations. Additionally or alternatively, the walls 214 can prevent excess mechanical adhesive 1002 and / or excess index matching material 1006 from flowing out of the grooves 210, thereby preventing excess material from leaking down the sides of the PIC die 102. For example, if excess mechanical adhesive 1002 flows down the sides of the PIC die 102 to the substrate 108, it may be impossible to remove the PIC die 102 from the substrate 108 for further packaging, thereby resulting in failure and lower yield.

[0058] In some embodiments, some flow along the sidewalls 308, 310 and / or along the wall 214 into the trenches 206, 208, 210 may be desirable because it provides additional surface for the mechanical adhesive 1002 to adhere. This can result in the formation of fillets 1004 that can provide strong adhesion of the optical interposer 104 to the PIC die 102.

[0059] It should be appreciated that the grooves 206, 208, 210 allow for flexibility in distributing various amounts of the mechanical adhesive 1002 and / or the index matching material 1006. For example, relatively small amounts such as Fig.10 As shown, there is no or little flow into the grooves 206, 208, 210. In another example, more, such as Fig.12 As shown in FIG. 1 , more mechanical adhesive 1002 flows into the grooves 208, 210. In yet another example, more refractive index matching material 1006 may be used, such as Fig.13 As shown, index matching material 1006 flows into trench 208 as well as trench 206 .

[0060] Mechanical adhesive 1002 may be any suitable adhesive, such as an epoxy or paste. Mechanical adhesive 1002 may be conductive or non-conductive. Mechanical adhesive 1002 may include filler materials, such as particles 1402, such as Fig.14 As shown, Fig.14 A cross section of mechanical adhesive 1002 is depicted. In the exemplary embodiment, particles 1402 are monodisperse silica particles having a diameter of approximately 800 nanometers. In other embodiments, particles 1402 may be monodisperse or non-monodisperse. Particles 1402 may be any suitable material other than silica. Particles 1402 may have any suitable diameter, for example, 200 nanometers to 10 micrometers. In the exemplary embodiment, particles 1402 may affect a coefficient of thermal expansion (CTE) that is lower than the intrinsic CTE of the adhesive component of mechanical adhesive 1002. The CTE of mechanical adhesive 1002 may be, for example, 0.2-10 x 10 -6 K -1102. In an exemplary embodiment, the CTE of the mechanical adhesive 1002 can be similar to or between the CTEs of the PIC die 102 and the optical interposer 104. Matching the CTE of the mechanical adhesive 1002 to the CTE of the PIC die 102 and / or the optical interposer 104 can reduce the chance of delamination during further processing, packaging, and / or use of the PIC die 102. It should be understood that the particles 1402 can reduce the optical transmission of light through the mechanical adhesive 1002. However, since there is no mechanical adhesive 1002 between the waveguides 106, 212, the particles 1402 in the mechanical adhesive 1002 do not result in lower optical coupling between the waveguides 106, 212.

[0061] In an exemplary embodiment, the mechanical adhesive 1002 is applied as a relatively high viscosity paste to allow for limited flow or leakage of the mechanical adhesive 1002 when the mechanical adhesive 1002 is applied. In one embodiment, the mechanical adhesive 1002 is heat curable. For example, a machine may be able to position the optical interposer 104 on the PIC die 102 and apply heat to cure the mechanical adhesive 1002. In some cases, such a machine may not be able to apply UV light while holding the optical interposer 104 in place relative to the PIC die 102, resulting in the optical interposer 104 being misaligned before the UV-cured mechanical adhesive 1002 can be cured. In other embodiments, the mechanical adhesive 1002 may be UV-curable and the optical interposer 104 may be held in place relative to the PIC die 102 while the UV light is applied. The mechanical adhesive 1002 may have any suitable viscosity, such as 500-10,000,000 centipoise.

[0062] The index matching material 1006 may be any suitable material, such as an epoxy or a paste. The index matching material 1006 may have any suitable refractive index, such as 1.4-3.6. In some embodiments, the index matching material 1006 may have a refractive index between the refractive indexes of the waveguide 106 and the waveguide 212, thereby reducing reflective coupling losses at the interface between the waveguides 106, 212 and the index matching material 1006. The index matching material 1006 may not include particles, such as Fig.15 As shown, low optical loss of light transmitted through the refractive index matching material 1006 is achieved. The refractive index matching material 1006 may have any suitable viscosity, such as a viscosity of 10-10,000 centipoise. In an exemplary embodiment, the refractive index matching material 1006 has a viscosity of 30-80 centipoise.

[0063] The CTE of the index matching material 1006 may be relatively high, for example, in the range of 10-100 x 10 -6 K-1 Since the amount of index matching material 1006 is relatively small and the optical interposer 104 is held in place relative to the PIC die 102 by the mechanical adhesive 1002, the relatively high CTE of the index matching material 1006 does not cause excessive stress or separation of the optical interposer 104 from the PIC die 102.

[0064] In the exemplary embodiment, the index matching material 1006 is applied as a relatively low viscosity epoxy, allowing the index matching material 1006 to flow to completely fill the area between the waveguides 106, 212. Fig.10 , Fig.12 and Fig.13 As shown, the index matching material 1006 may flow into the grooves 206 and / or the grooves 208. It should be appreciated that the index matching material 1006 prevents the mechanical adhesive 1002 from being positioned between the waveguides 106, 212, which may reduce coupling between the waveguides 106, 212.

[0065] In an exemplary embodiment, the index matching material 1006 is UV cured, and the mechanical adhesive 1002 is heat cured. For example, in one embodiment, a machine may be able to position the optical interposer 104 on the PIC die 102 and apply heat to cure the mechanical adhesive 1002 without curing the index matching material 1006. The mechanical adhesive 1002 can then hold the optical interposer 104 in place relative to the PIC die 102 while UV light is applied to cure the index matching material 1006. In other embodiments, the index matching material 1006 may be heat cured, and / or the mechanical adhesive 1002 may be UV cured.

[0066] Reference now Fig.16 and Fig.17 , in one embodiment, Fig.16 A cross-sectional view of the optical interposer 104 is shown in FIG. Fig.16 The cross-sectional view of the optical interposer 104 in FIG. 1 is taken perpendicular to the V-grooves of the V-groove array 302. In the exemplary embodiment, the V-grooves of the V-groove array 302 are Figure 6 and Figure 7 The V-grooves of the V-groove arrays 202, 205 shown in FIG. 2 are more rounded. Fig.17 A cross-sectional view of a system 100 including a PIC die 102 and an optical interposer 104 is shown. Fig.16 The cross-sectional view of the system 100 in FIG. 1 is taken perpendicular to the V-grooves of the V-grooves arrays 202, 205, across the grooves 208. For clarity, the cross-sectional view of the system 100 in FIG. 1 is taken perpendicular to the V-grooves of the V-grooves arrays 202, 205, across the grooves 208. Fig.17 The mechanical adhesive 1002 and the refractive index matching material 1006 are omitted.

[0067] like Fig.17 As shown, the width of the valley 305 of the V-groove in the V-groove array 302 is wider than the peak 203 of the V-groove in the V-groove arrays 202 and 205, thereby allowing the peak 203 to mechanically cooperate with the valley 305. This approach avoids stress caused by contact between the sidewalls of the V-groove of the V-groove array 302 and the sidewalls of the V-groove of the V-groove arrays 202 and 205. In addition or alternatively, the depth of the V-groove of the V-groove array 302 is less than the depth of the V-groove of the V-groove arrays 202 and 205, thereby resulting in a small gap 1702 between the peak 304 and the valley 204. Such a gap 1702 can reduce sensitivity to foreign matter such as dust that may be trapped between the V-groove array 302 and the V-groove arrays 202 and 205. The gap 1702 can be any suitable amount, such as 2-50 microns.

[0068] Reference now Fig.18 In one embodiment, the integrated circuit package 1800 includes one or more PIC dies 102, one or more optical interposers 104, a substrate 1802, one or more optical receptacles 1804, and an electrical integrated circuit (EIC) die 1806. In the exemplary embodiment, the optical receptacle 1804 is formed by the substrate 1802 and the optical interposer 104. The optical interposer 104 has a face 1814 in which the ends of one or more waveguides are positioned. When the optical plug 1900 (see Fig.19 ) when mated with the optical receptacle 1804, aligning the optical fiber of the optical plug 1900 with the waveguide 306 in the optical interposer 104, for example, within less than 1 micron.

[0069] In the exemplary embodiment, the optical receptacle 1804 is at least partially defined by a cavity 1818 defined in the substrate 1802. The exemplary cavity 1818 is cut all the way through the substrate 1802. The sidewalls of the cavity 1818 define a rough lateral alignment feature for the optical plug 1900. The optical plug 1900 can be roughly vertically aligned by the cover 1934 and another substrate 1932, as described below in conjunction with Fig.19 Described in more detail.

[0070] The cavity 1818 may include an indentation 1820 that acts as a latching feature. The indentation 1820 extends from the sidewall of the cavity 1818 further into the substrate 1802. The protrusion 1930 of the optical plug 1900 may lock into position in the indentation 1820, thereby preventing the optical plug 1900 from being removed.

[0071] In the exemplary embodiment, the optical interposer 104 is positioned on a shelf 1816 that is slightly recessed from the top surface 1822 of the substrate 1802. The shelf 1816 can position the optical interposer 104 at a desired height relative to other components such as the substrate 1802, the cover 1934, the plug 1900, etc. The shelf 1816 can have any suitable depth, such as 0-250 microns.

[0072] In the exemplary embodiment, a photonic integrated circuit (PIC) die 102 is mated with an optical interposer 104. In the exemplary embodiment, a waveguide 306 in the optical interposer 104 can transmit light between an optical fiber of the optical plug 1900 and a waveguide of the PIC die 102.

[0073] The substrate 1802 may support several additional integrated circuit dies 1810 , which may be PIC dies, EIC dies, or a combination of both. The additional integrated circuit dies 1810 may facilitate communication, power delivery, and other appropriate connections between the PIC die 102 and the EIC die 1806 .

[0074] Exemplary substrate 1802 can be any suitable substrate, such as glass, silicon, ceramic, circuit board, etc. In some embodiments, substrate 1802 is a circuit board made of any suitable material, such as ceramic, glass, and / or an organic-based material with glass fiber and resin, such as FR-4. In some embodiments, substrate 1802 is formed of or otherwise includes bismaleimide triazine (BT) resin. Substrate 1802 can have any suitable length or width, such as 10-500 mm. Substrate 1802 can have any suitable thickness, such as 0.2-5 mm. Substrate 1802 can support other than Figure 1 Additional components beyond those shown, such as resistors, capacitors, other integrated circuit dies, power electronics, traces, etc.

[0075] The EIC die 1806 may include any suitable electronic integrated circuit package, such as resistors, capacitors, inductors, transistors, etc. The EIC die 1806 may include any suitable analog and / or digital circuitry, such as a processor, memory, application specific integrated circuit (ASIC), field programmable gate array (FPGA), etc. The EIC 1806 may be embodied as or include a central processing unit (CPU), a graphics processing unit (GPU), or any other processing unit (XPU) or form part of them. In some embodiments, the integrated circuit package 1800 may be embodied as a router, a switch, a network interface controller, etc. In such an embodiment, the EIC die 1806 may include a network interface controller circuitry to process, parse, route, etc. the network packets sent and received by the integrated circuit package 1800 through the optical plug 1900.

[0076] Reference now Fig.19 , in one embodiment, the optical cable 1900 may be capable of being connected to the optical receptacle 1804 of the integrated circuit package 1800. The optical cable 1900 includes one or more optical fibers in a jacket 1906 connected to an optical plug 1902. The housing 1914 houses a ferrule and a ferrule holder, which mates with the optical interposer 104. When the plug 1902 is inserted into the receptacle, the protrusion 1930 of the spring clip mates with the indentation 1820 of the receptacle 1804, thereby securing the optical plug 1902 in place. Pulling the tab 1920 of the retaining mechanism will pull the protrusion 1930 of the spring clip inwardly, thereby releasing the plug 1902 from the receptacle 1804.

[0077] Housing 1914 includes slot 1924, which can be used to roughly align plug 1902 and act as an orientation key, thereby preventing optical plug 1902 from being inserted upside down. Slot 1924 can be used with Fig.19 The ribs 1940 shown in FIG.

[0078] Optical cable 1900 can include any appropriate number of optical fibers, for example, 1-32 optical fibers. The optical fibers can be arranged in a one-dimensional or two-dimensional array at the sleeve. Exemplary optical fibers are made of glass and can carry light of any appropriate wavelength, for example, 400-2000 nanometers. In an exemplary embodiment, the optical fiber can support light in the C-band, O-band, L-band, S-band, etc. In other embodiments, the optical fiber can be made of different materials.

[0079] The optical plug 1902 can have any suitable dimensions. In an exemplary embodiment, the optical plug 1902 has a width of approximately 5 mm and a height of approximately 1.5 mm. In other embodiments, the optical plug 1902 can have a height and / or width of, for example, 1-10 mm. The optical cable 1900 can have optical plugs on opposite ends that can be similar, identical, or different from the optical plug 1902.

[0080] In one embodiment, the integrated circuit component 1800 can be mounted on another component such as a substrate 1932. The substrate 1932 can be, for example, a motherboard, another circuit board connecting the integrated circuit package 1800 to other components, a housing, etc. The substrate 1932 can be a similar or identical material to the substrate 1802.

[0081] like Fig.19 As shown, in use, the integrated circuit package 1800 can include a cover 1934. The cover 1934 can provide a rough alignment for the plug 1902. The cover 1934 can have a rib 1940 that forms part of the receptacle 1804. The rib 1940 can align with the slot 1924 defined in the optical plug 1902. The rib 1940 and the slot 1924 can establish a keying to prevent the optical plug 1902 from being inserted upside down.

[0082] Reference now Fig. 20 , in one embodiment, a flow chart of a method 2000 for creating an integrated circuit package with an optical socket is shown. The method 2000 may be performed by a technician and / or one or more automated machines. In some embodiments, one or more machines may be programmed to perform some or all of the steps of the method 2000. Such a machine may include, for example, a memory, a processor, a data storage device, etc. The memory and / or the data storage device may store instructions that, when executed by the machine, cause the machine to perform some or all of the steps of the method 2000. The method 2000 may use any suitable set of techniques used in semiconductor processing, such as chemical vapor deposition, atomic layer deposition, physical layer deposition, molecular beam epitaxy, layer transfer, lithography, ion implantation, dry etching, wet etching, selective laser etching, thermal processing, flip chip, layer transfer, magnetron sputtering deposition, pulsed laser deposition, laser machining, 3D lithography, etc. It should be understood that the method 2000 is only one embodiment of a method for creating one embodiment of the system, and other methods may be used to create any suitable embodiment of the system. In some embodiments, the steps of the method 2000 may be performed in an order different from the order shown in the flow chart.

[0083] The method 2000 begins at block 2002, where a PIC die 102 is formed. The PIC die 102 may include active or passive optical components, such as splitters, couplers, filters, optical amplifiers, lasers, photodetectors, modulators, etc. The PIC die 102 may include electrical connections for connecting to a substrate and / or an EIC die, e.g., for power delivery, sending and receiving data, etc.

[0084] In block 2004, an optical interposer 104 is formed. The optical interposer 104 may include one or more waveguides defined in the optical interposer 104. In an exemplary embodiment, the optical interposer 104 may be embodied as silica. In other embodiments, other glasses or other materials may be used, as described in more detail above. The optical interposer 104 may include one or more waveguides 306 defined therein. The waveguide 306 may be embodied as a direct write waveguide, which is formed by applying a laser to the optical interposer 104 to modify the refractive index of a portion of the optical interposer 104. For example, the optical interposer 104 may be formed using selective laser etching. In block 2006, the PIC die 102 is mounted on a substrate such as the substrate 108.

[0085] In block 2008, an underfill material is deposited on the PIC die 102 and / or the optical interposer 104. In block 2010, a mechanical adhesive 1002 and / or an index matching material 1006 may be applied to the PIC die 102, such as Fig.21 Additionally or alternatively, in block 2012, a mechanical adhesive 1002 and / or a refractive index matching material 1006 may be applied to the optical interposer 104, such as Fig. 22 and Fig.23 In some embodiments, a mechanical adhesive 1002 may be applied across the V-groove array 302, such as Fig. 22 Additionally or alternatively, a mechanical adhesive 1002 may be applied to the wings of the optical interposer 104, such as Fig.23 shown.

[0086] In block 2014, the optical interposer 104 is mounted on the PIC die 102. The optical interposer 104 may be positioned so that the waveguide 306 is aligned to within one micron or less to the waveguide 212. In block 2016, the mechanical adhesive 1002 is cured. In an exemplary embodiment, the mechanical adhesive 1002 is thermally cured in block 2018 while holding the optical interposer 104 in place relative to the PIC die 102.

[0087] In block 2020, the index matching material 1006 is cured. In an exemplary embodiment, the index matching material 1006 is cured in block 2022 using ultraviolet light.

[0088] In block 2024, the PIC die 102 and optical interposer 104 are removed from substrate 108. In block 2026, packaging of the PIC die 102 may be completed, for example, by integrating the PIC die 102 and optical interposer 104 with a substrate, with an electronic integrated circuit die (EIC), or the like.

[0089] Fig.24 1806). The wafer 2400 may be comprised of a semiconductor material and may include one or more dies 2402 having integrated circuit structures formed on a surface of the wafer 2400. The individual dies 2402 may be repeating units of an integrated circuit product including any suitable integrated circuit. After fabrication of the semiconductor product is complete, the wafer 2400 may undergo a singulation process in which the dies 2402 are separated from one another to provide discrete “chips” of an integrated circuit product. The dies 2402 may be any of the dies 102, 1806 disclosed herein. The dies 2402 may include one or more transistors (e.g., the transistors discussed below). Fig.25 Some of the transistors 2540), supporting circuit systems for routing electrical signals to the transistors, passive components (e.g., signal traces, resistors, capacitors, or inductors), and / or any other integrated circuit components. In some embodiments, wafer 2400 or die 2402 may include memory devices (e.g., random access memory (RAM) devices, such as static RAM (SRAM) devices, magnetic RAM (MRAM) devices, resistive RAM (RRAM) devices, conductive bridge RAM (CBRAM) devices, etc.), logic devices (e.g., AND, OR, NAND, or XOR gates), or any other suitable circuit elements. Multiple of these devices may be combined on a single die 2402. For example, a memory array formed by multiple memory devices may be combined with a processor unit (e.g., a processor unit) configured to store information in the memory devices or execute instructions stored in the memory array. Fig.28 The integrated circuit packages 1800 disclosed herein may be fabricated using a die-to-wafer assembly technique in which some of the dies 102, 1806 are attached to a wafer 2400 including other dies 102, 1806, and the wafer 2400 is then singulated.

[0090] Fig.251800 (e.g., in any of the dies 102, 1806). One or more of the integrated circuit devices 2500 may be included in one or more of the dies 2402 ( Fig.24 ). The integrated circuit device 2500 may be formed on a die substrate 2502 (eg, Fig.24 2400) and may be included in a die (e.g., Fig.24 The die substrate 2502 may be a semiconductor substrate composed of a semiconductor material system including, for example, an n-type or p-type material system (or a combination of the two). For example, the die substrate 2502 may include a crystalline substrate formed using bulk silicon or a silicon-on-insulator (SOI) substructure. In some embodiments, the die substrate 2502 may be formed using alternative materials that may or may not be combined with silicon, including but not limited to germanium, indium antimonide, lead telluride, indium arsenide, indium phosphide, gallium arsenide, or gallium antimonide. Other materials classified as Group II-VI, Group III-V, or Group IV may also be used to form the die substrate 2502. Although several examples of materials that may form the die substrate 2502 are described herein, any material that may serve as the basis for the integrated circuit device 2500 may be used. The die substrate 2502 may be a singulated die (e.g., Fig.24 of die 2402) or wafer (e.g., Fig.24 portion of wafer 2400).

[0091] The integrated circuit device 2500 may include one or more device layers 2504 disposed on a die substrate 2502. The device layer 2504 may include features of one or more transistors 2540 (e.g., metal oxide semiconductor field effect transistors (MOSFETs)) formed on the die substrate 2502. The transistor 2540 may include, for example, one or more source and / or drain (S / D) regions 2520, a gate 2522 to control current flow between the S / D regions 2520, and one or more S / D contacts 2524 to route electrical signals to / from the S / D regions 2520. The transistor 2540 may include additional features not shown for clarity, such as device isolation regions and gate contacts, etc. The transistor 2540 is not limited to Fig.25 The types and configurations depicted in the drawings and may include a wide variety of other types and configurations, such as planar transistors, non-planar transistors, or a combination of both. Non-planar transistors may include FinFET transistors such as dual-gate transistors or tri-gate transistors and gate-wrap transistors or gate-around transistors such as nanoribbon transistors, nanosheet transistors, or nanowire transistors.

[0092] Figures 26A-26D is a simplified perspective view of exemplary planar transistors, FinFET transistors, gate-around transistors, and stacked gate-around transistors. Figures 26A-26D The transistor is shown formed on a substrate 2616 having a surface 2608. Isolation regions 2614 separate the source and drain regions of the transistor from other transistors and from a bulk region 2618 of the substrate 2616.

[0093] Fig.26A is a perspective view of an exemplary planar transistor 2600 including a gate 2602 that controls current flow between a source region 2604 and a drain region 2606. Transistor 2600 is planar because source region 2604 and drain region 2606 are planar relative to substrate surface 2608.

[0094] Fig.26B is a perspective view of an exemplary FinFET transistor 2620 including a gate 2622 that controls current flow between a source region 2624 and a drain region 2626. Transistor 2620 is non-planar because source region 2624 and drain region 2626 include a "fin" that extends upward from substrate surface 2628. Because gate 2622 surrounds three sides of the semiconductor fin extending from source region 2624 to drain region 2626, transistor 2620 can be considered a tri-gate transistor. Fig.26B One S / D fin is shown extending through the gate 2622 , but multiple S / D fins may extend through the gate of the FinFET transistor.

[0095] Fig.26C is a perspective view of a gate-around (GAA) transistor 2640 including a gate 2642 that controls current flow between a source region 2644 and a drain region 2646. The transistor 2640 is non-planar because the source region 2644 and the drain region 2646 are elevated from the substrate surface 2628.

[0096] Fig.26D 2660 is a perspective view of a GAA transistor 2660 including a gate 2662 that controls current flow between multiple elevated source regions 2664 and multiple elevated drain regions 2666. Transistor 2660 is a stacked GAA transistor because the gate controls current flow between multiple elevated S / D regions stacked on top of each other. Transistors 2640 and 2660 are considered gate-wrap transistors because the gate wraps around all sides of the semiconductor portion extending from the source region to the drain region. Transistors 2640 and 2660 may alternatively be referred to as nanowire, nanosheet, or nanoribbon transistors, depending on the width of the semiconductor portion extending through the gate (e.g., widths 2648 and 2668 of transistors 2640 and 2660, respectively).

[0097] refer to Fig.25 , transistor 2540 may include a gate 2522 formed of at least two layers (gate dielectric and gate electrode). The gate dielectric may include one layer or a stack of layers. One or more layers may include silicon oxide, silicon dioxide, silicon carbide and / or high-k dielectric material.

[0098] High-k dielectric materials may include elements such as hafnium, silicon, oxygen, titanium, tantalum, lanthanum, aluminum, zirconium, barium, strontium, yttrium, lead, scandium, niobium, and zinc. Examples of high-k materials that may be used in gate dielectrics include, but are not limited to, hafnium oxide, hafnium silicon oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead tantalum scandium oxide, and lead zinc niobate. In some embodiments, an annealing process may be performed on the gate dielectric to improve its quality when a high-k material is used.

[0099] The gate electrode can be formed on the gate dielectric and can include at least one p-type work function metal or n-type work function metal, depending on whether the transistor 2540 will be a p-type metal oxide semiconductor (PMOS) transistor or an n-type metal oxide semiconductor (NMOS) transistor. In some embodiments, the gate electrode can be composed of a stack of two or more metal layers, wherein one or more metal layers are work function metal layers and at least one metal layer is a fill metal layer. Other metal layers can be included for other purposes, such as a barrier layer.

[0100] For PMOS transistors, metals that can be used for the gate electrode include, but are not limited to, ruthenium, palladium, platinum, cobalt, nickel, conductive metal oxides (e.g., ruthenium oxide), and any of the metals discussed below with reference to NMOS transistors (e.g., for work function adjustment). For NMOS transistors, metals that can be used for the gate electrode include, but are not limited to, hafnium, zirconium, titanium, tantalum, aluminum, alloys of these metals, carbides of these metals (e.g., hafnium carbide, zirconium carbide, titanium carbide, tantalum carbide, and aluminum carbide), and any of the metals discussed above with reference to PMOS transistors (e.g., for work function adjustment).

[0101] In some embodiments, when viewed from a cross section of transistor 2540 along the source-channel-drain direction, the gate electrode may be composed of a U-shaped structure including a bottom portion substantially parallel to the surface of die substrate 2502 and two sidewall portions substantially perpendicular to the top surface of die substrate 2502. In other embodiments, at least one of the metal layers forming the gate electrode may simply be a planar layer substantially parallel to the top surface of die substrate 2502 and does not include a sidewall portion substantially perpendicular to the top surface of die substrate 2502. In other embodiments, the gate electrode may be composed of a combination of a U-shaped structure and a planar non-U-shaped structure. For example, the gate electrode may be composed of one or more U-shaped metal layers formed on top of one or more planar non-U-shaped layers.

[0102] In some embodiments, a pair of sidewall spacers may be formed on opposite sides of the gate stack to support the gate stack. The sidewall spacers may be formed of materials such as silicon nitride, silicon oxide, silicon carbide, carbon-doped silicon nitride, and silicon oxynitride. Processes for forming sidewall spacers are known in the art and generally include deposition and etching process steps. In some embodiments, multiple pairs of spacers may be used, for example, two, three, or four pairs of sidewall spacers may be formed on opposite sides of the gate stack.

[0103] The S / D region 2520 may be formed within the die substrate 2502 adjacent to the gate 2522 of the individual transistor 2540. For example, the S / D region 2520 may be formed using an implantation / diffusion process, or may be formed using an etching / deposition process. In the former process, dopants such as boron, aluminum, antimony, phosphorus, or arsenic may be ion implanted into the die substrate 2502 to form the S / D region 2520. The ion implantation process may be followed by an annealing process, which activates the dopant and diffuses it further into the die substrate 2502. In the latter process, the die substrate 2502 may first be etched to form a recess at the location of the S / D region 2520. Thereafter, an epitaxial deposition process may be performed to fill the recess with the material used to make the S / D region 2520. In some embodiments, the S / D region 2520 may be made using a silicon alloy such as silicon germanium or silicon carbide. In some embodiments, the epitaxially deposited silicon alloy may be in-situ doped with dopants such as boron, arsenic, or phosphorus. In other embodiments, one or more alternative semiconductor materials (eg, germanium or III-V materials or alloys) may be used to form S / D region 2520. In other embodiments, S / D region 2520 may be formed using one or more layers of metals and / or metal alloys.

[0104] By providing one or more interconnect layers (in Fig.25The device layer 2504 may be provided with a plurality of interconnect layers 2506-2510 (shown as interconnect layers 2506-2510) to route electrical signals, such as power signals and / or input / output (I / O) signals, to and / or from devices (e.g., transistors 2540) of the device layer 2504. For example, the conductive features (e.g., gates 2522 and S / D contacts 2524) of the device layer 2504 may be electrically coupled to the interconnect structures 2528 of the interconnect layers 2506-2510. One or more interconnect layers 2506-2510 may form a metallization stack (also referred to as an "ILD stack") 2519 of the integrated circuit device 2500.

[0105] Interconnect structures 2528 may be arranged within interconnect layers 2506-2510 to route electrical signals according to a wide variety of designs; in particular, the arrangement is not limited to Fig.25 Although the specific configuration of interconnect structure 2528 is depicted in Fig.25 A particular number of interconnect layers 2506 - 2510 are depicted in FIG. 2 , but embodiments of the present disclosure include integrated circuit devices having more or fewer interconnect layers than depicted.

[0106] In some embodiments, the interconnect structure 2528 may include a line 2528a and / or a via 2528b filled with a conductive material such as a metal. The line 2528a may be arranged to route electrical signals in the direction of a plane substantially parallel to the surface of the die substrate 2502 on which the device layer 2504 is formed. For example, the line 2528a may route electrical signals in the direction of entering and exiting the page and / or in the direction of crossing the page. The via 2528b may be arranged to route electrical signals in the direction of a plane substantially perpendicular to the surface of the die substrate 2502 on which the device layer 2504 is formed. In some embodiments, the via 2528b may electrically couple the lines 2528a of different interconnect layers 2506-2510 together.

[0107] The interconnect layers 2506-2510 may include a dielectric material 2526 disposed between interconnect structures 2528, such as Fig.252506-2510. In some embodiments, the dielectric material 2526 disposed between the interconnect structures 2528 in different layers of the interconnect layers 2506-2510 may have different compositions; in other embodiments, the composition of the dielectric material 2526 between different interconnect layers 2506-2510 may be the same. The device layer 2504 may also include a dielectric material 2526 disposed between the transistor 2540 and the bottom layer of the metallization stack. The dielectric material 2526 included in the device layer 2504 may have a different composition than the dielectric material 2526 included in the interconnect layers 2506-2510; in other embodiments, the composition of the dielectric material 2526 in the device layer 2504 may be the same as the composition of the dielectric material 2526 included in any of the interconnect layers 2506-2510.

[0108] A first interconnect layer 2506 (referred to as metal 1 or "M1") can be formed directly on the device layer 2504. In some embodiments, the first interconnect layer 2506 can include lines 2528a and / or vias 2528b, as shown. The lines 2528a of the first interconnect layer 2506 can be coupled to contacts (e.g., S / D contacts 2524) of the device layer 2504. The vias 2528b of the first interconnect layer 2506 can be coupled to the lines 2528a of the second interconnect layer 2508.

[0109] A second interconnect layer 2508 (referred to as metal 2 or "M2") may be formed directly on the first interconnect layer 2506. In some embodiments, the second interconnect layer 2508 may include vias 2528b to couple lines 2528a of the second interconnect layer 2508 with lines 2528a of the third interconnect layer 2510. Although the lines 2528a and vias 2528b are structurally outlined with lines within individual interconnect layers for clarity, in some embodiments, the lines 2528a and vias 2528b may be continuous in structure and / or material (e.g., filled simultaneously during a dual damascene process).

[0110] A third interconnect layer 2510 (referred to as metal 3 or "M3") (and additional interconnect layers, as needed) may be formed successively on the second interconnect layer 2508 according to similar techniques and configurations described in connection with the second interconnect layer 2508 or the first interconnect layer 2506. In some embodiments, "higher" (i.e., farther from the device layer 2504) interconnect layers in the metallization stack 2519 in the integrated circuit device 2500 may be thicker than lower interconnect layers in the metallization stack 2519, wherein the lines 2528a and vias 2528b in the higher interconnect layers are thicker than those in the lower interconnect layers.

[0111] The integrated circuit device 2500 may include a solder resist material 2534 (eg, polyimide or similar material) formed on the interconnect layers 2506-2510 and one or more conductive contacts 2536. Fig.25 , the conductive contact 2536 is shown as taking the form of a bonding pad. The conductive contact 2536 can be electrically coupled to the interconnect structure 2528 and configured to route electrical signals of the (multiple) transistors 2540 to external devices. For example, a solder joint can be formed on one or more of the conductive contacts 2536 to mechanically and / or electrically couple the integrated circuit die including the integrated circuit device 2500 to another component (e.g., a printed circuit board). The integrated circuit device 2500 may include additional or alternative structures to route electrical signals from the interconnect layers 2506-2510; for example, the conductive contacts 2536 may include other similar features (e.g., pillars) that route electrical signals to external components.

[0112] In some embodiments where the integrated circuit device 2500 is a double-sided die, the integrated circuit device 2500 may include another metallization stack (not shown) on the opposite side of the device layer(s) 2504. The metallization stack may include a plurality of interconnect layers as discussed above with reference to the interconnect layers 2506-2510, thereby providing conductive pathways (e.g., including conductive lines and vias) between the device layer(s) 2504 and additional conductive contacts (not shown) on the opposite side of the integrated circuit device 2500 from the conductive contacts 2536.

[0113] In other embodiments where the integrated circuit device 2500 is a double-sided die, the integrated circuit device 2500 may include one or more through silicon vias (TSVs) through the die substrate 2502; these TSVs may make contact with the device layer(s) 2504 and may provide a conductive path between the device layer(s) 2504 and additional conductive contacts (not shown) located on the side of the integrated circuit device 2500 opposite the conductive contacts 2536. In some embodiments, the TSVs extending through the substrate may be used to route power and ground signals from conductive contacts located on the side of the integrated circuit device 2500 opposite the conductive contacts 2536 to the transistor 2540 and any other components integrated into the die 2500, and the metallization stack 2519 may be used to route I / O signals from the conductive contacts 2536 to the transistor 2540 and any other components integrated into the die 2500.

[0114] A plurality of integrated circuit devices 2500 may be stacked, wherein one or more TSVs in each stacked device provide a connection between one of the devices in the stack and any other device. For example, one or more high bandwidth memory (HBM) integrated circuit dies may be stacked on top of a base integrated circuit die, and the TSVs in the HBM die may provide a connection between the individual HBM and the base integrated circuit die. The conductive contacts may provide additional connections between adjacent integrated circuit dies in the stack. In some embodiments, the conductive contacts may be fine pitch solder bumps (microbumps).

[0115] Fig. 27 2700 . 2700 is a cross-sectional side view of an integrated circuit device assembly 2700 that may include any integrated circuit package 1800 disclosed herein. In some embodiments, the integrated circuit device assembly 2700 may be an integrated circuit package 1800. The integrated circuit device assembly 2700 includes a number of components disposed on a circuit board 2702 (which may be a motherboard, a system board, a main board, etc.). The integrated circuit device assembly 2700 includes components disposed on a first side 2740 of the circuit board 2702 and an opposite second side 2742 of the circuit board 2702; in general, the components may be disposed on one or both of the sides 2740 and 2742. Any integrated circuit component discussed below with reference to the integrated circuit device assembly 2700 may take the form of any suitable embodiment in the embodiments of the integrated circuit package 1800 disclosed herein.

[0116] In some embodiments, circuit board 2702 may be a printed circuit board (PCB) comprising a plurality of metal (or interconnect) layers separated from each other by layers of dielectric material and interconnected by conductive vias. Individual metal layers include conductive traces. Any one or more of the metal layers may be formed in a desired circuit pattern, thereby (optionally in conjunction with other metal layers) routing electrical signals between components coupled to circuit board 2702. In other embodiments, circuit board 2702 may be a non-PCB substrate. In some embodiments, circuit board 2702 may be, for example, circuit board 1802 or 1932. Fig. 27 The integrated circuit device assembly 2700 shown in FIG. 27 includes a package structure on an interposer 2736 coupled to a first side 2740 of a circuit board 2702 via a coupling component 2716. The coupling component 2716 can electrically and mechanically couple the package structure on the interposer 2736 to the circuit board 2702 and can include solder balls (e.g., Fig. 27), pins (e.g., as part of a pin grid array (PGA)), contacts (e.g., as part of a land grid array (LGA)), male and female portions of a socket, adhesives, underfill materials, and / or any other suitable electrical and / or mechanical coupling structures. Coupling component 2716 can function as a coupling component as illustrated or described for any substrate assembly or substrate assembly component described herein, as appropriate.

[0117] The package-on-interposer structure 2736 may include an integrated circuit component 2720 coupled to the interposer 2704 via a coupling component 2718. The coupling component 2718 may take any suitable form for the application, such as the forms discussed above with reference to the coupling component 2716. Fig. 27 2704, but multiple integrated circuit components may be coupled to interposer 2704; indeed, additional interposers may be coupled to interposer 2704. Interposer 2704 may provide an intermediate substrate for bridging circuit board 2702 and integrated circuit components 2720.

[0118] Integrated circuit component 2720 may be a packaged or unpackaged integrated circuit product that includes one or more integrated circuit dies (eg, Fig.24 The tube core 2402, Fig.25 The integrated circuit device 2500 of the packaged integrated circuit device 2500) and / or one or more other appropriate components. The packaged integrated circuit component includes one or more integrated circuit dies mounted on a packaging substrate, wherein the integrated circuit die and the packaging substrate are encapsulated in a housing material such as metal, plastic, glass or ceramic. In one example of an unpackaged integrated circuit component 2720, a single monolithic integrated circuit die includes solder bumps attached to contacts on the die. The solder bumps allow the die to be directly attached to the interposer 2704. The integrated circuit component 2720 may include one or more computing system components, such as one or more processor units (e.g., system on chip (SoC), processor core, graphics processor unit (GPU), accelerator, chipset processor), I / O controller, memory or network interface controller. In some embodiments, the integrated circuit component 2720 may include one or more additional active or passive devices, such as capacitors, decoupling capacitors, resistors, inductors, fuses, diodes, transformers, sensors, electrostatic discharge (ESD) devices and memory devices.

[0119] In embodiments where the integrated circuit component 2720 includes multiple integrated circuit dies, the dies may be of the same type (a homogeneous multi-die integrated circuit component) or of two or more different types (a heterogeneous multi-die integrated circuit component). A multi-die integrated circuit component may be referred to as a multi-chip package (MCP) or a multi-chip module (MCM).

[0120] In addition to including one or more processor units, the integrated circuit component 2720 may include additional components, such as embedded DRAM, stacked high bandwidth memory (HBM), shared cache memory, an input / output (I / O) controller, or a memory controller. Any of these additional components may be located on the same integrated circuit die as the processor unit, or on one or more integrated circuit dies separate from the integrated circuit die that includes the processor unit. These separate integrated circuit dies may be referred to as "chiplets." In embodiments where the integrated circuit component includes multiple integrated circuit dies, the interconnections between the dies may be provided by a packaging substrate, one or more silicon interposers, one or more silicon bridges embedded in the packaging substrate (e.g., Embedded Multi-Die Interconnect Bridge (EMIB)) or a combination thereof is provided.

[0121] In general, interposer 2704 can extend connections to a wider pitch or reroute connections to different connections. For example, interposer 2704 can couple integrated circuit component 2720 to a set of ball grid array (BGA) conductive contacts of coupling component 2716 for coupling to circuit board 2702. Fig. 27 In the illustrated embodiment, integrated circuit component 2720 and circuit board 2702 are attached to opposite sides of interposer 2704; in other embodiments, integrated circuit component 2720 and circuit board 2702 may be attached to the same side of interposer 2704. In some embodiments, three or more components may be interconnected via interposer 2704.

[0122] In some embodiments, interposer 2704 may be formed as a PCB including multiple metal layers separated from each other by layers of dielectric material and interconnected by conductive vias. In some embodiments, interposer 2704 may be formed of epoxy, glass fiber reinforced epoxy, epoxy with inorganic fillers, ceramic material, or polymer material such as polyimide. In some embodiments, interposer 2704 may be formed of alternative rigid or flexible materials, which may include the same materials as those used in the semiconductor substrate described above, such as silicon, germanium, and other III-V and IV materials. The interposer 2704 may include metal interconnects 2708 and vias 2710, which include but are not limited to through-hole vias 2710-1 (which extend from the first side 2750 of the interposer 2704 to the second side 2754 of the interposer 2704), blind vias 2710-2 (which extend from the first side 2750 or the second side 2754 of the interposer 2704 to internal metal layers), and buried vias 2710-3 (which connect internal metal layers).

[0123] In some embodiments, interposer 2704 may include a silicon interposer. Through-silicon vias (TSVs) extending through the silicon interposer may connect connections on a first side of the silicon interposer to an opposite second side of the silicon interposer. In some embodiments, interposer 2704 including a silicon interposer may further include one or more routing layers to route connections on a first side of interposer 2704 to an opposite second side of interposer 2704.

[0124] Interposer 2704 may also include embedded devices 2714, which include both passive and active devices. Such devices may include, but are not limited to, capacitors, decoupling capacitors, resistors, inductors, fuses, diodes, transformers, sensors, electrostatic discharge (ESD) devices, and memory devices. More complex devices, such as radio frequency devices, power amplifiers, power management devices, antennas, arrays, sensors, and micro-electromechanical systems (MEMS) devices, may also be formed on interposer 2704. Interposer package structure 2736 may take the form of any interposer package structure known in the art.

[0125] The integrated circuit device assembly 2700 may include an integrated circuit component 2724 coupled to the first side 2740 of the circuit board 2702 via a coupling component 2722. The coupling component 2722 may take the form of any of the embodiments discussed above with reference to the coupling component 2716, and the integrated circuit component 2724 may take the form of any of the embodiments discussed above with reference to the integrated circuit component 2720.

[0126] Fig. 27 The integrated circuit device assembly 2700 shown in FIG. 27 includes a package-on-package structure 2734 coupled to a second side 2742 of a circuit board 2702 by a coupling component 2728. The package-on-package structure 2734 may include an integrated circuit component 2726 and an integrated circuit component 2732, which are coupled together by a coupling component 2730, such that the integrated circuit component 2726 is disposed between the circuit board 2702 and the integrated circuit component 2732. The coupling components 2728 and 2730 may take the form of any of the embodiments of the coupling component 2716 discussed above, and the integrated circuit components 2726 and 2732 may take the form of any of the embodiments of the integrated circuit component 2720 discussed above. The package-on-package structure 2734 may be configured according to any package-on-package structure known in the art.

[0127] Fig.282 is a block diagram of an exemplary electrical device 2800 that may include one or more of the integrated circuit packages 1800 disclosed herein. For example, any suitable component of the components of the electrical device 2800 may include one or more of the integrated circuit device assembly 2700, the integrated circuit component 2720, the integrated circuit device 2500, or the integrated circuit die 2402 disclosed herein, and may be arranged in any of the integrated circuit packages 1800 disclosed herein. Fig.28 Several components are shown as included in the electrical device 2800, but any one or more of these components may be omitted or duplicated to suit the application. In some embodiments, some or all of the components included in the electrical device 2800 may be attached to one or more motherboards, mainboards, or system boards. In some embodiments, one or more of these components are fabricated on a single system-on-chip (SoC) die.

[0128] Furthermore, in various embodiments, the electrical device 2800 may not include Fig.28 2800 may include one or more of the components shown in , but the electrical device 2800 may include interface circuitry for coupling to one or more components. For example, the electrical device 2800 may not include the display device 2806, but may include display device interface circuitry (e.g., connector and driver circuitry) to which the display device 2806 may be coupled. In another set of examples, the electrical device 2800 may not include the audio input device 2824 or the audio output device 2808, but may include audio input or output device interface circuitry (e.g., connector and support circuitry) to which the audio input device 2824 or the audio output device 2808 may be coupled.

[0129] The electrical device 2800 may include one or more processor units 2802 (e.g., one or more processor units). As used herein, the term "processor unit," "processing unit," or "processor" may refer to any device or portion of a device that processes electronic data from registers and / or memory to transform the electronic data into other electronic data that can be stored in registers and / or memory. The processor unit 2802 may include one or more digital signal processors (DSPs), application specific integrated circuits (ASICs), central processing units (CPUs), graphics processing units (GPUs), general purpose GPUs (GPGPUs), accelerated processing units (APUs), field programmable gate arrays (FPGAs), neural network processing units (NPUs), data processor units (DPUs), accelerators (e.g., graphics accelerators, compression accelerators, artificial intelligence accelerators), controller cryptographic processors (special processors that execute cryptographic algorithms in hardware), server processors, controllers, or any other suitable type of processor unit. As such, a processor unit may be referred to as an XPU (or xPU).

[0130] The electrical device 2800 may include a memory 2804, which itself may include one or more memory devices, such as volatile memory (e.g., dynamic random access memory (DRAM)), static random access memory (SRAM), non-volatile memory (e.g., read-only memory (ROM), flash memory, chalcogenide-based phase change non-volatile memory), solid-state memory, and / or a hard disk drive. In some embodiments, the memory 2804 may include memory located on the same integrated circuit die as the processor unit 2802. The memory may be used as a cache memory (e.g., level 1 (L1), level 2 (L2), level 3 (L3), level 4 (L4), last level cache (LLC)), and may include embedded dynamic random access memory (eDRAM) or spin transfer torque magnetic random access memory (STT-MRAM).

[0131] In some embodiments, the electrical device 2800 may include one or more processor units 2802 that are heterogeneous or asymmetric relative to another processor unit 2802 in the electrical device 2800. There may be a variety of differences between the processing units 2802 in the system across a range of merit measures including architectural, microarchitectural, thermal, power consumption characteristics, etc. These differences may manifest themselves substantially as asymmetry and heterogeneity between the processor units 2802 in the electrical device 2800.

[0132] In some embodiments, electrical device 2800 may include communication components 2812 (e.g., one or more communication components). For example, communication components 2812 may manage wireless communications for transmitting data to and from electrical device 2800. The term "wireless" and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communication channels, etc. that can transmit data through a non-solid medium by using modulated electromagnetic radiation. The term "wireless" does not imply that the associated devices do not contain any wires, although in some embodiments they may not.

[0133] The communication component 2812 can implement any of a wide variety of wireless standards or protocols, including but not limited to Institute of Electrical and Electronics Engineers (IEEE) standards (including WiFi (IEEE 802.11 series), IEEE 802.16 standards (e.g., IEEE 802.16-2005 amendments)), Long Term Evolution (LTE) projects together with any amendments, updates and / or revisions (e.g., Advanced LTE projects, Ultra Mobile Broadband (UMB) projects (also known as "3GPP2"), etc.). IEEE 802.16-compatible broadband wireless access (BWA) networks are generally referred to as WiMAX networks, which is an acronym for Worldwide Interoperability for Microwave Access, which is a certification mark for products that have passed compliance and interoperability testing of the IEEE 802.16 standards. The communication component 2812 can operate according to a Global System for Mobile Communications (GSM), General Packet Radio Service (GPRS), Universal Mobile Telecommunications System (UMTS), High Speed ​​Packet Access (HSPA), Evolved HSPA (E-HSPA), or LTE network. The communication component 2812 can operate according to Enhanced Data Rates for GSM Evolution (EDGE), GSM EDGE Radio Access Network (GERAN), Universal Terrestrial Radio Access Network (UTRAN), or Evolved UTRAN (E-UTRAN). The communication component 2812 can operate according to Code Division Multiple Access (CDMA), Time Division Multiple Access (TDMA), Digital Enhanced Cordless Telecommunications (DECT), Evolution Data Optimized (EV-DO), their derivatives, and any other wireless protocols designated as 3G, 4G, 5G and higher generations. In other embodiments, the communication component 2812 can operate according to other wireless protocols. The electrical device 2800 may include an antenna 2822 to facilitate wireless communications and / or receive other wireless communications (e.g., AM or FM radio transmissions).

[0134] In some embodiments, the communication component 2812 can manage wired communications, such as electrical, optical, or any other suitable communication protocol (e.g., IEEE 802.3 Ethernet standard). As described above, the communication component 2812 can include multiple communication components. For example, the first communication component 2812 can be dedicated to shorter-range wireless communications, such as Wi-Fi or Bluetooth, and the second communication component 2812 can be dedicated to longer-range wireless communications, such as global positioning systems (GPS), EDGE, GPRS, CDMA, WiMAX, LTE, EV-DO and others. In some embodiments, the first communication component 2812 can be dedicated to wireless communications, and the second communication component 2812 can be dedicated to wired communications.

[0135] The electrical device 2800 may include a battery / power circuit system 2814. The battery / power circuit system 2814 may include one or more energy storage devices (e.g., batteries or capacitors) and / or circuit systems for coupling components of the electrical device 2800 to an energy source separate from the electrical device 2800 (e.g., AC line power).

[0136] The electrical device 2800 may include a display device 2806 (or corresponding interface circuitry, as described above). The display device 2806 may include one or more embedded or wired or wirelessly connected external visual indicators, such as a head-up display, a computer monitor, a projector, a touch screen display, a liquid crystal display (LCD), a light emitting diode display, or a flat panel display.

[0137] The electrical device 2800 may include an audio output device 2808 (or corresponding interface circuitry, as discussed above). The audio output device 2808 may include any embedded or wired or wirelessly connected external device that generates an audible indication, such as a speaker, headphones, or earbuds.

[0138] The electrical device 2800 may include an audio input device 2824 (or corresponding interface circuitry, as discussed above). The audio input device 2824 may include any embedded or wired or wirelessly connected device that generates a signal representing sound, such as a microphone, a microphone array, or a digital instrument (e.g., an instrument with a musical instrument digital interface (MIDI) output). The electrical device 2800 may include a global navigation satellite system (GNSS) device 2818 (or corresponding interface circuitry, as discussed above), such as a global positioning system (GPS) device. The GNSS device 2818 may communicate with a satellite-based system and may determine the geographic location of the electrical device 2800 based on information received from one or more GNSS satellites, as is known in the art.

[0139] Electrical device 2800 may include other output devices 2810 (or corresponding interface circuitry, as discussed above). Examples of other output devices 2810 may include an audio codec, a video codec, a printer, a wired or wireless transmitter for providing information to other devices, or additional storage.

[0140] The electrical device 2800 may include other input devices 2820 (or corresponding interface circuitry, as discussed above). Examples of other input devices 2820 may include an accelerometer, a gyroscope, a compass, an image capture device (e.g., a monoscopic or stereoscopic imaging camera), a trackball, a trackpad, a touchpad, a keyboard, a cursor control device such as a mouse, a stylus, a touch screen, a proximity sensor, a microphone, a barcode reader, a quick response (QR) code reader, an electrocardiogram (ECG) sensor, a PPG (photoplethysmography) sensor, a galvanic skin response sensor, any other sensor, or a radio frequency identification (RFID) reader.

[0141] The electrical device 2800 may have any desired form factor, such as a portable or mobile electrical device (e.g., a cellular phone, a smart phone, a mobile Internet device, a music player, a tablet computer, a laptop computer, a two-in-one convertible computer, a portable all-in-one computer, a notebook computer, an ultrabook computer, a personal digital assistant (PDA), an ultra-mobile personal computer, a portable game console, etc.), a desktop electrical device, a server, a rack-level computing solution (e.g., a blade, tray, or slide computing system), a workstation or other networked computing component, a printer, a scanner, a monitor, a set-top box, an entertainment control unit, a fixed game console, a smart TV, a vehicle control unit, a digital camera, a digital video recorder, a wearable electrical device, or an embedded computing system (e.g., a computing system as part of a vehicle, a smart appliance, a consumer electronic product or device, a manufacturing device). In some embodiments, the electrical device 2800 may be any other electronic device that processes data. In some embodiments, the electrical device 2800 may include multiple discrete physical components. In view of the range of devices that the electrical device 2800 can be in various embodiments, in some embodiments, the electrical device 2800 may be referred to as a computing device or a computing system.

[0142] Example

[0143] The following provides illustrative examples of the technology disclosed herein. Embodiments of the technology may include any one or more of the examples described below and any combination thereof.

[0144] Example 1 includes a device comprising: a photonic integrated circuit (PIC) die comprising one or more waveguides; an optical interposer mated with the PIC die, the optical interposer comprising one or more waveguides, wherein individual ones of the one or more waveguides of the optical interposer are aligned to individual ones of the one or more waveguides of the PIC die; a mechanical adhesive securing the optical interposer to the PIC die; and an index matching material located between the one or more waveguides of the PIC die and the one or more waveguides of the optical interposer, wherein the mechanical adhesive is different from the index matching material.

[0145] Example 2 includes the subject matter of Example 1, and wherein the mechanical binder comprises monodisperse particles suspended in the mechanical binder.

[0146] Example 3 includes the subject matter of any of Examples 1 and 2, and wherein the monodisperse particles have a diameter between 500 nanometers and 5 micrometers.

[0147] Example 4 includes the subject matter of any of Examples 1-3, and wherein the coefficient of thermal expansion (CTE) of the mechanical adhesive is less than 10 -5 K -1 , wherein the CTE of the refractive index matching material is greater than 2 x 10 -5 K -1 .

[0148] Example 5 includes the subject matter of any of Examples 1-4, and wherein the mechanical adhesive is thermally cured, and wherein the index matching material is ultraviolet light cured.

[0149] Example 6 includes the subject matter of any of Examples 1-5, and wherein the optical interposer includes one or more V-grooves defined in a surface of the optical interposer, wherein the PIC die includes one or more V-grooves defined in a surface of the PIC die, wherein the one or more V-grooves of the PIC die mate with the one or more V-grooves of the optical interposer, and wherein at least a portion of the mechanical adhesive is positioned between the one or more V-grooves of the PIC die and the one or more V-grooves of the optical interposer.

[0150] Example 7 includes the subject matter of any of Examples 1-6, and wherein the optical interposer further comprises a wing extending from an area of ​​the optical interposer having the one or more V-grooves to a side of the optical interposer, wherein at least a portion of the mechanical adhesive is positioned between the wing and a surface of the PIC die.

[0151] Example 8 includes the subject matter of any of Examples 1-7, and wherein the optical interposer extends beyond an edge of the PIC die, wherein a sidewall of the optical interposer extends below a plane defined by the surface of the PIC die, and wherein at least a portion of the mechanical adhesive is positioned between the sidewall of the optical interposer and a sidewall of the PIC die.

[0152] Example 9 includes the subject matter of any of Examples 1-8, and wherein the one or more V-grooves of the PIC die include one or more peaks and one or more valleys, wherein the one or more V-grooves of the optical interposer include one or more peaks and one or more valleys, wherein individual ones of the one or more peaks of the one or more V-grooves of the PIC die mate with individual ones of the one or more valleys of the one or more V-grooves of the optical interposer.

[0153] Example 10 includes the subject matter of any of Examples 1-9, and wherein sidewalls of individual ones of the one or more V-grooves of the optical interposer do not apply stress to sidewalls of individual ones of the one or more V-grooves of the PIC die.

[0154] Example 11 includes the subject matter of any of Examples 1-10, and wherein one or more grooves are defined in the PIC die between the one or more waveguides of the PIC die and the one or more V-grooves of the PIC die, wherein the index matching material at least partially fills the one or more grooves.

[0155] Example 12 includes the subject matter of any of Examples 1-11, and wherein the PIC die includes one or more additional V-grooves defined in the surface of the PIC die, wherein the one or more additional V-grooves of the PIC die mate with the one or more V-grooves of the optical interposer, and wherein a groove is defined in the PIC die between the one or more V-grooves of the PIC die and the one or more additional V-grooves of the PIC die.

[0156] Example 13 includes the subject matter of any of Examples 1-12, and wherein more than half of the trench is filled with the mechanical adhesive.

[0157] Example 14 includes the subject matter of any of Examples 1-13, and wherein more than half of the trench is filled with the index matching material.

[0158] Example 15 includes the subject matter of any of Examples 1-14, and wherein a groove is defined in the PIC die between the one or more V-grooves of the PIC die and a wall at a side surface of the PIC die, wherein the mechanical adhesive fills at least a portion of the groove.

[0159] Example 16 includes an integrated circuit package including the apparatus of Example 1, further including one or more electronic integrated circuit (EIC) dies, wherein the one or more EIC dies are electrically coupled to the PIC die.

[0160] Example 17 includes the subject matter of Example 16, and further includes an optical plug that mates with the optical interposer.

[0161] Example 18 includes the subject matter of any of Examples 16 and 17, and wherein the one or more waveguides of the optical interposer include at least eight waveguides.

[0162] Example 19 includes a device comprising: a photonic integrated circuit (PIC) die comprising one or more waveguides; one or more V-grooves defined in a surface of the PIC die, the one or more V-grooves of the PIC die comprising one or more peaks and one or more valleys; and an optical interposer mating with the PIC die, the optical interposer comprising one or more waveguides, wherein individual ones of the one or more waveguides of the optical interposer are aligned to individual ones of the one or more waveguides of the PIC die; and one or more V-grooves defined in a surface of the optical interposer, the one or more V-grooves of the optical interposer comprising one or more peaks and one or more valleys, wherein individual ones of the one or more peaks of the one or more V-grooves of the PIC die mate with individual ones of the one or more valleys of the one or more V-grooves of the optical interposer.

[0163] Example 20 includes the subject matter of Example 19, and wherein sidewalls of individual ones of the one or more V-grooves of the optical interposer do not apply stress to sidewalls of individual ones of the one or more V-grooves of the PIC die.

[0164] Example 21 includes the subject matter of any of Examples 19 and 20, and wherein one or more grooves are defined in the PIC die between the one or more waveguides of the PIC die and the one or more V-grooves of the PIC die, wherein the index matching material at least partially fills the one or more grooves.

[0165] Example 22 includes the subject matter of any of Examples 19-21, and wherein the PIC die includes one or more additional V-grooves defined in the surface of the PIC die, wherein the one or more additional V-grooves of the PIC die mate with the one or more V-grooves of the optical interposer, and wherein a groove is defined in the PIC die between the one or more V-grooves of the PIC die and the one or more additional V-grooves of the PIC die.

[0166] Example 23 includes the subject matter of any of Examples 19-22, and wherein more than half of the trench is filled with a mechanical adhesive.

[0167] Example 24 includes the subject matter of any of Examples 19-23, and wherein more than half of the trench is filled with an index matching material.

[0168] Example 25 includes the subject matter of any of Examples 19-24, and wherein a groove is defined in the PIC die between the one or more V-grooves of the PIC die and a wall at a side surface of the PIC die, wherein a mechanical adhesive fills at least a portion of the groove.

[0169] Example 26 includes the subject matter of any of Examples 19-25, and further includes: a mechanical adhesive that secures the optical interposer to the PIC die; and an index matching material between the one or more waveguides of the PIC die and the one or more waveguides of the optical interposer, wherein the mechanical adhesive is different from the index matching material.

[0170] Example 27 includes the subject matter of any of Examples 19-26, and wherein the mechanical binder includes monodisperse particles suspended in the mechanical binder.

[0171] Example 28 includes the subject matter of any of Examples 19-27, and wherein the monodisperse particles have a diameter between 500 nanometers and 5 micrometers.

[0172] Example 29 includes the subject matter of any of Examples 19-28, and wherein the coefficient of thermal expansion (CTE) of the mechanical adhesive is less than 10 -5 K -1 , wherein the CTE of the refractive index matching material is greater than 2 x 10 -5 K -1 .

[0173] Example 30 includes the subject matter of any of Examples 19-29, and wherein the mechanical adhesive is thermally cured, and wherein the index matching material is UV cured.

[0174] Example 31 includes the subject matter of any of Examples 19-30, and wherein at least a portion of the mechanical adhesive is positioned between the one or more V-grooves of the PIC die and the one or more V-grooves of the optical interposer.

[0175] Example 32 includes the subject matter of any of Examples 19-31, and wherein the optical interposer further comprises a wing extending from an area of ​​the optical interposer having the one or more V-grooves to a side of the optical interposer, wherein at least a portion of the mechanical adhesive is positioned between the wing and a surface of the PIC die.

[0176] Example 33 includes the subject matter of any of Examples 19-32, and wherein the optical interposer extends beyond an edge of the PIC die, wherein sidewalls of the optical interposer extend below a plane defined by the surface of the PIC die, and wherein at least a portion of the mechanical adhesive is positioned between the sidewalls of the optical interposer and the sidewalls of the PIC die.

[0177] Example 34 includes an integrated circuit package including the apparatus of Example 19, further comprising one or more electronic integrated circuit (EIC) dies, wherein the one or more EIC dies are electrically coupled to the PIC die.

[0178] Example 35 includes the subject matter of Example 34, and further includes an optical plug that mates with the optical interposer.

[0179] Example 36 includes the subject matter of any of Examples 34 and 35, and wherein the one or more waveguides of the optical interposer include at least eight waveguides.

[0180] Example 37 includes a method comprising: positioning an optical interposer on a photonic integrated circuit (PIC) die, wherein the optical interposer includes one or more waveguides, wherein the PIC die includes one or more waveguides, wherein the optical interposer is positioned so that individual ones of the one or more waveguides of the optical interposer are aligned to individual ones of the one or more waveguides of the PIC die, wherein a refractive index matching material is positioned between the one or more waveguides of the PIC die and the one or more waveguides of the optical interposer, wherein a mechanical adhesive is positioned between at least a portion of the optical interposer and at least a portion of the PIC die; thermally curing the mechanical adhesive without curing the refractive index matching material; and curing the refractive index matching material using ultraviolet light after thermally curing the mechanical adhesive.

[0181] Example 38 includes the subject matter of Example 37, and wherein the PIC die includes a wall at a side surface of the PIC die, wherein the wall forms part of a groove defined in the PIC die, wherein the wall prevents at least one of the mechanical adhesive and the index matching material from leaking down the side surface of the PIC die prior to being cured.

[0182] Example 39 includes the subject matter of any of Examples 37 and 38, and wherein the mechanical adhesive has a viscosity greater than 10,000 centipoise prior to curing, and wherein the index matching material has a viscosity less than 1,000 centipoise prior to curing.

[0183] Example 40 includes the subject matter of any of Examples 37-39, and wherein the mechanical binder includes monodisperse particles suspended in the mechanical binder.

[0184] Example 41 includes the subject matter of any of Examples 37-40, and wherein the monodisperse particles have a diameter between 500 nanometers and 5 micrometers.

[0185] Example 42 includes the subject matter of any of Examples 37-41, and wherein the coefficient of thermal expansion (CTE) of the mechanical adhesive is less than 10 -5 K -1 , wherein the CTE of the refractive index matching material is greater than 2 x 10 -5 K -1 .

[0186] Example 43 includes the subject matter of any of Examples 37-42, and wherein the mechanical adhesive is thermally cured, and wherein the index matching material is ultraviolet light cured.

[0187] Example 44 includes the subject matter of any of Examples 37-43, and wherein the optical interposer includes one or more V-grooves defined in a surface of the optical interposer, wherein the PIC die includes one or more V-grooves defined in a surface of the PIC die, wherein the one or more V-grooves of the PIC die mate with the one or more V-grooves of the optical interposer, and wherein at least a portion of the mechanical adhesive is positioned between the one or more V-grooves of the PIC die and the one or more V-grooves of the optical interposer.

[0188] Example 45 includes the subject matter of any of Examples 37-44, and wherein the optical interposer further comprises a wing extending from an area of ​​the optical interposer having the one or more V-grooves to a side of the optical interposer, wherein at least a portion of the mechanical adhesive is positioned between the wing and a surface of the PIC die.

[0189] Example 46 includes the subject matter of any of Examples 37-45, and wherein the optical interposer extends beyond an edge of the PIC die, wherein a sidewall of the optical interposer extends below a plane defined by the surface of the PIC die, and wherein at least a portion of the mechanical adhesive is positioned between the sidewall of the optical interposer and a sidewall of the PIC die.

[0190] Example 47 includes the subject matter of any of Examples 37-46, and wherein the one or more V-grooves of the PIC die include one or more peaks and one or more valleys, wherein the one or more V-grooves of the optical interposer include one or more peaks and one or more valleys, wherein individual ones of the one or more peaks of the one or more V-grooves of the PIC die mate with individual ones of the one or more valleys of the one or more V-grooves of the optical interposer.

[0191] Example 48 includes the subject matter of any of Examples 37-47, and wherein sidewalls of individual ones of the one or more V-grooves of the optical interposer do not apply stress to sidewalls of individual ones of the one or more V-grooves of the PIC die.

[0192] Example 49 includes the subject matter of any of Examples 37-48, and wherein one or more grooves are defined in the PIC die between the one or more waveguides of the PIC die and the one or more V-grooves of the PIC die, wherein the index matching material at least partially fills the one or more grooves.

[0193] Example 50 includes the subject matter of any of Examples 37-49, and wherein the PIC die includes one or more additional V-grooves defined in the surface of the PIC die, wherein the one or more additional V-grooves of the PIC die mate with the one or more V-grooves of the optical interposer, and wherein a groove is defined in the PIC die between the one or more V-grooves of the PIC die and the one or more additional V-grooves of the PIC die.

[0194] Example 51 includes the subject matter of any of Examples 37-50, and wherein more than half of the trench is filled with a mechanical adhesive.

[0195] Example 52 includes the subject matter of any of Examples 37-51, and wherein more than half of the trench is filled with an index matching material.

[0196] Example 53 includes the subject matter of any of Examples 37-52, and wherein a groove is defined in the PIC die between the one or more V-grooves of the PIC die and a wall at a side surface of the PIC die, wherein the mechanical adhesive fills at least a portion of the groove.

[0197] Example 54 includes the subject matter of any of Examples 37-53, and further includes mating an optical plug with the optical interposer.

[0198] Example 55 includes the subject matter of any of Examples 37-54, and wherein the one or more waveguides of the optical interposer include at least eight waveguides.

Claims

1. A device comprising: a photonic integrated circuit (PIC) die comprising one or more waveguides; an optical interposer mated to the PIC die, the optical interposer comprising one or more waveguides, wherein individual ones of the one or more waveguides of the optical interposer are aligned to individual ones of the one or more waveguides of the PIC die; a mechanical adhesive securing the optical interposer to the PIC die; and and an index matching material between the one or more waveguides of the PIC die and the one or more waveguides of the optical interposer, wherein the mechanical adhesive is different from the index matching material.

2. The device according to claim 1, wherein: The mechanical binder includes monodisperse particles suspended in the mechanical binder.

3. The device according to claim 1, wherein: The coefficient of thermal expansion (CTE) of the mechanical adhesive is less than 10 -5 K -1 , wherein the CTE of the refractive index matching material is greater than 2 x 10 -5 K -1 .

4. The device according to claim 1, wherein: The mechanical adhesive is heat cured, wherein the index matching material is UV cured.

5. The device according to any one of claims 1 to 4, wherein: The optical interposer includes one or more V-grooves defined in a surface of the optical interposer, wherein the PIC die includes one or more V-grooves defined in a surface of the PIC die, wherein the one or more V-grooves of the PIC die mate with the one or more V-grooves of the optical interposer, and wherein at least a portion of the mechanical adhesive is positioned between the one or more V-grooves of the PIC die and the one or more V-grooves of the optical interposer.

6. The device according to claim 5, wherein: The optical interposer further includes a wing extending from an area of ​​the optical interposer having the one or more V-grooves to a side of the optical interposer, wherein at least a portion of the mechanical adhesive is positioned between the wing and a surface of the PIC die.

7. The device according to claim 6, wherein: The optical interposer extends beyond an edge of the PIC die, wherein sidewalls of the optical interposer extend below a plane defined by the surface of the PIC die, wherein at least a portion of the mechanical adhesive is positioned between the sidewalls of the optical interposer and the sidewalls of the PIC die.

8. The device according to claim 5, wherein: One or more trenches are defined in the PIC die between the one or more waveguides of the PIC die and the one or more V-grooves of the PIC die, wherein the index matching material at least partially fills the one or more trenches.

9. The device according to claim 5, wherein: The PIC die includes one or more additional V-grooves defined in the surface of the PIC die, wherein the one or more additional V-grooves of the PIC die cooperate with the one or more V-grooves of the optical interposer, and wherein a groove is defined in the PIC die between the one or more V-grooves of the PIC die and the one or more additional V-grooves of the PIC die.

10. The device according to claim 9, wherein: More than half of the trench is filled with the mechanical adhesive.

11. The device according to claim 9, wherein: More than half of the trench is filled with the index matching material.

12. The device according to claim 5, wherein: A groove is defined in the PIC die between the one or more V-grooves of the PIC die and a wall at a side surface of the PIC die, wherein the mechanical adhesive fills at least a portion of the groove.

13. An integrated circuit package comprising the apparatus of claim 1, further comprising one or more electronic integrated circuit (EIC) dies, wherein: The one or more EIC dies are electrically coupled to the PIC die.

14. A device comprising: Photonic integrated circuit (PIC) die, including: one or more waveguides; one or more V-grooves defined in a surface of the PIC die, the one or more V-grooves of the PIC die comprising one or more peaks and one or more valleys; and An optical interposer that cooperates with the PIC die, the optical interposer comprising: one or more waveguides, wherein individual ones of the one or more waveguides of the optical interposer are aligned to individual ones of the one or more waveguides of the PIC die; and one or more V-grooves defined in a surface of the optical interposer, the one or more V-grooves of the optical interposer comprising one or more peaks and one or more valleys, Wherein, individual ones of the one or more peaks of the one or more V-grooves of the PIC die mate with individual ones of the one or more valleys of the one or more V-grooves of the optical interposer.

15. The device according to claim 14, wherein: Sidewalls of individual ones of the one or more V-grooves of the optical interposer do not apply stress to sidewalls of individual ones of the one or more V-grooves of the PIC die.

16. The apparatus according to claim 14 or 15, wherein: One or more trenches are defined in the PIC die between the one or more waveguides of the PIC die and the one or more V-grooves of the PIC die, wherein an index matching material at least partially fills the one or more trenches.

17. The apparatus according to claim 14 or 15, wherein: The PIC die includes one or more additional V-grooves defined in the surface of the PIC die, wherein the one or more additional V-grooves of the PIC die cooperate with the one or more V-grooves of the optical interposer, and wherein a groove is defined in the PIC die between the one or more V-grooves of the PIC die and the one or more additional V-grooves of the PIC die.

18. The apparatus according to claim 17, wherein: The trench is more than half filled with a mechanical adhesive.

19. The apparatus according to claim 17, wherein: More than half of the trench is filled with index matching material.

20. The apparatus according to claim 14 or 15, wherein: A groove is defined in the PIC die between the one or more V-grooves of the PIC die and a wall at a side surface of the PIC die, wherein a mechanical adhesive fills at least a portion of the groove.

21. The apparatus according to claim 14 or 15, further comprising: a mechanical adhesive securing the optical interposer to the PIC die; as well as and an index matching material between the one or more waveguides of the PIC die and the one or more waveguides of the optical interposer, wherein the mechanical adhesive is different from the index matching material.

22. The apparatus according to claim 21, wherein The mechanical binder includes monodisperse particles suspended in the mechanical binder.

23. A method comprising: positioning an optical interposer on a photonic integrated circuit (PIC) die, wherein the optical interposer comprises one or more waveguides, wherein the PIC die comprises one or more waveguides, wherein the optical interposer is positioned such that individual ones of the one or more waveguides of the optical interposer are aligned to individual ones of the one or more waveguides of the PIC die, wherein a refractive index matching material is positioned between the one or more waveguides of the PIC die and the one or more waveguides of the optical interposer, wherein a mechanical adhesive is positioned between at least a portion of the optical interposer and at least a portion of the PIC die; thermally curing the mechanical adhesive without curing the index matching material; and After thermally curing the mechanical adhesive, ultraviolet light is used to cure the index matching material.

24. The method according to claim 23, wherein: The PIC die includes a wall at a side surface of the PIC die, wherein the wall forms part of a groove defined in the PIC die, wherein the wall prevents at least one of the mechanical adhesive and the index matching material from leaking down the side surface of the PIC die before being cured.

25. The method according to claim 23 or 24, wherein: The mechanical adhesive has a viscosity of more than 10,000 centipoise before curing, wherein the refractive index matching material has a viscosity of less than 1,000 centipoise before curing.

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