True random number generator and entropy maintenance method thereof

Abstract

The invention relates to a true random number generator and an entropy maintenance method thereof. The true random number generator comprises a plurality of first ring oscillation output circuits, and the entropy maintaining method of the true random number generator comprises the following steps: providing at least one second ring oscillation output circuit in the true random number generator, the at least one second ring oscillation output circuit is not started during initial operation; after the true random number generator starts to operate, recording logic of a random bit signal generated at each default time; counting the logic of the random bit signal to obtain a statistical value; and according to the statistical value, determining whether the second ring oscillation output circuit performs combined operation or not so as to generate the random bit signal.

Description

Technical Field

[0001] The present application relates to a true random number generator technology, and in particular to a true random number generator and an entropy value maintenance method thereof. Background Art

[0002] TRNG is the abbreviation of True Random Number Generator, which is a device or algorithm that can generate random numbers physically. TRNG uses the randomness of physical processes to generate random numbers, such as radioactive decay, thermal noise, thermal fluctuations of electronic devices, etc. The random numbers generated by TRNG are highly random and unpredictable, so they are widely used in cryptography, analog computing and other fields. The entropy of the ring oscillator can be applied to the TRNG because its output sequence is random and uncertain. Through proper processing and screening, the output sequence of the ring oscillator can be used as the source of the TRNG.

[0003] The entropy of a ring oscillator indicates the degree of randomness and uncertainty of its output sequence. The higher the entropy value, the more random and uncertain the output sequence is. The entropy of a ring oscillator is related to signal jitter. Since the waveform of the output signal of a ring oscillator is irregular and random, there is a large amount of clock deviation and clock signal jitter in its output sequence. The magnitude of signal jitter depends on the degree of randomness and uncertainty of the internal signal waveform of the ring oscillator. When the entropy of a ring oscillator is higher, the clock deviation and clock jitter in the output sequence may be larger.

[0004] In order to increase the entropy of the true random number generator, multiple ring oscillators are used. However, using more ring oscillators will result in higher power consumption. Summary of the invention

[0005] The present application provides a true random number generator and an entropy value maintenance method thereof, which are used to generate random bit values, maintain the entropy value of the generated random bit values, and reduce power consumption.

[0006] The embodiment of the present application provides a true random number generator, which includes a plurality of first ring oscillation output circuits, at least one second ring oscillation output circuit, a first logic circuit, an output latch circuit, and a temporary storage and control circuit. Each first ring oscillation output circuit receives a first frequency, and each first ring oscillation output circuit outputs a first logic signal according to the first frequency. When the second ring oscillation output circuit is activated, the activated second ring oscillation output circuit receives the first frequency, and according to the first frequency, the activated second ring oscillation output circuit outputs a second logic signal. The first logic circuit includes a plurality of input terminals and an output terminal, each input terminal is respectively coupled to the plurality of first ring oscillation output circuits and the second ring oscillation output circuit to receive the plurality of first logic signals and the second logic signal to output a logic output signal. The output latch circuit receives the logic output signal and the first frequency to sequentially output a random bit signal according to the logic output signal and the first frequency. The temporary storage and control circuit receives the random bit signal and temporarily stores the random bit signal according to the timing. When the number of the temporarily stored random bit signals reaches a default number, it is determined whether to start the second ring oscillation output circuit according to the entropy value of the stored random bit signal.

[0007] According to the true random number generator described in the preferred embodiment of the present application, the true random number generator further includes a plurality of second ring oscillation output circuits, wherein when the number of temporarily stored random bit signals reaches a default number, whether to activate the plurality of second ring oscillation output circuits is determined according to the entropy values ​​of the stored random bit signals. In another preferred embodiment, the true random number generator further includes a plurality of second ring oscillation output circuits, wherein when the number of temporarily stored random bit signals reaches a default number, the number of the second ring oscillation output circuits to be activated is determined according to the entropy values ​​of the stored random bit signals.

[0008] According to the true random number generator described in the preferred embodiment of the present application, each of the above-mentioned first ring oscillation output circuits includes a first ring oscillator and a first latch circuit. The first ring oscillator includes an output end. A first latch circuit includes an input end, an output end and a frequency end, wherein the input end of the first latch circuit is coupled to the output end of the first ring oscillator, the output end of the first latch circuit is correspondingly coupled to the output end of the first logic circuit, and the frequency end of the first latch circuit receives the first frequency.

[0009] According to the true random number generator described in the preferred embodiment of the present application, the second ring oscillator output circuit includes a second ring oscillator and a second latch circuit. The second ring oscillator includes an output terminal. The second latch circuit includes an input terminal, an output terminal and a frequency terminal, wherein the input terminal of the second latch circuit is coupled to the output terminal of the second ring oscillator, the output terminal of the second latch circuit is correspondingly coupled to the output terminal of the first logic circuit, and the frequency terminal of the second latch circuit receives the first frequency.

[0010] According to the true random number generator described in the preferred embodiment of the present application, the temporary storage and control circuit is used to count the number of the first logic values ​​of the random bit signals to determine the entropy value of the random bit signals. In a preferred embodiment of the present application, the number of the first logic values ​​of the random bit signals is greater than a first threshold value, and the temporary storage and control circuit activates the second ring oscillation output circuit, wherein the number of the first logic values ​​of the random bit signals is less than a second threshold value, and the temporary storage and control circuit activates the second ring oscillation output circuit.

[0011] The embodiment of the present application further provides an entropy value maintaining method for a true random number generator, wherein the true random number generator includes multiple first ring oscillation output circuits, and the entropy value maintaining method for the true random number generator includes: providing at least one second ring oscillation output circuit in the true random number generator, wherein the at least one second ring oscillation output circuit is not enabled during initial operation; after the true random number generator starts to operate, recording the logic value of the random bit signal generated at each default time; counting the logic value of the random bit signal to obtain a statistical value; and determining whether the second ring oscillation output circuits are combined for operation to generate the random bit signal based on the statistical value.

[0012] According to the entropy value maintaining method of the true random number generator described in the preferred embodiment of the present application, the above-mentioned statistical value is the number of first logic values ​​of the logic value of the above-mentioned random bit signal, wherein the entropy value maintaining method of the true random number generator further includes: when the number of the first logic values ​​of the above-mentioned random bit signal is greater than a first threshold value, starting the above-mentioned second ring oscillation output circuit; and when the number of the first logic values ​​of the above-mentioned random bit signal is less than a second threshold value, starting the above-mentioned second ring oscillation output circuit.

[0013] According to the preferred embodiment of the present application, the entropy value maintaining method of the true random number generator is described, wherein, in the true random number generator, at least the second ring oscillation output circuit is provided, wherein the at least the second ring oscillation output circuit is not enabled during the initial operation, and further includes: in the true random number generator, a plurality of second ring oscillation output circuits are provided; wherein the statistical value is the number of first logic values ​​of the logic value of the random bit signal, wherein the entropy value maintaining method of the true random number generator further includes: when the number of the first logic values ​​of the random bit signal is greater than a first threshold value, according to the difference between the number of the first logic values ​​and the first threshold value, determining the number of the second ring oscillation output circuits to be enabled; and when the number of the first logic values ​​of the random bit signal is less than a second threshold value, according to the difference between the number of the first logic values ​​and the second threshold value, determining the number of the second ring oscillation output circuits to be enabled.

[0014] In summary, the embodiments of the present application use an additional built-in spare ring oscillator, which is generally not enabled to save energy. When statistics are collected for a period of time and it is found that the entropy value of the output random bits is out of specification, the additional built-in spare ring oscillator is enabled to improve the entropy value of the true random number generator and increase the entropy value of the random bits.

[0015] In order to further understand the technology, means and effects of the present application, reference may be made to the following detailed description and drawings, so that the purpose, features and concepts of the present application can be thoroughly and specifically understood. However, the following detailed description and drawings are only used for reference and explanation of the implementation of the present application, and are not intended to limit the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] The accompanying drawings are provided to enable a person with ordinary knowledge in the technical field to which the present application belongs to further understand the present application, and are incorporated into and constitute a part of the specification of the present application. The accompanying drawings illustrate exemplary embodiments of the present application, and are used together with the specification of the present application to explain the principles of the present application.

[0017] Figure 1 FIG. 4 is a system block diagram of a true random number generator according to a preferred embodiment of the present application.

[0018] Figure 2 A flowchart of a method for maintaining entropy of a true random number generator according to a preferred embodiment of the present application is shown.

[0019] Figure 3 A flowchart of the sub-steps of step S205 of the method for maintaining entropy value of a true random number generator according to a preferred embodiment of the present application is shown.

[0020] Figure 4 A flowchart of the sub-steps of step S205 of the method for maintaining entropy value of a true random number generator according to a preferred embodiment of the present application is shown. DETAILED DESCRIPTION

[0021] Reference will now be made in detail to the exemplary embodiments of the present application, which are illustrated in the accompanying drawings. Where possible, the same component symbols are used in the drawings and the specification to refer to the same or similar components. In addition, the exemplary embodiments are only one of the implementation methods of the design concept of the present application, and the following examples are not intended to limit the present application.

[0022] Figure 1 FIG. 1 is a block diagram of a true random number generator according to a preferred embodiment of the present invention. Figure 1 , this true random number generator includes a plurality of first ring oscillation output circuits 101, at least one second ring oscillation output circuit 102, a first logic circuit 103, an output latch circuit 104, a temporary storage and control circuit 105, and a frequency generating circuit 106. In this embodiment, each first ring oscillation output circuit 101 is composed of a series of inverters 1011 (inverter) and a latch circuit 1012 (latch circuit). A person with ordinary knowledge in the relevant technical field should know that the ring oscillator does not necessarily have to use an inverter, and can also use, for example, a ring series amplifier or other logic gates, so the present application is not limited to this. Furthermore, in order to allow the first ring oscillation output circuit 101 to output its logic according to the frequency, a latch circuit 1012 is additionally coupled to the output end to synchronously lock the logic output by the inverter 1011 series according to the frequency. Although the latch circuit 1012 of this embodiment is a D-type flip-flop, a person skilled in the art should know that other latch circuits, such as RS flip-flops, JK flip-flops, and T-type flip-flops, can also be used as embodiments, and the present application is not limited thereto.

[0023] The first ring oscillation output circuit 101 receives a first frequency FS output by the frequency generating circuit 106, and outputs a first logic signal OUT1 according to the first frequency FS. In addition, in this embodiment, the second ring oscillation output circuit 102 is a standby ring oscillation output circuit. In the initial state, the second ring oscillation output circuit 102 is in a disabled state. The second ring oscillation output circuit 102 in this embodiment is also composed of an inverter 1021 (inverter) and a latch circuit 1022 (latch circuit). For the same reason, as mentioned above, the present application is not limited to this. When the second ring oscillation output circuit 102 is activated, the activated second ring oscillation output circuit 102 also receives the first frequency FS, and according to the first frequency FS, the activated second ring oscillation output circuit 102 outputs a second logic signal OUT2.

[0024] The first logic circuit 103 includes a plurality of input terminals and an output terminal, and each input terminal is respectively coupled to the plurality of first ring oscillation output circuits 101 and the second ring oscillation output circuit 102 to receive the plurality of first logic signals OUT1 and the second logic signal OUT2 to output a logic output signal LOUT. In this embodiment, the first logic circuit 103 can be implemented using an exclusive OR gate (XOR). Similarly, the first logic circuit 103 can also be implemented using other logic circuits, and the present application is not limited thereto.

[0025] Furthermore, in order to synchronize the output, an output latch circuit 104 is also coupled to the output end of the first logic circuit 103. The output latch circuit 104 receives the logic output signal LOUT and the first frequency FS, and sequentially outputs a random bit signal according to the logic output signal LOUT and the first frequency FS. The temporary storage and control circuit 105 receives the random bit signal and temporarily stores the random bit signal according to the timing. When the number of temporarily stored random bit signals reaches a default number, the temporary storage and control circuit 105 will determine whether the entropy value of the temporarily stored random bit signal meets the circuit specification. If the entropy value of the currently temporarily stored random bit signal still meets the specification, the second ring oscillation output circuit 102 will not be activated. If the entropy value does not meet the specification, it means that the randomness of the output random bit signal is insufficient, and the temporary storage and control circuit 105 activates the above-mentioned second ring oscillation output circuit 102 to increase the entropy value of this true random number generator.

[0026] For example, assuming that the preset number is 1000 random bit signals, the temporary storage and control circuit 105 will store the 1000 random bit signals in sequence. Under the most ideal conditions, the 1000 random bit signals should be 500 logical "1"s and 500 logical "0". However, the actual situation may not be so ideal. Therefore, in this embodiment, upper and lower thresholds are set. Taking logical "1" as an example, the threshold setting method is, for example, the number of logical "1", the upper threshold is 600, and the lower threshold is 400. If the number of logical "1" is between 600 and 400, it means that the entropy value meets the specification. If the number of logical "1" is greater than 600 or less than 400, it means that the entropy value does not meet the specification. At this time, the temporary storage and control circuit 105 starts the second ring oscillation output circuit 102 to increase the entropy value of this true random number generator.

[0027] In addition, in circuit design, different thresholds can be set according to different bit rates. For example, the above threshold setting is based on an upper limit of 0.6 and a lower limit of 0.4. When the bit rate is 100 times, the above threshold setting will be adjusted to an upper limit of 0.62 and a lower limit of 0.38. That is, when 1000 random bit signals are sampled, the number of logical "1"s is greater than 620 or less than 380, which means that the entropy value does not meet the specification. When the bit rate is 1000 times, the above threshold setting will be adjusted to an upper limit of 0.64 and a lower limit of 0.36. That is, when 1000 random bit signals are sampled, the number of logical "1"s is greater than 640 or less than 360, which means that the entropy value does not meet the specification.

[0028] Furthermore, in another preferred embodiment, multiple threshold ranges can be set, and different numbers of second ring oscillator output circuits 102 can be activated according to the offset range. For example, the first threshold range is set to be, for example, 0.6-0.4, the second threshold range is set to be, for example, 0.65-0.35, and the third threshold range is set to be, for example, 0.7-0.3. In the above embodiment, if 1000 random bit signals are sampled, if the number of logic "1"s is greater than 600 and less than 650, then one second ring oscillator output circuit 102 is activated; if the number of logic "1"s is greater than 650 and less than 700, then two second ring oscillator output circuits 102 are activated; if the number of logic "1"s is greater than 700, then three second ring oscillator output circuits 102 are activated.

[0029] Similarly, in the above embodiment, if 1000 random bit signals are sampled, if the number of logic "1"s is less than 400 and greater than 350, then one second ring oscillator output circuit 102 is started; if the number of logic "1"s is less than 350 and greater than 300, then two second ring oscillator output circuits 102 are started; if the number of logic "1"s is less than 300, then three second ring oscillator output circuits 102 are started. The above embodiment is only for illustrating the spirit of the present application, and does not actually set three second ring oscillator output circuits 102. The threshold value is also an example for illustrating the spirit of the present application. Designers can make different settings according to different product requirements, and the present application is not limited thereto.

[0030] According to the above embodiments, it can be summarized into a method for maintaining the entropy value of a true random number generator. Figure 2 A flowchart of a method for maintaining entropy of a true random number generator according to a preferred embodiment of the present invention is shown. Figure 2 , the entropy value maintenance method of the true random number generator comprises the following steps:

[0031] Step S201: Start.

[0032] Step S202: Provide at least one second ring oscillation output circuit in the true random number generator. The at least one second ring oscillation output circuit will not be enabled during initial operation.

[0033] Step S203: After the true random number generator starts to operate, the logic value of the random bit signal generated at each default time is recorded.

[0034] Step S204: Count the logic values ​​of the random bit signal to obtain a statistical value.

[0035] Step S205: According to the statistical value, determine whether the second ring oscillation output circuit is combined to operate to generate the random bit signal, and return to step S203 to re-count.

[0036] Figure 3 The flowchart of the sub-steps of step S205 of the method for maintaining the entropy value of a true random number generator according to a preferred embodiment of the present application is shown. Figure 3 The step S205 of the method for maintaining the entropy value of the true random number generator comprises the following steps:

[0037] Step S301: Determine whether the number of the first logic value (RDN) of the random bit signal is greater than a first threshold value (T1). If not, proceed to step S302. If yes, proceed to step S304.

[0038] Step S302: Determine whether the number of the first logic value of the random bit signal is less than a second threshold value (T2). If not, proceed to step S303. If yes, proceed to step S304.

[0039] Step S303: Do not start the second ring oscillation output circuit. Return to step S203.

[0040] Step S304: Start the second ring oscillation output circuit. Return to step S203.

[0041] The above embodiment is a technique that has only one set of second ring oscillator output circuits (not necessarily one second ring oscillator output circuit) and determines whether to start or not through a threshold value. In another embodiment, there is also an example of setting multiple thresholds and multiple sets of second ring oscillator output circuits. Figure 4 The flowchart of the sub-steps of step S205 of the method for maintaining the entropy value of a true random number generator according to a preferred embodiment of the present application is shown. Figure 4 The step S205 of the method for maintaining the entropy value of the true random number generator comprises the following steps:

[0042] Step S401: Determine whether the number of the first logic value (RDN) of the random bit signal is greater than a first threshold value (T1). If it is less than the first threshold value, proceed to step S402. If it is greater than the first threshold value, it means that the entropy value does not meet the specification, and proceed to step S404.

[0043] Step S402: Determine whether the number of the first logic value (RDN) of the random bit signal is less than a second threshold value (T2). If it is greater than the second threshold value, proceed to step S403. If it is greater than the first threshold value, it means that the entropy value does not meet the specification, and proceed to step S40X.

[0044] Step S403: Do not start the second ring oscillation output circuit. Return to step S203.

[0045] Step S404: Determine the number of activated second ring oscillator output circuits according to the difference between the number of first logic values ​​and the first threshold value. As described above, multiple threshold ranges are set and different numbers of second ring oscillator output circuits 102 are activated according to the offset range.

[0046] Step S405: Determine the number of activated second ring oscillator output circuits according to the difference between the number of first logic values ​​and the second threshold value. As described above, multiple threshold ranges are set and different numbers of second ring oscillator output circuits 102 are activated according to the offset range.

[0047] In summary, the embodiments of the present application use an additional built-in spare ring oscillator, which is generally not enabled to save energy. When statistics are collected for a period of time and it is found that the entropy value of the output random bits is out of specification, the additional built-in spare ring oscillator is enabled to increase the entropy value of the true random number generator and increase the entropy value of the random bits. Since the spare ring oscillator is enabled only when the entropy value is insufficient, power consumption can be saved.

[0048] It should be understood that the examples and embodiments described herein are for illustrative purposes only and that various modifications or changes in view thereof will be suggested to those skilled in the art and are to be included within the spirit and scope of the present application and the scope of the appended claims.

Claims

1. A true random number generator, characterized in that: include: A plurality of first ring oscillation output circuits, wherein each of the first ring oscillation output circuits receives a first frequency respectively, and each of the first ring oscillation output circuits outputs a first logic signal according to the first frequency; a second ring oscillation output circuit, wherein when the second ring oscillation output circuit is activated, the activated second ring oscillation output circuit receives the first frequency, and outputs a second logic signal according to the first frequency; a first logic circuit, comprising a plurality of input terminals and an output terminal, wherein each of the plurality of input terminals is respectively coupled to the plurality of first ring oscillation output circuits and the second ring oscillation output circuit to receive the plurality of first logic signals and the second logic signal to output a logic output signal; an output latch circuit receiving the logic output signal and the first frequency to sequentially output a random bit signal according to the logic output signal and the first frequency; and A temporary storage and control circuit receives the random bit signal and temporarily stores the random bit signal according to a timing sequence, wherein when the number of the temporarily stored random bit signals reaches a default number, it is determined whether to start the second ring oscillation output circuit according to the entropy value of the temporarily stored random bit signals.

2. The true random number generator according to claim 1, characterized in that: Also includes: A plurality of second ring oscillation output circuits, wherein when the number of the temporarily stored random bit signals reaches the default number, it is determined whether to start the plurality of second ring oscillation output circuits according to the entropy value of the temporarily stored random bit signals.

3. The true random number generator according to claim 1, characterized in that: Also includes: A plurality of second ring oscillation output circuits, wherein when the number of the temporarily stored random bit signals reaches the default number, the number of the activated second ring oscillation output circuits is determined according to the entropy value of the temporarily stored random bit signals.

4. The true random number generator according to claim 1, characterized in that: Each of the plurality of first ring oscillation output circuits further comprises: a first ring oscillator comprising an output terminal; and A first latch circuit includes an input terminal, an output terminal and a frequency terminal, wherein the input terminal of the first latch circuit is coupled to the output terminal of the first ring oscillator, the output terminal of the first latch circuit is correspondingly coupled to the output terminal of the first logic circuit, and the frequency terminal of the first latch circuit receives the first frequency.

5. The true random number generator according to claim 1, characterized in that: The second ring oscillation output circuit further comprises: a second ring oscillator comprising an output terminal; and A second latch circuit comprises an input terminal, an output terminal and a frequency terminal, wherein the input terminal of the second latch circuit is coupled to the output terminal of the second ring oscillator, the output terminal of the second latch circuit is correspondingly coupled to the output terminal of the first logic circuit, and the frequency terminal of the second latch circuit receives the first frequency.

6. The true random number generator according to claim 1, characterized in that: The temporary storage and control circuit is used to count the number of the first logic value of the random bit signal to determine the entropy value of the random bit signal.

7. The true random number generator according to claim 6, characterized in that: The number of the first logic values ​​of the random bit signal is greater than a first threshold value, the temporary storage and control circuit starts the second ring oscillation output circuit, Wherein, the number of the first logic values ​​of the random bit signal is smaller than a second threshold value, and the temporary storage and control circuit activates the second ring oscillation output circuit.

8. A method for maintaining entropy value of a true random number generator, characterized in that: The true random number generator includes a plurality of first ring oscillation output circuits, and the entropy value maintaining method of the true random number generator includes: In the true random number generator, at least one second ring oscillation output circuit is provided, wherein the at least one second ring oscillation output circuit is not enabled during initial operation; After the true random number generator starts to operate, recording the logic value of the random bit signal generated at each default time; Counting the logic value of the random bit signal to obtain a statistical value; and According to the statistical value, it is determined whether the second ring oscillation output circuits are to be combined and operated to generate the random bit signal.

9. The method for maintaining entropy of a true random number generator according to claim 8, characterized in that: The statistical value is the number of the logic value of the random bit signal having a first logic value, wherein the entropy value maintaining method of the true random number generator further comprises: When the number of the first logic values ​​of the random bit signal is greater than a first threshold value, starting the second ring oscillation output circuit; and When the number of the first logic values ​​of the random bit signal is less than a second threshold value, the second ring oscillation output circuit is started.

10. The method for maintaining entropy value of a true random number generator according to claim 8, characterized in that: In the true random number generator, at least the second ring oscillation output circuit is provided, wherein the at least the second ring oscillation output circuit is not enabled during initial operation, and further comprises: In the true random number generator, a plurality of second ring oscillation output circuits are provided; The statistical value is the number of the logic value of the random bit signal having a first logic value, and the entropy value maintaining method of the true random number generator further comprises: When the number of the first logic values ​​of the random bit signal is greater than a first threshold value, determining the number of the plurality of second ring oscillation output circuits to be enabled according to the difference between the number of the first logic values ​​and the first threshold value; and When the number of the first logic values ​​of the random bit signal is less than a second threshold value, the number of enabled second ring oscillation output circuits is determined according to the difference between the number of the first logic values ​​and the second threshold value.

Images