Task scheduling recovery method and system, operating system and storage medium

Abstract

The invention provides a task scheduling recovery method and system, an operating system and a storage medium. The task scheduling recovery method comprises the steps that whether scheduling of a current task is stopped or not is judged according to a first register value and a second register value which are detected at the same time; if the scheduling of the current task is stopped, task scheduling recovery is executed, and the task scheduling is recovered at least by triggering an interrupt trigger register or adjusting the value of the second register. According to the method and the device, the task scheduling stop abnormity can be quickly detected, the task scheduling can be normally recovered, and the stability, the reliability and the operation efficiency of an operating system are improved.

Description

Technical Field

[0001] The present application relates to the technical field of task scheduling, and in particular to a task scheduling recovery method, a recovery system, an operating system and a storage medium. Background Art

[0002] In modern computers and embedded operating systems, task scheduling is a critical process that involves how to effectively allocate resources in a multi-tasking environment to ensure that all tasks can be executed according to the expected priority and time nodes.

[0003] In some cases, tasks may be in a stopped scheduling state for various reasons; when a task is stopped, the system may experience performance degradation, response delays, or resource waste. Therefore, how to quickly and accurately resume task scheduling when a task is stopped is a key issue in improving system efficiency and reliability. Summary of the invention

[0004] In order to solve the above technical problems, the present application provides a task scheduling recovery method, a recovery system, an operating system and a storage medium.

[0005] Specifically, the present application provides a task scheduling recovery method, comprising the following steps: The first register value and the second register value are detected simultaneously to determine whether the current task has stopped scheduling according to the first register value and the second register value.

[0006] A judgment result is obtained, so as to execute task scheduling recovery when the judgment result is that the current task has stopped scheduling.

[0007] The task scheduling is restored at least by triggering an interrupt trigger register or adjusting the second register value.

[0008] In the above technical solution, the task scheduling stop exception can be quickly detected by detecting the register value, and the task scheduling can be restored normally by triggering the interrupt trigger register or adjusting the second register value, thereby improving the stability, reliability and operation efficiency of the operating system.

[0009] Further, before detecting the first register value and the second register value, the method includes: Send a global interrupt disable instruction to the interrupt controller, or clear the interrupt flag bit corresponding to the interrupt controller to disable the interrupt controller.

[0010] In the above technical solution, after turning off the global interrupt, the system can avoid the interference of external interrupts on the detection process when detecting the first register value and the second register value. This ensures that when detecting the task scheduling status, no other interrupts affect the accuracy of the judgment, thereby improving the reliability of the overall system.

[0011] Further, judging whether the current task has stopped scheduling according to the first register value and the second register value includes: Send a global interrupt enable instruction to the interrupt controller, or write an interrupt flag to the interrupt controller to enable the interrupt controller.

[0012] The first register value and the second register value are compared. If the first register value is greater than the second register value, it is determined that the current task has stopped scheduling; otherwise, the process ends.

[0013] In the above technical solution, after the global interrupt is enabled, the system can respond to other tasks or events immediately. This flexibility allows other important interrupts that may occur to be handled in a timely manner when judging the task scheduling status, thereby improving the overall responsiveness of the system. By comparing the first register value and the second register value, it can be clearly determined whether the task has stopped scheduling. If the first register value is greater than the second register value, the system will clearly believe that the current task is in a stopped state. This comparison-based judgment mechanism enhances the reliability of task scheduling and helps avoid incorrect decisions.

[0014] Furthermore, before executing task scheduling recovery, it includes: Determine whether the current operating system supports register-triggered interrupt operations; if so, restore by triggering the interrupt trigger register; otherwise, restore by adjusting the second register value.

[0015] In the above technical solution, by judging whether the current operating system supports register-triggered interrupt operations, the system can select the most appropriate recovery method according to different operating systems and hardware environments. This compatibility ensures the wide applicability of the scheduling recovery method in different systems and enhances the flexibility and portability of the system. If the operating system supports register-triggered interrupt operations, the method of recovering by triggering the interrupt-triggered register is more efficient, and the hardware interrupt mechanism can be used to quickly recover task scheduling. If the operating system does not support this operation, it is recovered by adjusting the second register value. Although this method is slightly slower, it can also effectively recover task scheduling and avoid recovery failures due to hardware limitations.

[0016] In addition, systems that support register-triggered interrupt operations usually have more efficient hardware interrupt processing capabilities. By utilizing this feature for task scheduling and recovery, the recovery efficiency can be significantly improved. For time-sensitive applications (such as real-time systems), this efficient recovery method can quickly respond to task requirements and improve system performance.

[0017] Further, the recovery by triggering an interrupt trigger register includes: Write a specific bit to the interrupt trigger register to trigger a tick interrupt.

[0018] In the above technical solution, the tick interrupt (usually a timer interrupt) can quickly wake up the operating system, prompting it to reschedule tasks. By triggering the tick interrupt, the system can effectively and quickly respond to task recovery requirements, ensuring that the system returns to normal working state as soon as possible.

[0019] The tick interrupt provides a mechanism for fine-grained control of time; when a specific bit is written to trigger this interrupt, the system can not only accurately control the timing of task scheduling, but also provide the required time guarantee for real-time tasks, ensuring that the tasks can be executed within the expected time.

[0020] It can be seen that the solution of writing specific bits to trigger the tick interrupt for task scheduling recovery significantly improves the efficiency and reliability of task recovery. The tick interrupt not only provides precise time control and seamless task switching capabilities, but also enhances the system's compatibility and self-monitoring capabilities, providing effective support for complex scheduling requirements in multi-tasking environments.

[0021] Further, the recovering by adjusting the second register value includes: Obtain performance parameters of the current operating system; wherein the performance parameters include at least clock frequency, task scheduling granularity, interrupt delay time and hardware characteristics.

[0022] Determine N according to the performance parameter; wherein N is a positive integer.

[0023] An addition N operation is performed on the second register value based on the first register value to trigger a tick interrupt.

[0024] In the above technical solution, by obtaining the performance parameters of the current operating system, the system can adaptively adjust the value N according to the actual hardware and software environment. This adaptive mechanism ensures that the recovery operation can still run efficiently in a high-performance and high-concurrency environment; adjusting the second register based on the dynamically confirmed N value can more accurately trigger the tick interrupt, thereby improving the efficiency of task recovery, especially for tasks that need to be recovered quickly. This efficient method can reschedule tasks in a short time and improve the system response speed.

[0025] In addition, this approach ensures the robustness of the task recovery mechanism under different hardware and software configurations by comprehensively considering multiple performance parameters of the operating system. Reliable task recovery can be achieved through adaptive adjustment regardless of whether the system is in a high-performance or low-performance state.

[0026] Furthermore, after the tick interrupt is triggered, the method further includes: Determine whether the tick interrupt is triggered successfully. If successful, call the tick interrupt processing function to update the first register value and activate the scheduler to switch to the next task through the scheduler; otherwise, re-trigger the tick interrupt. If the re-triggering fails for a preset number of times, record an error message.

[0027] In the above technical solution, by judging whether the tick interrupt is triggered successfully, the system can ensure that the interrupt event is handled in a timely manner, which not only can accurately control the timing of task scheduling, but also can improve the overall response accuracy of the system, ensuring that key tasks are executed within the expected time; if the tick interrupt is triggered successfully, the system will immediately call the tick interrupt processing function to update the first register value and activate the scheduler. This immediate response mechanism enhances the reliability of task scheduling and ensures quick switching to the next task during efficient interrupt processing.

[0028] In addition, if the tick interrupt fails to be triggered, the system will try to trigger the tick interrupt again. By setting a preset number of retry mechanisms, the waste of system resources due to a single interrupt failure can be avoided. If it still fails within the preset number of times, the system will record the error information for subsequent analysis, avoiding the extra consumption caused by blind retries.

[0029] Based on the same concept, the present application also provides a task scheduling recovery system, which adopts the task scheduling recovery method, specifically including: The detection module is used to detect the first register value and the second register value at the same time, so as to determine whether the current task has stopped scheduling according to the first register value and the second register value.

[0030] The recovery module is used to obtain a judgment result, so as to perform task scheduling recovery when the judgment result is that the current task has stopped scheduling; wherein the task scheduling is recovered at least by triggering an interrupt trigger register or adjusting the second register value.

[0031] In the above technical solution, the flexibility, reliability and system performance of task scheduling are significantly improved through real-time monitoring and automatic recovery mechanism; the efficient design of detection module and recovery module enhances the maintainability and resource utilization efficiency of the system, so that the system can continue to work efficiently and stably in various complex operating environments; this not only provides solutions for task scheduling in different application scenarios, but also lays a solid foundation for future system expansion and upgrade.

[0032] Based on the same concept, the present application also provides an operating system, wherein the operating system at least runs an idle task, the task scheduling recovery system is deployed in the idle task, and the task scheduling recovery system uses the task scheduling recovery method to perform task scheduling recovery.

[0033] Based on the same concept, the present application also provides a storage medium, in which a computer program is stored, wherein the computer program is configured to execute the task scheduling recovery method when running.

[0034] Compared with the prior art, the beneficial effects of this application are: The present application determines whether the current task has stopped scheduling by detecting the first register value and the second register value at the same time; if the current task has stopped scheduling, task scheduling recovery is performed, wherein the task scheduling is at least restored by triggering an interrupt trigger register or adjusting the second register value. The present application can quickly detect the abnormal stop of task scheduling and ensure that the scheduling of the task can be restored normally, thereby improving the stability, reliability and operation efficiency of the operating system. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] Figure 1 This is a flow chart of the task scheduling recovery method described in this application.

[0036] Figure 2 This is a framework diagram of the task scheduling and recovery system described in this application. DETAILED DESCRIPTION

[0037] The following is a further detailed description of a task scheduling recovery method, recovery system, operating system and storage medium of the present application in conjunction with specific embodiments and drawings.

[0038] See also Figure 1 , the present application provides a task scheduling recovery method, comprising the following steps: The first register value and the second register value are detected simultaneously to determine whether the current task has stopped scheduling according to the first register value and the second register value.

[0039] In some embodiments, the first register value is preferably a system clock count register value CV (ClockValue), and the second register value is preferably a system clock timing register value TV (TimerValue).

[0040] Among them, the system clock count register value CV usually represents the count value of the current operating system clock, which records the number of ticks of the system since a certain starting time (such as when the system starts); the number of ticks is usually related to the system clock frequency and is used to track the passage of time; in task scheduling, CV can be used to determine how long the system has been running and whether there are tasks that should be scheduled or switched. By monitoring CV, the system can determine the time point for task scheduling and perform task switching at the appropriate time.

[0041] The system clock timing register value TV is usually used to represent a timing value, that is, the expected time of the next timing event (such as a tick interrupt). It determines when the system clock counter triggers a timing interrupt (such as a tick interrupt). In task scheduling, TV can be used to set or adjust the time point for the next task scheduling. By adjusting TV, the system can control the triggering timing of the timing interrupt, thereby affecting the scheduling of tasks.

[0042] Furthermore, the values ​​of CV and TV can be checked regularly; if CV exceeds the value of TV but the task is not scheduled as expected, it can be determined that the task has been stopped from being scheduled, and corresponding recovery measures can be taken.

[0043] It should be noted that when to detect CV and TV can be set and selected by those skilled in the art according to actual application requirements, and is not limited here.

[0044] Further, before detecting the first register value and the second register value, the method includes: Send a global interrupt disable instruction to the interrupt controller, or clear the interrupt flag bit corresponding to the interrupt controller to disable the interrupt controller.

[0045] In some embodiments, the global interrupt can be disabled by executing a corresponding disable assembly instruction; or by reading the value of an interrupt controller and setting the interrupt flag position therein to 0.

[0046] Only after the global interrupt is turned off, the system clock count register value CV and the system clock timing register value TV will be read.

[0047] In the above technical solution, after turning off the global interrupt, the system can avoid the interference of external interrupts on the detection process when detecting the first register value and the second register value. This ensures that when detecting the task scheduling status, no other interrupts affect the accuracy of the judgment, thereby improving the reliability of the overall system.

[0048] Further, judging whether the current task has stopped scheduling according to the first register value and the second register value includes: Send a global interrupt enable instruction to the interrupt controller, or write an interrupt flag to the interrupt controller to enable the interrupt controller.

[0049] Among them, after completing the detection of the register value, it is necessary to restore the global interrupt and the operating system continues the normal operation process; the global interrupt can be enabled by executing the corresponding enabled assembly instruction; or it can be achieved by reading the value of the interrupt controller and setting the interrupt flag position therein to 1.

[0050] The first register value and the second register value are compared. If the first register value is greater than the second register value, it is determined that the current task has stopped scheduling; otherwise, the process ends.

[0051] In some embodiments, after the global interrupt is enabled, the detected CV and TV values ​​are compared. If CV is greater than TV, it indicates an abnormal situation and no more clock tick interrupts are generated, which means that the task is stopped from being scheduled.

[0052] If CV is less than or equal to TV, the global interrupt is disabled again after a corresponding set period to obtain the CV and TV values ​​for judgment again.

[0053] In the above technical solution, after the global interrupt is enabled, the system can respond to other tasks or events immediately. This flexibility allows other important interrupts that may occur to be handled in a timely manner when judging the task scheduling status, thereby improving the overall responsiveness of the system. By comparing the first register value and the second register value, it can be clearly determined whether the task has stopped scheduling. If the first register value is greater than the second register value, the system will clearly believe that the current task is in a stopped state. This comparison-based judgment mechanism enhances the reliability of task scheduling and helps avoid incorrect decisions.

[0054] A judgment result is obtained, so as to execute task scheduling recovery when the judgment result is that the current task has stopped scheduling.

[0055] The task scheduling is restored at least by triggering an interrupt trigger register or adjusting the second register value.

[0056] Furthermore, before executing task scheduling recovery, it includes: Determine whether the current operating system supports register-triggered interrupt operations; if so, restore by triggering the interrupt trigger register; otherwise, restore by adjusting the second register value.

[0057] In some embodiments, assuming that the current operating system is an embedded operating system, it is necessary to confirm whether its embedded chip hardware supports register-triggered interrupts.

[0058] Among them, it can be done by checking whether the operating system provides a management interface or function for triggering interrupts, or checking whether the operating system provides a hardware abstraction layer, etc. There is no restriction on the method of confirming whether the operating system supports register-triggered interrupt operations, and it is not rigidly adhered to this.

[0059] It should be noted that usually, the interrupt trigger register is used for recovery first, and only when the operating system does not support register-triggered interrupts or other specific performance requirements, the second register value is adjusted.

[0060] In the above technical solution, by judging whether the current operating system supports register-triggered interrupt operations, the system can select the most appropriate recovery method according to different operating systems and hardware environments. This compatibility ensures the wide applicability of the scheduling recovery method in different systems and enhances the flexibility and portability of the system. If the operating system supports register-triggered interrupt operations, the method of recovering by triggering the interrupt-triggered register is more efficient, and the hardware interrupt mechanism can be used to quickly recover task scheduling. If the operating system does not support this operation, it is recovered by adjusting the second register value. Although this method is slightly slower, it can also effectively recover task scheduling and avoid recovery failures due to hardware limitations.

[0061] In addition, systems that support register-triggered interrupt operations usually have more efficient hardware interrupt processing capabilities. By utilizing this feature for task scheduling and recovery, the recovery efficiency can be significantly improved. For time-sensitive applications (such as real-time systems), this efficient recovery method can quickly respond to task requirements and improve system performance.

[0062] Further, the recovery by triggering an interrupt trigger register includes: Write a specific bit to the interrupt trigger register to trigger a tick interrupt.

[0063] In some embodiments, after it is detected that the task stops being scheduled, the system clock tick interrupt is triggered by setting the system tick interrupt trigger register position to 1 (ie, the specific bit).

[0064] In the above technical solution, the tick interrupt (usually a timer interrupt) can quickly wake up the operating system, prompting it to reschedule tasks. By triggering the tick interrupt, the system can effectively and quickly respond to task recovery requirements, ensuring that the system returns to normal working state as soon as possible.

[0065] The tick interrupt provides a mechanism for fine-grained control of time; when a specific bit is written to trigger this interrupt, the system can not only accurately control the timing of task scheduling, but also provide the required time guarantee for real-time tasks, ensuring that the tasks can be executed within the expected time.

[0066] It can be seen that the solution of writing specific bits to trigger the tick interrupt for task scheduling recovery significantly improves the efficiency and reliability of task recovery. The tick interrupt not only provides precise time control and seamless task switching capabilities, but also enhances the system's compatibility and self-monitoring capabilities, providing effective support for complex scheduling requirements in multi-tasking environments.

[0067] Further, the recovering by adjusting the second register value includes: Obtain performance parameters of the current operating system; wherein the performance parameters include at least clock frequency, task scheduling granularity, interrupt delay time and hardware characteristics.

[0068] Among them, the clock frequency (usually in Hz) determines the length of each clock cycle, and a higher clock frequency means a shorter cycle; the task scheduling granularity refers to the minimum time unit for the operating system to switch tasks in a multi-tasking environment; the interrupt latency refers to the time from the hardware triggering the interrupt to the operating system actually processing the interrupt; different hardware platforms may have different interrupt processing capabilities and clock accuracy limitations, and the hardware characteristics include at least the processor interrupt response time and clock accuracy.

[0069] Determine N according to the performance parameter; wherein N is a positive integer.

[0070] An addition N operation is performed on the second register value based on the first register value to trigger a tick interrupt.

[0071] In some embodiments, after detecting that task scheduling stops, the system clock timing register value TV can be set to the value corresponding to the current system clock count register value CV+1 millisecond, and then the system clock tick interrupt will be triggered after 1 millisecond (ie, N).

[0072] It should be noted that 1 millisecond is only an example. The specific N value is determined based on the performance parameters. A value as small as possible is set to ensure that the abnormality of stopping task scheduling is detected in the shortest time possible and restored to normal, thereby minimizing the impact of the abnormality on the operation of the task program.

[0073] In the above technical solution, by obtaining the performance parameters of the current operating system, the system can adaptively adjust the value N according to the actual hardware and software environment. This adaptive mechanism ensures that the recovery operation can still run efficiently in a high-performance and high-concurrency environment; adjusting the second register based on the dynamically confirmed N value can more accurately trigger the tick interrupt, thereby improving the efficiency of task recovery, especially for tasks that need to be recovered quickly. This efficient method can reschedule tasks in a short time and improve the system response speed.

[0074] In addition, this approach ensures the robustness of the task recovery mechanism under different hardware and software configurations by comprehensively considering multiple performance parameters of the operating system. Reliable task recovery can be achieved through adaptive adjustment regardless of whether the system is in a high-performance or low-performance state.

[0075] Furthermore, after the tick interrupt is triggered, the method further includes: Determine whether the tick interrupt is triggered successfully. If successful, call the tick interrupt processing function to update the first register value and activate the scheduler to switch to the next task through the scheduler; otherwise, re-trigger the tick interrupt. If the re-triggering fails for a preset number of times, record an error message.

[0076] In some embodiments, after each failed re-triggering of the interruption, the number of failures is recorded. If a preset number of consecutive attempts (such as 3 or 5 times) fail, an error message is recorded. The error message may include the number of failures, the current system status, etc. After recording the error message, further error handling measures can be taken, such as restarting the system, sending an error report, or performing other recovery operations.

[0077] In the above technical solution, by judging whether the tick interrupt is triggered successfully, the system can ensure that the interrupt event is handled in a timely manner, which not only can accurately control the timing of task scheduling, but also can improve the overall response accuracy of the system, ensuring that key tasks are executed within the expected time; if the tick interrupt is triggered successfully, the system will immediately call the tick interrupt processing function to update the first register value and activate the scheduler. This immediate response mechanism enhances the reliability of task scheduling and ensures quick switching to the next task during efficient interrupt processing.

[0078] In addition, if the tick interrupt fails to be triggered, the system will try to trigger the tick interrupt again. By setting a preset number of retry mechanisms, the waste of system resources due to a single interrupt failure can be avoided. If it still fails within the preset number of times, the system will record the error information for subsequent analysis, avoiding the extra consumption caused by blind retries.

[0079] For further information, see Figure 2 , the present application also provides a task scheduling recovery system, specifically including: The detection module is used to detect the first register value and the second register value at the same time, so as to determine whether the current task has stopped scheduling according to the first register value and the second register value.

[0080] The recovery module is used to obtain a judgment result, so as to perform task scheduling recovery when the judgment result is that the current task has stopped scheduling; wherein the task scheduling is recovered at least by triggering an interrupt trigger register or adjusting the second register value.

[0081] It should be noted that the task scheduling recovery system adopts the task scheduling recovery method described above to perform task scheduling recovery, and its implementation example is the same as this method, which will not be described in detail here.

[0082] In the above technical solution, the flexibility, reliability and system performance of task scheduling are significantly improved through real-time monitoring and automatic recovery mechanism; the efficient design of detection module and recovery module enhances the maintainability and resource utilization efficiency of the system, so that the system can continue to work efficiently and stably in various complex operating environments; this not only provides solutions for task scheduling in different application scenarios, but also lays a solid foundation for future system expansion and upgrade.

[0083] Furthermore, the present application also provides an operating system, wherein the operating system at least runs an idle task, the task scheduling recovery system is deployed in the idle task, and the task scheduling recovery system uses the task scheduling recovery method described above to perform task scheduling recovery.

[0084] In some embodiments, after task scheduling stops, the currently running task will automatically release CPU resources after execution, thereby automatically switching to a lower task in a waiting state, and finally switching to an idle task and staying in the idle task; therefore, the corresponding code of the task scheduling recovery system can be deployed in the idle task, and after an exception occurs and the task stops scheduling, the detection and recovery code can still be run, thereby realizing system self-recovery.

[0085] In addition to the idle task, whether other tasks will run for the last time when the task stops scheduling depends on whether the task is in the waiting state, that is, other tasks may not run when the task stops scheduling. Therefore, the code must be deployed in the idle task to ensure that the detection and recovery code can run when the task stops scheduling.

[0086] Furthermore, the present application also provides a storage medium, in which a computer program is stored, wherein the computer program is configured to execute the task scheduling recovery method described above when running.

[0087] In some embodiments, the storage medium stores a number of computer programs to enable the task scheduling and recovery system to execute all or part of the steps of the methods described in each embodiment of the present application; the storage medium may include a U disk, a mobile hard disk, a read-only memory, a random access memory, a magnetic disk or an optical disk, and other media that can store program codes.

[0088] In summary, the present application provides a task scheduling recovery method, recovery system, operating system and storage medium; judging whether the current task has stopped scheduling by simultaneously detecting the first register value and the second register value; if the current task has stopped scheduling, executing task scheduling recovery, wherein the task scheduling is at least restored by triggering an interrupt trigger register or adjusting the second register value. The present application can quickly detect the abnormal stop of task scheduling, and can ensure that the scheduling of the task can be restored normally, thereby improving the stability, reliability and operation efficiency of the operating system.

[0089] Although example embodiments have been described herein with reference to the accompanying drawings, it should be understood that the above example embodiments are merely exemplary and are not intended to limit the scope of the present application to this. Those of ordinary skill in the art may make various changes and modifications therein without departing from the scope and spirit of the present application. All these changes and modifications are intended to be included within the scope of the present application as required by the appended claims.

[0090] Those of ordinary skill in the art will appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professional and technical personnel can use different methods to implement the described functions for each specific application, but such implementation should not be considered to be beyond the scope of this application.

[0091] In the several embodiments provided in this application, it should be understood that the disclosed devices and methods can be implemented in other ways. For example, the device embodiments described above are only schematic, for example, the division of the units is only a logical function division, and there may be other division methods in actual implementation, such as multiple units or components can be combined or integrated into another device, or some features can be ignored or not executed.

[0092] The various component embodiments of the present application can be implemented in hardware, or in software modules running on one or more processors, or in a combination thereof. It should be understood by those skilled in the art that a microprocessor or digital signal processor (DSP) can be used in practice to implement some or all functions of some modules according to the embodiments of the present application. The application can also be implemented as a device program (e.g., computer program and computer program product) for executing a part or all of the methods described herein. Such a program implementing the present application can be stored on a computer-readable medium, or can have the form of one or more signals. Such a signal can be downloaded from an Internet website, or provided on a carrier signal, or provided in any other form.

[0093] It should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the sentence "comprise a ..." do not exclude the existence of other identical elements in the process, method, article or device including the elements.

[0094] Although the description of the present application is carried out in conjunction with the above specific embodiments, it is obvious that those skilled in the art can make many substitutions, modifications and changes based on the above content. Therefore, all such substitutions, improvements and changes are included in the spirit and scope of the appended claims.

Claims

1. A task scheduling recovery method, characterized in that: The following steps are involved: Simultaneously detecting the first register value and the second register value to determine whether the current task has stopped scheduling according to the first register value and the second register value; Obtaining a judgment result, and executing task scheduling recovery when the judgment result is that the current task has stopped scheduling; The task scheduling is restored at least by triggering an interrupt trigger register or adjusting the second register value.

2. The task scheduling recovery method according to claim 1, characterized in that: Before detecting the first register value and the second register value, the method includes: Send a global interrupt disable instruction to the interrupt controller, or clear the interrupt flag bit corresponding to the interrupt controller to disable the interrupt controller.

3. The task scheduling recovery method according to claim 2, characterized in that: The step of judging whether the current task has stopped scheduling according to the first register value and the second register value includes: Sending a global interrupt enable instruction to the interrupt controller, or writing an interrupt flag to the interrupt controller, to enable the interrupt controller; The first register value and the second register value are compared. If the first register value is greater than the second register value, it is determined that the current task has stopped scheduling; otherwise, the process ends.

4. The task scheduling recovery method according to claim 3, characterized in that: Before executing task scheduling recovery, include: Determine whether the current operating system supports register-triggered interrupt operations; if so, restore by triggering the interrupt trigger register; otherwise, restore by adjusting the second register value.

5. The task scheduling recovery method according to claim 4, characterized in that: The recovery by triggering an interrupt trigger register includes: Write a specific bit to the interrupt trigger register to trigger a tick interrupt.

6. The task scheduling recovery method according to claim 4, characterized in that: The recovering by adjusting the second register value includes: Obtaining performance parameters of the current operating system; wherein the performance parameters include at least clock frequency, task scheduling granularity, interrupt delay time and hardware characteristics; Determine N according to the performance parameter; wherein N is a positive integer; An addition N operation is performed on the second register value based on the first register value to trigger a tick interrupt.

7. The task scheduling recovery method according to claim 5 or 6, characterized in that: After the tick interrupt is triggered, the following steps are also included: Determine whether the tick interrupt is triggered successfully. If successful, call the tick interrupt processing function to update the first register value and activate the scheduler to switch to the next task through the scheduler; otherwise, re-trigger the tick interrupt. If the re-triggering fails for a preset number of times, record an error message.

8. A task scheduling recovery system, characterized in that: The task scheduling recovery system adopts the task scheduling recovery method according to any one of claims 1 to 7, specifically comprising: A detection module, used for detecting the first register value and the second register value at the same time, so as to determine whether the current task has stopped scheduling according to the first register value and the second register value; The recovery module is used to obtain a judgment result, so as to perform task scheduling recovery when the judgment result is that the current task has stopped scheduling; wherein the task scheduling is recovered at least by triggering an interrupt trigger register or adjusting the second register value.

9. An operating system, characterized in that: The operating system at least runs an idle task, the task scheduling recovery system is deployed in the idle task, and the task scheduling recovery system uses the task scheduling recovery method according to any one of claims 1 to 7 to perform task scheduling recovery.

10. A storage medium, characterized in that: The storage medium stores a computer program, wherein the computer program is configured to execute the task scheduling recovery method according to any one of claims 1 to 7 when running.

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