A high parallel programming method for crossbar structure computing-in-memory chip

Abstract

The application discloses a high-parallel programming method for a crossbar structure memory-computing chip. The method comprises the following steps: step 1, subtracting a target matrix from an initial value of the chip to obtain a programming step matrix for this time programming; step 2, adjusting a single programming pulse step according to characteristics of the chip and a programming task target, adjusting a value of the programming step matrix, and then re-dividing the programming step matrix according to a corresponding threshold range to obtain a programming level matrix; step 3, using a crossbar splitting method on the programming level matrix to split the programming level matrix into a matrix supported by single programming of the memory-computing chip with the least total splitting times, and obtaining programming row and column information according to a splitting result; and step 4, completing programming operation according to the programming row and column information obtained in step 3. The application can improve the programming parallelism of the crossbar structure memory-computing chip, and further speed up the programming speed of the crossbar structure memory-computing chip.

Description

TECHNICAL FIELD

[0001] The application relates to a high-parallel programming method for a crossbar structure memory-compute chip, and belongs to the programming field of memory-compute chips. BACKGROUND

[0002] A memory-compute chip integrates computation and storage, greatly improves the energy efficiency ratio, and is one of important research technologies for solving the current von Neumann structure "memory wall" and "power consumption wall" bottlenecks.

[0003] A crossbar structure is suitable for matrix vector computation, can be naturally and efficiently applied to a deep neural network, and therefore becomes a mainstream structure of a memory-compute chip. However, the current memory-compute device has problems such as poor consistency and complex programming process, the crossbar structure can only realize control of a chip array through row and column switches, and cannot realize independent control of each unit of the array, so that the parallelism of programming is difficult to improve, and the slow programming speed of the memory-compute chip is further magnified.

[0004] Chinese patent ZL201811398206.9 discloses an optoelectronic computing unit, an optoelectronic computing array and an optoelectronic computing method. The optoelectronic computing array adopts a crossbar structure, and can be programmed by controlling row and column switches to control each unit. However, since there is only one switch in each column and each row, at most, synchronous programming of one row or one column can be realized, and since each unit has different programming targets, as the programming progresses, the programming parallelism will further decrease. In Chinese patent ZL202310341637.6 "A fast programming method for a memory-compute chip", the method considers the slow programming speed of 0 values, and separately programs the 0 values to improve the programming speed. However, when programming 0, the programming can only be performed row by row or column by column, the maximum programming parallelism is not realized, and the non-0 value programming cannot be accelerated. SUMMARY

[0005] In order to improve the programming parallelism of a crossbar structure memory-compute chip and accelerate the programming speed, the application provides a high-parallel programming method for a crossbar structure memory-compute chip.

[0006] The technical scheme adopted by the application is as follows:

[0007] A high-parallel programming method for a crossbar structure memory-compute chip, the method comprising the following steps:

[0008] Step 1: obtaining an initial value of a chip, subtracting a target matrix from the initial value of the chip to obtain a programming step matrix for this programming;

[0009] Step 2, adjust the single programming pulse step size according to the characteristics of the chip and the programming task target, and adjust the values of the programming step size matrix, and then re-divide the programming step size matrix according to the corresponding threshold range to obtain a programming level number matrix, each level in the programming level number matrix representing one programming operation;

[0010] Step 3, using a crossbar splitting method on the programming level number matrix to split the programming level number matrix into a matrix supported by the single programming of the in-memory computing chip with the least total splitting number, and obtaining the programming row and column information according to the splitting result;

[0011] Step 4, completing the programming operation according to the programming row and column information obtained in step 3.

[0012] Further, in step 3, the crossbar splitting method specifically includes the following steps:

[0013] Step 3-1, merging the rows with the same column switch information from the row dimension, and merging the columns with the same row switch information from the column dimension;

[0014] Step 3-2, removing the all-0 rows and all-0 columns in the merging result to obtain a row dimension matrix and a column dimension matrix, and at this time, the minimum splitting numbers of the row dimension and the column dimension are obtained;

[0015] Step 3-3, comparing the minimum splitting numbers of the row dimension and the column dimension, taking the smaller one as the final splitting result, if taking the row dimension splitting, then 1 in each row in the row dimension matrix represents opening, and 0 represents closing, as the column switch information of this programming operation, and the positions of all the same rows before merging are set to 1, and the rest positions are set to 0, as the row switch information corresponding to the programming; if taking the column dimension splitting, then 1 in each column in the column dimension matrix represents opening, and 0 represents closing, as the row switch information of this programming operation, and the positions of all the same columns before merging are set to 1, and the rest positions are set to 0, as the column switch information corresponding to the programming.

[0016] Further, in step 1, the initial value of the chip can be a factory value or a current read result of the chip.

[0017] Further, in step 2, according to the programming characteristic curve of the chip, the programming step size matrix is first divided into different threshold ranges, and then the programming level number is set according to the threshold range to obtain the programming level number matrix, which is a matrix closer to the real programming result of the in-memory computing chip.

[0018] Further, in step 3, the same row and column information obtained after splitting is merged as the programming row and column information, and at this time, the programming step size information is included in the row and column information of each programming, so as to save the setting time between the same row and column information programming links.

[0019] Further, in step 3, for the case that the number of row switches is much larger than the number of column switches, only the crossbar switch splitting method is used from the row direction to save unnecessary calculation; otherwise, for the case that the number of column switches is much larger than the number of row switches, only the crossbar switch splitting method is used from the column direction.

[0020] Further, the method supports precise programming and also supports rough programming; the rough programming is used as pre-programming before the precise programming, and the chip is programmed to the vicinity of the target value to speed up the subsequent precise programming.

[0021] Further, for the precise programming, the result of the chip needs to be read out and verified after each programming in step 4 to see whether the precision requirement is met, and if the precision requirement is not met, steps 1-4 are repeated until the programming precision meets the requirement; for the rough programming, the programming is completed in step 4, and the current programming is ended, and no verification is needed.

[0022] Further, if the target of the rough programming is used as the pre-processing of the precise programming, the value adjustment of the programming step matrix in step 2 includes: before the programming step matrix is re-divided, the programming step matrix is multiplied by a coefficient less than 1, so that the programming result is in the vicinity of the target value while avoiding over-programming.

[0023] The present application fully considers the angle that the existing crossbar structure computing chip can only control the programming of the chip array through row and column switches, and designs a matrix minimum splitting method suitable for the crossbar structure. The programming method of the present application first obtains the step matrix of each programming, and processes the programming step matrix into a programming level matrix suitable for control according to the chip characteristics and the task target, and then applies the minimum splitting method in the row direction and / or the column direction to realize the minimum splitting number, so as to realize the maximum average parallelism of programming, shorten the total programming time, and have a significant improvement compared with the existing programming mode of programming one by one or programming in the whole row or column. Taking N*N matrix programming as an example, the present application can realize N*N device parallel programming at most, which can be accelerated by N times compared with the row or column programming. If the same programming information is combined to reduce the configuration time between two programming operations, the acceleration ratio will be greater. BRIEF DESCRIPTION OF DRAWINGS

[0024] Figure 1 The flow chart of the high parallel programming method of the present application without combining the same programming information.

[0025] Figure 2 The flow chart of the high parallel programming method of the present application with combining the same programming information.

[0026] Figure 3 The flow chart of the crossbar splitting method of the present application.

[0027] Figure 4 Figure 1 is a schematic diagram of a photoelectric storage and calculation chip structure in a crossbar structure according to an embodiment of the present application. DETAILED DESCRIPTION

[0028] The technical solutions of the present application will be further described in detail below in combination with the drawings and specific embodiments.

[0029] A high-parallel programming method for a crossbar structure storage and calculation chip according to an embodiment of the present application, as shown in Figure 1, comprises the following steps: Figure 1

[0030] Step 1, obtaining a programming step matrix. First, obtain the initial value of the chip, and subtract the target matrix from the initial value of the chip to obtain the programming step matrix of this programming.

[0031] Step 2, processing the programming step matrix to obtain a programming level matrix. According to the selected chip characteristics and programming task target, adjust the single programming pulse step, and adjust the value of the programming step matrix, and then re-divide to obtain a programming level matrix according to the corresponding threshold requirement, each level representing one programming operation. The programming level matrix is a matrix closer to the real programming result of the storage and calculation chip.

[0032] Step 3, obtaining the row and column information of the programming. Use a crossbar splitting method on the programming level matrix to split the programming level matrix into a matrix supported by a single programming of the storage and calculation chip with the least total splitting times, and obtain the row and column information of the programming according to the splitting result. The crossbar splitting method specifically comprises the following steps:

[0033] Step 3-1, merging rows with the same column switch information from the row dimension, and merging columns with the same row switch information from the column dimension; for example, assuming that the size of the target matrix is 3X3, in the row dimension merging, the column switch information of the first row is 001, the column switch information of the second row is 001, and the column switch information of the third row is 100, the first row and the second row can be merged, and the third row is retained, and the size of the new matrix after merging becomes 2X3

[0034] Step 3-2, removing all 0 rows and all 0 columns in the merging result to obtain a row dimension matrix and a column dimension matrix, at this time, the minimum splitting number of the row dimension and the column dimension is obtained.

[0035] ​Step 3-3, compare the minimum split number of row dimension and column dimension, take the minimum split number as the final split result, if taking row dimension split, 1 in each row of row dimension matrix represents opening, 0 represents closing, as column switch information of this programming operation, the position of all same rows before merging is set to 1, and the rest is set to 0, as row switch information corresponding to the programming; if taking column dimension split, 1 in each column of column dimension matrix represents opening, 0 represents closing, as row switch information of this programming operation, the position of all same columns before merging is set to 1, and the rest is set to 0, as column switch information corresponding to the programming.

[0036] Step 4, start programming, that is, store data into the chip. According to the programming row and column information obtained in step 3, all programming operations are completed. Here, the split method result can be directly used for programming, or the same operation can be merged and then programmed, that is, the same row and column information obtained after splitting is merged and used as the programming row and column information, at this time, the information for each programming contains programming step information in addition to row information and column information, so as to save the setting time between the same row and column information programming links and further speed up the programming speed.

[0037] Therefore, the whole programming target matrix is split into a plurality of matrix forms supported by single programming of the chip, and then programmed, so that the parallel degree of programming can be effectively improved, wherein the smaller the number of split matrix is, the higher the average parallel degree of programming is, and the faster the programming speed is. The following will be specifically illustrated by examples.

[0038] Example 1

[0039] In this embodiment, the optoelectronic memory and calculation chip with crossbar structure is adopted, and the structure is shown in the attached Figure 4 The chip controls the array through the word line WL, the bit line BL and the source line SL, the WL, the BL and the SL of the corresponding device are turned on in the programming state, the WL and the SL are kept unchanged and the corresponding BL is turned off in the checking state, the current value is converted into the voltage value through the Sample & IV Circuits at the SL end, and finally the result is read out through the ADC. The Adder is used to realize the accumulation of the calculation result of multiple bits, and is not involved in the programming link.

[0040] In this embodiment, a random matrix with a value range of [0, 64] and an array size of 512*512 is programmed into the optoelectronic memory and calculation chip with crossbar structure, only the method of the present application is used as the pre-programming before accurate programming, that is, the rough programming scheme, no checking is needed, and the strategy of not merging the same programming information is adopted, and the work flow is shown in the attached Figure 1 The specific process of the method is as follows.

[0041] Firstly, in step 1 of the method of the present application, the initial value of the selected corresponding region of the optoelectronic memory chip is read, and in this embodiment, the initial value of the corresponding 512*512 region is 64. The initial value of the chip is subtracted from the to-be-programmed matrix to obtain the programming step matrix, and the value range of the programming step matrix is still [0, 64].

[0042] In step 2, in order to prevent over-programming, the programming step matrix is multiplied by 0.8, and in addition, the programming curve of the optoelectronic memory chip is processed according to the ideal linear case, and no additional processing is required for the programming step matrix. However, due to the non-uniformity of the optoelectronic memory chip, there is no obvious benefit in dividing too many segments in the pre-programming stage. In this embodiment, the programming step is divided into 5 segments, and the programming level in the programming step matrix (0, 12] threshold range is set to 1, the programming level in the range (13, 24] is set to 2, the programming level in the range (25, 36] is set to 3, the programming level in the range (37, 48] is set to 4, and the programming level in the range (49, 60] is set to 5. At this time, the programming level matrix matrix is obtained, and the value range is [0, 5]. Each level in the programming level matrix represents one programming operation.

[0043] In step 3, all non-zero values in the programming level matrix matrix are set to 1 to obtain the target array matrix_sub of this programming, where 1 represents opening and 0 represents closing (not programming). The matrix_sub is split into multiple matrices supporting single programming of the optoelectronic memory chip using the cross switch splitting method of the present application, and the row switch information (corresponding to the WL switch) and the column switch information (corresponding to the BL, SL switch) corresponding to these matrices are obtained. The specific process is as shown in FIG. 4. Figure 3As shown, matrix_sub is taken as the input of the crossbar splitting method, and the same rows and columns are merged from the row direction and the column direction, respectively. The number of rows and columns after merging is the corresponding split number rowsplit and cowsplit. Then, the all-zero rows and columns are removed, and the size of the new rowsplit and cowsplit is compared. If rowsplit is small, the row splitting number is small, and the splitting effect is good. At this time, row splitting is selected, and each row (i.e., UniqueRows) after merging of the row splitting represents a splitting result. The row switch information (WL) of each splitting result is the corresponding position row_idx of UniqueRows before merging of the input matrix matrix, and the column switch information (BL, SL) is the value of UniqueRows itself. Conversely, if cowsplit is small, column splitting is selected, and each row (i.e., UniqueCows) after merging of the column splitting represents a splitting result. The row switch information (WL) of each splitting result is the value of UniqueCows itself, and the column switch information (BL, SL) is the corresponding position cow_idx of UniqueCows before merging of the input matrix matrix.

[0044] In step 4, the WL, BL, and SL information obtained in step 3 is transmitted into the chip, and programming is started. After the current programming is completed, the new matrix is obtained by subtracting matrix_sub from matrix, and it is judged whether the matrix is all zero. If it is all zero, the current pre-programming is completed. If it is not all zero, step 3 and step 4 are repeated until the matrix becomes all zero.

[0045] To embody the effect of the crossbar splitting method of the present application, taking the existing row programming method as an example, 5*512 programming operations are required to achieve the same pre-programming. Compared with the row programming, the present application can obtain an acceleration ratio of 1-512 times. If the random matrix has values only in the opposite direction, the crossbar splitting method of the present application cannot be accelerated. If the values of each row of the random matrix are the same, the acceleration ratio of the crossbar splitting method can reach 512 times. In actual situations, the crossbar splitting method of the present application can usually obtain a good acceleration effect.

[0046] Example 2

[0047] In this embodiment, the same optoelectronic storage and calculation chip as in Example 1 is used. In the 512*512 array to be programmed, the values of the front 512*128 part are all 0, the values of the middle 512*128 part are all 16, and the values of the rear 512*256 part are all 32. The initial values of the corresponding 512*512 array of the chip are all 64. In this embodiment, the method of the present application is taken as accurate programming, and the same row and column information programming operation merging process is used. The working process is shown in the attached Figure 2 The same content as in Example 1 is not repeated.

[0048] In step 1 of the method of the present application, the current reading result of the chip is directly taken as the initial value of this programming, without the need of restoring the chip to the factory value, and a programming step matrix is obtained, wherein the values of the first 512*256 part are all 64, and the values of the second 512*256 part are all 32.

[0049] In step 2, since the programming curve of the optoelectronic memory chip can be considered as ideal, the programming step can be divided into 4 segments in the present embodiment, the programming step matrix is set as 1 in the range of (0, 16], as 2 in the range of (17, 32], as 3 in the range of (33, 48], and as 4 in the range of (49, 64]. At this time, a 512*512 programming step matrix matrix is obtained, wherein the values of the first 512*128 part are all 4, the values of the second 512*128 part are all 3, and the values of the second 512*256 part are all 2.

[0050] In step 3, the non-0 values in the programming step matrix matrix are all set as 1, a target array matrix_sub of this programming is obtained, and the corresponding split result is obtained by using the cross switch splitting method. At this time, the split result is saved without programming, a new matrix is obtained by subtracting the matrix_sub from the matrix, and a new matrix_sub is obtained again. The process is repeated until the matrix is all 0. After the same row and column switch information is merged, step 4 is entered to start all programming operations. After the programming is completed, a verification stage is entered, the current value of the chip is read out and compared with the to-be-programmed array, if the requirement is met, the programming is completed, if the requirement is not met, steps 1-4 are repeated until the programming precision meets the requirement.

[0051] In the present embodiment, the existing row programming method needs 4*512 unit programming times, while the present embodiment only needs 4 unit programming times, and a speedup ratio of 512 times is obtained, and only 3 programming configuration operations are performed by merging the same row and column switch information, if the merging strategy is not used, 4 programming configuration operations are needed. The programming efficiency of the present application is obviously improved.

[0052] The above only describes one specific embodiment of the present application, but the protection scope of the present application is not limited thereto, any changes or replacements within the technical range disclosed by the present application can be easily thought by those skilled in the art, and should be covered in the protection scope of the present application. Therefore, the protection scope of the present application should be subject to the protection scope of the claims.

Claims

1. A high parallelism programming method for crossbar architecture compute-in-memory chip, characterized in that, The method comprises the following steps: Step 1, obtaining the initial value of the chip, subtracting the target matrix from the initial value of the chip to obtain the programming step matrix of this programming; Step 2, adjusting the single programming pulse step according to the characteristics of the chip and the programming task target, adjusting the value of the programming step matrix, and then re-dividing the programming step matrix according to the corresponding threshold range to obtain the programming level matrix, each level in the programming level matrix representing one programming operation; Step 3, using the crossbar splitting method on the programming level matrix to split the programming level matrix into a matrix supported by the single programming of the memory-computing chip with the least total splitting times, and obtaining the programming row and column information according to the splitting result; Step 4, completing the programming operation according to the programming row and column information obtained in step 3.

2. The high parallel programming method for the crossbar structure compute-in-memory chip according to claim 1, wherein, In step 3, the crossbar splitting method specifically comprises the following steps: Step 3-1, merging the rows with the same column switch information from the row dimension, and merging the columns with the same row switch information from the column dimension; Step 3-2, removing the all-0 rows and all-0 columns in the merging result to obtain a row dimension matrix and a column dimension matrix, and obtaining the minimum splitting numbers of the row dimension and the column dimension at this time; Step 3-3, comparing the minimum splitting numbers of the row dimension and the column dimension, taking the smaller one as the final splitting result, if the row dimension splitting is taken, the 1 in each row of the row dimension matrix represents opening, and the 0 represents closing, which is taken as the column switch information of this programming operation, and the positions of all the same rows before merging are set to 1, and the remaining positions are set to 0, which are taken as the row switch information of the corresponding programming; if the column dimension splitting is taken, the 1 in each column of the column dimension matrix represents opening, and the 0 represents closing, which is taken as the row switch information of this programming operation, and the positions of all the same columns before merging are set to 1, and the remaining positions are set to 0, which are taken as the column switch information of the corresponding programming.

3. The method of claim 1, wherein, In step 1, the initial value of the chip can be the factory value or the current reading result of the chip.

4. The method of claim 1, wherein, In step 2, the programming step matrix is divided into different threshold ranges according to the programming characteristic curve of the chip, and then the programming level is set according to the threshold range to obtain the programming level matrix, which is a matrix closer to the real programming result of the memory-computing chip.

5. The method of claim 1, wherein, In step 3, the same row and column information obtained after splitting is merged as the programming row and column information, and at this time, the programming step information is included in the row information and the column information of each programming, so as to save the setting time between the programming links of the same row and column information.

6. The method of claim 1, wherein, In step 3, for the case that the number of row switches is much larger than the number of column switches, the crossbar splitting method is used only from the row direction to save unnecessary calculation; on the contrary, for the case that the number of column switches is much larger than the number of row switches, the crossbar splitting method is used only from the column direction.

7. The method of claim 1, wherein, The method supports accurate programming and also supports rough programming; the rough programming is used as the pre-programming before the accurate programming to program the chip to the vicinity of the target value, so as to speed up the subsequent accurate programming.

8. The method of claim 7, wherein, For the accurate programming, the result of the chip needs to be read out and checked after the end of the programming in step 4 each time to see if the accuracy requirement is met, and if the accuracy requirement is not met, steps 1-4 are repeated until the programming accuracy meets the requirement; for the rough programming, the programming in step 4 is completed, and the current programming is ended, and no checking is needed.

9. The method of claim 8, wherein, If the target of the rough programming is a pretreatment of the accurate programming, the value of the programming step matrix in step 2 is adjusted, including: before the programming step matrix is re-divided, the programming step matrix is multiplied by a coefficient less than 1, so that the result of the programming is around the target value while avoiding over-programming.

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