FPGA (Field Programmable Gate Array) dynamic allocation device and method based on server cluster

Abstract

According to the FPGA dynamic allocation device and method based on the server cluster, the field programmable characteristic of an FPGA can be greatly utilized, FPGA hardware is rewritten in real time, and the FPGA resource utilization rate and the operation efficiency of a server are greatly improved. The system comprises a data acquisition module, a controller, a first memory, a second memory and an FPGA device, the data acquisition module collects information, wherein the information comprises current time, user access habits, current server resource consumption conditions and to-be-executed task contents; the first memory stores FPGA engineering files in a binary code stream form, and each engineering file is a solution for accelerating a demand scene of a server cluster; the second memory stores an instruction program, and the instruction program directs the controller to download a specified FPGA project file into a specified FPGA device; and the controller downloads the FPGA project file to a specified FPGA device.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuits, and in particular to an FPGA dynamic allocation device based on a server cluster, and also to a method for an FPGA dynamic allocation device based on a server cluster. Background Art

[0002] With the development of cloud computing and big data technology, server clusters are increasingly widely used in enterprises, scientific research and government departments. Server clusters can provide high-performance, high-reliability and high-flexibility computing, storage and network services, helping users to quickly complete complex computing and data tasks, improve efficiency and reduce costs. In large-scale server clusters, FPGA (Field-Programmable Gate Array) is a programmable logic device with excellent parallel computing capabilities and flexibility, and is widely used to accelerate specific computing tasks. In traditional server clusters, the configuration of FPGA is static, that is, once the configuration is completed, it will not be modified. However, in actual applications, different tasks and different time-sharing intervals have different requirements for computing resources, such as user access habits and requirements during the day and at night, and static configuration cannot meet such dynamic changes. Therefore, the present invention proposes an FPGA dynamic allocation device based on a server cluster, which stores multiple acceleration schemes in advance, such as image processing, encryption and decryption algorithms, machine learning and other engineering files, and then dynamically downloads the engineering to the corresponding FPGA device according to specific needs. For example, during the daytime on weekdays, when there are more real-time communications, the network data packet processing project can be downloaded to the FPGA to improve network service performance; at night, when users have more demand for video viewing, the video processing algorithm project can be downloaded to the FPGA to accelerate video encoding and decoding. This invention utilizes the field programmable feature of FPGA to dynamically modify the FPGA project according to actual needs, improve the FPGA utilization rate, thereby improving the working performance of the server in different time periods and different scenarios, and improving the computing efficiency and flexibility of the server.

[0003] FPGA is a flexible and programmable digital circuit and a new type of programmable logic device based on programmable logic device (PLD). Compared with traditional ASIC (Application Specific Integrated Circuit) chips, FPGA allows users to program and customize its internal logic gate circuits according to the requirements of specific applications to form hardware circuits with specific functions. A server is a computer device used to store, process and transmit data. Servers are usually built on high-performance hardware platforms, using powerful processors (CPUs) with multiple processing cores and high clock frequencies to support parallel computing and fast response, and are also equipped with large-capacity memory (RAM) to simultaneously process large amounts of data and run complex applications. With the development of the Internet and the increase in data volume, servers need to process more requests and data. Traditional server technology may encounter challenges when processing large-scale data and high-concurrency requests, especially in complex tasks and intensive computing scenarios. Therefore, server clusters often introduce FPGAs to enhance parallel computing capabilities. Traditional servers integrate FPGAs, which download specific acceleration algorithms such as image processing algorithm engineering to FPGAs and do not change them, to accelerate server image processing. However, when the server needs to perform encryption and decryption operations, the FPGA is idle and cannot play its role in accelerating operations again. Summary of the invention

[0004] In order to overcome the defects of the prior art, the technical problem to be solved by the present invention is to provide an FPGA dynamic allocation device based on a server cluster, which can make full use of the field programmable characteristics of FPGA and rewrite FPGA hardware in real time, thereby greatly improving the FPGA resource utilization and the server's computing efficiency.

[0005] The technical solution of the present invention is: the FPGA dynamic allocation device based on server cluster includes: a data acquisition module, a controller, a first memory, a second memory, and an FPGA device; The data collection module collects information, including the current time, user access habits, current server resource consumption, and the content of tasks to be performed; The first memory stores FPGA project files in the form of binary code streams. Each project file is a solution for accelerating a demand scenario of the server cluster. The second memory stores an instruction program, which instructs the controller to download a specified FPGA project file to a specified FPGA device; The controller downloads the FPGA project file to the specified FPGA device.

[0006] The beneficial technical effects of the present invention are as follows: 1. Realize dynamic allocation of FPGA and improve the server's ability to process data.

[0007] 2. Make full use of FPGA field programmability to improve the utilization rate of FPGA devices.

[0008] 3. Rewrite FPGA hardware in real time, greatly improving FPGA resource utilization and server computing efficiency.

[0009] 4. It can reduce the number of FPGA devices in the server cluster and reduce costs.

[0010] A method for dynamically allocating an FPGA device based on a server cluster is also provided, the method comprising the following steps: (1) The data collection module collects information, including the current time, user access habits, current server resource consumption, and the content of the tasks to be performed; (2) The first memory stores FPGA project files in the form of binary code streams. Each project file is a solution for accelerating a demand scenario of the server cluster. (3) The second memory stores an instruction program, and the instruction program instructs the controller to download a specified FPGA project file to a specified FPGA device; (4) The controller downloads the FPGA project file to the specified FPGA device according to the instruction program. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Figure 1 It is a principle block diagram of an FPGA dynamic allocation device based on a server cluster according to the present invention.

[0012] Figure 2 The correspondence between FPGA projects and FPGA devices is shown.

[0013] Figure 3 Shows FPGA engineering development and storage.

[0014] Figure 4 Shows the principle block diagram of the data acquisition module.

[0015] Figure 5 It is a flow chart of a method for dynamically allocating an FPGA device based on a server cluster according to the present invention.

[0016] Figure 6 It is a flowchart of a program stored in the second memory of the FPGA dynamic allocation device based on the server cluster according to the present invention. DETAILED DESCRIPTION

[0017] In order to make the purpose, technical solution and advantages of the present invention more clearly understood, the present invention is further described in detail below in conjunction with the accompanying drawings and specific embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not used to limit the present invention.

[0018] In order to make the description of the present disclosure more detailed and complete, the following provides an illustrative description of the implementation and specific embodiments of the present invention; however, this is not the only form of implementing or using the specific embodiments of the present invention. The implementation covers the features of multiple specific embodiments and the method steps and sequences used to construct and operate these specific embodiments. However, other specific embodiments can also be used to achieve the same or equivalent functions and step sequences.

[0019] like Figure 1 As shown, the FPGA dynamic allocation device based on the server cluster includes: a data acquisition module, a controller, a first memory, a second memory, and an FPGA device; The data collection module collects information, including the current time, user access habits, current server resource consumption, and the content of tasks to be performed; The first memory stores the FPGA project file in the form of a binary code (bit) stream (i.e. Figure 1 Projects 1-n in the figure), each project file is a solution for accelerating a certain scenario of the server cluster ( Figure 2 It shows the correspondence between FPGA project and FPGA device. Figure 3 shows FPGA engineering development and storage); The second memory stores an instruction program, which instructs the controller to download a specified FPGA project file to a specified FPGA device; The controller downloads the FPGA project file to the specified FPGA device.

[0020] The beneficial technical effects of the present invention are as follows: 1. Realize dynamic allocation of FPGA and improve the server's ability to process data.

[0021] 2. Make full use of FPGA field programmability to improve the utilization rate of FPGA devices.

[0022] 3. Rewrite FPGA hardware in real time, greatly improving FPGA resource utilization and server computing efficiency.

[0023] 4. It can reduce the number of FPGA devices in the server cluster and reduce costs.

[0024] Preferably, if Figure 4As shown, the data acquisition module is connected to a timer, a key input module, a temperature sensor, an Internet port, an image processing unit, an encryption and decryption unit, and a storage unit; The timer records the current time and the start and end time of each task, and counts the working time nodes and time-consuming information of each task, which helps to understand the periodicity and regularity of the tasks, so as to predict future resource requirements; the network port monitors the data traffic of the network interface, obtains the network busyness and data transmission efficiency, identifies network bottlenecks and optimizes network resources; the image processing unit collects data related to image processing (such as the number, type and processing time of image processing tasks) in order to evaluate the load of image processing tasks and reasonably allocate FPGA resources; the encryption and decryption unit collects data related to encryption and decryption operations (such as the number, type and execution time of encryption and decryption tasks); the storage unit monitors the usage of the storage system, including read and write speeds and storage space occupancy; the temperature sensor monitors the working environment temperature of the server to ensure that the server runs within a safe temperature range and avoids system failures caused by excessive temperature; the user manually configures each FPGA device through the key input module, providing a means of manual intervention in an emergency.

[0025] Preferably, the FPGA engineering file is an RTL code written in Verilog hardware description language according to different requirements, and then the RTL code is synthesized, laid out and routed through an FPGA synthesis tool, and finally a binary code stream file is generated.

[0026] Preferably, when the existing requirements are TCP / IP protocol stack processing and AES encryption, after the corresponding RTL code is written and the binary code stream file is generated, the TCP / IP protocol stack processing corresponds to the first FPGA project file, which is stored in the low address space of the first memory; AES encryption corresponds to the second FPGA project file, which is stored in the high address space of the first memory; the address space allocation of the first memory is allocated according to the actual size and number of project files.

[0027] Preferably, the second memory also stores configuration information, and the instruction program defines a selection strategy for the FPGA project file in the first memory.

[0028] The controller is one of the core components of the FPGA dynamic allocation device based on the server cluster. It is responsible for receiving various information from the data acquisition module, including time information, temperature, server resource consumption, etc. Then it executes the instruction program in the second memory, and combines various information from the data acquisition module to decide when and which FPGA project in the first memory should be downloaded to which specific FPGA device.

[0029] Assume that during the day, people in a server cluster have a huge demand for real-time communication to handle their daily work, but the server cannot handle it in time, resulting in communication delays and poor user experience. At night, people's demand for entertainment and watching movies increases dramatically, but the server cannot process the video stream data in time, resulting in a poor viewing experience at night. Traditional FPGA acceleration solutions use an FPGA to program the network protocol processing project to increase network throughput and solve daytime problems. However, the FPGA device is not changed after programming, so it is useless at night, resulting in idle FPGA hardware resources. The FPGA dynamic allocation device based on server clusters proposed in the present invention, such as Figure 1 , the network protocol processing project (accelerating real-time communication) and the video codec project (accelerating the parsing of video data) can be stored in the first memory, the data acquisition module collects the current time and feeds it back to the controller module, and then stores the pre-written instruction program in the second memory. The program is used to control a specific time, such as downloading the FPGA project of network protocol processing to all FPGAs or multiple FPGA devices at 8 am, and downloading the FPGA project of video codec project to all FPGAs or multiple FPGA devices after 6 pm. The controller executes instructions according to the program content and the time data fed back by the data acquisition module, and performs control to realize real-time and accurate scheduling of FPGA resources.

[0030] like Figure 5 As shown, a method for dynamically allocating an FPGA device based on a server cluster is also provided, the method comprising the following steps: (1) The data collection module collects information, including the current time, user access habits, current server resource consumption, and the content of the tasks to be performed; (2) The first memory stores FPGA project files in the form of binary code streams. Each project file is a solution for accelerating a demand scenario of the server cluster. (3) The second memory stores an instruction program, and the instruction program instructs the controller to download a specified FPGA project file to a specified FPGA device; (4) The controller downloads the FPGA project file to the specified FPGA device according to the instruction program.

[0031] Preferably, in step (1), the data acquisition module is connected to the timer, the key input module, the temperature sensor, the network port, the image processing unit, the encryption and decryption unit, and the storage unit; The timer records the current time and the start and end time of each task, and counts the working time nodes and time-consuming information of each task; the network port monitors the data traffic of the network interface, obtains the network busyness and data transmission efficiency, identifies network bottlenecks and optimizes network resources; the image processing unit collects data related to image processing in order to evaluate the load of image processing tasks and reasonably allocate FPGA resources; the encryption and decryption unit collects data related to encryption and decryption operations; the storage unit monitors the usage of the storage system, including read and write speeds and storage space occupancy; the temperature sensor monitors the working environment temperature of the server to ensure that the server runs within a safe temperature range; the user manually configures each FPGA device through the key input module.

[0032] Preferably, in step (2), the FPGA project file is an RTL code written in Verilog hardware description language according to different requirements, and then the RTL code is synthesized, laid out and routed by an FPGA synthesis tool, and finally a binary code stream file is generated.

[0033] Preferably, in step (2), when the existing requirements are TCP / IP protocol stack processing and AES encryption, after the corresponding RTL code is written and the binary code stream file is generated, the TCP / IP protocol stack processing corresponds to the first FPGA project file, which is stored in the low address space of the first memory; the AES encryption corresponds to the second FPGA project file, which is stored in the high address space of the first memory; the address space allocation of the first memory is allocated according to the actual size and number of project files.

[0034] Preferably, in step (1), the data acquisition module acquires the current time and feeds it back to the controller; in step (2), the network protocol processing project file and the video codec project file are stored in the first memory; in step (3), the pre-written instruction program is stored in the second memory, and the instruction program is used to control the downloading of the network protocol processing project file to all FPGA devices or multiple FPGA devices at a specific time, and the downloading of the video codec project file to all FPGA devices or multiple FPGA devices at another specific time; in step (4), the controller executes the instruction and performs control according to the instruction program and the current time fed back by the data acquisition module, so as to realize real-time scheduling of FPGA resources.

[0035] Figure 6 It is a flowchart of a program stored in the second memory of the FPGA dynamic allocation device based on the server cluster according to the present invention. Specifically, it includes the following steps: (I) Initializing the data acquisition module, initializing the controller, and initializing the first memory; (II) Get the current time, monitor server resource consumption, analyze user access patterns, and obtain a list of pending tasks; (III) Determine whether the current time = working day and the task type = real-time communication. If so, the project to be executed = network data packet processing project, and execute step (VI). Otherwise, execute step (IV). (IV) Determine whether the current time = non-working day and the task type = video analysis. If so, the project to be executed = video processing algorithm project, and execute step (VI). Otherwise, execute step (V). (V) Determine if there are no other task conditions. If yes, the project to be executed = other task project, and execute step (VI); (VI) determining whether the current FPGA project is not the FPGA project to be executed, if so, executing step (VII), otherwise executing step (VIII); (VII) Current FPGA project = load the corresponding project from the first memory and update it to the specified FPGA device, then jump to step (IX); (VIII) Current FPGA project = original FPGA project, FPGA device does not need to be updated; (IX) Execute a certain number of times and jump to step (II).

[0036] Figure 6 In the third and fourth lines, "Current time == working day", "Task type == real-time communication", "Current time == non-working day", "Task type == video analysis", "Network packet processing project", and "Video processing algorithm project" are all for reference. Task judgment and specific FPGA project content need to be adjusted according to specific actual needs. The flowchart is only for reference to explain the process.

[0037] The above description is only a preferred embodiment of the present invention and does not limit the present invention in any form. Any simple modification, equivalent changes and modifications made to the above embodiments based on the technical essence of the present invention are still within the protection scope of the technical solution of the present invention.

Claims

1. An FPGA dynamic allocation device based on a server cluster, characterized in that: It includes: Data acquisition module, controller, first memory, second memory, FPGA device; The data collection module collects information, including the current time, user access habits, current server resource consumption, and the content of tasks to be performed; The first memory stores FPGA project files in the form of binary code streams. Each project file is a solution for accelerating a demand scenario of the server cluster. The second memory stores an instruction program, which instructs the controller to download a specified FPGA project file to a specified FPGA device; The controller downloads the FPGA project file to the specified FPGA device.

2. The FPGA dynamic allocation device based on server cluster according to claim 1, characterized in that: The data acquisition module is connected to a timer, a key input module, a temperature sensor, an Internet port, an image processing unit, an encryption and decryption unit, and a storage unit; The timer records the current time and the start and end time of each task, and counts the working time nodes and time-consuming information of each task; the network port monitors the data traffic of the network interface, obtains the network busyness and data transmission efficiency, identifies network bottlenecks and optimizes network resources; the image processing unit collects data related to image processing in order to evaluate the load of image processing tasks and reasonably allocate FPGA resources; the encryption and decryption unit collects data related to encryption and decryption operations; The storage unit monitors the usage of the storage system, including read and write speeds and storage space occupancy; the temperature sensor monitors the server's working environment temperature to ensure that the server operates within a safe temperature range; the user manually configures each FPGA device through the key input module.

3. The FPGA dynamic allocation device based on server cluster according to claim 2, characterized in that: The FPGA project file is an RTL code written in the Verilog hardware description language according to different requirements. The RTL code is then synthesized, laid out and routed through an FPGA synthesis tool, and finally a binary code stream file is generated.

4. The FPGA dynamic allocation device based on server cluster according to claim 3, characterized in that: When the existing requirements are TCP / IP protocol stack processing and AES encryption, after the corresponding RTL code is written and the binary code stream file is generated, the TCP / IP protocol stack processing corresponds to the first FPGA project file, which is stored in the low address space of the first memory; the AES encryption corresponds to the second FPGA project file, which is stored in the high address space of the first memory; The address space of the first memory is allocated according to the actual size and number of project files.

5. The FPGA dynamic allocation device based on server cluster according to claim 4, characterized in that: The second memory also stores configuration information, and the instruction program defines a selection strategy for the FPGA project file in the first memory.

6. The method of FPGA dynamic allocation device based on server cluster according to claim 1, characterized in that: The method comprises the following steps: (1) The data collection module collects information, including the current time, user access habits, current server resource consumption, and the content of the tasks to be performed; (2) The first memory stores FPGA project files in the form of binary code streams. Each project file is a solution for accelerating a demand scenario of the server cluster. (3) The second memory stores an instruction program, and the instruction program instructs the controller to download a specified FPGA project file to a specified FPGA device; (4) The controller downloads the FPGA project file to the specified FPGA device according to the instruction program.

7. The method of FPGA dynamic allocation device based on server cluster according to claim 6, characterized in that: In the step (1), the data acquisition module is connected to the timer, the key input module, the temperature sensor, the network port, the image processing unit, the encryption and decryption unit, and the storage unit; The timer records the current time and the start and end time of each task, and counts the working time nodes and time-consuming information of each task; the network port monitors the data traffic of the network interface, obtains the network busyness and data transmission efficiency, identifies network bottlenecks and optimizes network resources; the image processing unit collects data related to image processing in order to evaluate the load of image processing tasks and reasonably allocate FPGA resources; the encryption and decryption unit collects data related to encryption and decryption operations; The storage unit monitors the usage of the storage system, including read and write speeds and storage space occupancy; the temperature sensor monitors the server's working environment temperature to ensure that the server operates within a safe temperature range; the user manually configures each FPGA device through the key input module.

8. The method of FPGA dynamic allocation device based on server cluster according to claim 7, characterized in that: In the step (2), the FPGA project file is an RTL code written in the Verilog hardware description language according to different requirements, and then the RTL code is synthesized, laid out and routed by the FPGA synthesis tool, and finally a binary code stream file is generated.

9. The method of FPGA dynamic allocation device based on server cluster according to claim 8, characterized in that: In the step (2), when the existing requirements are TCP / IP protocol stack processing and AES encryption, after the corresponding RTL code is written and the binary code stream file is generated, the TCP / IP protocol stack processing corresponds to the first FPGA project file, which is stored in the low address space of the first memory; the AES encryption corresponds to the second FPGA project file, which is stored in the high address space of the first memory; The address space of the first memory is allocated according to the actual size and number of project files.

10. The method of FPGA dynamic allocation device based on server cluster according to claim 8, characterized in that: In the step (1), the data acquisition module acquires the current time and feeds it back to the controller; in the step (2), the network protocol processing project file and the video codec project file are stored in the first memory; in the step (3), the pre-written instruction program is stored in the second memory, and the instruction program is used to control the downloading of the network protocol processing project file to all FPGA devices or multiple FPGA devices at a specific time, and the downloading of the video codec project file to all FPGA devices or multiple FPGA devices at another specific time; in the step (4), the controller executes the instruction according to the instruction program and the current time fed back by the data acquisition module, and performs control so as to realize real-time scheduling of FPGA resources.

Images