A multi-scenario multi-algorithm adaptation vector memory access controller implementation method

Abstract

The application relates to the technical field of a vector processor and discloses a multi-scene multi-algorithm adaptive vector memory controller implementation method, which comprises the following steps: a memory control module acquires a configuration signal of an upper computer, determines a data reading mode and an algorithm parallel degree, and generates a memory control signal; a memory state module generates reading control instructions and writing control instructions in response to the memory control signal; a source data module reads source data from a storage resource in response to the reading control instructions, and sends the source data into a calculation resource for data operation to obtain result data; and a result data module acquires the result data from the calculation resource and writes the result data into the storage resource in response to the writing control instructions. The application can flexibly select an algorithm implementation mode according to an algorithm parallel degree, a data batch number and a data point number, so that better vector memory performance can be achieved under different application scenes or different data dimensions.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of vector processors, and particularly relates to a vector memory access controller implementation method for multi-scene and multi-algorithm adaptation. BACKGROUND

[0002] Vector operations can simultaneously calculate one or more groups of data, which can significantly improve the speed of data processing, and thus are particularly suitable for parallel processing architectures. However, to fully exploit the advantages of vector operations, data must be quickly and accurately read from the memory to the calculation unit, and the calculation result must be efficiently written back to the memory. This not only requires the storage system to have high bandwidth characteristics, but also requires an effective mechanism to manage data flow so that data can reach the correct processing unit at the correct time point.

[0003] Currently, there are many vector processor design schemes optimized for specific scenarios in the industry. For example, the SIMD (Single Instruction Multiple Data) architecture is widely used in graphics processors (GPU) to accelerate large-scale parallel computing tasks; and in some ASIC (Application Specific Integrated Circuit) or FPGA (Field Programmable Gate Array) solutions, highly optimized data paths are achieved through customized hardware logic. Although these schemes perform well in their respective application ranges, they often have difficulty in flexibly responding to diversified computing needs or require high development costs. Many existing schemes are designed specifically to solve a certain type of problem, and lack sufficient versatility and configurability. Once the application scenario changes, the entire system may need to be redesigned. When the size of the data set being processed is small or irregular, the existing vector processor may have a large number of idle cycles, resulting in a decline in overall performance. Even in the case of using cache technology, frequent memory access is still an important factor limiting overall performance. This situation is particularly prominent in tasks involving large amounts of small batch data processing. In the face of the above situation, it is particularly important to build a vector memory access control system that has both wide applicability and provides excellent performance.

[0004] A vector data access control method and a vector memory supporting limited sharing are disclosed in Chinese Patent No. CN102279818B. The method steps are as follows: 1) uniformly addressing the vector memory; 2) obtaining access information, decomposing, expanding, and shifting and circularly arranging the vector address in the access information to generate N sets of access information; 3) sending the N sets of access information to the access pipeline of the vector memory bank; if the current vector access instruction is a read instruction, performing reverse shift and circular arrangement on the N-way write-back data according to the shared shift address to obtain N sets of write-back data and sending the write-back data to the corresponding vector processing unit in the vector processor; the vector memory includes a vector address generator, a vector memory bank unit, and an access management control unit, and the access management control unit includes a vector address arrangement unit and a vector data arrangement unit. The invention has the advantages of low hardware implementation cost, support for limited sharing of vector data, and non-aligned access.

[0005] A vector processor for online time series prediction is disclosed in Patent Application No. CN104699458A. It is to solve the problem that the existing vector processor cannot be optimized for specific methods, resulting in poor universality and inability to meet the needs of online computing. The fixed-point vector processor described in the invention includes a program counter, a microcode memory, a vector memory, an arithmetic logic unit, and a data control unit. The complete fixed-point vector processor is formed through the signal processing flow between the modules of the aforementioned fixed-point vector processor. Through heterogeneous ALU design, the ALU structure of each data path can be flexibly changed according to the computing needs, realizing flexible configuration of the instruction set. It is suitable for occasions with complex computing needs.

[0006] The above patents all have the problem proposed in the background art: the access does not distinguish between data configuration information, and the same method is used to implement algorithms under different configurations, resulting in low resource utilization and low handling efficiency.

[0007] The information disclosed in this BACKGROUND section is only intended to increase an understanding of the general context in which the present application can be practiced. It should not be taken as an acknowledgement or any form of suggestion that this information forms a prior art that is commonly known to those skilled in the art. SUMMARY

[0008] The technical problem solved by the present application is to overcome the defects of the prior art and provide a vector memory access controller implementation method suitable for multiple scenes and multiple algorithms, which is designed based on the design idea of storage and calculation decoupling, separates data storage and data processing, extracts common factors among vector algorithms, and designs a vector memory access controller supporting two implementation modes of stream mode and batch mode, and can implement vector addition, vector dot multiplication, vector multiplication, vector summation, vector mean and other vector algorithms based on configuration information sent by a host computer.

[0009] To solve the above technical problems, the present application provides the following technical solutions:

[0010] In one aspect, the present application provides a vector memory access controller implementation method suitable for multiple scenes and multiple algorithms, which comprises a memory access state module, a memory access control module, a source data module and a result data module; the method comprises the following steps:

[0011] The memory access control module obtains the configuration signal of the host computer, determines the source data reading mode, the result data writing mode and the algorithm parallel degree, and generates a memory access control signal;

[0012] The memory access state module generates a reading control instruction and a writing control instruction in response to the memory access control signal;

[0013] The source data module reads source data from the storage resource in response to the reading control instruction and sends the data to the calculation resource for data operation to obtain result data;

[0014] The result data module obtains result data from the calculation resource and writes it into the storage resource in response to the writing control instruction.

[0015] As a preferred scheme of the vector memory access controller implementation method suitable for multiple scenes and multiple algorithms, wherein: the source data reading mode comprises stream mode and batch mode; the source data reading mode is determined in the following manner:

[0016] If the data collected by a single sensor is collected in a data stream mode and stored horizontally in the storage resource, the source data reading mode adopts the stream mode; wherein, the horizontal storage means that the data received in each clock cycle with a length of Δt is arranged in the storage resource in time sequence;

[0017] If the single type of data collected by the multiple sensors is collected in the form of multiple batches of data, and the data is stored in the storage resource in batches in the vertical direction, the source data reading mode adopts a batch mode; the storage in batches in the vertical direction means that the data collected by different sensors is stored in the form of a two-dimensional array in the storage resource, wherein any row of the two-dimensional array represents the same batch of data collected by different sensors, and any column represents different batches of data collected by the corresponding sensor.

[0018] As a preferred scheme of the vector memory controller implementation method for multi-scene multi-algorithm adaptation of the application, wherein: the algorithm parallelism represents the number of source data read from the storage resource at any time;

[0019] The configuration signal is a signal sent by the upper computer to the vector memory controller, used for configuring the behavior of the controller.

[0020] The memory control signal is used to control the state jump of the main state machine, the source data state machine, and the result data state machine.

[0021] As a preferred scheme of the vector memory controller implementation method for multi-scene multi-algorithm adaptation of the application, wherein: the memory state module includes a main state machine, a source data state machine, and a result data state machine; the main state machine is used to respond to the memory control signal and control the working state of the vector memory controller, including controlling the state jump of the source data state machine and the result data state machine; the source data state machine is used to generate a read control instruction to drive the source data module to perform the source data reading operation; and the result data state machine is used to generate a write control instruction to control the result data module to perform the result data writing operation.

[0022] As a preferred scheme of the vector memory controller implementation method for multi-scene multi-algorithm adaptation of the application, wherein: if the source data reading mode is a stream mode, the method for reading the source data from the storage resource is as follows: the source data module reads m source data from the storage resource in the horizontal direction each time, m being the algorithm parallelism; the m source data read in the horizontal direction each time are consecutive m source data in the same batch, wherein any batch of source data is collected based on the same sensor; if the single batch of source data involved in the i-th time of reading the source data has n remaining source data, and n is less than m, i being any positive integer, the control module generates a batch end zero assignment signal, the source data module responds to the batch end zero assignment signal, reads the remaining n source data, and adds m-n zero assignment data after the n source data, which are collectively transmitted to the computing resource; if the data reading of all batches is not completed at this time, at the beginning of the i+1-th time of reading the source data, the control module generates a batch start zero assignment signal, the source data module responds to the batch start zero assignment signal, reads m-n source data in the next batch of source data, and adds n zero assignment data before the m-n source data, which are collectively transmitted to the computing resource.

[0023] As a preferred solution of the vector memory controller implementation method for multi-scenario multi-algorithm adaptation of the present application, if the source data reading mode is batch mode, the method for reading source data from the storage resource is as follows: the source data module reads m source data from the storage resource horizontally each time, m being the algorithm parallelism; the m source data read horizontally each time are m batches of source data at the same time point, wherein the m batches of source data are collected based on m sensors respectively; if the number of source data batches involved in the jth reading of source data is k, and k is less than m, j being any positive integer, the algorithm parallelism is adjusted to k, and k source data is read horizontally and sent to the computing resource.

[0024] As a preferred solution of the vector memory controller implementation method for multi-scenario multi-algorithm adaptation of the present application, if the source data reading mode is stream mode, the method for data operation is as follows: the vector algorithm is called by using the algorithm-level API, or the stream mode of the computing unit is called by using the unit-level API, and the vector operation is performed by calling the multiply-accumulate tree.

[0025] If the source data reading mode is batch mode, the method for data operation is as follows: the batch mode of the computing unit is called by using the unit-level API, and the vector operation is performed by calling the multiply-accumulate.

[0026] As a preferred solution of the vector memory controller implementation method for multi-scenario multi-algorithm adaptation of the present application, the source data module is instantiated in the vector memory controller , wherein m is the algorithm parallelism and is a positive integer, , indicating rounding up; each source data module generates two groups of source data channels, and controls the vector memory controller to interact with the storage resource and the computing resource for source data in the two groups of source data channels at the same time;

[0027] The result data module is instantiated in the vector memory controller , and each result data module generates two groups of result data channels, and controls the vector memory controller to interact with the storage resource and the computing resource for result data in the two groups of result data channels at the same time.

[0028] In a second aspect, the present application provides an electronic device, comprising: a memory for storing instructions; a processor for executing the instructions, so that the device performs the operations of the vector memory controller implementation method for multi-scenario multi-algorithm adaptation of the present application.

[0029] In a third aspect, the present application provides a computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the vector memory controller implementation method for multi-scenario multi-algorithm adaptation of the present application.

[0030] Compared with the prior art, the application has the following beneficial effects:

[0031] The application provides a vector memory access controller implementation method for multi-scene and multi-algorithm adaptation, which can adaptively adjust its working mode according to different application scenes and algorithm requirements, thereby providing wider applicability while maintaining high performance. By supporting two data reading modes of stream mode and batch mode, the application can efficiently utilize computing resources in different scenes. The stream mode is suitable for continuous data streams generated by a single sensor, ensuring real-time processing capability; and the batch mode is suitable for data collected by multiple sensors at the same time, which can reduce the number of memory access times and improve overall efficiency. This flexibility enables the controller to optimize performance for specific applications.

[0032] The application sends a configuration signal to the vector memory access controller through the host computer to determine the specific source data reading mode, result data writing mode and algorithm parallelism. This design gives the system high configurability, enabling it to adapt to diversified computing tasks and environmental changes, improving the versatility and expansion capability of the entire system. When the complete data block size is not met, the application fills the insufficient part by generating a batch end zero signal or a batch start zero signal, ensuring that the data input to the computing unit always has a fixed format, which not only simplifies the computing logic, but also prevents result errors caused by inconsistent data, ensuring the accuracy and reliability of the computing result.

[0033] In summary, the application solves some key problems in the current technology through innovative design of the vector memory access controller, achieving higher performance, better adaptability and lower power consumption, laying a solid foundation for further development in related fields. BRIEF DESCRIPTION OF DRAWINGS

[0034] In order to more clearly illustrate the technical solutions of the embodiments of the application, the following will briefly introduce the drawings needed to be used in the embodiment description. Obviously, the drawings in the following description are only some embodiments of the application, and for those skilled in the art, other drawings can also be obtained without creative labor. Among them:

[0035] Figure 1 A flow chart of a vector memory access controller implementation method for multi-scene and multi-algorithm adaptation is provided for the application.

[0036] Figure 2 A data stream path schematic diagram for source data reading based on stream mode is provided for the application.

[0037] Figure 3 A data stream path schematic diagram for source data reading based on batch mode is provided for the application. DETAILED DESCRIPTION

[0038] The technical solutions of the present application will be described in detail below with reference to the drawings and specific embodiments. It should be understood that the embodiments of the present application and the specific features in the embodiments are detailed descriptions of the technical solutions of the present application, rather than limitations of the technical solutions of the present application. In the case of no conflict, the technical features in the embodiments of the present application and the embodiments can be combined with each other.

[0039] Embodiment 1

[0040] This embodiment introduces a vector memory access controller implementation method for multi-scene and multi-algorithm adaptation. The vector memory access controller includes a memory access state module, a memory access control module, a source data module, and a result data module. Referring to Figure 1 The method includes the following steps:

[0041] The memory access control module acquires the configuration signal of the upper computer, determines the source data reading mode, the result data writing mode, and the algorithm parallelism, and generates a memory access control signal;

[0042] The source data reading mode includes a stream mode and a batch mode. The source data reading mode is determined in the following manner:

[0043] If the data collected by a single sensor is collected in a data stream manner and the data is stored horizontally in the storage resource, the source data reading mode adopts the stream mode. The horizontal storage means that the data received in each clock cycle with a length of Δt is arranged horizontally in the storage resource in time sequence. In this state, the stream mode is used to sequentially send the data into the calculation unit for calculation. At this time, all the calculation resources in the calculation unit can be mobilized, so the operation real-time performance is strong, and the fast real-time calculation of a single data stream can be realized.

[0044] If the single type data collected by multiple sensors is collected in a multi-batch data manner and the data is stored vertically in the storage resource by batch, the source data reading mode adopts the batch mode. The vertical storage by batch means that the data collected by different sensors is stored in the form of a two-dimensional array in the storage resource. Any row of the two-dimensional array represents the same batch data collected by different sensors, and any column represents the different batch data collected by the corresponding sensor. In this state, the batch mode is used to read the data horizontally, that is, the data collected by multiple sensors is sent into the calculation unit in batches for calculation. One batch of data only contains one data collected by each sensor. For a single sensor, the data reading and calculation are performed in batches one by one, rather than a continuous data stream, so the calculation resources are not fully utilized, resulting in poor real-time performance. However, multiple device information can be processed simultaneously, and a batch of data can be read at a time, which reduces the number of times of reading data. This has great advantages in reducing the number of memory access times and improving the overall efficiency when the data volume is large.

[0045] The algorithm parallelism represents the number of source data read from the storage resource at a time;

[0046] The configuration signal is a signal sent by the host computer to the vector memory controller, used to configure the behavior of the controller. The configuration signal can include start, stop signals, read-write address, data width, algorithm type, and other configuration information.

[0047] The memory control signal is used to control the state jump of the main state machine, the source data state machine, and the result data state machine, including read-write enable signal, address signal, data valid signal, etc. Through the control of the memory control signal, the behavior of each module in the memory process can be coordinated to ensure that data is correctly read from the storage resource to the computing resource or written back from the computing resource to the storage resource, realizing the ordered reading and writing of data and ensuring the normal operation of the vector memory controller.

[0048] The memory state module generates read control instructions and write control instructions in response to the memory control signal;

[0049] The memory state module includes a main state machine, a source data state machine, and a result data state machine. The main state machine is used to respond to the memory control signal and control the working state of the vector memory controller, including controlling the state jump of the source data state machine and the result data state machine. It also includes the main control logic of the entire vector memory controller, such as initialization, start, stop, and other global states. The source data state machine is used to generate read control instructions to drive the source data module to read source data. The result data state machine is used to generate write control instructions to control the result data module to write result data. The working process of the memory state module is as follows:

[0050] First, the main state machine, the source data state machine, and the result data state machine are all in the initialization state. Under the control of the memory control signal, the main state machine jumps to the start state and controls the source data state machine and the result data state machine to jump to the start state. The source data state machine controls the source data module to read data from the storage resource, and the result data state machine controls the result data module to write result data back to the storage resource. When all data processing is completed, the main state machine switches to the end state, controls the source data state machine and the result data state machine to jump to the end state, and sends an end signal to the host computer, indicating that the entire vector memory process has been completed.

[0051] The source data module reads source data from the storage resource in response to the read control instructions and sends it to the computing resource for data operation to obtain result data;

[0052] If the source data reading mode is the stream mode, the method for reading the source data from the storage resource is as follows: the source data module reads m source data from the storage resource each time, m is the algorithm parallelism; the m source data read each time are continuous m in the same batch of source data, and any batch of source data is collected based on the same sensor; the data reading mode can ensure that the source data is sent into the computing resource in time sequence; if the single batch of source data involved when the source data is read for the i-th time is left with n, and n is less than m, i is any positive integer, the control module generates a batch end zero assignment signal, the source data module reads the remaining n source data in response to the batch end zero assignment signal, and adds m-n data with a value of 0 after the n source data, and the n source data and the m-n data are collectively transmitted to the computing resource; if the data reading of all batches is not completed at this time, the control module generates a batch start zero assignment signal when the source data is read for the i+1-th time, and the source data module reads m-n source data in the next batch of source data in response to the batch start zero assignment signal, and adds n data with a value of 0 before the m-n source data, and the n data and the m-n source data are collectively transmitted to the computing resource.

[0053] Through the control of the batch end zero assignment signal, the data positions less than m are assigned to the computing resource, which can ensure the consistency of the data format, so that the next batch of source data will not affect the calculation result of the current batch of source data. Similarly, through the control of the batch start zero assignment signal, the data positions corresponding to the last batch less than m are assigned to the computing module, which can also ensure the consistency of the data format, so that the last batch of source data will not affect the calculation result of the current batch of source data.

[0054] If the source data reading mode is the batch mode, the method for reading the source data from the storage resource is as follows: the source data module reads m source data from the storage resource each time, m is the algorithm parallelism; the m source data read each time are m batches of source data at the same time point, and the m batches of source data are collected based on m sensors respectively; if the number of batches of source data involved when the source data is read for the j-th time is k, and k is less than m, j is any positive integer, the algorithm parallelism is adjusted to k, and k source data is read horizontally and sent to the computing resource.

[0055] Through single batch reading data and adaptive adjustment of algorithm parallelism, the vector memory controller can be applied to the transmission of multiple batches of data in a single type signal scenario of multiple devices, the data transfer is simplified, and the transfer frequency is reduced.

[0056] If the source data reading mode is the stream mode, the method for performing data operation is as follows: the algorithm level API is called to call the vector algorithm, or the stream mode of the unit level API is called to call the computing unit, and the multiply-accumulate tree is called to perform vector operation.

[0057] In the stream mode, vector operations can be implemented by directly calling functions through the algorithm-level API, or by accessing and controlling the underlying computing units to process continuous data streams of source data in stream mode and calling a multiply-accumulate tree (MAC Tree) to specifically perform vector multiplication and accumulation operations. The computing unit is a computing resource that performs specific operation tasks, which can be a hardware or software component, such as a computing unit in a CPU, GPU, FPGA, etc. The multiply-accumulate tree is a data structure used to efficiently process multiply-accumulate operations in continuous data streams. In stream mode, data enters the system one by one, and each incoming data is multiplied and the result is accumulated into the current result. This data structure is suitable for processing continuous input streams and can maintain low latency. Since the stream mode processes continuous data streams, the amount of data processed at a time is small, and the data processing logic is relatively simple, so the algorithm-level API can be used to directly call vector algorithms.

[0058] If the source data reading mode is batch mode, the method for data operation is as follows: the batch mode of the computing unit is called through the unit-level API, and multiply-accumulate is called to perform vector operations.

[0059] In batch mode, the batch mode of the computing unit is called through the algorithm-level API, which can process multiple batches of data at the same time, and multiply-accumulate (MAC) is called to perform vector multiplication and accumulation operations. The multiply-accumulate operation is performed on a batch of data at the same time, which means that a batch of data is collected first, and then batch multiplication and accumulation operations are performed on the batch of data. This method is suitable for processing large amounts of data, as it can improve efficiency through parallel processing while reducing the number of intermediate result storage and transmission. In stream mode, the structure of the multiply-accumulate tree may be needed to continuously update the multiply-accumulate result because data flows in one by one. In batch mode, a batch of data is loaded at a time, so batch multiply-accumulate operations can be directly performed on the batch of data. By calling the multiply-accumulate tree or multiply-accumulate, common vector operations such as vector addition, dot product, multiplication, summation, and mean value calculation can be implemented.

[0060] The result data module obtains result data from the computing resource and writes it to the storage resource in response to the write number control instruction.

[0061] The source data module instantiates m in the vector memory controller where m is the algorithm parallelism and is a positive integer, which means rounding up; each source data module generates 2 groups of source data channels to control the vector memory controller to simultaneously interact with the storage resource and the computing resource in the 2 groups of source data channels;

[0062] The result data module instantiates m in the vector memory controller Each result data module generates 2 groups of result data channels, and the vector memory access controller simultaneously interacts with the storage resource and the computing resource in the 2 groups of result data channels.

[0063] By creating multiple identical source data module instances and multiple identical result data module instances, parallel processing of multiple groups of data can be achieved; each source data module or result data module generates two groups of data channels, meaning that two data streams can be processed simultaneously, further improving the parallelism of data processing.

[0064] Embodiment 2

[0065] Based on the same concept as Embodiment 1, this embodiment introduces a data reading method based on stream mode in combination with a specific vector operation task.

[0066] Taking the vector operation with an algorithm parallelism of 16, a batch number of 2, and a single batch point number of 102 as an example, when the stream mode is adopted, the data stream path is as shown in Figure 2 Each row of squares represents the source data module reading source data from the storage resource once, and each square represents a source data or a data point with a value of 0; among them, the shaded squares represent the source data read from the storage resource, and the blank squares represent the data points with a value of 0 added before or after the source data based on the batch end zero signal or the batch start zero signal; the source data read for 1-7 times is the first batch, and the source data read for 8-14 times is the second batch.

[0067] Referring to Figure 2 , from the first reading of source data to the sixth reading of source data, 16 source data are read from the first batch of source data each time based on the algorithm parallelism; when the seventh source data is read, since the first batch of source data is not full 16, 6 remaining source data are read and 10 zeros are added after them based on the control of the batch end zero signal, completing the reading of the first batch of source data; when the eighth source data is read, since the last read source data is not full 16, 6 zeros are added at the beginning and in the corresponding position of the last read source data based on the control of the batch start zero signal, and 10 are read from the second batch of source data after them; from the ninth to the thirteenth reading, 16 are read from the second batch of source data; when the fourteenth reading is performed, since the second batch of source data is not full 16, 12 remaining source data are read and 4 zeros are added after them based on the control of the batch end zero signal, completing the reading of the second batch of source data, a total of 14 times to complete the reading of all data. In this scenario, if the batch mode is adopted, 102 data readings are required, and the vector operation efficiency is greatly reduced.

[0068] For the vector access scene of few devices and many points, the flow mode has the advantages of high resource utilization and fast response speed compared with the batch mode. Taking the complex vector multiplication with the algorithm parallelism of 16 and the batch point number configuration as shown in Table 1 as an example, the data processing speed of the vector access controller in the flow mode is improved by the multiple shown in Table 1 compared with the batch mode; wherein the batch number represents the number of devices (such as sensors), and the single batch point number represents the data amount of each device; the values in Table 1 are the multiples of the flow mode transfer speed compared with the batch mode transfer speed under the corresponding batch number and point number configuration, for example, when the batch number is 1 and the single point batch number is 16, the corresponding multiple is 16x, which means that the data processing speed of the flow mode is 16 times that of the batch mode in this scene.

[0069] Table 1: Multiple of flow mode data processing speed compared with batch mode

[0070]

[0071] Embodiment 3

[0072] Based on the same concept as other embodiments, this embodiment introduces a data reading method based on the batch mode in combination with a specific vector operation task.

[0073] Taking the vector access controller introduced in Embodiment 1 as the control basis, taking the vector operation with the algorithm parallelism of 16, the batch number of 28, and the single batch point number of 8 as an example, when the batch mode is adopted, the data flow path is as shown in Figure 3 Each row of squares represents reading source data from the storage resource once, and each square represents reading one source data, and the number on the square represents the batch number of the source data, that is, the number of the device from which the source data comes;

[0074] Referring to Figure 3 , the first to eighth times of reading data from the storage resource, the parallelism is 16, and 1 is read from 1-16 batch source data in turn, and after 8 rounds of reading, the reading of 1-16 batch source data is completed. When reading the source data for the ninth time, there are 12 batches of source data left, which is not enough for 16 batches, so the parallelism is adjusted to 12, and 1 is read from 17-28 batch source data respectively each time; until the 16th reading, the reading of all source data is completed. In this scene, if the flow mode is adopted, 28 times of data reading are required, which is lower in vector operation efficiency compared with the batch mode as shown in Figure 3

[0075] ​For the scene of single type signal processing of multiple devices, batch mode has the advantages of less carrying times and high data processing efficiency compared with stream mode. Taking the complex vector multiplication with the parallel degree of algorithm being 16 and the batch number and point number configuration as shown in Table 2 as an example, the data processing speed of the vector memory controller in batch mode is improved by the multiple shown in Table 2 compared with that in stream mode; wherein the batch number represents the number of devices (such as sensors), and the single batch point number represents the data volume of each device; the values in Table 2 are the multiples of the carrying speed of stream mode compared with that of batch mode under the corresponding batch number and point number configuration, for example, the multiple corresponding to the batch number of 32 and the single point batch number of 1 is 16x, which means that the data processing speed of batch mode is 16 times that of stream mode in this scene.

[0076] Table 2: Multiple of data processing speed of batch mode compared with stream mode

[0077]

[0078]

[0079] Those skilled in the art will appreciate that embodiments of the application can be provided as methods, systems, or computer program products. Accordingly, the application can be embodied in the form of an entirely hardware embodiment, an entirely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, the application can be embodied in the form of a computer program product on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROMs, optical storage media, etc.) having computer usable program code embodied therein.

[0080] Embodiment 4

[0081] Based on the same inventive concept as other embodiments, this embodiment introduces an electronic device, including a memory and a processor, the memory is used to store instructions, and the processor is used to execute the instructions, so that the computer device executes a kind of vector memory controller implementation method for realizing multi-scene multi-algorithm adaptation provided by the above embodiment.

[0082] Since the electronic device introduced in this embodiment is the electronic device used to implement the multi-scene multi-algorithm adaptation vector memory controller implementation method in the embodiments of the application, based on the multi-scene multi-algorithm adaptation vector memory controller implementation method introduced in the embodiments of the application, those skilled in the art can understand the specific implementation mode of the electronic device of this embodiment and its various forms, so the electronic device how to implement the method in the embodiments of the application is not introduced in detail. As long as the electronic device used to implement the multi-scene multi-algorithm adaptation vector memory controller implementation method in the embodiments of the application is implemented by those skilled in the art, it belongs to the scope of the application.

[0083] Embodiment 5

[0084] Based on the same inventive concept as other embodiments, the embodiment introduces a computer readable storage medium, which stores a computer program, and the computer program is executed by a processor to implement the multi-scene multi-algorithm adaptive vector memory controller implementation method provided by the above embodiment.

[0085] The embodiments of the present application are described above with reference to the drawings; however, the present application is not limited to the specific embodiments described above, and the specific embodiments described above are merely illustrative rather than restrictive, and a person of ordinary skill in the art can make many forms under the inspiration of the present application without departing from the purpose of the present application and the scope of protection, and these all belong to the protection of the present application.

Claims

1. A method for implementing a vector memory access controller for multi-scenario multi-algorithm adaptation, the method comprising: The vector memory access controller comprises a memory access state module, a memory access control module, a source data module and a result data module; the method comprises the following steps: ​ The memory access control module acquires a configuration signal of the upper computer, determines a source data reading mode, a result data writing mode and an algorithm parallel degree, and generates a memory access control signal; The source data reading mode comprises a stream mode and a batch mode; the source data reading mode is determined in the following manner: If data collected by a single sensor is collected in a data stream manner and stored horizontally in the storage resource, the source data reading mode adopts the stream mode; the horizontal storage means that the data received in each clock cycle with a length of Δt is arranged horizontally in the storage resource in time sequence; If single type data collected by multiple sensors is collected in a multi-batch data manner and stored vertically in the storage resource, the source data reading mode adopts the batch mode; the vertical storage in batches means that the data collected by different sensors is stored in a two-dimensional array in the storage resource, wherein any row of the two-dimensional array represents the same batch of data collected by different sensors, and any column represents different batches of data collected by the corresponding sensor; The memory access state module generates a reading control instruction and a writing control instruction in response to the memory access control signal; The source data module reads the source data from the storage resource in response to the reading control instruction and sends the source data to the calculation resource for data operation to obtain the result data; The result data module acquires the result data from the calculation resource and writes the result data into the storage resource in response to the writing control instruction.

2. The method of claim 1, wherein: The algorithm parallel degree represents the number of source data read from the storage resource at a time; The configuration signal is a signal sent by the upper computer to the vector memory access controller and used for configuring the behavior of the controller; The memory access control signal is used for controlling the state jump of the main state machine, the source data state machine and the result data state machine.

3. The method of claim 2, wherein: The memory access state module comprises a main state machine, a source data state machine and a result data state machine; the main state machine is used for responding to the memory access control signal, controlling the working state of the vector memory access controller, and controlling the state jump of the source data state machine and the result data state machine; the source data state machine is used for generating a reading control instruction and driving the source data module to perform the source data reading operation; the result data state machine is used for generating a writing control instruction and controlling the result data module to perform the result data writing operation.

4. The method of claim 3, wherein: If the source data reading mode is the stream mode, the method for reading the source data from the storage resource is as follows: the source data module reads m source data from the storage resource horizontally each time, m is the algorithm parallel degree; the m source data read horizontally each time are continuous m source data in the same batch, wherein any batch of source data is collected based on a same sensor; If the single batch of source data involved in the i-th time of reading source data has n remaining source data and n is less than m, i is any positive integer, the control module generates a batch end zero assignment signal, and the source data module reads the remaining n source data and adds m-n data with a value of 0 after the n source data in response to the batch end zero assignment signal, and the n source data and the m-n data are collectively transmitted to the calculation resource. If all batches of source data are not read at this time, the control module generates a batch start zero assignment signal at the start of the (i+1)th reading of source data, and the source data module reads m-n source data in the next batch of source data and adds n data with a value of 0 before the m-n source data in response to the batch start zero assignment signal, and transmits them to the computing resource together.

5. The method of claim 4, wherein: If the source data reading mode is a batch mode, the method for reading source data from the storage resource is as follows: the source data module reads m source data from the storage resource horizontally each time, and m is the algorithm parallelism; the m source data read horizontally each time are m batches of source data at the same time point, and the m batches of source data are collected based on m sensors respectively; If the number of batches of source data involved in the jth reading of source data is k, and k is less than m, and j is any positive integer, the algorithm parallelism is adjusted to k, and k source data is read horizontally and sent to the computing resource.

6. The method of claim 5, wherein: If the source data reading mode is a stream mode, the method for performing data operation is as follows: a vector algorithm is called by using an algorithm-level API, or a stream mode of a computing unit is called by using a unit-level API, and a multiply-accumulate tree is called to perform vector operation; If the source data reading mode is a batch mode, the method for performing data operation is as follows: a batch mode of a computing unit is called by using a unit-level API, and a multiply-accumulate is called to perform vector operation.

7. The method of claim 6, wherein: The source data module is instantiated in a vector memory controller where m is an algorithm parallelism degree, and is a positive integer, represents upward rounding; each source data module generates two groups of source data channels, and controls the vector memory controller to simultaneously interact with the storage resource and the computing resource in the two groups of source data channels. The result data modules are instantiated in a vector memory controller Two sets of result data channels are generated by each result data module, and the vector memory controller is controlled to interact with the storage resources and the computing resources for result data in the two sets of result data channels simultaneously.

8. An electronic device, comprising: The computer program is executed by a processor to implement a multi-scene multi-algorithm adaptive vector memory controller implementation method as claimed in any one of claims 1-7. The computer program is executed by a processor to implement a multi-scene multi-algorithm adaptive vector memory controller implementation method as claimed in any one of claims 1-7. ​ 9. A computer readable storage medium having stored thereon a computer program, characterized in that, ​

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