A data carrying method, a DMA resource controller, an SOC system and a terminal device

Abstract

The application discloses a data carrying method, a DMA resource controller, an SOC system and a terminal device, and belongs to the chip technical field, and the technical scheme points of the application are the data carrying method, which comprises the following steps: determining a data carrying mode of current data to be carried according to a data transmission type of the current data to be carried in a first memory; and carrying the current data to be carried to a second memory based on the data carrying mode, wherein one of the first memory and the second memory is a DMA module, and the data carrying mode is designed according to the data transmission type of the current data to be carried and an algorithm, so that all types of source data and result data can use the data carrying mode provided by the application to realize data transmission.

Description

TECHNICAL FIELD

[0001] The present application relates to the chip technical field, more particularly to a data carrying method, a DMA resource controller, an SOC system and a terminal device. BACKGROUND

[0002] Data transmission is essential in the whole DSP chip work, and the existing technology usually uses a DMA controller for data transmission, for example, a kind of data transmission method and ping-pong DMA architecture provided by the Chinese patent with the authorization announcement No.CN110399322A adopts two DMA modules to configure data, when the first DMA module is busy, the second DMA module can also configure data, and according to the different state types of the register, different state types corresponding data operation is executed, but the above-mentioned patent uses two DMA modules, which increases the consumption of resources,

[0003] In addition, the DMA module in the prior art usually includes multiple sets of DMA_Port, and each set of DMA_Port is suitable for different carrying modes, but the increase of the number of DMA_Port will also increase the consumption of resources, so the prior art has defects. SUMMARY

[0004] In view of the defects in the prior art, the purpose of the present application is to provide a data carrying method, a DMA resource controller, an SOC system and a terminal device, according to the type and algorithm characteristics of the current data to be carried, the present application provides multiple data carrying modes, so that all types of source data and result data can use the data carrying mode provided by the present application to realize data transmission, and the resource consumption is reduced.

[0005] To achieve the above purpose, the present application provides the following technical scheme:

[0006] The present application provides a data carrying method, comprising:

[0007] According to the data transmission type of the current data to be carried in the first memory, the data carrying mode of the current data to be carried is determined;

[0008] Based on the data carrying mode, the current data to be carried is carried to the second memory, wherein one of the first memory and the second memory is a DMA module.

[0009] As a further improvement of the present application, the data transmission type includes one-dimensional data transmission or two-dimensional data transmission, and the data carrying mode of the current data to be carried is determined according to the data transmission type of the current data to be carried in the first memory, comprising:

[0010] if the data transmission type is one-dimensional data transmission, determining the data carrying mode as a sequential carrying mode;

[0011] if the data transmission type is two-dimensional data transmission, determining the data carrying mode as one of a matrix column carrying mode or a matrix transposition carrying mode according to a data processing algorithm of the current data to be carried.

[0012] As a further improvement of the present application, the data transmission type comprises one-dimensional data transmission and two-dimensional data transmission, and correspondingly, the data processing algorithm of the current data to be carried is a fast Fourier transform algorithm, and the determining of the data carrying mode of the current data to be carried according to the data transmission type of the current data to be carried in the first memory comprises:

[0013] if the current data to be carried is small-point data, determining the data carrying mode as a sequential carrying mode;

[0014] if the current data to be carried is large-point data, determining the data carrying mode as a two-dimensional column carrying mode and a two-dimensional row carrying mode in sequence.

[0015] As a further improvement of the present application, if the data carrying mode is a sequential carrying mode, the carrying of the current data to be carried to the second memory based on the data carrying mode comprises:

[0016] reading data before a set bit in the current data to be carried as a data unit to be carried;

[0017] writing the data unit to be carried into a storage circular queue;

[0018] updating the current data to be carried as data after the removal of the data unit to be carried, repeating the step of reading data before a set bit in the current data to be carried to obtain a data unit to be carried again, and writing the data unit to be carried into the storage circular queue, until the current data to be carried is completely written into the second memory.

[0019] As a further improvement of the present application, if the data carrying mode is a matrix column carrying mode, the current data to be carried is a two-dimensional data matrix, and the carrying of the current data to be carried to the second memory based on the data carrying mode comprises:

[0020] reading a first row of data in the two-dimensional data matrix which has not been read;

[0021] writing the currently read row data into a storage queue in sequence according to column order;

[0022] The two-dimensional data matrix is updated to a matrix after the two-dimensional data matrix removes the row data, the step of reading the first row of data in the two-dimensional data matrix which is not read currently is repeated, and the currently read row data is sequentially written into the storage queue in column order until all the data to be transported is written into the second memory.

[0023] As a further improvement of the application, if the data transport mode is matrix transposition transport, the current data to be transported is a two-dimensional data matrix, and the transporting the current data to be transported to the second memory based on the data transport mode comprises:

[0024] The current data to be transported is divided into a plurality of matrix units according to a preset number of rows, with the first row as the starting row, wherein the number of rows of the last matrix unit is less than or equal to the preset number of rows, and the number of rows of the remaining matrix units is equal to the preset number of rows.

[0025] For the matrix unit with the number of rows equal to the preset number of rows, column transport is performed.

[0026] For the matrix unit with the number of rows less than the preset number of rows, the data length transported by each transport shot is reduced, the data length of each write shot of the second memory is configured synchronously, and a corresponding tag register is created for the data transported by each transport shot; wherein if the transport data corresponding to each transport shot is valid through mask judgment, the number of the corresponding tag register is updated.

[0027] As a further improvement of the application, the column transport for the matrix unit with the number of rows equal to the preset number of rows comprises:

[0028] If the total number of rows of the current data to be transported is odd, the data at the end of the odd column data and the data at the first data bit of the opposite next even column data in each adjacent two column data are written into the second memory in the same write shot.

[0029] As a further improvement of the application, if the data transport mode is a sequential transport mode, the transporting the current data to be transported to the second memory based on the data transport mode comprises:

[0030] The current data to be transported is sequentially transported to the second memory based on the same index-address conversion rule as the butterfly memory controller.

[0031] As a further improvement of the application, the data transport mode is a two-dimensional column transport mode and a two-dimensional row transport mode in sequence, and the transporting the current data to be transported to the second memory based on the data transport mode comprises:

[0032] The current data to be carried is carried according to the two-dimensional column carrying mode, and after a Fourier transform operation, intermediate result data of fast Fourier transform is obtained.

[0033] The intermediate result data of fast Fourier transform is carried to the second memory according to the two-dimensional row carrying mode.

[0034] As a further improvement of the present application, the carrying of the current data to be carried to the second memory based on the data carrying mode further comprises:

[0035] If the data length of the current data to be carried is not an integer power of 2, the current data to be carried is zero-padded to the nearest integer power of 2.

[0036] The present application provides a DMA resource controller applied to the above-mentioned data carrying method, comprising:

[0037] The DMA module comprises a state register;

[0038] The logic control module is used for controlling the state machine to jump, and the state machine is composed of the state register and a combination logic circuit;

[0039] The data configuration module is used for configuring the DMA module;

[0040] The DMA_Port is used for carrying out data transmission between the first memory and the second memory.

[0041] As a further improvement of the present application, the DMA module comprises:

[0042] The DMA register unit is used for maintaining DMA registers, and the DMA registers comprise control registers, configuration registers and the state register;

[0043] The DMA read-write control unit is used for controlling signals of a read address channel, a read data channel, a write data channel, a write address channel and a write response channel of AXI4;

[0044] The DMA cache unit is used for caching data read into the DMA module and processed;

[0045] The DMA matrix control unit is used for generating relevant read-write information of two-dimensional transmission and matrix transposition transmission, and sending the relevant read-write information to the DMA read-write control module.

[0046] The present application provides a SOC system comprising the above-mentioned DMA resource controller.

[0047] The present application provides a terminal device comprising the above-mentioned SOC system.

[0048] The present application proposes multiple data transfer modes according to the type of current data to be transferred and the algorithm characteristics, and realizes the above transfer modes through a set of DMA_Port, so that the source data and result data of all algorithms only need to select the above transfer modes to realize data transmission, avoiding the drawbacks of using multiple sets of DMA_Port logic for similar algorithm transmission modes, and reducing resource consumption. BRIEF DESCRIPTION OF DRAWINGS

[0049] Figure 1 Figure 1 is a schematic diagram of the matrix column transfer mode;

[0050] Figure 2 Figure 2 is a schematic diagram of the matrix transpose transfer mode;

[0051] Figure 3 Figure 3 is a schematic diagram of the 16 BANK sequential transfer (horizontal) mode;

[0052] Figure 4 Figure 4 is a schematic diagram of the 32 BANK sequential transfer (horizontal) mode;

[0053] Figure 5 Figure 5 is a schematic diagram of the 16 BANK sequential transfer (horizontal) mode;

[0054] Figure 6 Figure 6 is a schematic diagram of the 32 BANK sequential transfer (horizontal) mode;

[0055] Figure 7 Figure 7 is a schematic diagram of the FFT small point sequential transfer mode;

[0056] Figure 8 Figure 8 is a schematic diagram of the FFT large point sequential transfer column transfer data selection rule;

[0057] Figure 9 Figure 9 is a schematic diagram of the FFT large point sequential transfer row transfer data selection rule;

[0058] Figure 10 Figure 10 is a design block diagram of the DMA resource controller;

[0059] Figure 11 Figure 11 is an architecture diagram of the DMA module;

[0060] Figure 12 Figure 12 is a work flow diagram of the DMA resource controller;

[0061] Figure 13 Figure 13 is a state transition diagram of the master state machine in the DMA resource controller;

[0062] Figure 14 Figure 14 is a state transition diagram of the slave state machine in the DMA resource controller. DETAILED DESCRIPTION

[0063] The technical solutions of the present application will be described in detail below with reference to the accompanying drawings and specific embodiments. It should be understood that the embodiments and specific features in the embodiments are detailed descriptions of the technical solutions of the present application, but not limitations of the technical solutions of the present application.

[0064] The term "and / or" in the following is only a description of the association relationship of the associated objects, which means that there can be three relationships, for example, A and / or B can represent the following three cases: A exists alone, A and B exist together, and B exists alone. In addition, the character " / " generally represents that the associated objects before and after it are in an "or" relationship.

[0065] The embodiment of the present application provides a data carrying method, comprising:

[0066] According to the data transmission type of the current data to be carried in the first memory, the data carrying mode of the current data to be carried is determined;

[0067] Based on the data carrying mode, the current data to be carried is carried to the second memory, wherein one of the first memory and the second memory is a DMA module.

[0068] Specifically, when the data carrying mode is the carrying-in mode, the first memory is the DMA module, and the second memory is the SRAM (static random access memory); when the data carrying mode is the carrying-out mode, the first memory is the SRAM, and the second memory is the DMA module.

[0069] The data carrying method provided by the embodiment can accurately determine the data carrying mode according to the data transmission type of the current data to be carried, and improve the data transmission efficiency.

[0070] Further, the data transmission type includes one-dimensional data transmission or two-dimensional data transmission,

[0071] If the data transmission type is one-dimensional data transmission, the data carrying mode is determined as a sequential carrying mode;

[0072] If the data transmission type is two-dimensional data transmission, according to the data processing algorithm of the current data to be carried, the data carrying mode is determined as one of matrix column carrying or matrix transposition carrying.

[0073] Further, if the data carrying mode is the sequential carrying mode, the step of carrying the current data to be carried to the second memory based on the data carrying mode comprises:

[0074] Reading the data before the set bit in the current data to be carried as a data unit to be carried;

[0075] write the data unit to be carried into the storage circular queue;

[0076] update the current data to be carried as the data after removing the data unit to be carried, repeat the step of reading the data before the set bit in the current data to be carried, re-obtain the data unit to be carried, and write the data unit to be carried into the storage circular queue, until the current data to be carried is completely written into the second memory.

[0077] Further, if the data carrying mode is matrix column carrying, the current data to be carried is a two-dimensional data matrix, and the step of carrying the current data to be carried into the second memory based on the data carrying mode comprises:

[0078] reading the first row of data in the two-dimensional data matrix which has not been read;

[0079] writing the currently read row data into the storage queue in column order;

[0080] updating the two-dimensional data matrix as the matrix after removing the row data from the two-dimensional data matrix, repeating the step of reading the first row of data in the two-dimensional data matrix which has not been read, and writing the currently read row data into the storage queue in column order, until the data to be carried is completely written into the second memory.

[0081] The set bit is preferably 256 bits, and the storage circular queue is a continuous queue, which can maximize the use of storage space. For example, when the total number of BANKs is 16, data needs to be stored in each BANK in the order of BANK0-BANK16. Only after storing data in BANK16, can the data be stored in BANK0 in order. Unlike this, the storage queue does not need to store data in each BANK. For example, when the total number of BANKs is 16, after the currently read row data is written into the storage queue in column order, all BANKs cannot be filled, and some BANKs are still idle. However, when the next writing step is performed, data needs to be stored in BANK0 in order, and does not need to be stored in the idle BANKs in the last step.

[0082] Further, if the data carrying mode is matrix transpose carrying, the current data to be carried is a two-dimensional data matrix, and the step of carrying the current data to be carried into the second memory based on the data carrying mode comprises:

[0083] dividing the current data to be carried into a plurality of matrix units according to a preset row number, taking the first row as the starting row, wherein the row number of the last matrix unit is less than or equal to the preset row number, and the row number of the remaining matrix units is equal to the preset row number;

[0084] performing column carrying on the matrix unit with the row number equal to the preset row number;

[0085] For the matrix unit with the number of rows less than the preset number of rows, the data length carried by each carrying clock is reduced, the data length of each write clock of the second memory is configured synchronously, and a corresponding tag register is created for the data carried by each carrying clock; wherein, if the carrying data corresponding to each carrying clock is valid through the mask judgment, the number of the corresponding tag register is updated.

[0086] For example, when the two-dimensional data matrix is 255 rows, the preset number of rows is 128 rows, the first matrix unit is 128 rows, and the second matrix unit is 127 rows. When carrying the first matrix unit, the data length carried by each carrying clock is 4*64bit. When carrying the second matrix unit, the data length carried by each carrying clock is reduced to 1*64bit because the number of rows of the second matrix unit is less than the preset number of rows. The carrying data corresponding to each carrying clock needs to be judged for validity through the mask. If it is valid, the value of the tag corresponding to the register number is incremented by one, that is, the data carried by the next carrying clock is stored in the next register. For example, if the current carrying clock data is valid and stored in register a, the tag value of register a is 1, and the next carrying clock data is valid and stored in register b, the tag value of register b is 2.

[0087] Further, for the matrix unit with the number of rows equal to the preset number of rows, column carrying is performed, including:

[0088] If the total number of rows of the current data to be carried is odd, for each adjacent two column data, the data at the end of the odd column data and the data at the first data bit of the opposite next even column data are written into the second memory in the same write clock.

[0089] Wherein, the carrying clock is for the first memory, that is, the data is carried out of the first memory; the write clock is for the second memory, that is, the data carried out of the first memory is carried into the second memory.

[0090] Further, the data transmission type includes one-dimensional data transmission and two-dimensional data transmission, and the corresponding data processing algorithm of the current data to be carried is the fast Fourier transform algorithm. According to the data transmission type of the current data to be carried in the first memory, the data carrying mode of the current data to be carried is determined, including:

[0091] If the current data to be carried is small dot data, the data carrying mode is determined to be the sequential carrying mode.

[0092] If the current data to be carried is large dot data, the data carrying mode is determined to be the two-dimensional column carrying mode and the two-dimensional row carrying mode in sequence.

[0093] Further, if the data carrying mode is the sequential carrying mode, carrying the current data to be carried to the second memory based on the data carrying mode comprises:

[0094] sequentially carrying the current data to be carried to the second memory based on the same index-address conversion rule as the butterfly memory access controller.

[0095] and if the data length of the current data to be carried is not an integer power of 2, zero-padded the current data to be carried to the nearest integer power of 2 data length, and then carried.

[0096] Further, if the data carrying mode is the two-dimensional column carrying mode and the two-dimensional row carrying mode in sequence, carrying the current data to be carried to the second memory based on the data carrying mode comprises:

[0097] carrying the current data to be carried according to the two-dimensional column carrying mode, and obtaining the intermediate result data of the fast Fourier transform after the Fourier transform operation;

[0098] carrying the intermediate result data of the fast Fourier transform to the second memory according to the two-dimensional row carrying mode.

[0099] From the above analysis, it can be seen that the embodiment designs multiple data carrying modes according to the type and processing algorithm of the current data to be carried. The carrying modes are introduced in sequence as follows.

[0100] Fine granularity carrying mode:

[0101] The fine granularity carrying mode includes the matrix column carrying mode, the matrix transpose carrying mode, the sequential carrying mode and the sequential carrying mode.

[0102] Matrix column carrying mode:

[0103] The matrix column carrying mode is used for source data carrying of matrix and related algorithms. This mode supports source data writing with total bank number 16 and ping-pong splitting, as shown in Figure 1 When the DMA module reads the source data in two dimensions, it reads and writes 256 bits each time, and each 256-bit data is split into 4 64-bit data. Every two data is written into a bank of 128 bits, i.e. bank 16 stores the first and second column data of the first row, bank 17 stores the third and fourth column data, and so on. Bank 23 stores the 15th and 16th column data. The first and second column data of the second row are stored in bank 16 in sequence, and so on. If the number of columns S is less than 16, the first and second column data of the second row are still stored in bank 16, instead of being stored continuously after the Sth data of the first row.

[0104] Matrix transpose carrying mode:

[0105] Matrix transpose transfer mode, for when the matrix multiplication matrix data column number is less than 16, due to the small column number, the parallelism is low, in order to improve the parallelism, the matrix multiplication is realized by using vector multiplication, in the process of realization, the data taken out needs to be placed in the SRAM by column, at this time the SRAM is the second memory, therefore the DMA module uses the transpose transfer. As shown in the figure, when transferring a small matrix of 128 rows, the DMA module transfers the small matrix by column, 256bit data (i.e. 4 64bit complex numbers) are transferred each time, four registers are set to store the labels of the storage positions of the four data, wherein the lower 16 bits correspond to the BANK where the data should be stored, and the remaining bits correspond to the address where the data should be stored, and the data is written into the SRAM by changing the label. In this transfer process, the following cases are subdivided: Figure 2

[0106] (1) When transferring a small matrix of 128 rows, the DMA module transfers the small matrix by column, 256bit data (i.e. 4 64bit complex numbers) are transferred each time, four registers are set to store the labels of the storage positions of the four data, wherein the lower 16 bits correspond to the BANK where the data should be stored, and the remaining bits correspond to the address where the data should be stored, and the data is written into the SRAM by changing the label. In this transfer process, the following cases are subdivided:

[0107] I: the total number of rows is odd:

[0108] In order to improve the speed, the DMA module transfers 4 64bit data per beat, and at the same time the transpose port writes 4 64bit data into the SRAM per beat. Since two of the data sent in per beat need to be written into the same BANK, the 128bit write mode of the BANK is used. However, when the number of rows is odd, there will be the first column last row data of the last transfer and the second column first row data of the first transfer, which should be written into the same BANK together in the 128bit write mode. Similarly, the second column 128th row data of the first transfer and the second column 129th row data of the second transfer should also be written together. Therefore, when the total number of rows is odd, it is further subdivided into two cases:

[0109] a: when the DMA transfers odd column data, there is no non-same transfer to be written into the BANK together, and the 128bit data of two BANKs are written per beat.

[0110] b: when the DMA module transfers even column data, there is non-same transfer to be written into the BANK together. Eight 64bit registers are set to store the eight data of the last row of even column of the last transfer, and the data is selected according to the column number counter and spliced into the data of the current transfer (0 is spliced in the first transfer), and the 128bit data of three BANKs are written per beat. ​

[0111] II: The total number of rows is even.

[0112] In the absence of the special case of an odd number, 128 bits of data are normally written to both banks in one clock cycle.

[0113] (2) When moving the last small matrix with fewer than 128 rows, due to the possibility of the DMA module sending invalid data (identified by a mask), a method of writing one 64-bit data per clock cycle is used. The ACK signal to the DMA module is controlled to ensure that the DMA module sends one 256-bit data every four clock cycles, while the SRAM write mode is switched to 64-bit write. Four 64-bit data are processed in each of the four clock cycles. If the corresponding 64-bit data is valid according to the mask, the set tag write enable is pulled high, and the tag is incremented by 1. If the data is deemed invalid, the tag remains unchanged. The BANK and address to be written to for that clock cycle are selected based on the tag.

[0114] Sequential transport mode:

[0115] Sequential transport modes include sequential inbound mode and sequential outbound mode. Sequential inbound mode includes 16BANK inbound mode and 32BANK inbound mode, and sequential outbound mode includes 16BANK outbound mode and 32BANK outbound mode.

[0116] 16BANK import mode:

[0117] The 16BANK import mode is used for importing source data that requires matrix, vector, sorting, or related algorithms. It supports writing source data or coefficients with a total of 16 banks and ping-pong splitting. For example... Figure 3 As shown, when reading source data or coefficients sequentially, 256 bits are read and written each time. If the data read is a complex number, each 256-bit data is split into four 64-bit data. If the data read is a real number, each 256-bit data is split into eight 32-bit data. The split data is stored in each Bank in turn. Bank0 stores the first and second data, Bank1 stores the third and fourth data, and after a ping area has eight Banks storing 16 data, the 17th data is stored below the second data in Bank0, and so on.

[0118] 32BANK import mode:

[0119] The 32BANK import mode is used for importing source data that requires FIR, correlation, or other related algorithms. It supports writing source data with a total of 32 banks and ping-pong splitting. For example... Figure 4As shown, when sequentially reading the source data, each time 256 bits are read and written, if the read-in data is complex, each 256-bit data is split into 4 64-bit data; if the read-in data is real, each 256-bit data is split into 8 32-bit data; the split data is sequentially stored in each Bank, Bank 0 stores the 1st and 2nd data, Bank 1 stores the 3rd and 4th data, and after 16 Banks in a ping-pong area store 32 data, the 33rd data is continuously stored below the 2nd data in Bank 0, and so on.

[0120] 16 BANK move-out mode:

[0121] The 16 BANK move-out mode is used for moving out result data of related algorithms such as matrix, vector, FIR, correlation, sorting, etc., and supports moving out result data of a total of 16 Banks and ping-pong splitting. As shown in Figure 5 As shown, the result data is stored horizontally in the Banks, i.e., 0-7 result data is serially stored in the 0 address of 8 Banks, and 8-15 result data is serially stored in the 1 address of 8 Banks.

[0122] 32 BANK move-out mode:

[0123] The 32 BANK move-out mode is used for moving out result data of related algorithms such as matrix, Doppler, etc., and supports moving out result data of a total of 32 Banks and ping-pong splitting. As shown in Figure 6 As shown, the result area is stored horizontally in the Banks, i.e., 0-15 result data is serially stored in the 0 address of 16 Banks, and 16-31 result data is serially stored in the 1 address of 16 Banks.

[0124] Coarse-grained move mode:

[0125] The coarse-grained move mode includes FFT move-in mode and FFT move-out mode, the FFT move-in mode includes FFT small-point sequential move-in mode and FFT large-point two-dimensional move-in mode, and the FFT large-point two-dimensional move-in mode includes row move and column move.

[0126] FFT small-point sequential move-in mode:

[0127] In the FFT small-point sequential move-in case, as shown in Figure 7As shown, the source data is sequentially stored in DDR (Double Data Rate SDRAM, double rate synchronous dynamic random access memory), and the AXI bus is 256 bits when the DMA module reads the source data, and the DMA_Port writes 256 bits of data in 1 clock cycle into 4 BANKs. The source data ping area is BANK0-BANK31, the DMA_Port receives 256 bits of data sequentially transmitted from the DMA module, and the input source data of non-2 integer power is zero-padded to 2 integer power, and if it is a multi-batch data, it is zero-padded to the nearest 2 integer power after all source data is transmitted. After zero padding, the DMA_Port transmits 256 bits of data, i.e. 4 source data per clock cycle, and the transmission address rule to the SRAM space is the same as the index-address conversion rule of the butterfly memory controller. The source data pong area is BANK32-BANK63, the DMA_Port receives the ping-pong signal transmitted from the DMA module, and selects the data transmission to jump to the source data pong area according to the ping-pong signal, and the data transmission mode is the same as that of the source data pong area

[0128] FFT large point two-dimensional moving-in mode:

[0129] In the FFT large point two-dimensional moving-in, the SRAM cannot buffer all the data at once, and must use a two-dimensional FFT algorithm, at which time the transmission mode of the DMA module is two-dimensional transmission, and the working state of the DMA_Port is similar to simultaneously moving multiple small point FFT data, and the DMA module performs column moving and row moving of two-dimensional FFT in sequence.

[0130] As shown in Figure 8 Taking 512k points as an example, in the column moving stage, the 512k points of data are abstractly divided into a two-dimensional matrix with 4k rows and 128 columns, and since the maximum storage capacity of the ping area is 128k, the large matrix will be divided into 4 small matrices every 32 columns; when moving the row, since the abstract matrix arrangement order is the same as the actual DDR address, the DMA module only needs to perform sequential transmission. When performing column moving, the DMA module will start the two-dimensional transmission mode, and move in turn according to the rows and columns of the divided small matrix, such as when transmitting the first 4k*32 matrix, first sequentially transmit the source data of addresses 0-31, then jump to the 128th address to transmit the second row of the small matrix, and when the first small matrix transmission is completed, send a ping-pong signal to the butterfly DMA_Port, then jump to address 32 to start the transmission of the second small matrix, and repeat 4 times until all 512k source data is transmitted.

[0131] And in the column transfer stage, the DMA_Port transfers 128K data each time, repeats 4 times, and stores it as 128 4k length input sequences in the SRAM; in the row transfer stage, it also transfers 128K data each time, repeats 4 times, but stores it as 4k 128 length input sequences in the SRAM.

[0132] FFT small dot sequential transfer out mode:

[0133] In the FFT small dot sequential transfer out, the result data is stored in the SRAM, the DMA_Port first generates the index of the reverse order, and then takes data from the corresponding SRAM address according to the index-address conversion rule, the DMA_Port takes 4 64bit result data each clock cycle, and combines every 4 data taken as 256bit output.

[0134] FFT large dot sequential transfer out mode:

[0135] In the FFT large dot two-dimensional transfer out, for two-dimensional FFT operation, the transfer out of the DMA_Port includes the transmission of the column transform result and the transmission of the row transform result (final result).

[0136] When processing the result of the column transform, the DMA_Port sorts the data in the ping / pong area by batch, then generates the index of the reverse order, and transfers out according to the index-address conversion rule, and repeats multiple times according to the large dot number, and the DMA module receives the data and returns the DDR using sequential transmission.

[0137] When processing the row transform result (final result), the DMA_Port first sorts the data in the ping / pong area by batch, then generates the index of the reverse order after transposition, and transfers out according to the index-address conversion rule, and repeats multiple times according to the large dot number, and the DMA module receives the data and returns the DDR using sequential transmission.

[0138] The embodiment combines algorithms with similar memory access methods at a fine granularity into four modes, and can realize the data transfer function of the protocol required fine-grained algorithm by combining and configuring the four modes. And due to the uniqueness of the in-place memory access of the FFT algorithm, it needs two transmission modes of sequential transmission and two-dimensional transmission, and both the source data and the result data must be accessed in place, which cannot be shared with other algorithms, so the FFT transfer in mode and the FFT sequential transfer out mode are designed at a coarse granularity. The source data and the result data of all algorithms only need to use the above modes to realize data transmission, which maximizes the saving of resource consumption.

[0139] As shown in Figure 10 The embodiment of the application further provides a DMA resource controller applied to the above data transfer method, which comprises:

[0140] a DMA module, the DMA module comprising a state register;

[0141] a logic control module for controlling state machine jump, the state machine being composed of the state register and a combinational logic circuit;

[0142] a data configuration module for configuring the DMA module;

[0143] a DMA_Port for performing data transmission between the first memory and the second memory.

[0144] In the three-dimensional reconfigurable acceleration core architecture, one of the first memory and the second memory is a DMA module, and the other is an SRAM.

[0145] The DMA_Port supports all the above data transfer modes when performing data transmission, avoiding the disadvantages of using multiple sets of DMA_Port logic for similar algorithm transmission modes.

[0146] Specifically, as shown in the figure, Figure 11 the DMA module further comprises:

[0147] a DMA register unit for maintaining DMA registers, the DMA registers comprising control registers, configuration registers and state registers;

[0148] a DMA read-write control unit comprising a DMA read control unit and a DMA write control unit, wherein the DMA read control unit is responsible for controlling the signals of the AXI4 read address channel and the read data channel, the DMA read control unit comprising a read control main module, a read address generation module and a data input module, the main module playing a main control role, the read address generation module being responsible for generating relevant addresses of the write internal buffer, and the data input module being responsible for address alignment, data splicing and splitting of the input data, the DMA write control unit having similar functions and structure to the DMA read control module, except that it corresponds to the AXI4 write data channel, write address channel and write response channel;

[0149] a DMA cache unit comprising 8 groups of 4kB SRAMs for caching the data read into the DMA module and processed, and reading out the data by the write control module.

[0150] a DMA matrix control unit for generating relevant read-write information of two-dimensional transmission and matrix transposition transmission, and sending the relevant read-write information to the DMA read-write control module.

[0151] Further, the DMA module provided by the embodiment is dedicated to a three-dimensional reconfigurable acceleration core architecture, supports AXI4 protocol, is mounted on an AXI bus as the only host in the core, and only interacts with the only slave DDR for data transmission between the DDR and the SRAM. Therefore, the DMA module only needs one channel, and all cross-clock domains are completed by a SOC (System on Chip), so that cross-clock domain processing is not needed. According to the transmission performance requirement of the three-dimensional reconfigurable acceleration core, the DMA module only needs to support burst transmission mode, and since the data bit width is 256 bits, the maximum burst length is 128. Since the loopback delay is large, the DMA module supports a maximum of 16 unfinished operations according to the internal cache size.

[0152] The three-dimensional reconfigurable acceleration core architecture adopts a static instruction flow control data flow mechanism to schedule internal operations (instruction level), and a reconfigurable architecture based on an SSD (static scheduling, static data flow) model that depends on a CPU to realize different configurations (thread level).

[0153] The DMA module provided by the embodiment adds a DMA matrix control unit, supports chain transmission, two-dimensional transmission, and transpose transmission in addition to sequential transmission, and improves the transmission and processing efficiency of matrix data.

[0154] Further, the data carrying step of the DMA resource manager provided by the embodiment is as shown in Figure 12 The configuration information is first input into the DMA resource manager, and then the logical control module judges the data area and executes the corresponding carrying step according to the judgment result.

[0155] Specifically, if the judgment result is source data, the single-time configuration of the DMA module is obtained by the data configuration module, the configuration of the DMA module is written into the register group in the DMA module through the APB bus, the DMA module is started, data is then taken from the DDR by the DMA module and transmitted to the DMA_Port, the data is placed in the SRAM by the DMA_Port, the single-time carrying of the source data is completed, and then it is judged whether the data needs to be carried again. If the data needs to be carried again, the logical control module continues to judge the data area; if the data does not need to be carried again, the carrying is stopped.

[0156] If the result is result data, the data configuration module obtains the configuration of the single-time DMA module, writes the configuration of the DMA module into the register group in the DMA module through the APB bus, starts the DMA module, and then issues a data fetching request to the DMA_Port by the DMA module, moves the data back to the DDR, and fetches the data from the SRAM by the DMA_Port to supply the DMA module, to complete the single-time movement of the result data, and then determines whether the data needs to be moved again. If the data needs to be moved again, the logic control module continues to determine the data area, and if the data does not need to be moved, the movement is stopped.

[0157] The configuration mode of the DMA module includes a master mode and a slave mode. In the slave mode, the DMA resource manager obtains the configuration information by polling the related information in the configuration register. In the master mode, the DMA resource controller moves the configuration information in the DDR to the configuration register as the configuration information for subsequent use, and calculates the single-time configuration of the DMA according to the start address and the data length and other related information in the configuration information.

[0158] Further, when the DMA resource controller performs different working steps, the state machine of the DMA resource controller enters different states. The state machine includes a master state machine and a slave state machine.

[0159] As shown in Figure 13 , the states of the master state machine can be divided into:

[0160] Idle state (DMA_IDLE): The master state machine is initially in the idle state. When the master state machine is started, the state machine enters the configuration information movement preparation state (DMA_MASTER_READY).

[0161] DMA_MASTER_READY: The DMA resource controller determines the master-slave mode. If it is the master mode, the master state machine starts the configuration information movement and enters the configuration information movement state (DMA_MASTER). If it is the slave mode, the master state machine enters the preparation state (DMA_READY).

[0162] DMA_MASTER: When the single-time configuration information movement is completed, the master state machine enters the configuration information movement completion state (DMA_MASTER_FINISH).

[0163] DMA_MASTER_FINISH: If the configuration information still needs to be moved, the master state machine enters the configuration information movement preparation state (DMA_MASTER_READY). If the configuration information does not need to be moved, the master state machine enters the preparation state (DMA_READY).

[0164] DMA_READY: The main state machine enters the first source data (SRC1) transfer preparation state (DMA_SRC1 READY) when it is ready to start the DMA module for transferring the source data.

[0165] DMA_SRC1 READY: The DMA resource controller determines whether SRC1 needs to be transferred at present. When SRC1 needs to be transferred, the main state machine enters the SRC1 transfer state (DMA_SRC1); when SRC1 does not need to be transferred, the main state machine enters the second source data (SRC2) transfer preparation state (DMA_SRC2 READY).

[0166] DMA_SRC1: When the single-time transmission of SRC1 is completed, the main state machine enters the SRC1 transfer completion state (DMA_SRC1_FINISH).

[0167] DMA_SRC1_FINISH: The main state machine enters the SRC2 transfer preparation state (DMA_SRC2 READY).

[0168] DMA_SRC2 READY: The DMA resource controller determines whether SRC2 needs to be transferred at present. When SRC2 needs to be transferred, the main state machine enters the SRC2 transfer state (DMA_SRC2); when SRC2 does not need to be transferred, the main state machine enters the result data (RES) transfer preparation state (DMA_RES READY).

[0169] DMA_SRC2: When the single-time transmission of SRC2 is completed, the main state machine enters the SRC2 transfer completion state (DMA_SRC2_FINISH).

[0170] DMA_SRC2_FINISH: The main state machine enters the RES transfer preparation state (DMA_RES READY).

[0171] DMA_RES READY: The DMA resource controller determines whether RES needs to be transferred at present. When the current ping-pong RES needs to be transferred and RES transfer is not skipped, the main state machine enters the RES transfer state (DMA_TRANS_RES); when the algorithm type RES does not need to be transferred, the main state machine enters the RES transfer completion state (DMA_RES_FINISH); when RES transfer needs to be skipped, the main state machine enters the SRC1 transfer preparation state (DMA_SRC1 READY).

[0172] DMA_TRANS_RES: When the single-time transmission of RES is completed, the main state machine enters the RES transfer completion state (DMA_RES_FINISH).

[0173] DMA_RES_FINISH: If the current mode is slave mode and the slave mode ends, the master state machine enters the idle state (DMA_IDLE); if the master mode or the slave mode has not ended and the next ping is needed, the master state machine enters the carrying SRC1 preparation state (DMA_SRC1_READY); if the current mode is master mode and the master mode is completed in a single time and the next carrying is needed, the master state machine enters the idle state (DMA_IDLE) and waits for the next start of the state machine.

[0174] When the above-mentioned master state machine enters any carrying state of DMA_MASTER, DMA_SRC1, DMA_SRC2, and DMA_RES, the slave state machine, also referred to as the data carrying state machine, is triggered, as shown in the following table. Figure 14 The data carrying state machine is described below by taking the state DMA_MASTER as an example.

[0175] DMA_TRANS_IDLE: The data carrying state machine is initially in the idle state, and when the configuration data in the configuration register is configured, the data carrying state machine enters the configuration calculation state (DMA_CONFIG_CAL).

[0176] DMA_CONFIG_CAL: The data carrying state machine is in the configuration calculation state, which is used for calculating the single-time DMA configuration. When the configuration calculation is completed, the data carrying state machine enters the configuration state (DMA_CONFIG).

[0177] DMA_CONFIG: In this state, the DMA controller configures the single-time DMA transmission of the DMA through the APB bus. After the configuration is completed, the data carrying state machine enters the DMA transmission state (DMA_TRANSING).

[0178] DMA_TRANSING: In this state, the DMA performs the single-time configuration carrying work. After the single-time configuration transmission is completed, the data carrying state machine enters the transmission completion state (DMA_TRANS_FINISH).

[0179] DMA_TRANS_FINISH: The data carrying state machine is in the single-time transmission completion state. After that, the data carrying state machine returns to the idle state (DMA_TRANS_IDLE) and waits for the next start.

[0180] As can be known from the above description, the DMA resource controller provided in the embodiment supports the configuration of the DMA module in the master-slave two modes, and the state machine in the DMA resource controller can jump to the matching carrying state according to the carrying requirements of different algorithms, thereby improving the carrying efficiency.

[0181] Further, the embodiment of the present application provides a SOC system, which comprises the above-mentioned DMA resource controller.

[0182] Further, the embodiment of the present application provides a terminal device comprising the SOC system.

[0183] The data carrying method, the DMA resource controller, the SOC system and the terminal device provided by the embodiment of the present application adopt the design of four fine-grained carrying modes and two coarse-grained carrying modes for the FFT algorithm after the induction of the DMA_Port of each algorithm, save resource overhead, improve resource utilization, support the configuration of the DMA module in the master-slave mode, and match the jump of the state machine carrying state according to the carrying requirement of different algorithms.

[0184] Those skilled in the art should understand that the embodiments of the present application can be provided as a method, a system or a computer program product. Therefore, the present application can adopt a complete hardware embodiment, a complete software embodiment or an embodiment combining software and hardware aspects. Moreover, the present application can adopt the form of a computer program product implemented on one or more computer usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer usable program codes.

[0185] The present application is described with reference to flowcharts and / or block diagrams of the method, device (system) and computer program product according to the embodiments of the present application. It should be understood that each flow and / or block in the flowcharts and / or block diagrams, and the combination of the flows and / or blocks in the flowcharts and / or block diagrams can be realized by computer program instructions. These computer program instructions can be provided to the processor of a general-purpose computer, a special-purpose computer, an embedded processor or other programmable data processing device to produce a machine, so that the instructions executed by the processor of the computer or other programmable data processing device produce a device for implementing the functions specified in the flowcharts and / or block diagrams. Figure 1 one or more flows and / or blocks Figure 1 an apparatus for performing the functions specified in one or more flows and / or blocks.

[0186] These computer program instructions can also be stored in a computer readable memory capable of guiding the computer or other programmable data processing device to work in a specific way, so that the instructions stored in the computer readable memory produce a product including instruction apparatus, which implements the functions specified in the flowcharts and / or block diagrams. Figure 1 one or more flows and / or blocks Figure 1 an apparatus for performing the functions specified in one or more flows and / or blocks.

[0187] These computer program instructions can also be loaded into the computer or other programmable data processing device, so that a series of operation steps are performed on the computer or other programmable device to produce a computer implemented process, so that the instructions executed on the computer or other programmable device provide a process for implementing the functions specified in the flowcharts and / or block diagrams. Figure 1one or more processes and / or blocks Figure 1 the steps of the functions specified in one or more blocks.

[0188] The above merely is the preferred embodiment of the present application, the protection scope of the present application is not limited to the above-mentioned embodiments, all the technical solutions falling into the idea of the present application belong to the protection scope of the present application. It should be pointed out that, for the ordinary skilled in the art, some improvements and refinements without departing from the principles of the present application, these improvements and refinements should also be considered as the protection scope of the present application.

Claims

1. A data movement method, characterized by, The method comprises the following steps: determining a data transfer mode of the current data to be transferred in the first memory according to a data transfer type of the current data to be transferred in the first memory; transferring the current data to be transferred to the second memory based on the data transfer mode, wherein one of the first memory and the second memory is a DMA module; wherein the data transfer type comprises one-dimensional data transfer or two-dimensional data transfer, and the determination of the data transfer mode of the current data to be transferred according to the data transfer type of the current data to be transferred in the first memory comprises: if the data transfer type is one-dimensional data transfer, determining that the data transfer mode is a sequential transfer mode; if the data transfer type is two-dimensional data transfer, determining that the data transfer mode is one of matrix column transfer or matrix transpose transfer according to a data processing algorithm of the current data to be transferred; wherein the data transfer type comprises one-dimensional data transfer and two-dimensional data transfer, and the data processing algorithm of the current data to be transferred corresponds to a fast Fourier transform algorithm, and the determination of the data transfer mode of the current data to be transferred according to the data transfer type of the current data to be transferred in the first memory comprises: if the current data to be transferred is small point data, determining that the data transfer mode is a sequential transfer mode; if the current data to be transferred is large point data, determining that the data transfer mode is a two-dimensional column transfer mode and a two-dimensional row transfer mode in sequence; wherein the data transfer mode is a two-dimensional column transfer mode and a two-dimensional row transfer mode in sequence, and the transferring of the current data to be transferred to the second memory based on the data transfer mode comprises: transferring the current data to be transferred according to the two-dimensional column transfer mode, and obtaining intermediate fast Fourier transform result data after performing a Fourier transform operation; transferring the intermediate fast Fourier transform result data to the second memory according to the two-dimensional row transfer mode.

2. The data movement method of claim 1, wherein, if the data transfer mode is a sequential transfer mode, the transferring of the current data to be transferred to the second memory based on the data transfer mode comprises: reading data before a set bit in the current data to be transferred as a data unit to be transferred; writing the data unit to be transferred to a storage circular queue; updating the current data to be transferred to data after removing the data unit to be transferred, repeating the step of reading data before the set bit in the current data to be transferred to obtain a data unit to be transferred again, and writing the data unit to be transferred to the storage circular queue, until the current data to be transferred is completely written to the second memory.

3. The data movement method of claim 1, wherein, if the data transfer mode is matrix column transfer, the current data to be transferred is a two-dimensional data matrix, and the transferring of the current data to be transferred to the second memory based on the data transfer mode comprises: reading a first row of data in the two-dimensional data matrix which has not been read; writing the read row data in column order to a storage queue in sequence; The two-dimensional data matrix is updated to a matrix after the two-dimensional data matrix removes the row data, the step of reading the first row of data in the two-dimensional data matrix which is not read currently is repeated, and the row data read currently is sequentially written into the storage queue in column order until all the data to be transported is written into the second storage.

4. The data movement method of claim 1, wherein, If the data transport mode is matrix transposition transport, the current data to be transported is a two-dimensional data matrix, and the transporting the current data to be transported to the second storage based on the data transport mode comprises: The current data to be transported is divided into a plurality of matrix units according to a preset row number, taking the first row as the starting row, wherein the row number of the last matrix unit is less than or equal to the preset row number, and the row number of the remaining matrix units is equal to the preset row number; For the matrix unit with the row number equal to the preset row number, column transport is performed; For the matrix unit with the row number less than the preset row number, the data length transported by each transport shot is reduced, the data length of each write shot of the second storage is configured synchronously, and a corresponding tag register is created for the data transported by each transport shot; wherein if the transport data corresponding to each transport shot is valid through mask judgment, the number of the corresponding tag register is updated.

5. A data movement method according to claim 4, wherein, The column transport for the matrix unit with the row number equal to the preset row number comprises: If the total row number of the current data to be transported is odd, the last data bit of the odd column data and the first data bit of the opposite next even column data in each adjacent two column data are written into the second storage in the same write shot.

6. The data movement method of claim 1, wherein, If the data transport mode is a sequential transport mode, the transporting the current data to be transported to the second storage based on the data transport mode comprises: The current data to be transported is sequentially transported to the second storage based on the same index-address conversion rule as the butterfly memory access controller.

7. A data movement method according to claim 6, wherein, The transporting the current data to be transported to the second storage based on the data transport mode further comprises: If the data length of the current data to be transported is not an integer power of 2, the current data to be transported is zero-padded to the nearest integer power of 2 data length.

8. A DMA resource controller applied to a data carrying method according to any one of claims 1-7, characterized in that, The DMA resource controller comprises: a DMA module, the DMA module comprising a DMA built-in memory and a state register; a logic control module for controlling state machine jumping, the state machine being composed of the state register and a combination logic circuit; a data configuration module for configuring the DMA module; a DMA_Port for performing data transmission between the DMA built-in memory and a device built-in memory.

9. The DMA resource controller of claim 8, wherein, The DMA module comprises: a DMA register unit for maintaining a DMA register, the DMA register comprising a control register, a configuration register and the state register; a DMA read-write control unit for controlling signals of an AXI4 read address channel, a read data channel, a write data channel, a write address channel and a write response channel; a DMA cache unit for caching data read into the DMA module and processed. A DMA matrix control unit is configured to generate relevant read-write information of two-dimensional transmission and matrix transposition transmission, and send the relevant read-write information to the DMA read-write control module.

10. A SOC system, characterized by, The SOC system comprises a DMA resource controller as claimed in any one of claims 8-9.

11. A terminal device, comprising: The terminal device comprises a SOC system as claimed in claim 10.

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