Data transmission system, method, computer device and storage medium

Abstract

The application relates to a data transmission system, method, computer device and storage medium. The system comprises a baseboard management controller, a complex programmable logic device, a first multiplexer group, a second multiplexer group, a processor and a plurality of storage chips; the baseboard management controller and the processor are connected with the complex programmable logic device; the storage chips at least comprise a first storage chip, a second storage chip, a third storage chip and a fourth storage chip; the first multiplexer group is used for receiving a control signal transmitted by the complex programmable logic device to turn on any data transmission channel between the baseboard management controller and the first storage chip, the second storage chip and the third storage chip; and the second multiplexer group is used for receiving a control signal transmitted by the complex programmable logic device and turning on any data transmission channel between the processor and the third storage chip and the fourth storage chip according to the control signal. The above system can improve the reliability of data transmission.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of computer security, and in particular to a data transmission system and method, a computer device and a storage medium. BACKGROUND

[0002] The devices in the existing server that need SPI FLASH (flash memory based on high-speed, double full-duplex synchronous serial bus) are mainly CPU (central processing unit), BMC (baseboard management controller) and some SW chips (switch chips), and these devices need to read the information in the FLASH (flash memory) when starting to complete initialization. The information in the first edition FLASH is usually burned into the chip offline by the factory, and the subsequent debugging usually uses a burner to manually burn the update file. When the BMC function development tends to be mature, remote flashing of the FLASH can be supported.

[0003] The SPI controller can transmit data between multiple types of peripheral devices. SPI supports multi-slave mode. In the prior art, a host and slaves are usually connected in a multi-NSS (a type of SPI signal line) or daisy chain form to enable data transmission between the host and the slaves. However, in the NSS mode, each slave needs a separate NSS line, and the corresponding NSS signal line is pulled low to communicate with the corresponding slave. However, if two NSS signal lines are pulled low at the same time, the slaves may both try to transmit data on the same MISO (a type of SPI signal line) line, which may result in garbled data reception. In the daisy chain mode, if a slave in the data link fails, the slaves with lower priority below it cannot be serviced, reducing system reliability. SUMMARY

[0004] Therefore, it is necessary to provide a data transmission system, method, computer device and storage medium capable of improving the reliability of a server system to solve the above technical problems.

[0005] To solve the above technical problems, in a first aspect, a data transmission system is provided, and the system includes:

[0006] a baseboard management controller, a complex programmable logic device, a multiplexer group, a processor and a plurality of memory chips;

[0007] The baseboard management controller and the processor are connected with the complex programmable logic device, and the baseboard management controller and the processor are connected with the multiplexer group, and the multiplexer group is connected with the plurality of memory chips.

[0008] The plurality of memory chips includes a first memory chip, a second memory chip, a third memory chip and a fourth memory chip.

[0009] The first multiplexer group comprises a first multiplexer, a second multiplexer, a third multiplexer, a fourth multiplexer, a fifth multiplexer and a sixth multiplexer; the second multiplexer group comprises a seventh multiplexer and an eighth multiplexer.

[0010] The second multiplexer group is configured to receive the control signal transmitted by the complex programmable logic device and to turn on any data transmission channel between the processor and the third storage chip and the fourth storage chip according to the control signal.

[0011] In one embodiment, the first multiplexer group comprises a first multiplexer, a second multiplexer, a third multiplexer, a fourth multiplexer, a fifth multiplexer and a sixth multiplexer; the second storage chip further comprises a first sub-storage chip and a second sub-storage chip.

[0012] The first interface of the first multiplexer is connected to the baseboard management controller, the second interface of the first multiplexer is connected to the first storage chip, and the third interface of the first multiplexer is connected to the first interface of the second multiplexer; the first interface of the third multiplexer is connected to the second interface of the second multiplexer, the second interface of the third multiplexer is connected to the second interface of the fourth multiplexer, the third interface of the third multiplexer is connected to the second interface of the fifth multiplexer, the first interface of the fourth multiplexer and the first interface of the fifth multiplexer are respectively connected to the first sub-storage chip and the second sub-storage chip, and the third interface of the fourth multiplexer and the third interface of the fifth multiplexer are respectively connected to the first switch chip and the second switch chip.

[0013] The first interface of the sixth multiplexer is connected to the third interface of the second multiplexer, and the second interface of the sixth multiplexer is connected to the third storage chip.

[0014] The control terminals of the first multiplexer, the second multiplexer, the third multiplexer, the fourth multiplexer, the fifth multiplexer and the sixth multiplexer are respectively connected to the output terminals of the complex programmable logic device.

[0015] In one embodiment, the second multiplexer group comprises a seventh multiplexer and an eighth multiplexer, the first interface of the seventh multiplexer is connected to the third interface of the eighth multiplexer, the second interface of the seventh multiplexer is connected to the third storage chip, the first interface of the eighth multiplexer is connected to the processor, and the second interface of the eighth multiplexer is connected to the fourth storage chip; the control terminals of the seventh multiplexer and the eighth multiplexer are respectively connected to the output terminals of the complex programmable logic device.

[0016] To solve the above technical problems, the second aspect provides a data transmission method, which applies the data transmission system of any one of the preceding claims, and the method comprises:

[0017] In response to the baseboard management controller and / or the processor obtaining the target storage chip information, a control instruction is generated according to the target storage chip information, and the control instruction is sent to the complex programmable logic device;

[0018] In response to the complex programmable logic device receiving the control instruction, a control signal is generated according to the control instruction, and the control signal is transmitted to the first multiplexer group and / or the second multiplexer group;

[0019] In response to the first multiplexer group and / or the second multiplexer group receiving the control signal, the signal value corresponding to the target signal of each multiplexer in the first multiplexer group and / or the second multiplexer group is controlled according to the control signal, thereby realizing data transmission between the baseboard management controller and / or the processor and the target storage chip.

[0020] In one embodiment, the target storage chip is a first storage chip, and the method further comprises:

[0021] In response to the baseboard management controller obtaining the first storage chip information, a first control instruction is generated according to the first storage chip information, and the first control instruction is sent to the complex programmable logic device; the first control instruction carries the level signals of the first pin and the second pin on the baseboard management controller, wherein the first pin transmits a low-level control signal, and the second pin transmits a low-level control signal;

[0022] In response to the complex programmable logic device receiving the first control instruction, a first control signal is generated according to the first control instruction, and the first control signal is transmitted to the first multiplexer group,

[0023] In response to the first multiplexer group receiving the first control signal, the signal value of the target signal of the first multiplexer of the first multiplexer group is controlled to be the minimum value, thereby turning on the first interface of the first multiplexer and the second interface of the first multiplexer, and realizing data transmission between the baseboard management controller and the first storage chip.

[0024] In one embodiment, the target storage chip is a first sub-storage chip in the second storage chip, and the method further comprises:

[0025] In response to the baseboard management controller obtaining the first sub-storage chip information, a second control instruction is generated according to the first sub-storage chip information, and the second control instruction is sent to the complex programmable logic device; the second control instruction carries the level signals of the first pin and the second pin on the baseboard management controller, wherein the first pin transmits a high-level control signal, and the second pin transmits a low-level control signal.

[0026] In response to the complex programmable logic device receiving the second control instruction, a second control signal is generated according to the second control instruction, and the second control signal is transmitted to the first multiplexer group.

[0027] In response to the first multiplexer group receiving the second control signal, the signal value of the target signal of the first multiplexer is controlled to be the maximum value, and then the first interface of the first multiplexer and the third interface of the first multiplexer are turned on.

[0028] The signal value of the target signal of the second multiplexer is controlled to be the minimum value, and then the first interface of the second multiplexer and the second interface of the second multiplexer are turned on.

[0029] The signal value of the target signal of the third multiplexer is controlled to be the minimum value, and then the first interface of the third multiplexer and the second interface of the third multiplexer are turned on.

[0030] The signal value of the target signal of the fourth multiplexer is controlled to be the minimum value, and then the first interface of the fourth multiplexer and the second interface of the fourth multiplexer are turned on, and then the data transmission between the baseboard management controller and the first sub-storage chip information is realized.

[0031] In one of the embodiments, the target storage chip is a second sub-storage chip in the second storage chip, and the method further comprises:

[0032] In response to the baseboard management controller obtaining the second sub-storage chip information, a third control instruction is generated according to the second sub-storage chip information, and the third control instruction is sent to the complex programmable logic device; the third control instruction carries the level signals of the first pin and the second pin on the baseboard management controller, wherein the first pin transmits a low-level control signal, and the second pin transmits a high-level control signal.

[0033] In response to the complex programmable logic device receiving the third control instruction, a third control signal is generated according to the third control instruction, and the third control signal is transmitted to the first multiplexer group.

[0034] In response to the first multiplexer group receiving the third control signal, the signal value of the target signal of the first multiplexer is controlled to be the maximum value, and then the first interface of the first multiplexer and the third interface of the first multiplexer are turned on.

[0035] controlling the signal value of the target signal of the second multiplexer to be the minimum value, and then turning on the first interface of the second multiplexer and the second interface of the second multiplexer;

[0036] controlling the signal value of the target signal of the third multiplexer to be the maximum value, and then turning on the first interface of the third multiplexer and the third interface of the third multiplexer;

[0037] controlling the signal value of the target signal of the fifth multiplexer to be the minimum value, and then turning on the first interface of the fifth multiplexer and the second interface of the fifth multiplexer, and then realizing data transmission between the baseboard management controller and the second sub-storage chip.

[0038] In one of the embodiments, the target storage chip is a third storage chip, and the method further comprises:

[0039] In response to the baseboard management controller obtaining the third storage chip information, generating a fourth control instruction according to the third storage chip information, and sending the fourth control instruction to the complex programmable logic device; the fourth control instruction carries the level signals of the first pin and the second pin on the baseboard management controller, wherein the first pin transmits a high-level control signal and the second pin transmits a high-level control signal;

[0040] In response to the complex programmable logic device receiving the fourth control instruction, generating a fourth control signal according to the fourth control instruction, and transmitting the fourth control signal to the first multiplexer group;

[0041] In response to the first multiplexer group receiving the fourth control signal, controlling the signal value of the target signal of the first multiplexer to be the maximum value, and then turning on the first interface of the first multiplexer and the third interface of the first multiplexer;

[0042] controlling the signal value of the target signal of the second multiplexer to be the maximum value, and then turning on the first interface of the second multiplexer and the third interface of the second multiplexer;

[0043] controlling the signal value of the target signal of the sixth multiplexer to be the minimum value, and then turning on the first interface of the sixth multiplexer and the second interface of the sixth multiplexer; and then realizing data transmission between the baseboard management controller and the third storage chip.

[0044] In one of the embodiments, the target storage chip is a third storage chip, and the method further comprises:

[0045] In response to the processor obtaining the third storage chip information, generating a fifth control instruction according to the third storage chip information, and sending the fifth control instruction to the complex programmable logic device; the fifth control instruction carries the level signals of the pins on the processor, wherein the pins on the processor transmit high-level control signals;

[0046] In response to the complex programmable logic receiving the fifth control instruction, a fifth control signal is generated according to the fifth control instruction, and the fifth control signal is transmitted to the second multiplexer group;

[0047] In response to the second multiplexer group receiving the fifth control signal, the signal value of the target signal of the seventh multiplexer is controlled to be the minimum value, thereby turning on the first interface of the seventh multiplexer and the second interface of the seventh multiplexer;

[0048] The signal value of the target signal of the eighth multiplexer is controlled to be the maximum value, thereby turning on the first interface of the eighth multiplexer and the third interface of the eighth multiplexer; and data transmission between the processor and the third storage chip is realized.

[0049] In one of the embodiments, the target storage chip is the fourth storage chip, and the method further comprises:

[0050] In response to the processor obtaining the fourth storage chip information, a sixth control instruction is generated according to the fourth storage chip information, and the sixth control instruction is sent to the complex programmable logic; the sixth control instruction carries a level signal of a pin on the processor, wherein the pin on the processor transmits a low-level control signal.

[0051] In response to the complex programmable logic receiving the sixth control instruction, a sixth control signal is generated according to the sixth control instruction, and the sixth control signal is transmitted to the second multiplexer group;

[0052] In response to the second multiplexer group receiving the sixth control signal, the signal value of the target signal of the eighth multiplexer is controlled to be the minimum value, thereby turning on the first interface of the eighth multiplexer and the second interface of the eighth multiplexer; and data transmission between the processor and the fourth storage chip is realized.

[0053] To solve the above technical problems, in a third aspect, a computer device is provided, comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, and the processor implements the steps of the first aspect method when executing the computer program.

[0054] To solve the above technical problems, in a fourth aspect, a computer readable storage medium is provided, which stores a computer program, and the computer program is executed by a processor to implement the steps of the first aspect method.

[0055] Different from the prior art, the application provides a data transmission system, which comprises a baseboard management controller, a complex programmable logic device, a plurality of multiplexers, a processor and a plurality of memory chips; the baseboard management controller and the processor are connected with the complex programmable logic device, the baseboard management controller and the processor are connected with the plurality of multiplexers, and the plurality of multiplexers are connected with the plurality of memory chips; the plurality of memory chips comprise a first memory chip, a second memory chip, a third memory chip and a fourth memory chip; the plurality of multiplexers comprise a first multiplexer group and a second multiplexer group; the first multiplexer group is used for receiving a control signal transmitted by the complex programmable logic device, and turns on any data transmission channel between the baseboard management controller and the first memory chip, the second memory chip and the third memory chip according to the control signal; and the second multiplexer group is used for receiving a control signal transmitted by the complex programmable logic device, and turns on any data transmission channel between the processor and the third memory chip and the fourth memory chip according to the control signal. In this way, the interface of the multiplexer can be turned on according to the control instruction, the data interaction between the baseboard management controller and the processor and the plurality of memory chips can be realized, and the reliability of data transmission can be improved. BRIEF DESCRIPTION OF DRAWINGS

[0056] Figure 1 It is a structural diagram of a data transmission system in the prior art;

[0057] Figure 2 It is a structural diagram of a data transmission system in the prior art;

[0058] Figure 3 It is a structural diagram of a data transmission system in an embodiment;

[0059] Figure 4 It is a structural diagram of a data transmission system in another embodiment;

[0060] Figure 5 It is an internal structural diagram of a computer device in an embodiment. DETAILED DESCRIPTION

[0061] In order to make the purpose, technical scheme and advantages of the application clearer, the application is further described in detail below with reference to the drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the application, and are not used to limit the application.

[0062] Please refer to Figure 1In existing technologies, multiple NSS (a type of SPI signal line) are used to connect the master and slave devices. In the NSS mode, each slave device requires a separate NSS line. To communicate with a specific slave device, the corresponding NSS signal line can be pulled low while keeping the other NSS signal lines high. If two NSS signal lines are pulled low at the same time, garbled data may occur because the slave devices may both attempt to transmit data on the same MISO line, ultimately resulting in garbled received data and reduced system reliability.

[0063] Please see Figure 2 In existing technologies, a daisy-chain configuration is used to connect the master and slave devices. Device signals are transmitted serially from one slave to the next, continuously cycling until the data reaches the target slave. The biggest drawback of daisy-chaining is the serial signal transmission. If a slave in the data link fails, lower-priority slaves below it will not receive service. Furthermore, slaves farther from the master have lower priority for service. Therefore, it is necessary to carefully manage slave priorities and set up bus detectors. If a slave times out, it should be short-circuited to prevent the failure of a single slave from causing the entire link to collapse, resulting in high maintenance costs.

[0064] To address the aforementioned technical problems, in one embodiment, such as Figure 3 As shown, this application provides a data transmission system, which includes a baseboard management controller, a complex programmable logic device, a multiplexer group, a processor, and multiple memory chips.

[0065] The Baseboard Management Controller (BMC), located on the board, is a dedicated controller used for monitoring and managing the server.

[0066] The Complex Programmable Logic Controller (CPLD) is located on the motherboard. The CPLD is connected to the baseboard management controller and the processor via pins. The baseboard management controller has a first pin and a second pin. Figure 3 The GPIO pin on the BMC is also the first pin on the processor, and this pin can be a GPIO. The motherboard is essentially a switching board with two CXL SW chips (hereinafter referred to as SW chips). They need to read information from the FLASH to complete their initialization. The information in SW0 FLASH0 and SW1 FLASH1 is initially programmed offline by the factory. It can be manually programmed later using a programmer or remotely programmed by the baseboard management controller.

[0067] The processor is located on a processor board card, which is located on a mainboard. The processor can be a CPU or an MCPU, or other types of processors. In the figure, an MCPU is used as an example.

[0068] The plurality of memory chips include a first memory chip, a second memory chip, a third memory chip, and a fourth memory chip. The plurality of memory chips are respectively located on a baseboard management controller board card, a mainboard, a processor board card, and a processor expansion card (MCPU RISER). The memory chips can be FLASH, PROM, EPROM, or other memory chips. For example, the plurality of memory chips can include Figure 3 The BMC FLASH (the first memory chip) is located on the board card, the FLASH0 (the first sub-memory chip in the second memory chip) is located on the mainboard, the FLASH1 (the second sub-memory chip in the second memory chip) is located on the mainboard, the BIOS FLASH0 is located on the server expansion card, and the BIOS FLASH1 is located on the processor board card.

[0069] As shown in Figure 4 The processor expansion card is mounted on the mainboard, and has a BIOS FLASH0 and two multiplexers. The BIOS FLASH0 is an external burning FLASH for the processor. The processor expansion card also has a TYPE7 connector, which can be inserted into the mainboard. The processor board card also has another burning FLASH for the MCPU, which is the BIOS FLASH1.

[0070] The multiplexer (MUX) group includes a first multiplexer group and a second multiplexer group. The first multiplexer group is used to receive a control signal transmitted by the complex programmable logic device, and to turn on any data transmission channel between the baseboard management controller and the first memory chip, the second memory chip, or the third memory chip according to the control signal. The second multiplexer group is used to receive a control signal transmitted by the complex programmable logic device, and to turn on any data transmission channel between the processor and the third memory chip or the fourth memory chip according to the control signal.

[0071] As shown in Figure 3As shown, the first multiplexer group includes a first multiplexer (MUX1), a second multiplexer (MUX2), a third multiplexer (MUX3), a fourth multiplexer (MUX4), a fifth multiplexer (MUX5), and a sixth multiplexer (MUX5); the second storage chip further includes a first sub-storage chip (FLASH0 located on the mainboard) and a second sub-storage chip (FLASH1 located on the mainboard); the first interface (D) of the first multiplexer is connected with the baseboard management controller (BMC), the second interface (A) of the first multiplexer is connected with the first storage chip, and the third interface (B) of the first multiplexer is connected with the first interface (D) of the second multiplexer.

[0072] The first interface (D) of the third multiplexer is connected with the second interface (A) of the second multiplexer, the second interface (A) of the third multiplexer is connected with the second interface (A) of the fourth multiplexer, the third interface (B) of the third multiplexer is connected with the second interface (A) of the fifth multiplexer, the first interface (D) of the fourth multiplexer and the first interface (D) of the fifth multiplexer are respectively connected with the first sub-storage chip and the second sub-storage chip, and the third interface (B) of the fourth multiplexer and the third interface (B) of the fifth multiplexer are respectively connected with the first switching chip and the second switching chip.

[0073] The sixth multiplexer and the fourth storage chip are located on the processor expansion card, the first interface (D) of the sixth multiplexer is connected with the third interface (B) of the second multiplexer, and the second interface (A) of the sixth multiplexer is connected with the third storage chip.

[0074] Specifically, the baseboard management controller board card includes a baseboard management controller, a first multiplexer, and a first storage chip, the first interface (D) of the first multiplexer is connected with the baseboard management controller (BMC), the second interface (A) of the first multiplexer (MUX1) is connected with the first storage chip (BMC FLASH), and the third interface (B) of the first multiplexer (MUX1) is connected with the first interface (D) of the second multiplexer; by controlling the conduction of the first interface (D) of the first multiplexer and the second interface (A) of the first multiplexer, data transmission between the baseboard management controller and the first storage chip on the baseboard management controller board card can be realized, by controlling the conduction of the first interface (D) of the first multiplexer and the third interface (B) of the first multiplexer, data transmission between the baseboard management controller and the second multiplexer on the mainboard can be realized, thereby providing the possibility of realizing data transmission between the baseboard management controller and the storage chip on the mainboard.

[0075] Specifically, the main board includes a second multiplexer, a third multiplexer, a fourth multiplexer, and a fifth multiplexer. By turning on the interfaces of the multiplexers, the first interface (D) of the second multiplexer is connected with the third interface (B) of the first multiplexer, the second interface (A) of the second multiplexer is connected with the first interface (D) of the third multiplexer, the second interface (A) of the third multiplexer is connected with the first end of the first level conversion chip, the second end of the first level conversion chip is connected with the second interface (A) of the fourth multiplexer, the first interface (D) of the fourth multiplexer is connected with the first sub-storage chip of the second storage chip, and the data transmission channel between the baseboard management controller and the second sub-storage chip is realized.

[0076] In another mode, by turning on the interfaces of the multiplexers, the first interface (D) of the second multiplexer is connected with the third interface (B) of the first multiplexer, the second interface (A) of the second multiplexer is connected with the first interface (D) of the third multiplexer, the third interface (B) of the third multiplexer is connected with the first end of the second level conversion chip, the second end of the second level conversion chip is connected with the second interface (A) of the fifth multiplexer, the first interface (D) of the fifth multiplexer is connected with the second sub-storage chip of the second storage chip, and the data transmission channel between the baseboard management controller and the second sub-storage chip is realized.

[0077] In an embodiment, the second multiplexer group further includes a seventh multiplexer and an eighth multiplexer. The seventh multiplexer is located on the processor expansion card, the eighth multiplexer and the fourth storage chip are located on the processor board card, the first interface (D) of the seventh multiplexer is connected with the third interface (B) of the eighth multiplexer, the second interface (A) of the seventh multiplexer is connected with the third storage chip, the first interface (D) of the eighth multiplexer is connected with the processor, and the second interface (A) of the eighth multiplexer is connected with the basic input and output system and the fourth storage chip.

[0078] Specifically, the processor expansion card includes a sixth multiplexer, a seventh multiplexer, and a third storage chip. In this embodiment, by turning on the interfaces of the multiplexers, the baseboard manager, the first multiplexer, the second multiplexer, the sixth multiplexer, and the third storage chip are connected, and the data transmission channel between the baseboard management controller and the third storage chip is realized. The processor main board includes a basic input and output system (BIOS), an eighth multiplexer, a processor, and a fourth storage chip. The fourth storage chip is connected with the second interface (A) of the eighth multiplexer. By turning on the first interface (D) of the eighth multiplexer and the second interface (A) of the eighth multiplexer, the data transmission channel between the processor and the fifth storage chip can be turned on.

[0079] In another embodiment, the data transmission channel between the processor and the third storage chip can be enabled by enabling the first interface (D) of the eighth multiplexer and the second interface (A) of the eighth multiplexer, and the first interface (D) of the seventh multiplexer and the second interface (A) of the seventh multiplexer.

[0080] In the present application, a master device (a baseboard management controller and a processor) is connected to multiple slave devices (storage chips), but only one line is connected at the same time. A method for the baseboard management controller to remotely program all storage chips in a system is provided. Multiple multiplexers are used to achieve the method. The pins of a complex programmable logic device are used to control the multiple multiplexers, so as to enable a specific path and achieve the functions of the baseboard management controller programming firmware in the storage chip or reading data from the storage chip.

[0081] The present application has eight multiplexers, each of which has the same function, that is, a two-way signal selector. The control end of each multiplexer is connected to the output end of a complex programmable logic device, which is used to obtain the control signal transmitted by the complex programmable logic device. The control signal is used to control the signal value of the target signal (SEL signal) in the multiplexer. Figure 1 The SEL signal (target signal) and the EN_L (first signal) are not shown in the figure. The EN_L signal is grounded, indicating that the multiplexer chip is open. The SEL signal of all multiplexer chips is connected to the CPLD. The SEL signal has its own default value.

[0082] The present application has two GPIOs between the CPLD and the BMC. The default values of the two GPIOs are both low. When the BMC wants to program other FLASH, it will send a GPIO signal to the CPLD. The CPLD reads the state of the GPIO to determine the operation that the BMC wants to perform, and then controls the SEL signal of each MUX to achieve the function.

[0083] The following table 1 shows the correspondence between the BMC function and the two GPIOs. GPIO0 is the first pin, GPIO1 is the second pin, and the value corresponding to GPIO0 or GPIO1 is 0, indicating that the pin transmits a low-level control signal. The value corresponding to GPIO0 or GPIO1 is 1, indicating that the pin transmits a high-level control signal.

[0084]

[0085] Table 1

[0086] As shown in the table, when the CPLD detects the GPIO issued by the BMC, it will control the corresponding interface to output the SEL (target signal of the multiplexer) information. Table 2 below shows the correspondence between BMC functions and SEL signals of MUX, where MUX1, MUX2, MUX3, MUX3, MUX5, MUX6, MUX7, and MUX8 correspond to the first multiplexer, the second multiplexer, the third multiplexer, the fourth multiplexer, the fifth multiplexer, the sixth multiplexer, the seventh multiplexer, and the eighth multiplexer in the present application. Each multiplexer corresponds to different values under various conditions, where 0 is the minimum value, representing that the first interface of the corresponding multiplexer is conductive with the second interface of the multiplexer, 1 is the maximum value, representing that the first interface of the corresponding multiplexer is conductive with the third interface of the multiplexer, and X represents an indefinite state, regardless of the value of X, which has no effect on the result:

[0087]

[0088] Table 2

[0089] In one embodiment, a data transmission method is provided. In this method, applied to a data transmission system in Figure 3 The method includes the following steps:

[0090] In response to the baseboard management controller and / or the processor obtaining the target storage chip information, a control instruction is generated according to the target storage chip information, and the control instruction is sent to the complex programmable logic device;

[0091] In response to the complex programmable logic device receiving the control instruction, a control signal is generated according to the control instruction, and the control signal is transmitted to the first multiplexer group and / or the second multiplexer group;

[0092] In response to the first multiplexer group and / or the second multiplexer group receiving the control signal, the signal value corresponding to the target signal of each multiplexer in the first multiplexer group and / or the second multiplexer group is controlled according to the control signal, thereby realizing data transmission between the baseboard management controller and / or the processor and the target storage chip.

[0093] According to which storage chip needs to interact with the substrate management controller or the processor, the corresponding control instruction is generated, the control instruction is sent to the CPLD, the corresponding control signal is generated according to the control instruction, the output end of the CPID is connected with each multiplexer, and the control signal is transmitted to the multiplexer. The generation process can be generated by searching the above table 1 and / or table 2, for example, when the BMC reads the BMC FLASH, the values of the first pin (GPIO0) and the second pin (GPIO1) on the BMC are set to 0 according to table 1, that is, the first pin transmits a low-level control signal, and the second pin transmits a high-level control signal. According to table 2, when the BMC reads the BMC FLASH, the signal value of the target signal of the first multiplexer is set to 0, and the signal values of the target signals of the remaining multiplexers are X. At this time, the BMC can read the data in the BMC FLASH. In this way, the control signal can be quickly and accurately obtained through the table lookup method, and the conduction of the interface of the multiplexer is performed.

[0094] In an embodiment, the target storage chip is a first storage chip, and the method further comprises: in response to the substrate management controller obtaining the first storage chip information, generating a first control instruction according to the first storage chip information, and sending the first control instruction to the complex programmable logic device; the first control instruction carries the level signals of the first pin and the second pin on the substrate management controller, wherein the first pin transmits a low-level control signal and the second pin transmits a low-level control signal; in response to the complex programmable logic device receiving the first control instruction, generating a first control signal according to the first control instruction, and transmitting the first control signal to the first multiplexer group; in response to the first multiplexer group receiving the first control signal, the signal value of the target signal of the first multiplexer of the first multiplexer group is the minimum value, and the first interface of the first multiplexer and the second interface of the first multiplexer are turned on, thereby realizing the data transmission between the substrate management controller and the first storage chip.

[0095] Specifically, in a specific embodiment, when the BMC (board management controller) acquires information in the BMC FLASH (first storage chip) on the BMC board, first, the BMC generates a first control instruction to the CPLD, wherein the first control instruction carries the first pin and the second pin signal, the values of the control signals transmitted by the first pin and the second pin on the BMC are both 0, when the values of the control signals transmitted by the first pin and the second pin on the BMC are both 0, the control signals transmitted by the first pin and the second pin are both low-level control signals, after the CPLD receives the first control instruction sent by the BMC, the CPLD sends a first control signal, in response to the first multiplexer receiving the first control signal, the signal value of the target signal of the first multiplexer is 0, wherein the corresponding first signal of the multiplexer is EN_L, the corresponding target signal of the multiplexer is SEL, the first signal in the application is grounded, and the type value of the first signal is 0 by default. At this time, the first interface (D) of the first multiplexer is conductive with the second interface (A) of the first multiplexer, at this time, the BMC can perform data transmission through the data channel formed between the first interface (D) and the second interface (A) of the first multiplexer.

[0096] In the application, the values of the control signals of the first pin and the second pin corresponding to different control instructions are transmitted to the CPLD through the control instruction, so that the CPLD controls the signal value of the target signal of the multiplexer, and then selectively conducts the data channel in the multiplexer.

[0097] In an embodiment, the target storage chip is a first sub-storage chip in the second storage chip, and the method further comprises: in response to the baseboard management controller obtaining the first sub-storage chip information, generating a second control instruction according to the first sub-storage chip information, and sending the second control instruction to the complex programmable logic device; the second control instruction carries a level signal of a first pin and a second pin on the baseboard management controller, wherein the first pin transmits a high-level control signal and the second pin transmits a low-level control signal; in response to the complex programmable logic device receiving the second control instruction, generating a second control signal according to the second control instruction, and transmitting the second control signal to the first multiplexer group; in response to the first multiplexer group receiving the second control signal, controlling the signal value of the target signal of the first multiplexer to be the maximum value, thereby turning on the first interface of the first multiplexer and the third interface of the first multiplexer; controlling the signal value of the target signal of the second multiplexer to be the minimum value, thereby turning on the first interface of the second multiplexer and the second interface of the second multiplexer; controlling the signal value of the target signal of the third multiplexer to be the minimum value, thereby turning on the first interface of the third multiplexer and the second interface of the third multiplexer; controlling the signal value of the target signal of the fourth multiplexer to be the minimum value; thereby turning on the first interface of the fourth multiplexer and the second interface of the fourth multiplexer, thereby realizing data transmission between the baseboard management controller and the first sub-storage chip information.

[0098] When the BMC needs to remotely burn information in the FLASH0 (first sub-storage chip) on the mainboard, the BMC generates a second control instruction to the CPLD, wherein the second control instruction carries the first pin and the second pin signal, the value of the control signal transmitted by the first pin on the BMC is 1, and the value of the control signal transmitted by the second pin is 0, that is, the control signal transmitted by the first pin is a high-level control signal, and the control signal transmitted by the second pin is a low-level control signal. After the CPLD receives the second control instruction, the CPLD sends out a second control signal. In response to the first, second, third and fourth multiplexers receiving the second control signal, the signal value of the target signal of the first multiplexer is 1, at this time, the first interface (D) of the first multiplexer is conductive with the third interface (B) of the first multiplexer; the signal value of the target signal of the second multiplexer is 0, at this time, the first interface (D) of the second multiplexer is conductive with the second interface (A) of the second multiplexer; the signal value of the target signal of the third multiplexer is 0, at this time, the first interface (D) of the third multiplexer is conductive with the second interface (A) of the third multiplexer; the signal value of the target signal of the fourth multiplexer is 0, at this time, the first interface (D) of the fourth multiplexer is conductive with the second interface (A) of the fourth multiplexer, at this time, the BMC can perform data transmission through the data channel formed between the BMC and the FLASH0 on the mainboard.

[0099] In an embodiment, the target storage chip is a second sub-storage chip in the second storage chip, and the method further comprises:

[0100] In response to the baseboard management controller obtaining the second sub-storage chip information, a third control instruction is generated according to the second sub-storage chip information, and the third control instruction is sent to the complex programmable logic device; the third control instruction carries the level signals of the first pin and the second pin on the baseboard management controller, wherein the first pin transmits a low-level control signal, and the second pin transmits a high-level control signal; in response to the complex programmable logic device receiving the third control instruction, a third control signal is generated according to the third control instruction, and the third control signal is transmitted to the first multiplexer group; in response to the first multiplexer group receiving the third control signal, the signal value of the target signal of the first multiplexer is controlled to be the maximum value, and then the first interface of the first multiplexer and the third interface of the first multiplexer are turned on; the signal value of the target signal of the second multiplexer is controlled to be the minimum value, and then the first interface of the second multiplexer and the second interface of the second multiplexer are turned on; the signal value of the target signal of the third multiplexer is controlled to be the maximum value, and then the first interface of the third multiplexer and the third interface of the third multiplexer are turned on; the signal value of the target signal of the fifth multiplexer is controlled to be the minimum value; and then the first interface of the fifth multiplexer and the second interface of the fifth multiplexer are turned on, so as to realize data transmission between the baseboard management controller and the second sub-storage chip.

[0101] When the BMC needs to remotely burn the information in the FLASH1 (first sub-storage chip) on the mainboard, the BMC generates a third control instruction to the CPLD. After the CPLD receives the third control instruction, the CPLD sends a third control signal, wherein the second control instruction carries the first pin and the second pin signal, that is, the value of the control signal transmitted by the first pin on the BMC is 0, and the value of the control signal transmitted by the second pin is 1, that is, the control signal transmitted by the first pin is a low-level control signal. In response to the first multiplexer, the second multiplexer, the third multiplexer and the fifth multiplexer receiving the third control signal, the signal value of the target signal of the first multiplexer is controlled to be 1, at this time, the first interface (D) of the first multiplexer and the third interface (B) of the first multiplexer are turned on; the signal value of the target signal of the second multiplexer is controlled to be 0, at this time, the first interface (D) of the second multiplexer and the second interface (A) of the second multiplexer are turned on; the signal value of the target signal of the third multiplexer is controlled to be 1, at this time, the first interface (D) of the third multiplexer and the third interface (B) of the third multiplexer are turned on; the signal value of the target signal of the fifth multiplexer is controlled to be 0, at this time, the first interface (D) of the fifth multiplexer and the second interface (A) of the fourth multiplexer are turned on, at this time, the BMC can perform data transmission through the data channel formed between the BMC and the FLASH1 on the mainboard.

[0102] In an embodiment, the target storage chip is a third storage chip, and the method further comprises: in response to the baseboard management controller obtaining the third storage chip information, generating a fourth control instruction according to the third storage chip information, and sending the fourth control instruction to the complex programmable logic device; the fourth control instruction carries a level signal of a first pin and a second pin on the baseboard management controller, wherein the first pin transmits a high-level control signal and the second pin transmits a high-level control signal; in response to the complex programmable logic device receiving the fourth control instruction, generating a fourth control signal according to the fourth control instruction, and transmitting the fourth control signal to the first multiplexer group; in response to the first multiplexer group receiving the fourth control signal, controlling the signal value of the target signal of the first multiplexer to be the maximum value, thereby turning on the first interface of the first multiplexer and the third interface of the first multiplexer; controlling the signal value of the target signal of the second multiplexer to be the maximum value, thereby turning on the first interface of the second multiplexer and the third interface of the second multiplexer; controlling the signal value of the target signal of the sixth multiplexer to be the minimum value, thereby turning on the first interface of the sixth multiplexer and the second interface of the sixth multiplexer; thereby realizing data transmission between the baseboard management controller and the fourth storage chip.

[0103] When the BMC needs to read the BIOS FLASH0 (third storage chip), the BMC generates a fourth control instruction to the CPLD. After the CPLD receives the fourth control instruction, the CPLD sends out a fourth control signal. The second control instruction carries a signal of a first pin and a second pin, wherein the first pin on the BMC transmits a control signal with a value of 1, and the second pin transmits a control signal with a value of 1, that is, the first pin transmits a high-level control signal, and the second pin transmits a high-level control signal. After the CPLD receives the third control instruction, the CPLD sends out a third control signal. In response to the first multiplexer, the second multiplexer, and the sixth multiplexer receiving the third control signal, the signal value of the target signal of the first multiplexer is controlled to be 1, at this time, the first interface (D) of the first multiplexer and the third interface (B) of the first multiplexer are turned on; the signal value of the target signal of the second multiplexer is controlled to be 1, at this time, the first interface (D) of the second multiplexer and the second interface (A) (B) of the second multiplexer are turned on; the signal value of the target signal of the sixth multiplexer is controlled to be 0, at this time, the first interface (D) of the sixth multiplexer and the second interface (A) of the sixth multiplexer are turned on; at this time, the BMC can perform data transmission through the data channel formed between the BMC and the BIOS FLASH0 by the plurality of multiplexers.

[0104] In an embodiment, the target storage chip is a third storage chip, and the method further comprises: in response to the processor obtaining the third storage chip information, generating a fifth control instruction according to the third storage chip information, and sending the fifth control instruction to the complex programmable logic device; the fifth control instruction carries a level signal of a pin on the processor, wherein the pin on the processor transmits a high-level control signal.

[0105] In response to the complex programmable logic device receiving the fifth control instruction, a fifth control signal is generated according to the fifth control instruction, and the fifth control signal is transmitted to the second multiplexer group; in response to the second multiplexer group receiving the fifth control signal, the signal value of the target signal of the seventh multiplexer is controlled to be the minimum value, thereby turning on the first interface of the seventh multiplexer and the second interface of the seventh multiplexer; the signal value of the target signal of the eighth multiplexer is controlled to be the maximum value, thereby turning on the first interface of the eighth multiplexer and the third interface of the eighth multiplexer; thereby realizing data transmission between the processor and the third storage chip.

[0106] When the MCPU (microprocessor) obtains the BIOS FLASH0 (fourth storage chip) on the MCPU RI SER, the MCPU generates a fifth control instruction to the CPLD, wherein the fifth control instruction transmits information of pulling up the level of the GPIO interface between the MCPU and the CPLD; after the CPLD receives the fifth control instruction, the CPLD generates a fifth control signal; in response to the second multiplexer group receiving the fifth control signal, the signal value of the target signal of the seventh multiplexer is controlled to be 0, at this time the first interface (D) of the seventh multiplexer and the second interface (A) of the seventh multiplexer are turned on, and the signal value of the target signal of the eighth multiplexer is controlled to be 1, at this time the first interface (D) of the eighth multiplexer and the third interface (B) of the eighth multiplexer are turned on; at this time, the MCPU can perform data transmission through the data channel formed between the MCPU and the BIOS FLASH0 (third storage chip) between the plurality of multiplexers.

[0107] In an embodiment, the target storage chip is a fourth storage chip, and the method further comprises: in response to the processor obtaining the fourth storage chip information, generating a sixth control instruction according to the fourth storage chip information, and sending the sixth control instruction to the complex programmable logic device; the sixth control instruction carries a level signal of a pin on the processor, wherein the pin on the processor transmits a low-level control signal; in response to the complex programmable logic device receiving the sixth control instruction, generating a sixth control signal according to the sixth control instruction, and transmitting the sixth control signal to the second multiplexer group; in response to the second multiplexer group receiving the sixth control signal, controlling the signal value of the target signal of the eighth multiplexer to be the minimum value, thereby turning on the first interface of the eighth multiplexer and the second interface of the eighth multiplexer; and thereby realizing data transmission between the processor and the fourth storage chip.

[0108] When the MCPU (microprocessor) obtains the BIOS FLASH1 (fifth storage chip, not shown in the figure) on the MCPU board, the MCPU generates a sixth control instruction to the CPLD, wherein the sixth control instruction transmits information that the GPIO interface level between the MCPU and the CPLD is pulled low, and after the CPLD receives the sixth control instruction, the CPLD generates a sixth control signal. In response to the second multiplexer group receiving the sixth control signal, the signal value of the target signal of the eighth multiplexer is controlled to be 0, at this time the first interface (D) of the eighth multiplexer and the second interface (A) of the eighth multiplexer are turned on. At this time, the MCPU can perform data transmission through the data channel formed between the MCPU and the BIOS FLASH1 (fifth storage chip) between the first interface (D) and the second interface (A) of the eighth multiplexer. However, the first interface (D) of the seventh selector and the third interface (B) of the seventh multiplexer are not turned on, and the signal is disconnected here.

[0109] From the above description, it can be seen that the present application supports two master devices of BMC and MCPU to read the SPI signal, supports multiple slaves under one master device, supports the BMC to remotely program all FLASH in the system, uses multiple gating switches to achieve this, controls the gating switch through the GPIO interface of the CPLD, thereby realizing specific path gating, and achieving the functions of programming FLASH by the BMC or reading FLASH by the device.

[0110] In an embodiment, after data access to a certain memory chip according to the control instruction, the data transmission data obtained by the data access is checked, and when the checking result is successful, data transmission is performed according to the data transmission data obtained by the data access. Specifically, the data transmission data can be calculated based on a preset checking algorithm to obtain checking data. The preset checking algorithm can be a message digest algorithm, such as an MD digest algorithm, a security hash algorithm (SHA), etc. For example, after the data transmission file is calculated by the message digest algorithm to obtain the checking data, the checking data includes a message digest, for example, an MD value obtained based on the MD digest algorithm, or a plurality of message values obtained based on the security hash algorithm. The calculated checking data and the upgrade instruction can be encrypted to obtain an encrypted checking data packet, and the encrypted checking data packet is sent to the host device (baseboard management controller, processor). Before data transmission, the host device can encrypt the data transmission data to obtain encrypted upgrade data, and then transmit the encrypted upgrade data to the host device, so as to improve the security of the data transmission data transmission.

[0111] The specific limitations of the data transmission system can be referred to the limitations of the data transmission method in the above, which will not be repeated here. The modules in the above data transmission system can be realized by software, hardware and their combinations. The modules can be embedded in or independent of the processor in the computer device in hardware form, or stored in the memory in the computer device in software form, so that the processor can call and execute the operations corresponding to the modules.

[0112] In an embodiment, a computer device is provided, which can be a terminal, and its internal structure diagram can be as shown in Figure 5 The computer device includes a processor, a memory, a network interface, a display screen and an input device connected by a system bus. The processor of the computer device is used to provide computing and control capabilities. The memory of the computer device includes a non-volatile storage medium and an internal memory. The non-volatile storage medium stores an operating system and a computer program. The internal memory provides an environment for the operating system and the computer program in the non-volatile storage medium to run. The network interface of the computer device is used to communicate with external terminals through network connection. The computer program is executed by the processor to implement a data transmission method. The display screen of the computer device can be a liquid crystal display screen or an electronic ink display screen. The input device of the computer device can be a touch layer overlaid on the display screen, or a key, trackball or touchpad arranged on the shell of the computer device, or an external keyboard, touchpad or mouse, etc.

[0113] Those skilled in the art can understand that,Figure 5 The structure shown in the figure is only a block diagram of part of the structure related to the scheme of the present application, and does not constitute a limitation on the computer device to which the scheme of the present application is applied. The specific computer device can include more or fewer components than those shown in the figure, or combine certain components, or have a different arrangement of components.

[0114] In an embodiment, the present application also provides a computer program product, which comprises a computer program stored on a non-transitory computer-readable storage medium, and the computer program comprises program instructions, when the program instructions are executed by a computer, the computer can execute the data transmission method provided by the above method.

[0115] In one embodiment, a computer device is provided, comprising a memory, a processor, and a computer program stored on the memory and executable on the processor, and the processor implements the following steps when executing the computer program:

[0116] In one embodiment, the processor further implements the following steps when executing the computer program:

[0117] In response to the baseboard management controller and / or the processor obtaining the target storage chip information, a control instruction is generated according to the target storage chip information, and the control instruction is sent to the complex programmable logic device;

[0118] In response to the complex programmable logic device receiving the control instruction, a control signal is generated according to the control instruction, and the control signal is transmitted to the first multiplexer group and / or the second multiplexer group;

[0119] In response to the first multiplexer group and / or the second multiplexer group receiving the control signal, the signal value corresponding to the target signal of each multiplexer in the first multiplexer group and / or the second multiplexer group is controlled according to the control signal, thereby realizing data transmission between the baseboard management controller and / or the processor and the target storage chip.

[0120] In one embodiment, the processor further implements the following steps when executing the computer program:

[0121] The target storage chip is a first storage chip, and the method further comprises:

[0122] In response to the baseboard management controller obtaining the first storage chip information, a first control instruction is generated according to the first storage chip information, and the first control instruction is sent to the complex programmable logic device; the first control instruction carries the level signals of the first pin and the second pin on the baseboard management controller, wherein the first pin transmits a low-level control signal, and the second pin transmits a low-level control signal;

[0123] In response to the complex programmable logic receiving the first control instruction, a first control signal is generated according to the first control instruction, and the first control signal is transmitted to the first multiplexer group,

[0124] In response to the first multiplexer group receiving the first control signal, the signal value of the target signal of the first multiplexer of the first multiplexer group is controlled to be the minimum value, thereby turning on the first interface of the first multiplexer and the second interface of the first multiplexer, and realizing data transmission between the baseboard management controller and the first storage chip.

[0125] In one embodiment, when the processor executes the computer program, the following steps are also implemented:

[0126] The target storage chip is a first sub-storage chip in the second storage chip, and the method further comprises:

[0127] In response to the baseboard management controller obtaining the first sub-storage chip information, a second control instruction is generated according to the first sub-storage chip information, and the second control instruction is sent to the complex programmable logic; the second control instruction carries the level signals of the first pin and the second pin on the baseboard management controller, wherein the first pin transmits a high-level control signal and the second pin transmits a low-level control signal;

[0128] In response to the complex programmable logic receiving the second control instruction, a second control signal is generated according to the second control instruction, and the second control signal is transmitted to the first multiplexer group;

[0129] In response to the first multiplexer group receiving the second control signal, the signal value of the target signal of the first multiplexer is controlled to be the maximum value, thereby turning on the first interface of the first multiplexer and the third interface of the first multiplexer;

[0130] The signal value of the target signal of the second multiplexer is controlled to be the minimum value, thereby turning on the first interface of the second multiplexer and the second interface of the second multiplexer;

[0131] The signal value of the target signal of the third multiplexer is controlled to be the minimum value, thereby turning on the first interface of the third multiplexer and the second interface of the third multiplexer;

[0132] The signal value of the target signal of the fourth multiplexer is controlled to be the minimum value, thereby turning on the first interface of the fourth multiplexer and the second interface of the fourth multiplexer, and realizing data transmission between the baseboard management controller and the first sub-storage chip information.

[0133] In one embodiment, when the processor executes the computer program, the following steps are also implemented:

[0134] The target storage chip is a second sub-storage chip in the second storage chip, and the method further includes:

[0135] In response to the baseboard management controller obtaining the second sub-storage chip information, a third control instruction is generated according to the second sub-storage chip information, and the third control instruction is sent to the complex programmable logic device; the third control instruction carries a level signal of the first pin and the second pin on the baseboard management controller, wherein the first pin transmits a low-level control signal, and the second pin transmits a high-level control signal;

[0136] In response to the complex programmable logic device receiving the third control instruction, a third control signal is generated according to the third control instruction, and the third control signal is transmitted to the first multiplexer group;

[0137] In response to the first multiplexer group receiving the third control signal, a signal value of a target signal of the first multiplexer is controlled to be a maximum value, and then a first interface of the first multiplexer and a third interface of the first multiplexer are turned on;

[0138] A signal value of a target signal of the second multiplexer is controlled to be a minimum value, and then a first interface of the second multiplexer and a second interface of the second multiplexer are turned on;

[0139] A signal value of a target signal of the third multiplexer is controlled to be a maximum value, and then a first interface of the third multiplexer and a third interface of the third multiplexer are turned on;

[0140] A signal value of a target signal of the fifth multiplexer is controlled to be a minimum value, and then a first interface of the fifth multiplexer and a second interface of the fifth multiplexer are turned on, and then data transmission between the baseboard management controller and the second sub-storage chip is realized.

[0141] In one embodiment, the processor further implements the following steps when executing the computer program:

[0142] The target storage chip is a third storage chip, and the method further includes:

[0143] In response to the baseboard management controller obtaining the third storage chip information, a fourth control instruction is generated according to the third storage chip information, and the fourth control instruction is sent to the complex programmable logic device; the fourth control instruction carries a level signal of the first pin and the second pin on the baseboard management controller, wherein the first pin transmits a high-level control signal, and the second pin transmits a high-level control signal;

[0144] In response to the complex programmable logic device receiving the fourth control instruction, a fourth control signal is generated according to the fourth control instruction, and the fourth control signal is transmitted to the first multiplexer group;

[0145] In response to the first multiplexer group receiving the fourth control signal, the signal value of the target signal of the first multiplexer is controlled to be the maximum value, thereby turning on the first interface of the first multiplexer and the third interface of the first multiplexer;

[0146] The signal value of the target signal of the second multiplexer is controlled to be the maximum value, thereby turning on the first interface of the second multiplexer and the third interface of the second multiplexer;

[0147] The signal value of the target signal of the sixth multiplexer is controlled to be the minimum value, thereby turning on the first interface of the sixth multiplexer and the second interface of the sixth multiplexer; and data transmission between the baseboard management controller and the third storage chip is realized.

[0148] In one embodiment, the processor further implements the following steps when executing the computer program:

[0149] The target storage chip is the fourth storage chip, and the method further includes:

[0150] In response to the processor obtaining the fourth storage chip information, a sixth control instruction is generated according to the fourth storage chip information, and the sixth control instruction is sent to the complex programmable logic device; the sixth control instruction carries a level signal of a pin on the processor, wherein the pin on the processor transmits a low-level control signal;

[0151] In response to the complex programmable logic device receiving the sixth control instruction, a sixth control signal is generated according to the sixth control instruction, and the sixth control signal is transmitted to the second multiplexer group;

[0152] In response to the second multiplexer group receiving the sixth control signal, the signal value of the target signal of the eighth multiplexer is controlled to be the maximum value, thereby turning on the first interface of the eighth multiplexer and the third interface of the eighth multiplexer; and data transmission between the processor and the fourth storage chip is realized.

[0153] The signal value of the target signal of the eighth multiplexer is controlled to be the maximum value, thereby turning on the first interface of the eighth multiplexer and the third interface of the eighth multiplexer; and data transmission between the processor and the fourth storage chip is realized.

[0154] In one embodiment, the processor further implements the following steps when executing the computer program:

[0155] The target storage chip is the fourth storage chip, and the method further includes:

[0156] In response to the processor obtaining the fourth storage chip information, a sixth control instruction is generated according to the fourth storage chip information, and the sixth control instruction is sent to the complex programmable logic device; the sixth control instruction carries a level signal of a pin on the processor, wherein the pin on the processor transmits a low-level control signal;

[0157] In response to the complex programmable logic receiving the sixth control instruction, a sixth control signal is generated according to the sixth control instruction, and the sixth control signal is transmitted to the second multiplexer group;

[0158] In response to the second multiplexer group receiving the sixth control signal, the signal value of the target signal of the eighth multiplexer is controlled to be the minimum value, thereby turning on the first interface of the eighth multiplexer and the second interface of the eighth multiplexer; thereby realizing data transmission between the processor and the fourth storage chip.

[0159] In one embodiment, a computer readable storage medium is provided, and the computer readable storage medium stores a computer program. When the computer program is executed by a processor, the following steps are implemented:

[0160] In one embodiment, when the computer program is executed by the processor, the following steps are further implemented:

[0161] In response to the baseboard management controller and / or the processor obtaining the target storage chip information, a control instruction is generated according to the target storage chip information, and the control instruction is sent to the complex programmable logic;

[0162] In response to the complex programmable logic receiving the control instruction, a control signal is generated according to the control instruction, and the control signal is transmitted to the first multiplexer group and / or the second multiplexer group;

[0163] In response to the first multiplexer group and / or the second multiplexer group receiving the control signal, the signal value corresponding to the target signal of each multiplexer in the first multiplexer group and / or the second multiplexer group is controlled according to the control signal, thereby realizing data transmission between the baseboard management controller and / or the processor and the target storage chip.

[0164] In one embodiment, when the computer program is executed by the processor, the following steps are further implemented:

[0165] The target storage chip is a first storage chip, and the method further includes:

[0166] In response to the baseboard management controller obtaining the first storage chip information, a first control instruction is generated according to the first storage chip information, and the first control instruction is sent to the complex programmable logic; the first control instruction carries the level signals of the first pin and the second pin on the baseboard management controller, wherein the first pin transmits a low-level control signal, and the second pin transmits a low-level control signal;

[0167] In response to the complex programmable logic receiving the first control instruction, a first control signal is generated according to the first control instruction, and the first control signal is transmitted to the first multiplexer group,

[0168] In response to the first multiplexer group receiving the first control signal, the signal value of the target signal of the first multiplexer of the first multiplexer group is the minimum value, thereby turning on the first interface of the first multiplexer and the second interface of the first multiplexer, and realizing data transmission between the baseboard management controller and the first storage chip.

[0169] In one embodiment, the computer program, when executed by the processor, further implements the following steps:

[0170] The target storage chip is a first sub-storage chip in the second storage chip, and the method further includes:

[0171] In response to the baseboard management controller obtaining the first sub-storage chip information, a second control instruction is generated according to the first sub-storage chip information, and the second control instruction is sent to the complex programmable logic device; the second control instruction carries the level signals of the first pin and the second pin on the baseboard management controller, wherein the first pin transmits a high-level control signal and the second pin transmits a low-level control signal;

[0172] In response to the complex programmable logic device receiving the second control instruction, a second control signal is generated according to the second control instruction, and the second control signal is transmitted to the first multiplexer group;

[0173] In response to the first multiplexer group receiving the second control signal, the signal value of the target signal of the first multiplexer is the maximum value, thereby turning on the first interface of the first multiplexer and the third interface of the first multiplexer;

[0174] The signal value of the target signal of the second multiplexer is the minimum value, thereby turning on the first interface of the second multiplexer and the second interface of the second multiplexer;

[0175] The signal value of the target signal of the third multiplexer is the minimum value, thereby turning on the first interface of the third multiplexer and the second interface of the third multiplexer;

[0176] The signal value of the target signal of the fourth multiplexer is the minimum value, thereby turning on the first interface of the fourth multiplexer and the second interface of the fourth multiplexer, and realizing data transmission between the baseboard management controller and the first sub-storage chip information.

[0177] In one embodiment, the computer program, when executed by the processor, further implements the following steps:

[0178] The target storage chip is a second sub-storage chip in the second storage chip, and the method further includes:

[0179] In response to the baseboard management controller obtaining the second sub-storage chip information, a third control instruction is generated according to the second sub-storage chip information, and the third control instruction is sent to the complex programmable logic device; the third control instruction carries the level signals of the first pin and the second pin on the baseboard management controller, wherein the first pin transmits a low-level control signal, and the second pin transmits a high-level control signal.

[0180] In response to the complex programmable logic device receiving the third control instruction, a third control signal is generated according to the third control instruction, and the third control signal is transmitted to the first multiplexer group.

[0181] In response to the first multiplexer group receiving the third control signal, the signal value of the target signal of the first multiplexer is controlled to be the maximum value, so as to turn on the first interface of the first multiplexer and the third interface of the first multiplexer.

[0182] The signal value of the target signal of the second multiplexer is controlled to be the minimum value, so as to turn on the first interface of the second multiplexer and the second interface of the second multiplexer.

[0183] The signal value of the target signal of the third multiplexer is controlled to be the maximum value, so as to turn on the first interface of the third multiplexer and the third interface of the third multiplexer.

[0184] The signal value of the target signal of the fifth multiplexer is controlled to be the minimum value, so as to turn on the first interface of the fifth multiplexer and the second interface of the fifth multiplexer, and then realize the data transmission between the baseboard management controller and the second sub-storage chip.

[0185] In one embodiment, the computer program is executed by the processor to further implement the following steps:

[0186] The target storage chip is a third storage chip, and the method further comprises:

[0187] In response to the baseboard management controller obtaining the third storage chip information, a fourth control instruction is generated according to the third storage chip information, and the fourth control instruction is sent to the complex programmable logic device; the fourth control instruction carries the level signals of the first pin and the second pin on the baseboard management controller, wherein the first pin transmits a high-level control signal, and the second pin transmits a high-level control signal.

[0188] In response to the complex programmable logic device receiving the fourth control instruction, a fourth control signal is generated according to the fourth control instruction, and the fourth control signal is transmitted to the first multiplexer group.

[0189] In response to the first multiplexer group receiving the fourth control signal, the signal value of the target signal of the first multiplexer is controlled to be the maximum value, thereby turning on the first interface of the first multiplexer and the third interface of the first multiplexer;

[0190] The signal value of the target signal of the second multiplexer is controlled to be the maximum value, thereby turning on the first interface of the second multiplexer and the third interface of the second multiplexer;

[0191] The signal value of the target signal of the sixth multiplexer is controlled to be the minimum value, thereby turning on the first interface of the sixth multiplexer and the second interface of the sixth multiplexer; and data transmission between the baseboard management controller and the third storage chip is realized.

[0192] In one embodiment, the computer program is executed by the processor to further implement the following steps:

[0193] The target storage chip is the fourth storage chip, and the method further includes:

[0194] In response to the processor obtaining the fourth storage chip information, a sixth control instruction is generated according to the fourth storage chip information, and the sixth control instruction is sent to the complex programmable logic device; the sixth control instruction carries a level signal of a pin on the processor, wherein the pin on the processor transmits a low-level control signal.

[0195] In response to the complex programmable logic device receiving the fifth control instruction, a fifth control signal is generated according to the fifth control instruction, and the fifth control signal is transmitted to the second multiplexer group;

[0196] In response to the second multiplexer group receiving the fifth control signal, the signal value of the target signal of the seventh multiplexer is controlled to be the minimum value, thereby turning on the first interface of the seventh multiplexer and the second interface of the seventh multiplexer;

[0197] The signal value of the target signal of the eighth multiplexer is controlled to be the maximum value, thereby turning on the first interface of the eighth multiplexer and the third interface of the eighth multiplexer; and data transmission between the processor and the fourth storage chip is realized.

[0198] In one embodiment, the computer program is executed by the processor to further implement the following steps:

[0199] The target storage chip is the fourth storage chip, and the method further includes:

[0200] In response to the processor obtaining the fourth storage chip information, a sixth control instruction is generated according to the fourth storage chip information, and the sixth control instruction is sent to the complex programmable logic device; the sixth control instruction carries a level signal of a pin on the processor, wherein the pin on the processor transmits a low-level control signal.

[0201] In response to the complex programmable logic device receiving the sixth control instruction, a sixth control signal is generated according to the sixth control instruction, and the sixth control signal is transmitted to the second multiplexer group;

[0202] In response to the second multiplexer group receiving the sixth control signal, the signal value of the target signal of the eighth multiplexer is controlled to be the minimum value, thereby turning on the first interface of the eighth multiplexer and the second interface of the eighth multiplexer; and data transmission between the processor and the fourth storage chip is realized. It can be understood by those skilled in the art that all or part of the processes in the above-mentioned embodiment methods can be completed by a computer program instructing related hardware. The computer program can be stored in a non-volatile computer readable storage medium. When the computer program is executed, it can include the processes of the above-mentioned embodiments. Any reference to memory, storage, database or other medium used in the embodiments provided by the present application can include non-volatile and / or volatile memory. Non-volatile memory can include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM) or flash memory. Volatile memory can include random access memory (RAM) or external cache memory. As an illustration but not limitation, RAM is available in various forms, such as static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double data rate SDRAM (DDR SDRAM), enhanced SDRAM (ESDRAM), synchronous link (Synch link) DRAM (SLDRAM), memory bus (Rambus) direct RAM (RDRAM), direct memory bus dynamic RAM (DRDRAM), and memory bus dynamic RAM (RDRAM), etc.

[0203] Any combination of the technical features of the above embodiments can be made. In order to make the description simple, all possible combinations of the technical features in the above embodiments are not described, however, as long as the combination of the technical features does not exist, it should be considered as the scope of the present application.

[0204] The above embodiments only express several implementation manners of the present application, and the description is more specific and detailed, but it should not be understood as a limitation on the scope of the patent. It should be noted that for those skilled in the art, without departing from the concept of the present application, some modifications and improvements can be made, which are all within the scope of the present application. Therefore, the scope of the patent of the present application should be subject to the appended claims.

Claims

1. A data transmission system, characterized by The application relates to a substrate management controller, a complex programmable logic device, a multiplexer group, a processor and a plurality of memory chips. The substrate management controller and the processor are connected with the complex programmable logic device respectively, and the substrate management controller and the processor are connected with the multiplexer group, and the multiplexer group is connected with the plurality of memory chips. The plurality of memory chips comprises a first memory chip, a second memory chip, a third memory chip and a fourth memory chip. The multiplexer group comprises a first multiplexer group and a second multiplexer group, the first multiplexer group is used for receiving a control signal transmitted by the complex programmable logic device, and any data transmission channel between the substrate management controller and the first memory chip, the second memory chip and the third memory chip is turned on according to the control signal. The second multiplexer group is used for receiving a control signal transmitted by the complex programmable logic device, and any data transmission channel between the processor and the third memory chip and the fourth memory chip is turned on according to the control signal. The first multiplexer group comprises a first multiplexer, a second multiplexer, a third multiplexer, a fourth multiplexer, a fifth multiplexer and a sixth multiplexer, and the second memory chip further comprises a first sub-memory chip and a second sub-memory chip. A first interface of the first multiplexer is connected with the substrate management controller, a second interface of the first multiplexer is connected with the first memory chip, and a third interface of the first multiplexer is connected with a first interface of the second multiplexer. A first interface of the fourth multiplexer and a first interface of the fifth multiplexer are connected with the first sub-memory chip and the second sub-memory chip respectively, and a third interface of the fourth multiplexer and a third interface of the fifth multiplexer are connected with the first exchange chip and the second exchange chip respectively. A first interface of the sixth multiplexer is connected with a third interface of the second multiplexer, and a second interface of the sixth multiplexer is connected with the third memory chip. Control ends of the first multiplexer, the second multiplexer, the third multiplexer, the fourth multiplexer, the fifth multiplexer and the sixth multiplexer are connected with output ends of the complex programmable logic device respectively. ​ 2. The system of claim 1, wherein, The second multiplexer group includes a seventh multiplexer and an eighth multiplexer, a first interface of the seventh multiplexer is connected with a third interface of the eighth multiplexer, a second interface of the seventh multiplexer is connected with a third storage chip, a first interface of the eighth multiplexer is connected with a processor, and a second interface of the eighth multiplexer is connected with a fourth storage chip; control ends of the seventh multiplexer and the eighth multiplexer are connected with output ends of the complex programmable logic device.

3. A data transmission method implemented based on the data transmission system according to claim 1, characterized in that, The method comprises: In response to the baseboard management controller and / or the processor obtaining target storage chip information, generating a control instruction according to the target storage chip information, and sending the control instruction to the complex programmable logic device; In response to the complex programmable logic device receiving the control instruction, generating a control signal according to the control instruction, and transmitting the control signal to the first multiplexer group and / or the second multiplexer group; In response to the first multiplexer group and / or the second multiplexer group receiving the control signal, controlling the signal value of the target signal of each multiplexer in the first multiplexer group and / or the second multiplexer group according to the control signal, thereby realizing data transmission between the baseboard management controller and / or the processor and the target storage chip.

4. The method of claim 3, wherein, The target storage chip is a first storage chip, and the method further comprises: In response to the baseboard management controller obtaining first storage chip information, generating a first control instruction according to the first storage chip information, and sending the first control instruction to the complex programmable logic device; the first control instruction carries the level signals of a first pin and a second pin on the baseboard management controller, wherein the first pin transmits a low-level control signal, and the second pin transmits a low-level control signal; In response to the complex programmable logic device receiving the first control instruction, generating a first control signal according to the first control instruction, and transmitting the first control signal to the first multiplexer group, In response to the first multiplexer group receiving the first control signal, controlling the signal value of the target signal of the first multiplexer of the first multiplexer group to be the minimum value, thereby turning on the first interface of the first multiplexer and the second interface of the first multiplexer, and realizing data transmission between the baseboard management controller and the first storage chip.

5. The method of claim 3, wherein, The target storage chip is a first sub-storage chip in the second storage chip, and the method further comprises: In response to the baseboard management controller obtaining first sub-storage chip information, generating a second control instruction according to the first sub-storage chip information, and sending the second control instruction to the complex programmable logic device; the second control instruction carries the level signals of a first pin and a second pin on the baseboard management controller, wherein the first pin transmits a high-level control signal, and the second pin transmits a low-level control signal; In response to the complex programmable logic device receiving the second control instruction, generating a second control signal according to the second control instruction, and transmitting the second control signal to the first multiplexer group; In response to the first multiplexer group receiving the second control signal, the signal value of the target signal of the first multiplexer is controlled to be the maximum value, thereby turning on the first interface of the first multiplexer and the third interface of the first multiplexer; the signal value of the target signal of the second multiplexer is controlled to be the minimum value, thereby turning on the first interface of the second multiplexer and the second interface of the second multiplexer; the signal value of the target signal of the third multiplexer is controlled to be the minimum value, thereby turning on the first interface of the third multiplexer and the second interface of the third multiplexer; the signal value of the target signal of the fourth multiplexer is controlled to be the minimum value, thereby turning on the first interface of the fourth multiplexer and the second interface of the fourth multiplexer, thereby realizing data transmission between the baseboard management controller and the first sub-storage chip information.

6. The method of claim 3, wherein, The target storage chip is a second sub-storage chip in a second storage chip, and the method further comprises: In response to the baseboard management controller obtaining the second sub-storage chip information, a third control instruction is generated according to the second sub-storage chip information, and the third control instruction is sent to the complex programmable logic device; the third control instruction carries the level signals of the first pin and the second pin on the baseboard management controller, wherein the first pin transmits a low-level control signal and the second pin transmits a high-level control signal; In response to the complex programmable logic device receiving the third control instruction, a third control signal is generated according to the third control instruction, and the third control signal is transmitted to the first multiplexer group; In response to the first multiplexer group receiving the third control signal, the signal value of the target signal of the first multiplexer is controlled to be the maximum value, thereby turning on the first interface of the first multiplexer and the third interface of the first multiplexer; the signal value of the target signal of the second multiplexer is controlled to be the minimum value, thereby turning on the first interface of the second multiplexer and the second interface of the second multiplexer; the signal value of the target signal of the third multiplexer is controlled to be the maximum value, thereby turning on the first interface of the third multiplexer and the third interface of the third multiplexer; the signal value of the target signal of the fifth multiplexer is controlled to be the minimum value, thereby turning on the first interface of the fifth multiplexer and the second interface of the fifth multiplexer, thereby realizing data transmission between the baseboard management controller and the second sub-storage chip.

7. The method of claim 3, wherein, The target storage chip is a third storage chip, and the method further comprises: In response to the baseboard management controller obtaining the third storage chip information, a fourth control instruction is generated according to the third storage chip information, and the fourth control instruction is sent to the complex programmable logic device; the fourth control instruction carries the level signals of the first pin and the second pin on the baseboard management controller, wherein the first pin transmits a high-level control signal and the second pin transmits a high-level control signal; In response to the complex programmable logic device receiving the fourth control instruction, a fourth control signal is generated according to the fourth control instruction, and the fourth control signal is transmitted to the first multiplexer group; In response to the fourth control signal being received by the first multiplexer group, the signal value of the target signal of the first multiplexer is controlled to be the maximum value, thereby turning on the first interface of the first multiplexer and the third interface of the first multiplexer; the signal value of the target signal of the second multiplexer is controlled to be the maximum value, thereby turning on the first interface of the second multiplexer and the third interface of the second multiplexer; the signal value of the target signal of the sixth multiplexer is controlled to be the minimum value, thereby turning on the first interface of the sixth multiplexer and the second interface of the sixth multiplexer; and data transmission between the baseboard management controller and the third storage chip is realized.

8. The method of claim 3, wherein, The target storage chip is a fourth storage chip, and the method further comprises: In response to the processor obtaining fourth storage chip information, a fifth control instruction is generated according to the fourth storage chip information, and the fifth control instruction is sent to the complex programmable logic device; the fifth control instruction carries a level signal of a pin on the processor, wherein the pin on the processor transmits a low-level control signal; In response to the complex programmable logic device receiving the fifth control instruction, a fifth control signal is generated according to the fifth control instruction, and the fifth control signal is transmitted to the second multiplexer group; In response to the second multiplexer group receiving the fifth control signal, the signal value of the target signal of the seventh multiplexer is controlled to be the minimum value, thereby turning on the first interface of the seventh multiplexer and the second interface of the seventh multiplexer; the signal value of the target signal of the eighth multiplexer is controlled to be the maximum value, thereby turning on the first interface of the eighth multiplexer and the third interface of the eighth multiplexer; and data transmission between the processor and the fourth storage chip is realized.

9. The method of claim 3, wherein, The target storage chip is a fourth storage chip, and the method further comprises: In response to the processor obtaining fourth storage chip information, a fifth control instruction is generated according to the fourth storage chip information, and the fifth control instruction is sent to the complex programmable logic device; the fifth control instruction carries a level signal of a pin on the processor, wherein the pin on the processor transmits a low-level control signal; In response to the complex programmable logic device receiving the fifth control instruction, a fifth control signal is generated according to the fifth control instruction, and the fifth control signal is transmitted to the second multiplexer group; In response to the second multiplexer group receiving the fifth control signal, the signal value of the target signal of the seventh multiplexer is controlled to be the minimum value, thereby turning on the first interface of the seventh multiplexer and the second interface of the seventh multiplexer; 10. A computer device comprising a memory, a processor, and a computer program stored on the memory and executable on the processor, characterized in that, The processor executes the computer program to realize the steps of the method in any one of claims 3 to 9.

11. A computer readable storage medium having stored thereon a computer program, characterized in that, The computer program is executed by the processor to realize the steps of the method in any one of claims 3 to 9.

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