SMI interface read-write system and method

Abstract

The invention discloses an SMI read-write system and method. The system comprises the steps that a user module sends a clock signal and write request information to an SMI read-write module; the SMI read-write module writes data into an output cache signal bit by bit according to the clock signal and the write request information and an SMI protocol, and feeds back a transmission completion signal to the user module; when the output enable signal is 1, the output cache signal is transmitted to a register of the PHY chip module; the user module sends read request information to the SMI read-write module; the SMI read-write module writes data into a data input and output signal bit by bit according to the clock signal and the read request information and an SMI protocol, and feeds back a transmission completion signal to the user module; when the output enable signal is 0, a data input and output signal is transmitted to the SMI read-write module and stored in a read data signal; the user module reads data in the data reading signal when receiving the transmission completion signal; and effective communication is established.

Description

Technical Field

[0001] The present application generally relates to the field of communication technology, and specifically to an SMI interface reading and writing system and method. Background Art

[0002] If existing dedicated chips want to successfully connect to the SMI (Serial Management Interface) interface of the Ethernet physical layer (PHY) chip and access the registers of the PHY chip, the dedicated chip must have appropriate control logic, pin configuration, protocol compatibility and development support. However, the existing dedicated chips lack these conditions, resulting in their inability to achieve effective communication with the PHY chip alone. Therefore, we propose an SMI interface reading and writing system and method to solve the above defects. Summary of the invention

[0003] In view of the above-mentioned defects or deficiencies in the prior art, it is desirable to provide an SMI interface reading and writing system and method for efficient and reliable data exchange.

[0004] In a first aspect, the present application provides an SMI interface read / write system, comprising: a user module, an SMI read / write module and a PHY chip module in communication connection; The user module is used to send a clock signal and write request information to the SMI read-write module; the write request information at least includes: a PHY chip address, a register address, a write request and a write data signal; The SMI read / write module is used to write the data bit by bit into the output buffer signal according to the clock signal and the write request information in accordance with the SMI protocol, and to feed back a transmission completion signal to the user module; The SMI read / write module is further configured to transmit the output buffer signal to the register of the PHY chip module when the output enable signal is 1; The user module is further used to send read request information to the SMI read-write module; the read request information at least includes: a PHY chip address, a register address and a read request; The SMI read / write module is further used to write data bit by bit into the data input / output signal according to the clock signal and the read request information in accordance with the SMI protocol, and to feed back a transmission completion signal to the user module; The SMI read / write module is further used to receive data input / output signals when the output enable signal is 0; The data input and output signal, when the output enable signal is 0, the data input and output signal transmission direction is from the PHY chip module to the SMI read-write module; The data input and output signal, when the output enable signal is 1, the data input and output signal transmission direction is from the SMI read-write module to the PHY chip module; The user module is further used to obtain data in the read data signal when receiving the transmission completion signal.

[0005] According to the technical solution provided in the embodiment of the present application, the SMI read-write module has an idle state and an SMI write state; In the idle state, waiting for a write request or a read request sent by a user module; When the SMI read / write module receives the clock signal and the write request information, it jumps to the SMI write state according to the write request of the write request information; In the SMI write state, the output enable signal is set to 1 and the clock signal is counted; according to the value of the write counter, a total of 32 bits of data, including a 2-bit start code, a 2-bit operation code, a 5-bit phy chip address, a 5-bit register address, a 2-bit turn code and 16-bit output data, are written bit by bit into the output buffer signal in accordance with the SMI protocol. When the write counter reaches 33, it jumps to the write end state; In the write end state, the write count is stopped, the write counter is cleared, and a transmission completion signal is fed back to the user module.

[0006] According to the technical solution provided in the embodiment of the present application, the SMI read-write module also has an SMI read state; When the SMI read / write module receives the clock signal and the read request information, it jumps to the SMI read state according to the read request of the read request information, sets the output enable signal to 1 and counts the clock signal; In the SMI read state, the 2-bit start code, 2-bit operation code, 5-bit phy chip address, and 5-bit register address are written bit by bit into the data input and output signal in accordance with the SMI protocol, and when the count reaches 15, the output enable signal is set to 0 and jumps to the read flip state; In the read flip state, when the count reaches 17, it jumps to the read data state; In the read data state, each rising edge of the clock stores the value of the input and output signals bit by bit into the 16-bit read data signal; when the read counter reaches 33, it jumps to the read end state; In the read end state, the read count is stopped, the read counter is cleared, and a transmission completion signal is fed back to the user module; after receiving the transmission completion signal, the user module reads the data in the read data signal.

[0007] According to the technical solution provided in the embodiment of the present application, the SMI read-write module is communicatively connected to the PHY chip module via the mdc signal line and the mdio signal line.

[0008] According to the technical solution provided in the embodiment of the present application, the SMI read-write module is also used to set the data valid signal to 1 and feed it back to the user module after the data input-output signal is sent to the user module.

[0009] In a second aspect, the present application provides an SMI interface reading and writing method, which is implemented based on the above-mentioned SMI interface reading and writing system, and the method comprises the following steps: When receiving the clock signal and the write request information, the data is written bit by bit into the output buffer signal according to the clock signal and the write request information in accordance with the SMI protocol, and a transmission completion signal is fed back to the user module; the write request information includes at least: a PHY chip address, a register address, a write request and a write data signal; When the output enable signal is 1, the output buffer signal is transmitted to the register of the PHY chip module; When receiving the clock signal and the read request information, the data is written bit by bit into the data input and output signal according to the clock signal and the read request information in accordance with the SMI protocol, and a transmission completion signal is fed back to the user module; the read request information at least includes: a PHY chip address, a register address and a read request; When the output enable signal is 0, the data input and output signal is transmitted to the SMI read-write module; the user module is used to read the data in the data input and output signal when receiving the transmission completion signal; The data input and output signal, when the output enable signal is 0, the data input and output signal transmission direction is from the PHY chip module to the SMI read-write module; The data input and output signal, when the output enable signal is 1, the data input and output signal transmission direction is from the SMI read-write module to the PHY chip module.

[0010] According to the technical solution provided in the embodiment of the present application, according to the clock signal and the write request information, the data is written bit by bit into the output cache signal according to the SMI protocol, which specifically includes the following steps: When the SMI read / write module receives the clock signal and the write request information, it jumps to the SMI write state according to the write request of the write request information; In the SMI write state, the output enable signal is set to 1 and the clock signal is counted; according to the value of the write counter, a total of 32 bits of data, including a 2-bit start code, a 2-bit operation code, a 5-bit phy chip address, a 5-bit register address, a 2-bit turn code and 16-bit output data, are written bit by bit into the output buffer signal in accordance with the SMI protocol. When the write counter reaches 33, it jumps to the write end state; In the write end state, the write count is stopped, the write counter is cleared, and a transmission completion signal is fed back to the user module.

[0011] According to the technical solution provided in the embodiment of the present application, according to the clock signal and the read request information, the data is written bit by bit into the data input and output signal according to the SMI protocol, which specifically includes the following steps: When the SMI read / write module receives the clock signal and the read request information, it jumps to the SMI read state according to the read request of the read request information, sets the output enable signal to 1 and counts the clock signal; In the SMI read state, the 2-bit start code, 2-bit operation code, 5-bit phy chip address, and 5-bit register address are written bit by bit into the data input and output signal in accordance with the SMI protocol, and when the count reaches 15, the output enable signal is set to 0 and jumps to the read flip state; In the read flip state, when the count reaches 17, it jumps to the read data state; In the read data state, each rising edge of the clock stores the value of the input and output signals bit by bit into the 16-bit read data signal; when the read counter reaches 33, it jumps to the read end state; In the read end state, the read count is stopped, the read counter is cleared, and a transmission completion signal is fed back to the user module; after receiving the transmission completion signal, the user module reads the data in the read data signal.

[0012] It can be seen from the above technical solution that the present application has at least the following beneficial effects: The present application discloses an SMI interface read-write system, which includes: a user module, an SMI read-write module and a PHY chip module that are in communication connection; specifically, the user module is used to send a clock signal and write request information to the SMI read-write module; the write request information at least includes: a PHY chip address, a register address, a write request and a write data signal; the SMI read-write module is used to write data bit by bit into an output buffer signal according to the clock signal and the write request information and the SMI protocol, and feed back a transmission completion signal to the user module; the SMI read-write module is also used to transmit the output buffer signal to the register of the PHY chip module when the output enable signal is 1; the user module is also used to send a read request information to the SMI read-write module; This read request information includes at least: PHY chip address, register address and read request; the SMI read-write module is also used to write data bit by bit into the data input and output signal according to the SMI protocol based on the clock signal and the read request information, and feedback the transmission completion signal to the user module; the SMI read-write module is also used to receive the data input and output signal when the output enable signal is 0; data input and output signal, when the output enable signal is 0, the data input and output signal transmission direction is from the PHY chip module to the SMI read-write module; when the output enable signal is 1, the data input and output signal transmission direction is from the SMI read-write module to the PHY chip module; when the user module receives the transmission completion signal, it obtains the data in the read data signal.

[0013] The present application sends a clock signal and write request information or a clock signal and read request information through a user module, and the SMI read-write module performs write and read operations on the register of the PHY chip module according to the clock signal and write request information or the clock signal and read request information, that is, establishes effective communication between the user module and the PHY chip module. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] Other features, objects and advantages of the present application will become more apparent from the detailed description of non-limiting embodiments made with reference to the following drawings.

[0015] Figure 1 This is a structural diagram of the SMI interface reading and writing system.

[0016] Figure 2 This is a sample diagram of the various states of the SMI read and write module.

[0017] Figure 3 Output schematic diagram for mdio signal line.

[0018] Reference numerals in the figure: 100, user module; 200, SMI read / write module; 300, PHY chip module. DETAILED DESCRIPTION

[0019] The present application is further described in detail below in conjunction with the accompanying drawings and embodiments. It is to be understood that the specific embodiments described herein are only used to explain the relevant invention, rather than to limit the invention. It is also necessary to explain that, for ease of description, only the parts related to the invention are shown in the accompanying drawings.

[0020] It should be noted that, in the absence of conflict, the embodiments and features in the embodiments of the present application can be combined with each other. The present application will be described in detail below with reference to the accompanying drawings and in combination with the embodiments.

[0021] In order to make the description of the following embodiments clear and concise, a brief introduction to the related technology is first given: Most of the existing dedicated chips, such as some microcontrollers or FPGA chips, do not have built-in SMI control logic or protocol support. The SMI interface requires specific timing and signal control, which is beyond the functional scope of such microcontrollers or chips. Some dedicated chips may not support high impedance state or bidirectional data transmission. In addition, if the dedicated chip does not have the corresponding driver or register mapping document, it will be difficult for developers to correctly access and configure the PHY registers. Therefore, it is impossible to communicate with the PHY chip correctly.

[0022] In order to make the SMI interface reading and writing system provided in the embodiment of the present application clearer and easier to understand, the system is introduced below in conjunction with the accompanying drawings. Figure 1 As shown, this figure is a schematic diagram of the structure of the SMI interface reading and writing system provided in an embodiment of the present application, and the system includes: The user module 100, the SMI read / write module 200 and the PHY chip module 300 are communicatively connected; The user module 100 is used to send a clock signal and write request information to the SMI read / write module 200; the write request information at least includes: PHY chip address, register address, write request and write data signal; here, the user module 100 refers to the module for the user to process data and realize the user customized function. The clock signal is Figure 1 The clk in ensures that data is sent and received at the correct timing; the PHY chip address is Figure 1 The phy_addr in the register address is Figure 1 The write request is reg_addr in Figure 1 In write_req, the write data signal is Figure 1 in write_data.

[0023] The SMI read / write module 200 is used to write the data into the output buffer signal bit by bit according to the clock signal and the write request information in accordance with the SMI protocol, and to feed back a transmission completion signal to the user module 100; The SMI read / write module 200 is also used to transmit the output buffer signal to the register of the PHY chip module 300 when the output enable signal is 1; here, the output enable signal is mdio_en, which is used to indicate whether the SMI read / write module 200 is ready to send data on the mdio signal line. When the output enable signal is 1, that is, the output enable signal is at a high level, it indicates that it is ready to send data to the PHY chip module 300. In addition, when the output enable signal is 0, that is, the output enable signal is at a low level, it indicates that the SMI read / write module 200 does not send data, the mdio signal line is in a high impedance state, and only the PHY chip module 300 is allowed to send data to the SMI read / write module 200 on the mdio signal line. In this way, the data flow direction is effectively controlled to ensure that the state of the mdio signal line is correct during write and read operations.

[0024] The SMI read / write module 200 is connected to the PHY chip module 300 through the mdc signal line and the mdio signal line. The mdc signal line is used to transmit the clock signal, and the mdio signal line is used to transmit the data signal. When the clock signal is at the rising edge, the transmitted data signal is a valid signal. The SMI read / write module 200 starts the write operation by pulling down the mdio signal line and generating a clock signal on the mdc signal line.

[0025] It should be noted that the SMI read / write module 200 has an idle state and an SMI write state; in the idle state, it waits for a write request or a read request sent by the user module 100; Specifically, Figure 2 As shown, when the SMI read-write module 200 receives the clock signal and the write request information, it jumps to the SMI write state according to the write request of the write request information; In the SMI write state, the output enable signal is set to 1 and the clock signal is counted; the write count starts here, that is, the write counter write_cnt is incremented by 1 for each clock. According to the value of the write counter, the 2-bit start code, 2-bit operation code, 5-bit phy chip address, 5-bit register address, 2-bit steering code and 16-bit output data, a total of 32 bits of data, are written bit by bit into the output buffer signal in accordance with the SMI protocol. When the write counter reaches 33, it jumps to the write end state; In the write completion state, the write counting is stopped, the write counter is cleared, and a transmission completion signal is fed back to the user module 100 .

[0026] The output buffer signal is mdio_out, which is a data line signal output to the mdio signal line and is used to transmit data to be written into the register of the PHY chip module 300 .

[0027] The transfer completion signal is Figure 1The done in the module 100 is 1. As shown in Table 1, the written data includes: a 2-bit start code, a 2-bit operation code, a 5-bit PHY chip address, a 5-bit register address, a 2-bit turn code and a 16-bit write data signal, a total of 32 bits of data.

[0028] Table 1 Write operation data format

[0029] The user module 100 is also used to send a read request message to the SMI read / write module 200; the read request message at least includes: a PHY chip address, a register address and a read request; here, the PHY chip address is Figure 1 The phy_addr in the register address is Figure 1 The read request is reg_addr in Figure 1 in read_req.

[0030] The SMI read / write module 200 is also used to write data bit by bit into the data input / output signal according to the SMI protocol based on the clock signal and the read request information, and to feed back a transmission completion signal to the user module 100; here, the SMI read / write module 200 starts the read operation by pulling down the mdio signal line and generating a clock signal on the mdc signal line.

[0031] The user module 100 is further configured to read the data in the data input / output signal when receiving the transmission completion signal.

[0032] It should be noted that the SMI read / write module 200 also has an SMI read state; Specifically, Figure 2 As shown, when the SMI read-write module 200 receives the clock signal and the read request information, it jumps to the SMI read state according to the read request of the read request information, sets the output enable signal to 1 and counts the clock signal; here, the read count starts, that is, the read counter read_cnt is increased by 1 for each clock.

[0033] In the SMI read state, the 2-bit start code, 2-bit operation code, 5-bit phy chip address, and 5-bit register address are written bit by bit into the data input and output signal in sequence according to the SMI protocol, and when the count reaches 15, the output enable signal is set to 0 and jumps to the read flip state; here, in the read flip state, mido_en is set to 0 to continue to set mdio to read, the first bit of the steering code is high impedance, and the second bit is 0 input by the PHY chip module 300.

[0034] In the read flip state, when the count reaches 17, it jumps to the read data state; In the read data state, each rising edge of the clock stores the value of the input and output signals bit by bit into the 16-bit read data signal; when the read counter reaches 33, it jumps to the read end state; In the read end state, the read count is stopped, the read counter is cleared, and a transmission completion signal is fed back to the user module 100; after receiving the transmission completion signal, the user module 100 reads the data in the read data signal.

[0035] In the data reading state, each clock rising edge stores the value of mdio bit by bit into the 16-bit read data signal. Here, the read data signal is Figure 1 When the read counter reaches 33, it jumps to the read end state, stops reading, and clears the read counter. In the read end state, the done signal is set to 1.

[0036] Among them, the data input and output signal is mdio_out, which is in a high-impedance state, and the PHY chip module 300 feeds back the data to the SMI read-write module 200 through the mdio signal line.

[0037] As shown in Table 2, the read data includes: 2-bit start code, 2-bit operation code, 5-bit phy chip address, and 5-bit register address.

[0038] Table 2 Read operation data format

[0039] The SMI read / write module 200 is also used to transmit the data input / output signal to the user module 100 when the output enable signal is 0.

[0040] The SMI read / write module 200 is also used to set the data valid signal to 1 and feed it back to the user module 100 after the data input / output signal is sent to the user module 100. The data valid signal is Figure 1 in done.

[0041] mdio is a bidirectional signal, which can be used as a receiving signal or a sending signal; it mainly obtains the output value through a two-choice selector. Figure 3 As shown, when the output enable signal (mdio_en) is 0, the mdio signal line is in a high impedance state, and the data input and output signals are transmitted to the user module 100 .

[0042] The present application embodiment provides an SMI interface reading and writing method, which is implemented based on the above-mentioned SMI interface reading and writing system, and the method includes the following steps: When receiving the clock signal and the write request information, the data is written bit by bit into the output buffer signal according to the clock signal and the write request information in accordance with the SMI protocol, and a transmission completion signal is fed back to the user module 100; the write request information includes at least: a PHY chip address, a register address, a write request and a write data signal; When the output enable signal is 1, the output buffer signal is transmitted to the register of the PHY chip module 300; When receiving the clock signal and the read request information, the data is written bit by bit into the data input and output signal according to the clock signal and the read request information in accordance with the SMI protocol, and a transmission completion signal is fed back to the user module 100; the read request information includes at least: a PHY chip address, a register address and a read request; When the output enable signal is 0, the data input and output signal is transmitted to the SMI read-write module 200; the user module 100 is also used to obtain the data in the read data signal when receiving the transmission completion signal; Data input and output signal, when the output enable signal is 0, the data input and output signal transmission direction is from the PHY chip module 300 to the SMI read-write module 200; Data input and output signal: when the output enable signal is 1, the data input and output signal transmission direction is from the SMI read / write module 200 to the PHY chip module 300.

[0043] Further, according to the clock signal and the write request information, the data is written bit by bit into the output buffer signal according to the SMI protocol, which specifically includes the following steps: When the SMI read / write module 200 receives the clock signal and the write request information, it jumps to the SMI write state according to the write request of the write request information; In the SMI write state, the output enable signal is set to 1 and the clock signal is counted; according to the value of the write counter, the 2-bit start code, 2-bit operation code, 5-bit phy chip address, 5-bit register address, 2-bit turn code and 16-bit output data, a total of 32 bits of data, are written bit by bit into the output buffer signal in accordance with the SMI protocol. When the write counter reaches 33, it jumps to the write end state; In the write completion state, the write counting is stopped, the write counter is cleared, and a transmission completion signal is fed back to the user module 100 .

[0044] Further, according to the clock signal and the read request information, the data is written bit by bit into the data input and output signal according to the SMI protocol, which specifically includes the following steps: When the SMI read / write module 200 receives the clock signal and the read request information, it jumps to the SMI read state according to the read request of the read request information, sets the output enable signal to 1 and counts the clock signal; In the SMI read state, the 2-bit start code, 2-bit operation code, 5-bit phy chip address, and 5-bit register address are written bit by bit into the data input and output signal in accordance with the SMI protocol, and when the count reaches 15, the output enable signal is set to 0 and jumps to the read flip state; In the read flip state, when the count reaches 17, it jumps to the read data state; In the read data state, each rising edge of the clock stores the value of the input and output signals bit by bit into the 16-bit read data signal; when the read counter reaches 33, it jumps to the read end state; In the read end state, the read count is stopped, the read counter is cleared, and a transmission completion signal is fed back to the user module 100; after receiving the transmission completion signal, the user module 100 reads the data in the read data signal.

[0045] The present application sends a clock signal and write request information or a clock signal and read request information through the user module 100, and the SMI read-write module 200 performs write and read operations on the registers of the PHY chip module 300 according to the clock signal and write request information or the clock signal and read request information, that is, establishes effective communication between the user module 100 and the PHY chip module 300.

[0046] The above description is only a preferred embodiment of the present application and an explanation of the technical principles used. Those skilled in the art should understand that the scope of the invention involved in the present application is not limited to the technical solution formed by a specific combination of the above technical features, but should also cover other technical solutions formed by any combination of the above technical features or their equivalent features without departing from the inventive concept. For example, the above features are replaced with (but not limited to) technical features with similar functions disclosed in the present application.

Claims

1. An SMI interface reading and writing system, characterized in that: include: A user module (100), an SMI read / write module (200), and a PHY chip module (300) in communication connection; The user module (100) is used to send a clock signal and write request information to the SMI read / write module (200); the write request information at least includes: a PHY chip address, a register address, a write request and a write data signal; The SMI read / write module (200) is used to write the data bit by bit into the output buffer signal according to the clock signal and the write request information in accordance with the SMI protocol, and to feed back a transmission completion signal to the user module (100); The SMI read / write module (200) is further configured to transmit the output buffer signal to the register of the PHY chip module (300) when the output enable signal is 1; The user module (100) is further used to send read request information to the SMI read / write module (200); the read request information at least includes: a PHY chip address, a register address and a read request; The SMI read / write module (200) is further used to write data bit by bit into the data input / output signal according to the clock signal and the read request information in accordance with the SMI protocol, and to feed back a transmission completion signal to the user module (100); The SMI read / write module (200) is further used to receive a data input / output signal when the output enable signal is 0; The data input and output signal, when the output enable signal is 0, the data input and output signal transmission direction is from the PHY chip module (300) to the SMI read and write module (200); The data input and output signal, when the output enable signal is 1, the data input and output signal transmission direction is from the SMI read / write module (200) to the PHY chip module (300); The user module (100) is further used to obtain data in the read data signal when receiving the transmission completion signal.

2. An SMI interface reading and writing system according to claim 1, characterized in that: The SMI read / write module (200) has an idle state and an SMI write state; In the idle state, waiting for a write request or a read request sent by a user module (100); When the SMI read / write module (200) receives a clock signal and write request information, it jumps to an SMI write state according to a write request of the write request information; In the SMI write state, the output enable signal is set to 1 and the clock signal is counted; according to the value of the write counter, a total of 32 bits of data, including a 2-bit start code, a 2-bit operation code, a 5-bit phy chip address, a 5-bit register address, a 2-bit turn code and 16-bit output data, are written bit by bit into the output buffer signal in accordance with the SMI protocol. When the write counter reaches 33, it jumps to the write end state; In the write completion state, the write count is stopped, the write counter is cleared, and a transmission completion signal is fed back to the user module (100).

3. An SMI interface reading and writing system according to claim 2, characterized in that: The SMI read-write module (200) also has an SMI read state; When the SMI read / write module (200) receives a clock signal and read request information, it jumps to the SMI read state according to the read request of the read request information, sets the output enable signal to 1 and counts the clock signal; In the SMI read state, the 2-bit start code, 2-bit operation code, 5-bit phy chip address, and 5-bit register address are written bit by bit into the data input and output signal in accordance with the SMI protocol, and when the count reaches 15, the output enable signal is set to 0 and jumps to the read flip state; In the read flip state, when the count reaches 17, it jumps to the read data state; In the read data state, each rising edge of the clock stores the value of the input and output signals bit by bit into the 16-bit read data signal; when the read counter reaches 33, it jumps to the read end state; In the read completion state, the read count is stopped, the read counter is cleared, and a transmission completion signal is fed back to the user module (100); after receiving the transmission completion signal, the user module (100) reads the data in the read data signal.

4. The SMI interface reading and writing system according to claim 1, characterized in that: The SMI read / write module (200) is communicatively connected to the PHY chip module (300) via an mdc signal line and an mdio signal line.

5. The SMI interface reading and writing system according to claim 1, characterized in that: The SMI read / write module (200) is further configured to set a data valid signal to 1 and feed back the signal to the user module (100) after the data input / output signal is sent to the user module (100).

6. A SMI interface reading and writing method, implemented based on an SMI interface reading and writing system according to any one of claims 1 to 5, characterized in that: The method comprises the following steps: When a clock signal and write request information are received, data is written bit by bit into an output buffer signal according to the clock signal and the write request information in accordance with the SMI protocol, and a transmission completion signal is fed back to the user module (100); the write request information at least includes: a PHY chip address, a register address, a write request and a write data signal; When the output enable signal is 1, transmitting the output buffer signal to the register of the PHY chip module (300); When a clock signal and read request information are received, data is written bit by bit into a data input / output signal according to the clock signal and the read request information in accordance with the SMI protocol, and a transmission completion signal is fed back to the user module (100); the read request information at least includes: a PHY chip address, a register address and a read request; When the output enable signal is 0, the data input and output signal is transmitted to the SMI read-write module (200); the user module (100) is used to obtain the data in the read data signal when receiving the transmission completion signal; The data input and output signal, when the output enable signal is 0, the data input and output signal transmission direction is from the PHY chip module (300) to the SMI read and write module (200); The data input and output signal, when the output enable signal is 1, the data input and output signal transmission direction is from the SMI read / write module (200) to the PHY chip module (300).

7. A SMI interface reading and writing method according to claim 6, characterized in that: According to the clock signal and the write request information, writing the data bit by bit into the output buffer signal according to the SMI protocol specifically includes the following steps: When the SMI read / write module (200) receives a clock signal and write request information, it jumps to an SMI write state according to a write request of the write request information; In the SMI write state, the output enable signal is set to 1 and the clock signal is counted; according to the value of the write counter, a total of 32 bits of data, including a 2-bit start code, a 2-bit operation code, a 5-bit phy chip address, a 5-bit register address, a 2-bit turn code and 16-bit output data, are written bit by bit into the output buffer signal in accordance with the SMI protocol. When the write counter reaches 33, it jumps to the write end state; In the write completion state, the write count is stopped, the write counter is cleared, and a transmission completion signal is fed back to the user module (100).

8. The SMI interface reading and writing method according to claim 6, characterized in that: According to the clock signal and the read request information, writing the data bit by bit into the data input / output signal according to the SMI protocol specifically comprises the following steps: When the SMI read / write module (200) receives a clock signal and read request information, it jumps to the SMI read state according to the read request of the read request information, sets the output enable signal to 1 and counts the clock signal; In the SMI read state, the 2-bit start code, 2-bit operation code, 5-bit phy chip address, and 5-bit register address are written bit by bit into the data input and output signal in accordance with the SMI protocol, and when the count reaches 15, the output enable signal is set to 0 and jumps to the read flip state; In the read flip state, when the count reaches 17, it jumps to the read data state; In the read data state, each rising edge of the clock stores the value of the input and output signals bit by bit into the 16-bit read data signal; when the read counter reaches 33, it jumps to the read end state; In the read completion state, the read count is stopped, the read counter is cleared, and a transmission completion signal is fed back to the user module (100); after receiving the transmission completion signal, the user module (100) reads the data in the read data signal.

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