In-memory computing device having at least improved digital detector for more accurate current measurement

Abstract

The present disclosure relates to an in-memory computing device having at least an improved digital detector for more accurate current measurement. An in-memory computing device receives an input signal and provides an output signal. The apparatus includes a memory array having memory cells coupled to a word line receiving a word line activation signal indicative of an input signal and coupled to a bit line generating a bit line current; and a digital detector for sampling the bit line current and, in response, providing an output signal. The digital detector includes: a control stage comparing a bit line current with at least one reference current and generating a corresponding control signal; a selection stage generating a total selection current based on the first bit line current and based on a control signal; an integration stage sampling a total selection current; and a charge counter stage generating an output signal based on the sampled first total selection current and the control signal.

Description

[0001] Priority declaration

[0002] This application claims the benefit of priority from Italian Patent Application No. 102023000016299, filed on August 1, 2023, the contents of which are incorporated herein by reference in their entirety to the maximum extent permitted by law. Technical Field

[0003] The present invention relates to an in-memory computation (IMC) device having at least an improved digital detector for more accurate current measurement. The IMC device allows multiplication and accumulation operations to be performed, and the improved digital detector allows the current generated by the IMC device to be sampled in a more uniform and less dependent manner on the value of the generated current, thereby improving the measurement accuracy and thus improving the computational performance of the IMC device.

[0004] Furthermore, the present invention relates to a control method of an IMC device. Background Art

[0005] In-memory computing devices are known to use a specific arrangement of memory cells of a memory array to perform analog data processing at the cell level.

[0006] For example, in-memory computing devices are used to perform multiply and accumulate (MAC) operations, which are used, for example, to implement machine learning algorithms such as neural networks.

[0007] The multiplication and accumulation operation is provided as input vector x1,…,x N And calculate the weight g ij The vector or matrix product of the output vector y1,…,y M ,For example:

[0008] Right now:

[0009]

[0010] The in-memory computing device will calculate the weight g ij Stored in memory cells, and multiplication and summation operations are performed at the cell level.

[0011] In detail, for each output vector y i , the known in-memory device generates a current indicative of a corresponding MAC operation, namely And includes a read circuit having a corresponding analog-to-digital converter (ADC) for discretizing the current.

[0012] The in-memory computing device allows avoiding the transfer of data back and forth between the memory and the processing circuit. Therefore, the performance of the in-memory computing device is not limited by the data transfer bandwidth between the memory and the processing circuit, and has low power consumption.

[0013] However, it is recognized that in known in-memory computing devices, the measured current indicative of MAC operations is subject to errors due to the operation of the ADC. Therefore, the known in-memory computing devices have low computing accuracy.

[0014] In particular, the ADC has a non-linear behavior in response to the current to be measured, especially at high currents.

[0015] In fact, ideally, the charge packet measured by the ADC in response to the current at the ADC input should be independent of the current to be measured, thereby ensuring accurate measurement that is not dependent on the value of this same current to be measured. In other words, ideally, each measured charge packet should have the same amount of charge.

[0016] However, it has been demonstrated that in practice the amount of charge present in the charge packet being measured varies depending on the current being measured.

[0017] In fact, if Figure 1 As shown, during the measurement of each charge packet, the ADC reaches the switching threshold voltage V th,sw There is a delay interval t between the moment when the predetermined charge amount is reached (indicating that the predetermined charge amount identifies an ideal charge packet and should ideally result in the switching of the feedback loop of the ADC as a result) and the moment when the feedback loop of the ADC actually switches to terminate the measurement of the charge packet under consideration. d During the delay interval t d During this period, although the switching threshold voltage V th,sw , but the ADC continues to measure the current. This results in each charge packet having an additional and unwanted amount of charge that is d obtained during the period and hereinafter referred to as Q add The additional charge Q add Depends on the delay interval t d (However, the delay interval t d is usually constant, since it depends almost exclusively on the design of the ADC) and the current measured by the ADC at that moment, and in particular, it increases as said current increases. For example, Figure 1 shows the Figure 1The three voltage lines V shown have three different angles corresponding to the three currents). Therefore, as the current to be measured changes, the amount of additional charge also changes, whereby the current is discretized into charge packets that are not uniform with each other.

[0018] like Figure 2 As shown, the amount of charge actually received by the ADC at the input is Q real changes, so the additional charge Q measured by the ADC add The trend is nonlinear and its relative to the reference case (where the additional charge Q add The offset (independent of the input current) is minimal at low currents and increases as the current increases. Therefore, especially at high currents, the measurements made by known types of ADCs are inaccurate and do not correspond to the actual current generated by the in-memory computing device.

[0019] Obviously, this reduces the accuracy of the measurement of the current generated by the in-memory computing device, thereby reducing its computing performance.

[0020] A known solution to this problem is to reduce the frequency of the charge counter of the ADC, for example by increasing the size and storage capacity of the storage capacitor of the ADC, or to reduce the current at the input of the ADC. However, reducing the frequency of the charge counter results in a reduction in the measurement resolution (because fewer bits are available) or an increase in the time required to perform the measurement.

[0021] Another known solution is to use a "feed-forward" circuit in the ADC to dynamically update the switch threshold voltage V according to the current at the input of the ADC. th,sw However, this requires a complex and expensive calibration process.

[0022] Another known solution is to use a post-processing method to replace the actual measured current value with the actual current value. For example, this is achieved by using a lookup table in which each actual measured current value (i.e., the current value affected by the additional charge amount Q in each measured charge packet) is replaced by add The effect of the error caused by the error) is associated with the corresponding current value actually generated by the calculation device in the memory. However, this solution is only effective if the current to be measured remains constant during the period of integration of the ADC.

[0023] In other words, none of the currently known solutions is able to solve the problems listed above in an optimized manner.

[0024] There is a need in the art to overcome the above-mentioned shortcomings. Summary of the invention

[0025] According to the present invention, an in-memory computing device and a control method thereof are provided.

[0026] In one embodiment, an in-memory computing (IMC) device is configured to receive input signals indicating multiple input values ​​and is configured to provide at least output signals indicating multiple output values. The IMC device includes: a word line activation circuit configured to receive the input signal and configured to provide multiple word line activation signals, each word line activation signal is based on a corresponding input value of the input values; a bias circuit configured to provide a bias voltage; a memory array including a plurality of first memory cells, the plurality of first memory cells are coupled to a first bit line and each is coupled to a corresponding word line, the first bit line is configured to receive the bias voltage, the first memory cells are configured to each store a corresponding calculation weight and are configured to each receive a corresponding word line activation signal from the corresponding word line, the first memory cells are configured to each be traversed by a corresponding cell current according to the bias voltage, according to the corresponding word line activation signal and according to the corresponding calculation weight, the first bit line is configured to be traversed by a first bit line current, the first bit line current is a sum of the cell currents; and a first digital detector coupled to the first bit line and configured to sample the first bit line current and provide the output signal in response to the first bit line current.

[0027] The first digital detector includes: a control stage, electrically coupled to the first bit line and configured to receive the first bit line current, generate at least a first main control mirror current in response to the first bit line voltage, compare the first main control mirror current with at least a first reference current, and generate one or more control signals indicative of the comparison; a selection stage, electrically coupled to the control stage and the first bit line and configured to receive the first bit line current and the one or more control signals, and generate a total selection current in response to the first bit line current and based on the one or more control signals; an integration stage, electrically coupled to the selection stage and configured to receive and sample the total selection current; and a charge counter stage, electrically coupled to the integration stage and to the control stage, and configured to receive the sampled total selection current and the one or more control signals, and generate the output signal based on the one or more control signals in response to sampling of the first total selection current.

[0028] In one embodiment, a method for controlling an in-memory computing (IMC) device (such as the aforementioned device) includes: providing the multiple word line activation signals to the first memory cell through a word line activation circuit; generating a bias voltage through a bias circuit and applying the bias voltage to a first bit line; generating the at least first master control mirror current through a control stage in response to the first bit line current; comparing the at least first master control mirror current with the at least first reference current through the control stage; generating the one or more control signals indicating the comparison through the control stage; generating a total selection current through a selection stage in response to the first bit line current and according to the one or more control signals; sampling the total selection current through an integration stage; and generating the output signal through a charge counter stage in response to sampling the first total selection current according to the one or more control signals. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] For a better understanding of the present invention, preferred embodiments will now be described, by way of non-limiting examples only, with reference to the accompanying drawings, in which:

[0030] Figure 1 and Figure 2 is a graph of the corresponding electrical quantities generated by a known type of in-memory computing device;

[0031] Figure 3 A block diagram of one embodiment of an in-memory computing device is shown;

[0032] Figure 4 Shows Figure 3 A circuit diagram of a line activation circuit of a computing device in a memory;

[0033] Figure 5 Shows Figure 4 A circuit diagram of a timer of a line activated circuit;

[0034] Figure 6 Shows Figure 5 A detailed circuit diagram of a portion of a timer;

[0035] Figure 7 Shows Figure 4 Circuit diagram of the line activation circuit input to the time converter,

[0036] Figure 8 Shown by Figure 7 An example of an activation signal provided by the input to the time converter;

[0037] Fig. 9 Shows Figure 3 A circuit diagram of a digital detector of an in-memory computing device;

[0038] Fig.10 Shows Fig. 9 A detailed circuit diagram of a portion of a digital detector;

[0039] Fig.11 Shown in use by Fig. 9 An exemplary waveform generated by a digital detector of

[0040] Fig.12 Shows Figure 3 A circuit diagram of a bias circuit of a memory computing device. DETAILED DESCRIPTION

[0041] In the following description, the same reference numerals are used to indicate elements common to different embodiments.

[0042] Figure 3 An in-memory computing device 10 (hereinafter also referred to as IMC device 10) is shown, which includes a computing memory array (or matrix) 12 (hereinafter referred to as memory array 12), a word line activation circuit 14, a plurality of digital detectors 16 and a bias circuit 18.

[0043] The memory array 12 is of the non-volatile type and comprises a plurality of memory cells 20 organized according to a matrix arrangement having M columns and N rows.

[0044] The memory array 12 is configured to respond to input data x1, . . . , x n (usually n≤N, in Figure 3 In the example, in particular, a multiplication and accumulation (MAC) operation is performed on an input vector (or signal) X having n=N to generate output data y1, ..., y m (usually m≤M, in Figure 3 In the example, specifically the output vector (or signal) Y of m=M).

[0045] The memory cells 20 arranged in the same column are connected to the corresponding bit lines BL i The memory cells 20 arranged in the same row are connected to each other through corresponding word lines WL j are connected to each other, where j=1,…,N.

[0046] In practice, the corresponding word line WL j and the corresponding bit line BL i Associated with each memory unit 20 .

[0047] The memory cells 20 are programmed to store the corresponding calculated weights g ij , the weight g ij Can be used as weights to perform in-memory calculations such as multiply and accumulate operations.

[0048] The word line activation circuit 14 provides a plurality of word line activation signals 21 (each word line WL j A word line activation signal), which is configured to activate the corresponding word line WL j Each memory cell 20, as discussed in detail below.

[0049] The word line activation circuit 14 receives the plurality of input values ​​x1, . . . , x n The input vector X, for example, Figure 3 As schematically shown, each word line WL j An input value.

[0050] The word line activation signal 21 is a pulse (particularly, a rectangular pulse here), and the duration of each pulse (ie, the pulse width) is determined according to the corresponding input value x. j of.

[0051] The bias circuit 18 generates a bias voltage Vr in a manner known per se and supplies the bias voltage Vr to the bit lines BL1, . . . , BL M A bias voltage Vr is provided, as discussed in detail below. Specifically, Figure 3 As shown, the bias circuit 18 is electrically coupled to the bit lines BL1, . . . , BL M , for example between the memory unit 20 and the digital detector 16 .

[0052] In this embodiment, the bias circuit 18 provides bias current to all bit lines BL1, . . . , BL M However, according to the specific application, the bias circuit 18 can provide the same voltage Vr for the bit lines BL1, . . . , BL M Bias voltages different from each other are provided.

[0053] The digital detectors 16 are analog-to-digital converters (ADCs) each coupled to a corresponding bit line BL i , and each flows through the corresponding bit line BL by sampling i The current I BL,i To provide the corresponding output data y i .

[0054] The memory cells 20 each include a storage element 25 and a selection element 26 .

[0055] The storage element 25 of each memory cell 20 is a variable resistance element, in particular here a variable resistance element based on a phase change material (PCM) such as, for example, chalcogenide.

[0056] In detail, the weight g is calculated ijφ indicates a transconductance value of the storage element 25 of the corresponding memory cell 20 , ie, it indicates a programmed resistance of the storage element 25 .

[0057] Phase change materials have at least two phase states, such as an amorphous phase and a crystalline phase, and each phase state has a corresponding resistivity.

[0058] Phase change materials can be transformed from one phase state to another by means of heat transfer (eg using an electric current pulse).

[0059] The resistance of each storage element 25 associated with the respective phase state is used to distinguish between two or more logic states of the corresponding memory cell 20 .

[0060] For example, the amorphous phase may have a higher resistance than the crystalline phase. A logic state "0" (or reset state) may be associated with the amorphous phase of storage element 25. A logic state "1" (or set state) may be associated with the crystalline phase of storage element 25.

[0061] The first terminal of the storage element 25 is coupled to the corresponding bit line BL i The node 28 of the embodiment of the present invention is connected to the reference potential node (here, ground 29) through the selection element 26, and the second terminal is coupled to the reference potential node (here, ground 29) through the selection element 26.

[0062] The selection element 26 is a switch, such as a BJT transistor, a diode or a MOS transistor, here an NMOS transistor, which is arranged in series with the corresponding storage element 25 and whose switching is controlled by the corresponding word line WL j The word line activation signal 21 controls.

[0063] In this embodiment, the source of the NMOS transistor forming the selection element 26 is coupled (directly connected here) to the ground 29; its drain is coupled (directly connected here) to the second terminal of the storage element 25; and its gate is coupled (directly connected here) to the corresponding word line WL j .

[0064] In practice, the storage element 25 and the selection element 26 form a current path of the corresponding memory cell 20; the selection element 26 closes the corresponding current path in response to receiving the corresponding activation signal 21, thereby allowing the cell current i cell Flows from the common node 28 to ground 29.

[0065] The IMC device 10 may further include a plurality of components coupled to the bit lines BL1, . . . , BL M The interface circuit 30 can be used, for example, to modify the transconductance value g stored in the storage element 25 in a manner known per se. ij Programming.

[0066] In addition, the IMC device 10 may further include a control circuit 31, which is operably coupled to the word line activation circuit 14, the digital detector 16, and the interface circuit 30 to control these components of the IMC device. Alternatively, the control circuit 31 may be external to the IMC device 10 and operably coupled to the IMC device 10 to operate in a manner similar to that previously described. In this case, the IMC device 10 and the control circuit 31 are included in an in-memory computing device (not shown), for example.

[0067] Figure 4 A detailed and exemplary embodiment of the word line activation circuit 14 is shown.

[0068] The word line activation circuit 14 includes a timer (or a main counter) 45 that provides a timer signal TM and a plurality of inputs to a time converter 46 (one for each word line WL1, . . . , WL N one).

[0069] The plurality of input-to-time converters 46 each receive a timer signal TM and a corresponding input value x j , and in response, provides a corresponding word line activation signal 21.

[0070] The word line activation circuit 14 also receives an address signal ADR, which indicates which word lines WL are to be activated. j For example, the address signal ADR may be generated by the control circuit 31 and may be used to make only the word line WL j For example, if the input data x of the input vector X j The number n max Below the word line WL of the memory array 12 j The number of words is N.

[0071] For example, the address signal ADR may be an N-bit digital signal ADR j , where j = 1, ..., N (ie, each word line WL j A). Each bit of the address signal ADR j Corresponding to the corresponding word line WL j and can be, for example, on the word line WL j To be enabled, the word line WL j To be disabled, equal to logic 0. For example, ADR = '111...1000' means that the last three word lines WL j is not used, while the remaining word lines are used.

[0072] According to one embodiment, the timer 45 responds to the power supply current (hereinafter referred to as the reference current I REF) and provide a timer signal TM. For example, the reference current I REF By a current source (of known type, Figure 5 32 in the figure) is generated in a manner known per se.

[0073] The timer signal TM is an L-bit digital signal, also indicated as the timer signal TM below and in the drawings. <l:1>, which updates the frequency f according to the power supply current u Increases over time.

[0074] In practice, the timer signal TM is a counter signal.

[0075] The timer 45 may reset the timer signal TM to a start value, eg to zero, at the start of a new calculation to be performed by the IMC device 10 , eg in response to receiving a start signal from a user of the IMC device 10 .

[0076] According to one embodiment, again referring to Figure 4 , the word line activation circuit 14 may further include a calculation completion comparator 170 .

[0077] The calculation is completed. The comparator 170 receives the timer signal TM. <l:1>and the maximum count signal MAX_COUNT <l:1>, and in response, provides a count end signal END.

[0078] Maximum count signal MAX_COUNT <l:1>may be configured by the user of the IMC device 10 and indicates the maximum duration of a calculation performed by the IMC device 10. For example, when the corresponding bit line BL i When all the associated memory cells 20 are activated, the maximum count signal MAX_COUNT <l:1>Can indicate equal to or greater than any output data y i The maximum duration of time that will be consumed to reach the corresponding maximum value (e.g. all bits equal to 1). However, the maximum count signal MAX_COUNT <l:1>A lower maximum duration may also be indicated, for example, if a shorter calculation time of the IMC device 10 is desired.

[0079] Reference Figure 5 and Figure 6 One exemplary and non-limiting embodiment of the timer 45 is described in detail.

[0080] exist Figure 5 In the embodiment, the timer 45 includes a current mirror 180 and a counting part 181. The current mirror 180 responds to the reference current I REF The oscillator current I OSC , the counting part 181 is based on the oscillator current I OSC A timer signal TM is provided.

[0081] The mirror ratio of current mirror 180 is 1:p, so that the oscillator current I OSC p·I REF .

[0082] In detail, the current mirror 180 has a first branch and a second branch, wherein the first branch is formed by a corresponding PMOS transistor 183 and coupled to the current source 32 , and wherein the second branch is formed by a corresponding PMOS transistor 184 and coupled to the counting part 181 .

[0083] The sources of the PMOS transistors 183, 184 are coupled to a power supply node 185 (here at a power supply voltage VDD), and the gates of the PMOS transistors 183 and 184 are coupled to each other and to the drain of the PMOS transistor 183. The drain of the PMOS transistor 184 is coupled (particularly, directly connected) to an input node 187 of the counting portion 181.

[0084] The counting part 181 of the timer 45 includes an integration stage 190 and a counter stage 195. The integration stage 190 is formed here by a first integration circuit 191, a second integration circuit 192 and a switch circuit 193 coupled between the first and second integration circuits 191 and 192. The counter stage 195 is coupled to the integration stage 190 and provides a timer signal TM.

[0085] The first integrator circuit 191 and the second integrator circuit 192 are coupled to the input node 187 to receive the oscillator current I OSC .

[0086] The first integrator circuit 191 includes a first inverter 197 having an output 198, a first integrator circuit 198 having a capacitor C′ coupled to the output 198 of the first inverter 197, and a first integrator circuit 199 having a capacitor C′ coupled to the output 198 of the first integrator circuit 199. A A capacitor 199 and a second inverter 200 whose input is coupled to the output 198 of the first inverter 197.

[0087] The power supply node of the first inverter 197 is coupled to the input node 187 of the counting section 181 ( Figure 6 ), and receives a first oscillator control signal OS at the input A .

[0088] In practice, the first inverter 197 is driven by the oscillator current I OSC Bias.

[0089] A first terminal of the capacitor 199 is coupled to the output node 198 of the first inverter 197, and a second terminal thereof is coupled to a reference potential node (here, ground).

[0090] The output node 198 of the first inverter 197 is at the first oscillator integrated voltage V′ A , which voltage drops across capacitor 199.

[0091] The second inverter 200 has a first oscillator threshold V' th1 (hereinafter referred to as the first threshold V' th1 ), receiving the first oscillator integrated voltage V' at the input A , and according to the first threshold V' th1 and according to the first oscillator integrated voltage V' A A first oscillator switching signal S'1 is provided at the output.

[0092] In detail, when the first oscillator integrates the voltage V' A Below the first threshold V' th1 When the first oscillator integrated voltage V' A Above the first threshold V' th1 When , the first oscillator switch signal S'1 has a low logic value.

[0093] The second integrator circuit 192 includes a first inverter 202 having an output 203, a capacitor C′ coupled to the output 203 of the first inverter 202, and a B A capacitor 204 and a second inverter 205 whose input is coupled to the output 203 of the first inverter 202.

[0094] The power supply node of the first inverter 202 is coupled to the input node 187 of the counting section 181 ( Figure 6 ), and receives a second oscillator control signal OS at the input B .

[0095] In practice, the first inverter 202 is driven by the oscillator current I OSC Bias.

[0096] The capacitor 204 has a first terminal coupled to the output node 203 of the first inverter 202 and a second terminal coupled to a reference potential node (here, ground).

[0097] The output node 203 of the first inverter 202 is at the second oscillator integrated voltage V′ B , which voltage drops across capacitor 204 .

[0098] The second inverter 205 has a second oscillator threshold V' th2 (hereinafter referred to as the second threshold V' th2 ), receiving the second oscillator integrated voltage V' at the input B , and according to the second threshold V' th2 And according to the second oscillator integrated voltage V B A second oscillator switching signal S'2 is provided at the output.

[0099] In detail, when the second oscillator integrates the voltage V B Below the second threshold V' th2 When the second oscillator integrated voltage V' B Above the second threshold V' th2 When , the second oscillator switch signal S'2 has a low logic value.

[0100] Reference again Figure 5 The switch circuit 193 is a latch formed by two inverters 208, 209 arranged in a ring configuration, a first switch 210 controlled by a first oscillator switch signal S'1 and a second switch 211 controlled by a second oscillator switch signal S'2.

[0101] The switch circuit 193 has a first node 213 coupled to the input of the inverter 209 and to the output of the inverter 208 , and a second node 214 coupled to the output of the inverter 209 and to the input of the inverter 208 .

[0102] The first node 213 provides a first oscillator control signal OS A The second node 214 provides a second oscillator control signal OS B .

[0103] The first switch 210 is coupled to a first node 213 and a voltage V′ DD The second switch 211 is coupled between the second node 214 and the voltage V' DD between nodes.

[0104] exist Figure 5 In an embodiment of the present invention, the switch circuit 193 also receives an oscillator enable signal EN', which controls the activation of the switch circuit 193. For example, the oscillator enable signal EN' can be used to maintain the switch circuit 193 turned off when not in use, thereby allowing optimization of power consumption. In addition, the enable signal EN' can be used to set the switch circuit 193 to a defined state, such as when the IMC device 10 is turned on.

[0105] The counter stage 195 is coupled to the first and second nodes 213 , 214 of the switch circuit 193 .

[0106] In detail, the charge counter stage 195 includes an inverter 216, the input of which is coupled to the second node 214, and a counter, which includes an inverter 217 and a plurality of D-type flip-flops 218, the input of which is coupled to the first node 213, and the plurality of D-type flip-flops 218 including a first flip-flop 218.2, a second flip-flop 218.3 and a final flip-flop 218.L, where L is the timer signal TM <l:1>The number of digits.

[0107] In practice, the counter of the charge counter stage 195 has L−1 flip-flops 218 .

[0108] The output of the inverter 216 provides the first bit TM(1), ie the least significant bit, of the timer signal TM.

[0109] The flip-flops 218 are sequentially cascaded with each other from the first flip-flop 218 . 2 to the last flip-flop 218 .L.

[0110] The flip-flops 218 each have a clock input (CK-input), a data input (D-input), a Q-output, and -Output.

[0111] The CK-input of the first flip-flop 218.2 is coupled to the output of the inverter 217. The - output is fed back to the D- input of the first flip-flop 218.2. The Q- output of the first flip-flop 218.2 is the timer signal TM <l:1>The second TM(2).

[0112] The CK-input of the second flip-flop 218.3 is coupled to the CK-input of the first flip-flop 218.2. -Output.

[0113] The second trigger 218.3 The -output is fed back to the D-input of the second flip-flop 218.3.

[0114] The Q-output of the second flip-flop 218.3 is the timer signal TM <l:1>The third TM(3).

[0115] The description of the second flip-flop 218 . 3 applies mutatis mutandis to all subsequent flip-flops (also not shown) up to the L-1st flip-flop (not shown here).

[0116] Finally, the CK-input of the last flip-flop 218.L is coupled to the L-1th flip-flop - output. The last flip-flop 218.L The - output is fed back to the D-input of the last flip-flop 218.L. The Q-output of the last flip-flop 218.L is the timer signal TM <l:1>The most significant bit TM(L).

[0117] refer to Figure 6 1. In the detailed implementation of the integration stage 190 shown, the first inverter 197 of the first integration circuit 191 is a CMOS inverter formed by a series circuit of a PMOS transistor 220 and an NMOS transistor 221 commonly coupled to an output node 198. The PMOS and NMOS transistors 220, 221 receive the first oscillator control signal OS at their respective gate terminals. A .

[0118] The source of PMOS transistor 220 is coupled to input node 187 of integrating stage 190 of timer 45 .

[0119] The second inverter 200 of the first integrating circuit 191 is a CMOS inverter formed by a series circuit of a PMOS transistor 222 and an NMOS transistor 223 commonly coupled to a node 224 providing the first oscillator switching signal S′ 1 .

[0120] The first threshold V′ of the second inverter 200 th1 is the switching threshold of the second inverter and thus depends on the characteristics of the PMOS and NMOS transistors 222, 223, such as their threshold or on-resistance. In practice, the switching threshold may be the input voltage at which the output of the inverter has a high logic value, or the input voltage at which the output of the inverter has a low logic value.

[0121] For example, the switching threshold of the second inverter 200 may be defined as an operating point where the corresponding input voltage (ie, the first oscillator integrated voltage V'A) is equal to the corresponding output voltage (ie, the first oscillator switching signal S'1).

[0122] The first inverter 202 of the second integrating circuit 192 is a CMOS inverter formed by a series circuit of a PMOS transistor 225 and an NMOS transistor 226 commonly coupled to an output node 203. The PMOS and NMOS transistors 225, 226 receive a second oscillator control signal OS at respective gate terminals. B .

[0123] The source of PMOS transistor 225 is coupled to input node 187 of count portion 190 of timer 45 .

[0124] The second inverter 205 of the second integrating circuit 192 is a CMOS inverter formed by a series circuit of a PMOS transistor 227 and an NMOS transistor 228 commonly coupled to a node 229 providing the second oscillator switching signal S′ 2 .

[0125] The second threshold V′ of the second inverter 205 th2 is the switching threshold of the second inverter 205, and thus depends on the characteristics of the PMOS and NMOS transistors 227, 228, such as their thresholds or on-resistances. In practice, the switching threshold may be the input voltage at which the output of the inverter has a high logic value, or may be the input voltage at which the output of the inverter has a low logic value.

[0126] For example, the switching threshold of the second inverter 205 may be defined as an operating point where the corresponding input voltage (ie, the second oscillator integrated voltage V′B) is equal to the corresponding output voltage (ie, the second oscillator switching signal S′2 ).

[0127] like Figure 6 As shown in the detailed implementation, the first inverter and the second inverter 208, 209 of the switch circuit 193 are cross-coupled CMOS inverters, each of which includes a common series coupling at a power supply node (here at a voltage V' DD ) and ground.

[0128] In addition, the first inverter 208 and the second inverter 209 of the switch circuit 193 each include a corresponding enable switch (here, a PMOS transistor 232), which is coupled to the voltage V'. DD between the power supply node of the inverter and the PMOS transistor 230 of the corresponding inverter.

[0129] The PMOS transistor 232 is controlled by the oscillator enable signal EN′.

[0130] In this embodiment, refer to Figure 6 The timer 45 includes a first stop switch and a second stop switch (here, the first and second NMOS transistors 234 , 235 ) configured to stop the updating of the timer signal TM by the timer 45 .

[0131] In detail, the drain terminals of the first NMOS transistor 234 and the second NMOS transistor 235 are respectively coupled to the output nodes 198, 203 of the first integration circuit 191 and the second integration circuit 192; and their source terminals are coupled to the reference (here, ground). The first NMOS transistor 234 and the second NMOS transistor 235 receive the count end signal END at their respective gate terminals.

[0132] When the calculation is completed, the comparator 170 ( Figure 4 ) switches the end signal END to a high logic value, the first NMOS transistor 234 and the second NMOS transistor 235 are turned on, thereby short-circuiting the output nodes 198 and 203 of the first integration circuit 191 and the second integration circuit 192 to the ground.

[0133] Thus, the timer 45 stops updating the timer signal TM.

[0134] Thus, the timer 45 generates the timer signal TM by executing a plurality of successive timing iterations. <l:1>In each timing iteration, for example, the oscillator current I OSC The timing iteration of the first integration circuit 191 generates a first oscillator integrated voltage V' by the integration stage 190. A As the oscillator current I OSC The time integral of the first oscillator voltage V' A With the first threshold V' th,1 is compared, and in response to the first oscillator integrated voltage V' A Reaching the first threshold V' th,1 The first oscillator integrated voltage V' is reset A (Here, specifically, by switching the first oscillator control signal OS A The counter stage 195 responds to the first oscillator integrated voltage V' A Reaching the first threshold V' th,1 The update timer signal TM <l:1>.

[0135] In this embodiment, the least significant bit of the timer signal TM is the second oscillator control signal OS B The value of .

[0136] In other words, the timer 45 sets the oscillator current I OSC The oscillator current I is converted into a plurality of charge packets and counted. OSC Sampling is performed, wherein each charge packet corresponds to the charge accumulated on the capacitor 199 , 204 , which results in the switching of the second inverter 200 , 205 .

[0137] As a result, the timer signal TM <l:1>The update frequency f u The first oscillator control signal OS A The frequency of switching events is given by u Depends on the oscillator current I OSC (ie, the reference current I REF ) and depends on the mirror factor p of the current mirror 180, the capacitance C' A , C' B and the first and second thresholds V' of the second inverters 200 and 205 th,1 , V' th,2 .

[0138] In practice, the integrating stage 110 of the timer 45 behaves as a current controlled oscillator.

[0139] Reference Figure 7 , one embodiment of the input to the time converter 46 will now be described. In particular and by way of example only, Figure 7 The plurality of word lines WL1, ..., WL N Word line WL j The input to the time converter 46 j .

[0140] Input to Time Converter 46 j A comparator 50 is included which receives a timer signal TM <l:1>and the corresponding input value x j , and provides corresponding matching signals MTC in response to these inputs.

[0141] In this embodiment, the input data x j is also a digital signal. The comparator 50 (eg, a bit verification circuit based on an exclusive OR (XOR) logic gate) converts the input data x j With the timer signal TM <l:1>The comparison is made and the timer signal TM <l:1>becomes equal to the input data x j , the match signal MTC is asserted to a high logic value.

[0142] Input to Time Converter 46 j It also includes a pulse generating circuit (here formed by a NAND logic gate 51 and an inverter 52) which provides a pulse to the word line WL j A corresponding word line activation signal 21 is provided.

[0143] The NAND logic gate 51 receives the matching signal MTC and the address signal ADR (specifically, the bit ADR j ), the address signal ADR indicates whether the word line WL should be activated during the execution of the calculation in the memory j If the word line WL is activated during the calculation in the memory j , then the address signal ADR can have a high logic value.

[0144] Inverter 52 is coupled at an input to the output of NOT logic gate 51 and provides word line activation signal 21 at an output. In practice, inverter 52 operates as a logic gate for the corresponding word line WL j The driving circuit.

[0145] Reference word line WL j As long as the timer signal TM <l:1>Different from the input data x j , input to the time converter 46 to maintain the corresponding word line activation signal 21 at a high logic value (ie, here, thereby activating the word line WL coupled to the j The selection element 26 of the memory cell 20).

[0146] Therefore, each word line activation signal 21 has a corresponding activation length T j The activation length is related to the timer signal TM <l:1>The update frequency f u proportional to and corresponding to the input data x j Proportional.

[0147] Figure 8 The first word line WL1 and the last word line WL N The word line activation signal 21.

[0148] When the calculation of the IMC device 10 starts (time t0), the timer signal TM is reset to a starting value, and the inputs to the time converters 46 each switch the corresponding word line activation signal 21 to a high value.

[0149] exist Figure 8 In the example, the input data x1 associated with the first word line WL1 is lower than the input data x2 associated with the last positive word line WL N The associated output data x N Therefore, relative to the last word line WL N The associated input to the time converter 46, the input to the time converter 46 associated with the first word line WL1 maintains the corresponding word line activation signal 21 at a high value for a shorter time. This means that the activation length T1 of the word line activation signal 21 of the first positive word line WL1 is shorter than that of the last word line WL N The activation length T of the word line activation signal 21 N .

[0150] In use, the IMC device 10 can be used to perform an operation on an input vector X=x1, . . . , x N and the weight g is calculated by ij The multiplication and accumulation (MAC) operation between the matrices is formed.

[0151] In fact, each memory cell 20 sinks a cell current i cell (here, from the corresponding node 28 to ground 29) depends on the transconductance g of the corresponding storage element 25 ij , and depends on the activation time T of the corresponding selection element 26 j , that is, depends on the pulse length of the corresponding word line activation signal 21.

[0152] In detail, each unit current i cell The absolute value of depends on the corresponding transconductance g ij . Each unit current i cell The duration depends on the corresponding activation time T j .

[0153] Therefore, the charge can be related to each unit current i cell The charge is related to the corresponding transconductance value gij and the corresponding activation time T j of.

[0154] Since the pulse length of the word line activation signal 21 is determined according to the corresponding input value x j Therefore, each unit current i cell The associated charge is calculated from the product g ij ·x j of.

[0155] For each bit line BL i , the corresponding bit line current I BL,i is the unit current i cell Therefore, with each bit line current I BL,i The total charge associated is calculated from the multiplication and accumulation operation g i1 x1+g i2 ·x2+…+g iN ·x N of.

[0156] Therefore, by measuring the corresponding bit line current I BL,i (particularly by the corresponding bit line current I BL,i Each output data y obtained by integrating i Indicates MAC operation g i1 x1+g i2 ·x2+…+g iN ·x N .

[0157] exist Figure 3 In the exemplary embodiment shown and considered here, each bit line I BL,i The digital detectors 16 are electrically connected to corresponding ones of the digital detectors 16. Each digital detector 16 is configured to measure the current flowing into the corresponding bit line I BL,i The bit line current I BL,i , and generate the corresponding output data y i .

[0158] Fig. 9 One embodiment of the digital detector 16 is shown. In detail, the following reference is made to the plurality of bit lines BL1, . . . , BL M Any bit line BL i The digital detector 16 will be described with reference to the digital detector 16 of FIG.

[0159] The digital detector 16 includes a control stage 101 , a selection stage 102 , an integration stage 110 , and a charge counter stage 111 .

[0160] The control stage 101 and the selection stage 102 are electrically connected to the bit line BL i , and specifically includes and shares a main current mirror 115, which converts the bit line BL i The bit line current I BL,i The input branches of the main current mirror 115 are mirrored in the plurality of control input branches 103a, 103b of the control stage 101 and the selection input branches 103c, 103d and 103e of the selection stage 102 (the output branches of the main current mirror 115).

[0161] The main current mirror 115 has a respective mirror ratio for each of the considered input branches 103a, 103b, 103c, 103d and 103e.

[0162] Specifically, the main current mirror 115 has a main control mirror ratio of 1:k1 for both the first control input branch 103a and the second control input branch 103b of the control stage 101 (usually k1≤1, and in detail, in the embodiment considered here, the main control mirror ratio 1:k1 is exemplarily unity, i.e. k1=1), a first selection mirror ratio 1:k2 for the first selection input branch 103c of the selection stage 102 (in the example considered here, k2=1 / 4), a second selection mirror ratio 1:k3 for the second selection input branch 103d of the selection stage 102 (in the embodiment considered here, it is equal to the first selection mirror ratio 1:k2, and in the embodiment considered here, k2=k3=1 / 4), and a third selection mirror ratio 1:k4 for the third selection input branch 103e of the selection stage 102 (the mirror coefficient is equal to twice the mirror coefficient of the first selection mirror ratio 1:k2, and in the example considered here, k4=1 / 2). In this way, the main control mirror current k1·I BL,i (here it is equal to the bit line current I BL,i , because k1 = 1) flows through both the first control input branch 103a and the second control input branch 103b, the first selected mirror current k2·I BL,i Flows through the first selection input branch 103c, and the second selection mirror current k3·I BL,i flows through the second selection input branch 103d, and the third selection mirror current k4·I BL,i Flows through the third selection input branch 103e.

[0163] In detail, the main current mirror 115 has a first branch coupled to the bit line BLi (here, it is formed by a corresponding input PMOS transistor 117) and a plurality of second branches connected in parallel to each other, namely, input branches 103a, 103b, 103c, 103d and 103e of the control stage 101 and the selection stage 102. The input branches 103a, 103b, 103c, 103d and 103e are formed by corresponding output PMOS transistors 118a, 118b, 118c, 118d and 118e here. The first output PMOS transistor and the second output PMOS transistor 118a, 118b are included in the control stage 101, and the third output PMOS transistor to the fifth output PMOS transistor 118c-118e are included in the selection stage 102.

[0164] Specifically, the input PMOS transistor 117 is coupled to the bit line BL via the decoupling NMOS transistor 114. i The decoupling NMOS transistor is included in the control stage 101 and has its gate connected to the bias circuit 18 to receive the bias voltage Vr and its drain coupled to the bit line BL. i To receive the bit line current I BL,i , the source is coupled to the input PMOS transistor 117. In fact, the decoupling NMOS transistor 114 allows the bit line BL i The voltage on φ1 remains constant. Nevertheless, the decoupling NMOS transistor 114 may be replaced by any known type of circuit block that operates in a similar manner.

[0165] The sources of the PMOS transistors 117, 118a-118e are coupled to the corresponding power supply node 120 (here coupled to the power supply voltage V DD ), and the gate of the input PMOS transistor 117 is coupled to each gate of the output PMOS transistors 118a-118e and to the drain of the input PMOS transistor 117. The drain of the first output PMOS transistor 118a is coupled (particularly, directly connected here) to the first control input node 104a of the control stage 101; the drain of the second output PMOS transistor 118b is coupled (particularly, directly connected here) to the second control input node 104b of the control stage 101; the drain of the third output PMOS transistor 118c is coupled (particularly, directly connected here) to the selection common node 116 (hereinafter also referred to as the input node 116 of the integration stage 110); the drain of the fourth output PMOS transistor 118d is coupled The drain of the fifth output PMOS transistor 118e is coupled (particularly, directly connected here) to the first selection switch 105a of the selection stage 102, which is inserted in the second selection input branch 103d between the fourth output PMOS transistor 118d and the selection common node 116; the drain of the fifth output PMOS transistor 118e is coupled (particularly, directly connected here) to the second selection switch 105b of the selection stage 102, which is inserted in the third selection input branch 103e between the fifth output PMOS transistor 118e and the selection common node 116.

[0166] Therefore, as better described below, the first control input node 104a receives the main control mirror current k1·I BL,i The second control input node 104b receives the control mirror current k1·I BL,i , select the common node 116 to receive at least the first selected mirror current k2·I BL,i , the first selection switch 105a receives the second selection mirror current k3·I BL,i , and the second selection switch 105b receives the third selection mirror current k4·I BL,i .

[0167] The control stage 101 also includes a secondary current mirror 144, which is on the opposite side relative to the primary current mirror 115, and biases the bias current I bias is mirrored in the first control input node 104a of the control stage 101 and in the second control input node 104b. In other words, the secondary current mirror 144 biases the current I bias Mirrored in a first output branch 149a and a second output branch 149b, wherein the first output branch 149a is coupled to the first control input node 104a and extends on the opposite side of the first control input node 104a relative to the main current mirror 115, and the second output branch 149b is coupled to the second control input node 104b and extends on the opposite side of the second control input node 104b relative to the main current mirror 115.

[0168] For example, the bias current I bias is generated by a current generator 148 of a type known per se. The current generator 148 may be external to the digital detector 16, or may be internal thereto, for example, it may be provided by a bandgap circuit.

[0169] The secondary current mirror 144 has a corresponding mirror ratio for each of the considered output branches 149a and 149b. Specifically, the secondary current mirror 144 has a first secondary control mirror ratio 1: p1 for the first output branch 149a, and a second secondary control mirror ratio 1: p2 for the second control input branch 103b. The first secondary control mirror ratio and the second secondary control mirror ratio 1: p1, 1: p2 are different from each other and are usually also different from the main control mirror ratio 1: k1.

[0170] In detail, the first secondary control mirror ratio 1:p1 has a mirror coefficient p1 which is greater than (particularly, twice) a mirror coefficient p2 of the second secondary control mirror ratio 1:p2. For example, p1=4, p2=2.

[0171] In this way, the first secondary control mirror current p1·I bias Flowing through the first output branch 149a, the second secondary control mirror current p2·I bias The first secondary control mirror current and the second secondary control mirror current p1·I bia and p2·I bias Different from each other, in particular, p1·I bias >p2·I bias , because p1>p2 has been considered. In the example considered here where p1>1 and p2>1, the first secondary control mirror current and the second secondary control mirror current p1·I bias and p2·I bias Greater than the bias current I bias In the embodiment exemplarily considered here, since p1=4, the first secondary control mirror current p1·I bias Equal to the bias current I bias and since p2 = 2, the second secondary control mirror voltage p2·I bias Equal to the bias current I bias twice as much.

[0172] On the contrary, the bias current I bias When the first secondary control mirror current and the second secondary control mirror current p1·I are relatively high, the first secondary control mirror current and the second secondary control mirror current p1·I bias and p2·I bias p1<1 and p2<1 are selected in a way that the same value of p1 is obtained (for example, p1=1 / 2 and p2=1 / 4).

[0173] In detail, the secondary current mirror 144 has a first branch (here formed by the corresponding input NMOS transistor 173) coupled to the current generator 148, and a plurality of second branches (i.e., first and second output branches 149a, 149b) connected in parallel to each other. The output branches 149a and 149b are here formed by corresponding output NMOS transistors 174a and 174b (in detail, first and second output NMOS transistors 174a and 174b, respectively).

[0174] The sources of the NMOS transistors 173, 174a and 174b are coupled to a reference (here, ground), while the gate of the input NMOS transistor 173 is coupled to each gate of the output NMOS transistors 174a and 174b and to the drain of the input NMOS transistor 173. The drain of the first output NMOS transistor 174a is coupled (in particular, directly connected here) to the first control input node 104a of the control stage 101, and the drain of the second output NMOS transistor 174b is coupled (in particular, directly connected here) to the second control input node 104b of the control stage 101.

[0175] Therefore, the first control input node 104a also receives the first secondary control mirror current p1·I bias The second control input node 104b also receives the second secondary control mirror current p2·I bias .

[0176] Therefore, when the main control mirror current k1·I BL,i Greater than the first secondary control mirror current p1·I bias When the first control input node 104a becomes the power supply voltage V DD ; Vice versa, when the main control mirror current k1·I BL,i Less than the first secondary control mirror current p1·I bias , it becomes ground voltage. Similarly, when the main control mirror current k1·I BL,i Greater than the second secondary control mirror current p2·I bias When the second control input node 104b becomes the power supply voltage V DD ; Vice versa, when the main control mirror current k1·I BL,i Less than the second secondary control mirror current p2·I bias , the second control input node 104b becomes the ground voltage.

[0177] The control stage 101 includes first and second control inverters 106a and 106b and also includes first and second control flip-flops 107a and 107b of D type, which are coupled to the first and second control input nodes 104a and 104b through the first and second control inverters 106a, 106b, respectively.

[0178] In detail, the first control inverter 106a and the first control trigger 107a extend in another branch of the control stage 101, which is different from the first output branch 149a and different from the first control input branch 103a, and shares the first control input node 104a with them; similarly, the second control inverter 106b and the second control trigger 107b extend in another branch of the control stage 101, which is different from the second output branch 149b and different from the second control input branch 103b, and shares the second control input node 104b with them.

[0179] In particular, the control flip-flops 107a and 107b each have a clock input (CK-input), a data input (D-input), a reset input (R-input), and -Output.

[0180] The input of the first control inverter 106a is directly connected to the first control input node 104a, and its output is directly connected to the D-input of the first control flip-flop 107a.

[0181] The R-input of the first control flip-flop 107a receives an inverted reset signal: RESET_N, which is generated, for example, by the control circuit 31 and is configured to reset the first control flip-flop 107 when necessary (for example, after switching on the IMC device 10, more generally, whenever a known starting value needs to be stored in the control flip-flop 107a, for example between two calculations following each other).

[0182] The CK-input of the first control flip-flop 107 a receives the inverted clock signal CLK_N, which will be described in detail below.

[0183] The first control trigger 107a The output is directly coupled to the first intermediate node 108 a of the control stage 101 .

[0184] The input of the second control inverter 106b is directly connected to the second control input node 104b, and its output is directly connected to the D-input of the second control flip-flop 107b.

[0185] The R-input of the second control flip-flop 107 b receives the reset signal RESET_N (for any reset of the second control flip-flop 107 b ), and the CK-input of the second control flip-flop 107 b receives the inverted clock signal CLK_N.

[0186] The second control flip-flop 107b The output is directly coupled to the second intermediate node 108 b of the control stage 101 .

[0187] The first control flip-flop 107a and the second control flip-flop 107b basically convert the analog domain information carried by the voltage at the first control input node 104a and the second control input node 104b into digital domain information. - Output When the first control input node 104a is at the power supply voltage V DD When the first control input node 104a is at the ground voltage, it takes a high logic value (for example, "1"), and when the first control input node 104a is at the ground voltage, it takes a low logic value (for example, "0"), and similarly, the second control flip-flop 107b - Output When the second control input node 104b is at the power supply voltage V DD When the second control input node 104b is at the ground voltage, it takes a high logic value (eg, “1”), and when the second control input node 104b is at the ground voltage, it takes a low logic value.

[0188] In particular, switching of the control flip-flops 107 a and 107 b occurs at the rising edge of the negated clock signal CLK_N to synchronize the selection stage 102 and the charge counter stage 111 with each other, as better described below.

[0189] The control stage 101 also includes a set of control logic gates 109, which are coupled to the first and second control flip-flops 107a and 107b. - output and coupled to the first and second selection switches 105a and 105b, and configured based on - output to generate a plurality of control signals S for controlling the selection switches 105a, 105b and the charge counter stage 111 控制,1 -S 控制,3 (S control,1 -S control,3 )(Detailedly, the first control signal to the third control signal S control,1 -S control,3 and the first negation control signal ).

[0190] In the following, to simplify the representation, the first output is referred to as To indicate the first control trigger 107a - output, and references the second output To indicate the second control trigger 107b -Output.

[0191] The group of control logic gates 109 implements the following logic table:

[0192]

[0193] According to an exemplary embodiment, the set of control logic gates 109 includes a non-inverting control buffer 109a, a first control inverter 109b, a control NOR gate 109c, and a second control inverter 109d.

[0194] The non-inverting control buffer 109a is a non-inverting buffer whose input is directly connected to the first output And in response to the first output And at the output it generates an output equal to the first The first control signal S control,1 .

[0195] The first control inverter 109b is a logic inverter whose input is directly connected to the output of the non-inverting control buffer 109a and responds to the first control signal S control,1 At the output, a first control signal S is generated. control,1 The first inversion control signal of the inversion

[0196] The control NOR gate 109c is a NOR type logic gate having a non-inverted first input and an inverted second input, the first input being directly connected to the first output The second input is directly connected to the second output In response to the first output and the second output and The control NOR gate 109c generates a second control signal S at the output control,2 , this signal is output when the first has a low logic value and the second output When the first output and the second output have a high logic value, they take a high logic value. and has a high logic value and when the first output and the second input It takes a low logic value when it has a low logic value.

[0197] The second control inverter 109d is a logic inverter whose input is directly connected to the second output And in response to the second output And at the output it generates an output equal to the second The inverted third control signal S control,3 .

[0198] Referring to the selection stage 102, the selection switches 105a and 105b are controlled based on the control signal (in detail, according to the first inverted control signal and the third control signal S control,3 ) for control.

[0199] Specifically, the first selection switch 105a can be configured to receive the first inversion control signal The second selection switch 105a can be selectively controlled to be in a closed (conducting) state or an open (disabled) state according to the third control signal S control,3 Selectively controlled in a corresponding closed (conducting) state or a corresponding open (disabled) state.

[0200] For example, when the first negation control signal When the logic high value is taken, the first selection switch 105a is in a closed state and allows the second selection mirror current k3·I BL,i The second selection mirror current k3·I flows through the second selection input branch 103d until it reaches the selection common node 116, and when it takes a low logic value, the first selection switch 105a is in an off state and blocks the second selection mirror current k3·I BL,i flows through the second selection input branch 103d until reaching the selection common node 116; similarly, when the third control signal S control,3 When the logic value is high, the second selection switch 105b is in a closed state and allows the third selection mirror current k4·I BL,i The third selection mirror current k4·I flows through the third selection input branch 103e until it reaches the selection common node 116, and when it takes a low logic value, the second selection switch 105b is in an off state and blocks the third selection mirror current k4·I BL,i Flows through the third selection input branch 103 e until reaching the selection sharing node 116 .

[0201] Therefore, the common node 116 is selected to collect the total selected current I sel,tot , which total selection current depends on the state of the selection switches 105a, 105b, and the total selection current flows to the integration stage 110. Therefore, the state of the selection switches 105a, 105b determines the corresponding mutual combination of the selection mirror currents at each time, which corresponds to the total selection current I sel,tot .

[0202] Total selected current I sel,tot lower than or alternatively equal to the bit line current I BL,i In particular, I sel,tot BL,i .

[0203] In detail, the total selection current I​ sel,tot Relative to the bit line current I BL,i and the bit line current I BL,i The amount of increase is correspondingly (particularly, proportionally) reduced. In other words, the bit line current I BL,i The more it increases, the total selected current I sel,tot Relative to the bit line current I BL,i The more it is reduced, the less likely it is to cause the bit line current I BL,i The increase in increases accordingly.

[0204] In the embodiment considered here, the bit line current I BL,i can have a value that is contained in one of three current variation intervals at any time, which are successive to each other and have increasing values ​​(as better described below). BL,i Compared with the current variation range, the total selected current I sel,tot is selected accordingly so that the bit line current I BL,i The larger the bit line current I BL,i The greater the difference (i.e., the bit line current I BL,i With the total selected current I sel,tot When the bit line current I BL,i The first current variation interval is the smallest. When the bit line current I BL,i It is maximum when it belongs to the third current change interval (maximum).

[0205] In particular, the total selection current I sel,tot including at least a first selected mirror current k2·I BL,i , because the common node 116 is selected to be directly connected to the drain of the third output PMOS transistor 118c.

[0206] In addition, when the first negation control signal When the logic value is high, the total selection current I sel,tot Also includes the second selected mirror current k3·I BL,i .

[0207] In addition, when the third control signal S control,3 When the logic value is high, the total selection current I sel,tot Also includes the third selected mirror current k4·I BL,i .

[0208] In other words, in the embodiments considered here, the following may occur:

[0209] -If k1·I BL,i >p1·I bias (That is, in the example considered, if I BL,i >4·I bias , and thus in the third current variation interval), then and Therefore S control,1 = "1", S control,2 = "0", S control,3 ="0", Therefore I sel,tot =k2·I BL,i (That is, in the example considered, I sel,tot =I BL,i / 4);

[0210] -If p2·I bias <k1·I BL,i <p1·I bias (That is, in the example considered, if 2·I bias BL,i <4·I bias , and thus in the second current variation interval), then and Therefore S control,1 ="0", S control,2 = "1", S control,3 ="0", Therefore I sel,tot =k2·I BL,i +k3·I BL,i (That is, in the example considered, I sel,tot =I BL,i / 2);

[0211] -If k1·I BL,i <p2·I bias (That is, in the example considered, if I BL,i <2·I bias , and thus in the first current variation interval), then and Therefore S control,1 = "0", S control,2 = "0", S control,3 = "1", Therefore I sel,tot =k2·I BL,i +k3·I BL,i +k4·I BL,i (That is, in the example considered, I sel,tot =I BL,i ).

[0212] Therefore, even when the current flowing through the corresponding bit line BL i The current I BL,i ​When the value of is high (for example, included in the third current variation interval), the total selected current I arriving at the input of the integration stage 110 is sel,tot Keep below current I BL,i value, and is usually relatively small.

[0213] In fact, the control stage 101 implements the current variation based on three current variation intervals (k1·I BL,i >p1·I bias , p2·I bias <k1·I BL,i <p1·I bias or k1·I BL,i <p2·I bias ), and the total selection current I to be received by the selection stage 102 to the integration stage 110 sel,tot The corresponding selection (selected in three different ways, namely I sel,tot =k2·I BL,i +k3·I BL,i +k4·I BL,i , I sel,tot =k2·I BL,i +k3·I BL,i or I sel,tot =k2·I BL,i ), allowing even at high current I BL,I In the case of the total selected current I that the integration stage 110 needs to sample sel,tot It is also maintained low.

[0214] In detail, when the master control mirror current k1·I BL,i The intensity of the second secondary control mirror current p2·I bias ), the total selected current I arriving at the input of the integrating stage 110 sel,tot It is also relatively small (I sel,tot =k2·I BL,i +k3·I BL,i +k4·I BL,i , that is, lower than the second secondary control mirror current p2·I bias ); When the main control mirror current k1·I BL,i is of medium intensity (i.e., it is included in the first secondary control mirror current and the second secondary control mirror current p1·I bias With p2·I bias When the total selected current I reaches the input of the integrating stage 110 sel,tot But relatively small (I sel,tot =k2·I BL,i +k3·I BL,i , that is, lower than the second secondary control mirror current p2·I bias ); and when the main control mirror current k1·I BL,i has a high intensity (i.e., higher than the first secondary control mirror current p1·I bias ), the total selected current I arriving at the input of the integrating stage 110 sel,tot But relatively small (I sel,tot =k2·I BL,i , that is, lower than the second secondary control mirror current p2·I bias ). In other words, in any of the three cases, the total selected current I arriving at the input of the integrating stage 110 is sel,tot Are relatively small.

[0215] Furthermore, the presence of the first and second control flip-flops 107a and 107b results in synchronous switching of the control logic gate group 109, in particular, this occurs at the rising edge of the inverted clock signal CLK_N. This allows synchronous control of both the selection switches 105a and 105b and the charge counter stage 111, thereby preventing the total selection current I sel,tot changes while being integrated and prevents the charge counter stage 110 from incorrectly measuring the previously integrated total selected current I sel,tot In other words, this optimizes the operation of the digital detector 16 by preventing calculation errors of the IMC device 10 .

[0216] Referring now to the integrating stage 110, the integrating stage 110 allows the total selected current I sel,tot Sampling is performed to generate corresponding charge packets, which are then counted by the charge counter stage 111 .

[0217] The integration stage 110 includes a first integration circuit 121 , a second integration circuit 122 , and a switch circuit 123 coupled between the first and second integration circuits 121 , 122 .

[0218] The first and second integrator circuits 121, 122 are coupled to the input node 116 (ie, coupled to the selection common node 116) to receive the total selection current I sel,tot .

[0219] The first integrator circuit 121 includes a first inverter 124 having an output 125, a first integrator circuit 125 having a capacitor C coupled to the output 125 of the first inverter 124, and a first integrator circuit 126 having a capacitor C A A capacitor 127 and a second inverter 128 whose input is coupled to the output 125 of the first inverter 124.

[0220] The first inverter 124 has a power supply node coupled to the input node 116 of the integrating stage 110 and receives the first control signal IN at an input. A .

[0221] In practice, the first inverter 124 is selected by the total current I sel,tot Bias.

[0222] A first terminal of the capacitor 127 is coupled to the output node 125 of the first inverter 124, and a second terminal thereof is coupled to a reference node (here, ground).

[0223] The output node 125 of the first inverter 124 is at the first integrated voltage V A , which voltage drops across capacitor 127.

[0224] The second inverter 128 has a first sampling threshold (hereinafter referred to as the first threshold V th1 ), receiving a first integrated voltage V at the input A , and according to the first threshold V th1 and the first integrated voltage V A A first switching signal S1 is provided at the output.

[0225] In detail, the first switch signal S1 is a logic signal: when the first integrated voltage V A Below the first threshold V th1 has a high logic value, and when the first integrated current V A Above the first threshold V th1 has a low logic value.

[0226] The second integrator circuit 122 includes a first inverter 130 having an output 131, a capacitor C coupled to the output 131 of the first inverter 130, and a B A capacitor 132 and a second inverter 133 whose input is coupled to the output 131 of the first inverter 130.

[0227] The first inverter 130 has a power supply node coupled to the input node 116 of the integrating stage 110 and receives the second control signal IN at an input. B .

[0228] In practice, the first inverter 130 is selected by the total current I sel,tot Bias.

[0229] A first terminal of the capacitor 132 is coupled to the output node 131 of the first inverter 130, and a second terminal thereof is coupled to a reference node (here, ground).

[0230] The output node 131 of the first inverter 130 is at the second integrated voltage V B , which voltage drops across capacitor 131.

[0231] The second inverter 133 has a second sampling threshold V th2 (hereinafter referred to as the second threshold V th2 ), the second inverter 133 receives the second integrated voltage V at the input B , and according to the second threshold V th2 and the second integrated voltage V B A second switching signal S2 is provided at the output.

[0232] In detail, the second switch signal S2 is a logic signal: when the second integrated voltage V B Below the second threshold V th2 has a high logic value, and when the second integrated voltage V B Above the second threshold V th2 has a low logic value.

[0233] In this embodiment, the first threshold V th1 Equal to the second threshold V th2 However, depending on the specific application, the first threshold V th1 may be different from the second threshold V th2 .

[0234] The switch circuit 123 is a latch formed by two inverters 135 , 136 arranged in a ring configuration, a first switch 137 controlled by a first switch signal S1 , and a second switch 138 controlled by a second switch signal S2 .

[0235] Switch circuit 123 has a first node 140 coupled to the input of inverter 136 and to the output of inverter 135 , and a second node 141 coupled to the output of inverter 136 and to the input of inverter 135 .

[0236] The first node 140 provides a first control signal IN A The second node 141 provides a second control signal IN B .

[0237] The first switch 137 is coupled to the first node 140 and the voltage V′ DD The second switch 138 is coupled between the second node 141 and the voltage V' DD between nodes.

[0238] Voltage V' DD can be equal to or different from the power supply voltage V DD For example, if the voltage V' DD Different from (especially lower than) the power supply voltage V DD , the digital detector 16 may then include a voltage scaling circuit, such as a transistor (not shown here), whose source and drain terminals are coupled between the power supply node 120 and the input node 116 of the integrating stage 110 .

[0239] In this embodiment, the switch circuit 123 also receives an enable signal EN, which controls the activation of the switch circuit 123. For example, the enable signal EN can be used to maintain the switch circuit 123 turned off when not in use, thereby optimizing energy consumption. In addition, the enable signal EN can be used to set the switch circuit 123 to a defined state, such as when the IMC device 10 is turned on.

[0240] As the following reference Fig.10 and 11 To better describe, each switch of the switch circuit 123 corresponds to a response to the total selection current I sel,tot The detection of the corresponding charge packets is measured.

[0241] Referring now to the charge counter stage 111, the reference charge counter stage 111 is implemented by a "ripple counter", in particular using a D-type flip-flop.

[0242] The charge counter stage 111 is coupled to the integration stage 110 to count the charge packets measured by the integration stage 110, and is coupled to the control stage 101 to be controlled based on the control signal (in detail, according to the first to third control signals S control,1 -S control,3 ) is controlled in such a way that three different options are compensated in counting the charge packets for generating the total selection current I sel,tot , and thereby compensate for the corresponding values ​​they may take and the different weights that the charge packets may have.

[0243] In fact, the current flowing through the corresponding bit line BL i And the current I of different strengths (for example, belonging to different current variation intervals) BL,i The control stage 101 and the selection stage 102 convert the corresponding total selection current I sel,tot (with reduced intensity). However, since the charge packets actually have different weights, the currents I that are different from each other are responded to in the same way. BL,i Counting the measured charge packets will result in an incorrect final count.

[0244] Instead, the total selected current I on which the measurement is based sel,tot Assigning different weights to the charge packets avoids this drawback.

[0245] In other words, the charge counter stage 111 takes into account the total selection current I sel,tot With respect to the bit line BL i The current I BL,i The charge packets are counted according to the degree of scaling (operated by the selection stage 102). This is achieved by controlling the charge counter stage 111 based on the control signal.

[0246] In detail, the charge counter stage 111 is coupled to the first node 140 of the switch circuit 123 .

[0247] The charge counter stage 111 has a counter comprising a counting inverter 145, a plurality of counting selectors 175 (one for each current variation interval, thus three in this case) and a plurality of counting triggers 147 (particularly of D type and comprising a plurality of counting triggers 147 at least equal to the number of current variation intervals, thus three in this case).

[0248] The counting inverter 145 is a logic inverter having its input coupled to the first node 140 of the integrating stage 110 and its output configured to generate the previously described inverted clock signal CLK_N.

[0249] The counting selector 175 is a multiplexer, in particular a 2:1 type multiplexer (ie, each having a first input 175a, a second input 175b and an output 175c).

[0250] Each counter selector 175 also has a control input 175d coupled to the control stage 101 to receive a control signal S control,1 -S control,3 one of the.

[0251] The counter selector 175 is controlled by the control signal S control,1 -S control,3 The counter selectors 175 are controlled to selectively connect the output 175c to one of the first input 175a and the second input 175b according to the corresponding control signal. For example, when the corresponding control signal received at the control input 175d takes a logic high value ("1"), each counter selector 175 selectively connects the output 175c to the first input 175a, and when the corresponding control signal received at the control output 175d takes a low logic value ("0"), the output 175c is selectively connected to the second input 175b.

[0252] The count selector 175 is connected (particularly, directly connected) to the corresponding count flip-flops 147 , and in detail, to the first three count flip-flops 147 .

[0253] Specifically, a first count selector 175.1, a second count selector 175.2, and a third count selector 175.3 are presented.

[0254] The first input 175 a of each counting selector 175 is coupled (particularly, directly connected) to the output of the counting inverter 145 and thus receives the inverted clock signal CLK_N.

[0255] In addition, the second input 175 b of the first counter selector 175 . 1 receives a predetermined logic signal, in particular a high logic signal (“1”). For example, the predetermined logic signal is generated by the control circuit 31 .

[0256] The control input 175d of the first counter selector 175.1 is coupled (in particular, directly connected) to the output of the second control inverter 109d of the control stage 101 and thus receives the third control signal S control,3 .

[0257] The control input 175d of the second counter selector 175.2 is coupled (in particular, directly connected) to the output of the control NOR gate 109c of the control stage 101 and thus receives the second control signal S control,2 .

[0258] The control input 175d of the third counter selector 175.3 is coupled (in particular, directly connected) to the output of the non-inverting control buffer 109a of the control stage 101 and thus receives the first control signal S control,1 .

[0259] exist Fig. 9 In the exemplary embodiment shown, the first counting flip-flop 147.1 to the fourth counting flip-flop 147.4 and the last counting flip-flop 147.F are shown, where F is the output signal y i The number of digits.

[0260] In practice, the counter of the charge counter stage 111 has F counting flip-flops 147 .

[0261] The counting flip-flops 147 are sequentially cascaded to one another from the first counting flip-flop 147 . 1 to the last counting flip-flop 147 .F.

[0262] The counting flip-flops 147 each have a clock input (CK-input), a data input (D-input), a reset input (R-input), a Q-output (or a first output), and a - output (or second output).

[0263] The R-input of the counting flip-flop 147 receives a reset signal RESET_N, which is generated, for example, by the control circuit 31 and is configured to reset the counting flip-flop 147 when necessary (for example, after the IMC device 10 is turned on, more generally, whenever a known starting value needs to be stored in the counting flip-flop 147, for example between two consecutive calculations).

[0264] The CK-inputs of the first, second, and third counting flip-flops 147.1-147.3 are connected (particularly, directly coupled) to the outputs 175c of the corresponding counting selectors 175.1-175.3 to receive the trigger input signals generated by the counting selectors 175.1-175.3. In other words, the CK-input of the first counting flip-flop 147.1 is coupled to the output 175c of the first counting selector 175.1, the CK-input of the second counting flip-flop 147.2 is coupled to the output 175c of the second counting selector 175.2, and the CK-input of the third counting flip-flop 147.3 is coupled to the output 175c of the third counting selector 175.3.

[0265] Furthermore, the CK-inputs of the remaining counting flip-flops 147.4-147.F (i.e., those other than the first, second, and third counting flip-flops 147.1-147.3) are each connected (in particular, directly coupled) to the CK-input of the immediately preceding counting flip-flop. For example, the CK- input of the fourth counter flip-flop 147.4 is coupled to the CK- output of the third counter flip-flop 147.3. - output, the CK- input of the fifth counting flip-flop 147.5 is coupled to the CK- output of the fourth counting flip-flop 147.4. - output, and so on.

[0266] Each counting flip-flop 147 The - output is fed back to the D- input of the same counting flip-flop 147. In other words, the D- output of the first counting flip-flop 147.1 The -output is directly connected to the D-input of the first counting flip-flop 147.1, which applies mutatis mutandis to all subsequent counting flip-flops 147.

[0267] The Q-output of each counting flip-flop 147 is the output signal y i The corresponding bit y i In detail, the Q-output of the first flip-flop 147.1 is the output signal y i The first y i (1) (i.e., the least significant bit), the Q-output of the second flip-flop 147.2 is the output signal y i The second y i (2), and so on. This applies mutatis mutandis to all subsequent counting flip-flops 147. Thus, the Q-output of the last counting flip-flop 147.F is the output signal y i The most significant bit y i (F).

[0268] Reference Fig.10 , the structure of the integration stage 110 will now be described in more detail.

[0269] The first inverter 124 of the first integrator circuit 121 is a CMOS inverter formed by a series circuit of a PMOS transistor 150 and an NMOS transistor 151 commonly coupled to an output node 125. The PMOS and NMOS transistors 150, 151 receive a first control signal IN at respective gate terminals. A .

[0270] The source of the PMOS transistor 150 is coupled to the input node 116 of the integrating stage 110 .

[0271] The second inverter 128 of the first integrating circuit 121 is a CMOS inverter formed by a series circuit of a PMOS transistor 152 and an NMOS transistor 153 commonly coupled to a node 154 providing the first switching signal S1.

[0272] The first threshold V of the second inverter 128 th1 is the switching threshold of the second inverter 28 and therefore depends on the characteristics of the PMOS and NMOS transistors 152, 153, such as their threshold or on-resistance. In practice, the switching threshold may be the input voltage at which the output of the inverter has a high logic value, or the input voltage at which the output of the inverter has a low logic value.

[0273] For example, the switching threshold of the second inverter 128 can be defined as the corresponding input voltage (ie, the first integrated voltage V A ) is equal to the operating point of the corresponding output voltage (ie, the first switching signal S1).

[0274] The first inverter 130 of the second integration circuit 122 is a CMOS inverter formed by a series circuit of a PMOS transistor 155 and an NMOS transistor 156 commonly coupled to an output node 131. The PMOS and NMOS transistors 155, 156 receive a second control signal IN at respective gate terminals. B .

[0275] The source of the PMOS transistor 155 is coupled to the input node 116 of the integrating stage 110 .

[0276] The second inverter 133 of the second integrating circuit 122 is a CMOS inverter formed by a series circuit of a PMOS transistor 157 and an NMOS transistor 158 commonly coupled to a node 159 providing the second switching signal S2.

[0277] The second threshold V of the second inverter 133 th2 is the switching threshold of the second inverter 133, i.e., it depends on the characteristics of the PMOS transistor and the NMOS transistors 157, 158. For example, the switching threshold depends on the gate-source voltage that allows current to flow through the source-drain paths of the PMOS transistor and the NMOS transistors 157, 158.

[0278] As Fig.10 shown in the detailed implementation, the first inverter and the second inverters 135, 136 of the switching circuit 123 are cross-coupled CMOS inverters, each including a respective PMOS transistor 160 and a respective NMOS transistor 161 coupled in series between a power supply node (here at voltage V’ DD ) and ground.

[0279] In addition, the first inverter and the second inverters 135, 136 of the switching circuit 123 each further include a respective enable switch (here the PMOS transistor 162), which is coupled between the power supply node at voltage V’ DD and the PMOS transistor 160 of the respective inverter.

[0280] The PMOS transistor 162 is controlled by an enable signal EN.

[0281] In use, the total selection current I sel,tot is mirrored in the integration stage 110 of the respective digital detector 16.

[0282] Fig.11 Shows Fig. 9 an example of the trend over time of the first control signal IN A of the digital detector 16, the first integration voltage V A and the second integration voltage V B .

[0283] For t0 < t < t1, the first integration voltage V A is below the first threshold V th,1 . Accordingly, the PMOS transistor 152 of the second inverter 128 is turned on and the NMOS transistor 153 of the second inverter 128 is turned off. Accordingly, the first switch signal S1 (not shown here) has a high value and the first switch 137 is open. The first control signal IN A has a low value.

[0284] As a result, with reference to the first inverter 124 of the first integration circuit 121, for t0 < t < t1, the PMOS transistor 150 is turned on and the NMOS transistor 151 is turned off.

[0285] Meanwhile, for t0 < t < t1, the second control signal IN B has a high value. Thus, referring to the first inverter 130 of the second integration circuit 122, for t0 < t < t1, the PMOS transistor 155 is turned off and the NMOS transistor 156 is turned on.

[0286] Therefore, the total selection current I sel,tot flows only through the first inverter 124 of the first integration circuit 121 from the input node 116, and does not flow through the first inverter 130 of the second integration circuit 122.

[0287] Specifically, the total selection current I sel,tot flows through the PMOS transistor 150 and charges the capacitor 127. Thus, for t0 < t < t1, the first integration voltage V A increases with time.

[0288] Specifically, in the Fig.11 example, for t0 < t < t1, the first integration voltage V A increases linearly with time; however, the trend of the first integration voltage V A depends on the specific trend of the total selection current I sel,tot within the time interval t0 < t < t1.

[0289] When the first integration voltage V A becomes equal to the first threshold voltage V th,1 , the NMOS transistor 153 of the second inverter 128 is turned on and the PMOS transistor 152 is turned off.

[0290] In this embodiment, the first control signal IN A takes a high value at time t2.

[0291] The time delay between time t1 and t2 can correspond to, for example, the propagation delay of the second inverter 128 of the first integration circuit 121 and / or the switching time of the first switch 137.

[0292] For t1 < t < t2, the total selection current I sel,tot continues to charge the capacitor 127; thus the first integration voltage V A increases to the maximum value (time t2).

[0293] At time t2, when the first control signal IN A takes a high value, the second control signal IN B (not shown here) takes a low value (the inverter 136 of the switching circuit 123 receives the first control signal IN A at the input).

[0294] When the first control signal IN A When the second control signal IN has a high value, the PMOS transistor 150 and the NMOS transistor 151 of the first inverter 124 of the first integration circuit 121 are turned off and on, respectively. B With a low value, the PMOS transistor 155 and the NMOS transistor 156 of the first inverter 130 of the second integration circuit 122 are turned on and off, respectively.

[0295] Therefore, for t>t2, the total selected current I sel,tot The voltage from the input node 116 flows only through the first inverter 130 of the second integrating circuit 122 , but does not flow through the first inverter 124 of the first integrating circuit 121 .

[0296] In detail, the total selection current I sel,tot Flows through the PMOS transistor 155 and charges the capacitor 132 of the second integration circuit 122. Therefore, the second integration voltage V B It increases with time starting from time t2.

[0297] In detail, Fig.11 In the example, for t>t2, the second integrated voltage V B increases linearly with time; however, the second integrated voltage V B The trend depends on the total selected current I sel,tot specific trends.

[0298] When the first control signal IN A When the first integration circuit 121 has a high value, the capacitor 127 is discharged through the NMOS transistor 151 of the first inverter 124. Therefore, the first integration voltage V A Decrease to zero.

[0299] When the second integrated voltage V B becomes equal to the second threshold voltage V th,2 At time t3, the NMOS transistor 158 of the second inverter 133 is turned on, and the PMOS transistor 157 is turned off.

[0300] Therefore, at time t4, the second control signal IN B Takes a high value, similar to the first control signal IN at time t2 above A discussed.

[0301] In detail, in response to the second integrated voltage V B Reaching the second threshold V th,2 , the second switch signal S2 switches to a low value, and the second switch 138 is closed, so that the second node 141 is at a voltage V' DD Therefore, the second control signal IN B Take the high value.

[0302] The time delay between times t3 and t4 can correspond to, for example, the propagation delay of the second inverter 133 of the second integration circuit 122 and / or the switching time of the second switch 138.

[0303] For t3 < t < t4, the total selection current I sel,tot continues to charge the capacitor 132 of the second integration circuit 122; thus the second integration voltage V B increases until a maximum value (time t4).

[0304] For t2 < t < t4, the switching circuit 123 maintains the first control signal IN A at a high value and maintains the second control signal IN B at a low value.

[0305] At time t4, in response to the second control signal IN B taking a high value, the first control signal IN A again takes a low value.

[0306] In response to the first control signal IN A taking a low value, the total selection current I sel,tot returns to charging the capacitor 127 of the first integration circuit 121 until time t6, similar to that already discussed for t1 < t < t2.

[0307] Thus, from time t6 to time t7, the total selection current I sel,tot charges the capacitor 132 of the second integration circuit 122 until time t7, similar to that already discussed for t2 < t < t4.

[0308] / /

[0309] Referring again to Fig. 9 , the charge counter stage 111 counts the number of switching events of the first control signal IN A , and in particular, in this embodiment, it counts the number of rising edges of the first control signal IN A .

[0310] In practice, the digital detectors 16 each measure the bit line current I i of the corresponding bit line BL BL,i , and perform a plurality of successive sampling iterations of the total selection current I BL,i obtained in response to the corresponding bit line current I sel,tot .

[0311] In each sampling iteration, for example, referring to the sampling iteration in which the total selection current I sel,tot flows through the first integration circuit 121, the integration stage 110 generates a first integration voltage V A As the total selected current I sel,tot The time integral of the first integrated voltage V A With the first threshold V th,1 is compared, and in response to the first integrated voltage V A Reaching the first threshold V th,1 The first integrated voltage V is reset A , in particular, here, by switching the first control signal IN A To reset the first integration voltage V A This event corresponds to the detection of a charge packet. The charge counter stage 111 thus responds to the first integrated voltage V A Reaching the first threshold V th,1 And update the corresponding output signal y i .

[0312] In other words, the digital detectors 16 each convert the corresponding total selection current I sel,tot The sampling is into a plurality of charge packets and the charge packets are counted, wherein each charge packet corresponds to the charge accumulated on the capacitor 127 , 132 , which results in the switching of the second inverter 128 , 133 .

[0313] As a result, if the bit line current is integrated at once across the capacitor C tot Compared with the case of a single capacitor, the capacitors 127 and 132 may have reduced capacitance. In detail, the capacitance of the capacitors 127 and 132 may be 2 F The coefficient is lower than that of the capacitor C tot , where F is the output signal y i The number of digits.

[0314] Therefore, the digital detector 16 may have a small die area occupation, and thus, the IMC device 10 may have a low manufacturing cost.

[0315] In addition, when the bit line current I BL,i Through the corresponding bit line BL i When the digital detectors 16 start to detect the corresponding bit line current I BL,i Therefore, the output signal y i The IMC device 10 may be ready immediately after the calculation is completed, or immediately after the corresponding bit line current I BL,i After stopping, it is ready.

[0316] For example, according to one embodiment, the digital detectors 16 may each detect the corresponding bit line current I BL,i Sampling is performed until the digital detector 16 receives a stop signal (eg, from a user of the IMC device 10 or from the wordline activation circuit 14) indicating the end of the computation performed by the IMC device 10.

[0317] Therefore, the digital detector 16 may have a fast measurement time, thereby allowing the IMC device 10 to have a low computation time.

[0318] In addition, according to the illustrated embodiment, the switch circuit 123 responds to the first integrated signal V A Reaching the first threshold V th,1 The first integration circuit 121 is disabled and the second integration circuit 122 is enabled, and in response to the second integration signal V B Reaching the second threshold V th,2 The first integration circuit 121 is enabled and the second integration circuit 122 is disabled.

[0319] This allows the first integration circuit 121 and the second integration circuit 122 to alternately sample the total selection current I sel,tot , thus allowing the total selected current I sel,tot Capacitor 127 is charged when capacitor 132 is discharged, and capacitor 132 is charged when capacitor 127 is discharged. By doing so, no charge is lost during sampling, and digital detector 16 can achieve bit line current I BL,i High measurement accuracy.

[0320] Reference again Fig.10 The integration stage 110 may further include a first stop switch and a second stop switch (here, a first NMOS transistor and a second NMOS transistor 171, 172), which prevent the corresponding digital detector 16 from selecting the corresponding total current I sel,tot Take samples.

[0321] In detail, the drain terminals of the first and second NMOS transistors 171, 172 are respectively coupled to the output nodes 127, 131 of the first and second integration circuits 121, 122; and their source terminals are coupled to a reference potential line (here, ground). The first and second NMOS transistors 171, 172 receive a count end signal END at their respective gate terminals.

[0322] When the timer signal TM <l:1>becomes equal to the maximum count signal MAX_CNT <l:1>When , the calculation end comparator 170 switches the end signal END to a high logic value, thereby turning on the first and second NMOS transistors 171 and 172 and short-circuiting the output nodes 127 and 131 of the first and second integration circuits 121 and 122 to the ground.

[0323] Therefore, the first and second integrating circuits 121 and 122 stop the total selection current I sel,tot Perform integration.

[0324] In practice, the count end signal END may be used to determine the end of the MAC calculation of the IMC device 10 .

[0325] In practice, in the previously described embodiments, the integrating stage 181 of the timer 45 has the same circuit diagram as the integrating stage 110 of any digital detector 16 .

[0326] As a result, the timer 45 is synchronized with any digital detector 16 according to the corresponding total selected current I sel,tot Generate output data y i In the same way, according to the oscillator current I OSC Generates timer signal TM <l:1>.

[0327] In addition, in this embodiment, the first threshold value V′ of the second inverter 200 of the timer 45 is th1 is equal to the first threshold V of the second inverter 128 of the digital detector 16 th1 , the second threshold value V' of the second inverter 205 of the timer 45 th2 is equal to the second threshold value V of the second inverter 133 of the digital detector 16 th2 .

[0328] In addition, the voltage V' of the counting portion 181 of the timer 45 is DD can be equal to the voltage V′ of the integrating stage 110 of the digital detector 16 DD .

[0329] In use, the timer 45 and the digital detector 16 are each based on the corresponding total selection current I sel,tot Generate the corresponding output data y i In the same way, according to the oscillator current I OSC Generates timer signal TM <l:1>The fact that the corresponding integrator circuits 110, 181 have the same circuit diagram allows obtaining the timer signal TM <l:1>With the output data y1,…,y M The strong correlation between .

[0330] Therefore, global changes that may affect the IMC device 10, such as, for example, the supply voltage V DD 、V' DD Drift and / or temperature variations are compensated by the timer 45 and by the digital detector 16, without thereby affecting the accuracy of the MAC operation performed by the IMC device 10.

[0331] In use, the IMC device 10 can be controlled by a control method, which specifically includes the following steps: providing a word line activation signal 21 to the memory cell 20 through the word line activation circuit 14; generating a bias voltage Vr through the bias circuit 18, and applying the bias voltage Vr to the bit line BL i ; Through the control stage 101 in response to the bit line current I BL,i The main control mirror current k1·I is generated BL,i ; The main control mirror current k1·I is BL,i with the reference current (i.e., with p1·I bias The control signal S indicating the comparison is generated by the control stage 101 control,1 -S control,3 , The selection stage 102 responds to the bit line current I BL,i And according to the control signal S control,1 -S control,3 , Generates a total selection current I sel,tot ; Through the integration stage 110, the total selection current I sel,tot Sampling; and through the charge counter stage 111 according to the control signal S control,1 -S control,3 , In response to the first total selection current I sel,tot The output signal Y is generated by sampling.

[0332] From an examination of the features of the present invention as provided herein, the advantages provided are apparent.

[0333] The IMC device 10 allows MAC operations to be performed in an optimized manner with reduced time and high accuracy.

[0334] In particular, Fig. 9 The use of digital detectors 16 as shown allows the integrating stage 110 of each digital detector 16 to sample a low current (ie, a total selected current I sel,tot Sampling the bit line current I BL,i to generate a corresponding additional charge Q add The charge packets of the respective additional charge amounts are deducted to the extent that they are approximately equal to each other. This allows the sampled charge packets to be substantially identical to each other and to the bit line current I at the input of the digital detector 16 under consideration. BL,i Therefore, the bit line current I BL,i The measurement accuracy and overall calculation accuracy of the IMC device 10 are improved.

[0335] This can be done by evaluating the bit line current I based on a comparison of different current variation intervals (exemplarily three in the previously considered embodiment) BL,i The strength of the bit line current I is generated by the selection stage 102 according to the comparison result and thus BL,i The degree of the hypothetical current (i.e., the total selected current I sel,tot ) is achieved by successive sampling.

[0336] In other words, by limiting the amount of input current to the integrating stage 110, it is possible to ensure that the integrating stage 110 operates in an operating region where its operating accuracy is less affected by the amount of additional charge Q add Therefore, the entire measurement can be performed with a measurement accuracy approximately equal to the measurement accuracy of the case of identifying the low input current at the integration stage 110 (ie, the first current variation interval).

[0337] Finally, it is clear that modifications and variations may be made to the invention described and illustrated herein without departing from the scope of the invention as defined in the appended claims.For example, the different embodiments described may be combined with each other to provide further solutions.

[0338] Furthermore, the previously described embodiments of the timer 45, the integration stage 110 input to the time converter 46, and the digital detector 16 are provided for exemplary and non-limiting purposes only, and other embodiments may be similarly considered in a manner that is self-evident. For example, a voltage-controlled timer, a timer based on a ring oscillator having an odd number of inverters, an integration stage 110 of the digital detector 16 each including only an integration circuit and a counter circuit (and thus not even including a corresponding switching circuit) or each including a first integration circuit and a second integration circuit coupled to each other via a switching circuit, and the like may be similarly used.

[0339] In addition, the timer signal TM may be an analog signal, and the input to the time converter 46 may be configured to convert the corresponding input data x j The analog input signal is converted into an analog signal, and the analog input signal is compared with the analog timer signal. For example, the timer signal can be based on the current (in particular, based on the reference current I REF ) generates a voltage ramp (voltageramp); in this case, the update frequency of the analog timer signal indicates the slope of the voltage ramp.

[0340] The memory cells 20 may be resistive memory cells not based on PCM material but on a different technology; for example, they may be magnetoresistive (MRAM), resistive (RRAM) or static (SRAM) memory cells.

[0341] In addition, the storage element 25 of each memory cell 20 may be formed by a plurality of selectable resistive elements (equal to or different from each other), which are arranged in parallel with each other, for example, between the corresponding bit line and the ground, and these resistive elements may be selectively enabled or disabled when programming the memory array 12, so that the corresponding transconductance value g ij Can be a multi-bit value.

[0342] In addition, if Fig.12 As shown in the exemplary embodiment, the bias circuit 18 may include a circuit for generating a reference current I REF The current source 32 has an input node 34 and a reference impedance Z REF Reference network 33.

[0343] In this embodiment, the current source 32 is a controllable current source, which receives an external signal EXT (eg, from a user of the IMC device 10 ), the external signal EXT indicating a reference current I REF expected value.

[0344] By changing the reference current I REF , can change the oscillator current I OSC , thereby modifying the timer signal TM <l:1>The update frequency f u , and thus modify the total calculation time of the IMC device 10. In fact, for example, the oscillator current I OSC The increase in the oscillator integrated voltage V' A 、V' B increases faster; therefore, the first oscillator control signal and the second oscillator control signal OS A 、OS B Switches faster, thus also increasing the timer signal TM <l:1>The update frequency f u .

[0345] The reference network 33 receives a reference current I at an input node 34. REF The input node 34 is in accordance with the reference current I REF and reference impedance Z REF voltage.

[0346] The bias circuit 18 further comprises a voltage distribution circuit, here formed by an operational amplifier 36 having an output 37 providing a bias voltage Vr.

[0347] The non-inverting input of the operational amplifier 36 is coupled to the input node 34 of the reference network 33. The inverting input of the operational amplifier 36 is coupled (particularly, directly coupled here) to the output 37 of the operational amplifier 36.

[0348] Depending on the specific application, the output 37 of the amplifier 36 is coupled (eg, directly or through a specific voltage distribution circuit) to the bit lines BL1, . . . , BL M .

[0349] In practice, in this embodiment, the voltage at the input node 34 of the reference network 33 is the bias voltage Vr.

[0350] In detail, in this embodiment, the reference network 33 is formed by a reference memory array, therefore also denoted by 33 hereinafter, which has a total reference transconductance value gref and includes one or more reference cells of non-volatile type, here a plurality of reference cells 40 .

[0351] Reference memory array 33 may be part of memory array 12 or may be a separate memory array.

[0352] The reference cell 40 has the same circuit configuration as the memory cell 20 of the memory array 12 .

[0353] In detail, the reference cells 40 each include a storage element 41 and a selection element 42 , which are, in particular, respectively equivalent to the storage element 25 and the selection element 26 of the memory cell 20 .

[0354] In practice, the storage element 41 is based on the same technology used to obtain the storage element 25. For example, if the storage element 25 is based on a PCM material, then the storage element 41 is also based on a PCM material, in particular, on the same PCM material.

[0355] Reference cells 40 are programmed to store respective reference transconductance values, which may be equal to or different from each other depending on the specific application.

[0356] In a design step, the number of reference cells 40 and the corresponding reference transconductance values ​​may be selected so that reference memory array 33 is a statistically significant sample of memory array 12 .

[0357] In practice, the total reference transconductance value g of the reference memory array 205 is ref The total transconductance of the memory array 12 is statistically represented.

[0358] For example, the total transconductance of memory array 12 may be equal to the transconductance that memory array 12 would have if all reference cells 20 were activated simultaneously.

[0359] For example, the number of reference cells 206 may be greater than one hundred.

[0360] For example, reference cell 40 may be programmed so that the total reference transconductance g of reference memory array 33 is ref is equal to the average value of the total transconductance of the memory array 12.

[0361] For example, the average value may represent an average transconductance value that the memory array 12 has in use, such as determined during a calibration or initialization step of the IMC device 10 .

[0362] The storage element 41 has a first terminal coupled to the input node 34 of the reference network 33 and a second terminal coupled to a reference potential node, here to the ground 29 , via a selection element 42 .

[0363] In practice, the reference cells 40 all share the same reference bit line BL ref .

[0364] The selection elements 42 are each formed by a respective switch, for example a BJT transistor, a diode or a MOSFET transistor (here an NMOS transistor, in particular, equivalent to the selection element 26 of the memory cell 20 ), which is arranged in series with the respective storage element 41 .

[0365] In this embodiment, the selection elements 42 of all reference cells 40 are controlled by the same reference activation signal REF, which may be generated by the word line activation circuit 14 or other components (not shown here) of the IMC device 10, for example.

[0366] However, during calculations of the IMC device 10 , the selection elements 42 may each be controlled by a respective reference activation signal which differs from one another, for example depending on the reference cell 40 to be activated.

[0367] Reference impedance Z REF is the transconductance value g stored in the reference unit 40 ref and according to a reference activation signal REF.

[0368] Bit line current I BL,1 ,…,I BL,M Each also depends on the bias voltage Vr received from the bias circuit 18.

[0369] The bias voltage Vr is determined by the reference current I REF The fact that this is generated allows the variable reference impedance Z to be varied REF and / or reference current I REF To adjust the bias voltage Vr.

[0370] In fact, during the lifetime of the IMC device 10, the IMC device 10 may be affected by temperature variations, which may affect the transconductance value g of the memory cell 20. ij In addition, the transconductance value g of the memory cell 20 is ij may be subject to drift; for example, in case the memory cell 20 is a PCM memory cell, the storage element 25 may be affected by aging phenomena such as, for example, amorphization.

[0371] Transconductance g ij This deviation from the programmed value may change the bit line current I BL,i , resulting in an error in the output signal Y.

[0372] In the IMC device 10, such temperature variation or drift will also affect the reference transconductance value of the reference memory cell 40 in the same manner, and thus affect the overall reference transconductance value g of the reference memory array 33. ref , because the reference memory cell 40 represents a statistically significant sample of the memory cells 20 .

[0373] The change of the reference transconductance value of the reference memory cell 40 will cause the reference impedance Z REF The change in Vr thus causes a change in the voltage at the input node 34 of the reference network 33. Therefore, the bias voltage Vr also changes.

[0374] In detail, the change in bias voltage Vr compensates for the transconductance value g of the memory cell 20. ij changes.

[0375] For example, if the memory cell 20 experiences a transconductance value g ij Increased drift, then the corresponding bit line current I BL,i At the same time, the total reference transconductance g of the reference memory array 33 ref The value of also increases, resulting in the reference impedance Z REF decreases, which in turn causes the bias voltage Vr to decrease.

[0376] The decrease in bias voltage Vr causes the bit line current I BL,i of reduction.

[0377] In other words, the bias circuit 18 allows compensation of the transconductance g ij The drift of the bit line current I BL,i changes.

[0378] In addition, in this embodiment, since the reference current I REF is generated by the current source 32 and is therefore not affected by the reference transconductance g ref The drift of the timer signal TM causes the update frequency f u Keep it constant.

[0379] Therefore, the timing of the IMC device 10 remains constant. Thus, the IMC device 10 has an overall processing time that is independent of drift that may affect the memory cell 20.

[0380] However, the user of the IMC device 10 can change the power supply current of the timer 45 (ie, the reference current I REF ) (for example, through an external signal EXT) to change the timing of the IMC device, thereby changing the total processing time of the IMC device 10.

[0381] Alternatively, Figure 1 The reference impedance Z of the reference network 33 REF There may be a variable impedance, which may for example be controlled by a user in response to a drift of the memory cell 20 , which may be achieved in a different manner than that shown, ie it may not include the reference memory cell 40 .

[0382] In addition, in different embodiments, the first control trigger and the second control trigger 107a and 107b may not exist, and the first control inverter and the second control inverter 106a and 106b are replaced by corresponding non-inverting buffers. In this case, the switching of the control logic gate group 109 does not necessarily occur at the rising edge of the inverted clock signal CLK_N, but is asynchronous. This allows the selection switches 105a and 105b and the charge counter stage 111 to operate in an asynchronous manner, and also simplifies the circuit structure of the digital detector 16.

[0383] Furthermore, although two current references (i.e., the first secondary control mirror current and the second secondary control mirror current p1·I bias and p2·I bias , which are exemplarily equal to the bias current I bias Four times and half) describes the comparison of each bit line BL by the control stage 101. i The bit line current I BL,i , and thus the selection stage 102 selects (I sel,tot =k2·I BL,i +k3·I BL,i +k4·I BL,i , I sel,tot =k2·I BL,i +k3·I BL,i , or sel,tot =k2·I BL,i ) generates a total selection current I sel,tot , but obviously this can be generalized to Z current references and Z+1 combination selections to generate the total selection current I sel,tot In other words, Z+1 current variation intervals may be considered instead of the three previously described.

[0384] In detail, in this embodiment of the digital detector 16 (not shown and more general than previously described), the control stage 101 comprises Z control input branches of a main current mirror 115, whose main control mirror ratio is 1:k1, which allows the generation of a main control mirror current k1·I BL,i Z copies of .

[0385] Each of these Z control input branches of the primary current mirror 115 is connected to a corresponding output branch of the secondary current mirror 144 through a corresponding control input node. The secondary current mirror has Z output branches, so that the secondary current mirror can generate a bias current I bias Z different mirrored and scaled copies of (i.e., Z different current references).

[0386] The D-inputs of the corresponding control flip-flops are connected to the respective Z control input nodes.

[0387] Z controls the flip-flop The outputs are connected to a set of control logic gates 109 which implement the logic functions required to generate the Z control signals to be sent to the selection stage 102 and to the charge counter stage 111, similar to that previously described. In particular, the control logic gate set 109 can be implemented by a common decoder which receives at its input the Z control flip-flops. - outputs, and generating corresponding control signals at the outputs in a manner which is obvious per se in view of what has been described previously and of the number and chosen arrangement of the selection switches.

[0388] The selection stage 102 includes Z+1 selection input branches of the main current mirror 115, each having a corresponding selection mirror ratio, which allows the generation of Z+1 selection mirror currents.

[0389] The selection input branch of the main current mirror 115 has selection switches whose number and arrangement are suitable for combining the selection mirror currents with each other at the selection common node 116 according to the control signal and in such a way that there are Z+1 combination selections to generate a total selection current I sel,tot .

[0390] Next, as previously described, the total selection current I sel,tot Sampling is performed and the resulting charge packets are then counted by the charge counter stage 111 .

[0391] In particular, the charge counter stage 111 has Z+1 count selectors 175, which are coupled to the Z+1 first count flip-flops in a manner similar to that previously described, so that the control signal allows selection of the signal arriving at the CK-input of the count flip-flops (i.e., the inverted clock signal CLK_N if the corresponding control signal is "0", or for the first count flip-flop 175.1 if the corresponding control signal is "1", and for the remaining Z-1 first count flip-flops, the signal of the previous count flip-flop if the corresponding control signal is "1"). - output) method.

[0392] In particular, as the number Z increases, the measurement accuracy of the digital detector 16 increases because the bit line current I BL,i The size of the interval over which the selected pattern of current at the input of the integrating stage 110 can be varied without causing a corresponding change is reduced.

[0393] For example, Z may be equal to 1 or greater than 2.

[0394] Furthermore, generally, the control stage 101 is electrically coupled to at least the first bit line BL i , and is configured to receive a corresponding bit line current I BL,i , in response to the first bit line current I BL,i At least the first main control mirror current k1·I is generated BL,i , the first main control mirror current k1·I BL,i with at least a first reference current (eg, p1·I bias ) to compare, and to generate one or more control signals (S) indicating the comparison control,1 -S control,3 , The selection stage 102 is electrically coupled to the control stage 101 and the first bit line BL i , and is configured to receive the bit line current I BL,i and the one or more control signals, and in response to the bit line current I BL,i And generate a total selection current I according to the one or more control signals sel,tot The integrating stage 110 is electrically coupled to the selecting stage 102 and is configured to receive and sample the total selected current I sel,tot The charge counter stage 111 is electrically coupled to the integration stage 110 and to the control stage 101 and is configured to receive the sampled total selection current I sel,tot and the one or more control signals, and in response to the total selection current I sel,tot sampling, and generating an output signal Y according to the one or more control signals.

Claims

1. An in-memory computing (IMC) device, configured to receive an input signal indicating a plurality of input values, and configured to provide at least an output signal indicating a plurality of output values, the IMC device comprising: a word line activation circuit configured to receive an input signal and configured to provide a plurality of word line activation signals, each word line activation signal being based on a respective one of the input values; a bias circuit configured to provide a bias voltage; A memory array, comprising a plurality of first memory cells, the plurality of first memory cells being coupled to a first bit line and each being coupled to a corresponding word line, the first bit line being configured to receive a bias voltage, the first memory cells being configured to each store a corresponding calculation weight and being configured to each receive a corresponding word line activation signal from the corresponding word line, the first memory cells being configured to each be traversed by a corresponding cell current according to the bias voltage, according to the corresponding word line activation signal and according to the corresponding calculation weight, the first bit line being configured to be traversed by a first bit line current, the first bit line current being a sum of the cell currents; as well as a first digital detector coupled to the first bit line and configured to sample the first bit line current and provide the output signal in response to the first bit line current; The first digital detector comprises: a control stage electrically coupled to the first bit line and configured to receive the first bit line current, generate at least a first master control mirror current in response to the first bit line voltage, compare the first master control mirror current to at least a first reference current, and generate one or more control signals indicative of the comparison; a select stage electrically coupled to the control stage and the first bit line and configured to receive the first bit line current and the one or more control signals and to generate a total select current in response to the first bit line current and in accordance with the one or more control signals; an integrating stage electrically coupled to the selecting stage and configured to receive and sample the total selecting current; and A charge counter stage is electrically coupled to the integrating stage and to the control stage and is configured to receive the sampled total selection current and the one or more control signals and to generate the output signal according to the one or more control signals in response to the sampled first total selection current.

2. The IMC device of claim 1, wherein the total select current is lower than or equal to the first bit line current. 3 . The IMC device of claim 1 , wherein the total selection current is configured to decrease relative to the first bit line current in accordance with how much the first bit line current increases.

4. The IMC device of claim 1 , wherein the control stage is further configured to: generate at least a second master control mirror current in response to the first bit line current, compare the second master control mirror current with a second reference current, and generate the control signal indicating a comparison of the first master control mirror current with the first reference current and a comparison of the second master control mirror current with the second reference current.

5. The IMC device of claim 4 , wherein the control stage and the selection stage include a main current mirror electrically coupled to the first bit line and configured to receive the first bit line current and configured to mirror the first bit line current in at least a first control input branch and a second control input branch of the control stage and in at least a first selection input branch, a second selection input branch, and a third selection input branch of the selection stage.

6. The IMC device according to claim 5: in, The main current mirror has the same main control mirror ratio for both the first control input branch and the second control input branch of the control stage; wherein a first master control mirror current and a second master control mirror current are generated in response to the first bit line current and based on a master control mirror ratio, the first master control mirror current being configured to flow in a first control input branch to a first control input node of the control stage, and the second master control mirror current being configured to flow in a second control input branch to a second control input node of the control stage; wherein the control stage further comprises a secondary current mirror configured to receive a bias current and configured to mirror the bias current into a first output branch and a second output branch of the control stage; wherein the secondary current mirror has a first secondary control mirror ratio for the first output branch and a second secondary control mirror ratio for the second output branch in a manner that a first secondary control mirror current flows through the first output branch and a second secondary control mirror current flows through the second output branch, the first secondary control mirror current is greater than the second secondary control mirror current, wherein the first secondary control mirror current serves as the first reference current and the second secondary control mirror current serves as the second reference current; and The first control input node is shared between the first output branch and the first control input branch, and the second control input node is shared between the second output branch and the second control input branch.

7. The IMC device of claim 6, wherein the control stage further comprises: A first control inverter and a second control inverter, coupled to the first control input node and the second control input node, respectively; a first control flip-flop and a second control flip-flop, each control flip-flop having a respective input coupled to a first control input node and a second control input node, respectively, via a first control inverter and a second control inverter; as well as A set of control logic gates is coupled to the outputs of the first control flip-flop and the second control flip-flop, to the charge counter stage and to the selection stage, and is configured to generate a control signal based on the outputs of the first control flip-flop and the second control flip-flop.

8. The IMC device according to claim 7: in, The control signal includes a first control signal, a second control signal, a third control signal and a first negated control signal; Wherein, when the output of the first control trigger and the output of the second control trigger take the first logic value, the first control signal takes the first logic value, and when the output of the first control trigger and the output of the second control trigger take the second logic value or when the output of the first control trigger takes the second logic value and the output of the second control trigger takes the first logic value, the first control signal takes the second logic value, wherein the second control signal takes the first logic value when the output of the first control trigger takes the second logic value and the output of the second control trigger takes the first logic value, and the second control signal takes the second logic value when the output of the first control trigger and the output of the second control trigger take the first logic value or the second logic value; wherein the third control signal takes the first logic value when the output of the first control trigger and the output of the second control trigger take the second logic value, and the third control signal takes the second logic value when the output of the first control trigger and the output of the second control trigger take the first logic value, or when the output of the first control trigger takes the second logic value and the output of the second control trigger takes the first logic value; and When the first control signal takes the second logic value, the first negation control signal takes the first logic value, and when the first control signal takes the first logic value, the first negation control signal takes the second logic value.

9. The IMC device according to claim 5: in, The main current mirror has a corresponding selection mirror ratio for each of the first selection input branch, the second selection input branch, and the third selection input branch of the selection stage in such a manner that the first selection mirror current, the second selection mirror current, and the third selection mirror current flow in the first selection input branch, in the second selection input branch, and in the third input branch, respectively; wherein the first selection input branch, the second selection input branch and the third selection input branch share a selection common node, and the total selection current is configured to flow through the selection common node; as well as The selection stage includes one or more selection switches, which extend along at least some of the first selection input branch, the second selection input branch and the third selection input branch, and are configured to receive a control signal and to be selectively switched according to the control signal in such a way that a total selection current in the selection common node is correspondingly generated at the selection common node with corresponding mutual combinations of selection mirror currents, second selection mirror currents and third selection mirror currents that are different from and replace each other, and the total selection current in the selection common node is defined by the corresponding combination of the selection mirror current, the second selection mirror current and the third selection mirror current at each time.

10. The IMC device of claim 1 , wherein the charge counter stage comprises: one or more counting selectors, coupled to the integrating stage to receive the negated clock signal indicative of a sample of the total selected current, coupled to the control stage to receive the control signal, and capable of being controlled in accordance with the control signal; as well as A plurality of counting flip-flops are coupled to the one or more counting selectors and are configured to receive corresponding trigger input signals generated by the counting selectors according to the control signal and to generate the output signals based on the trigger input signals.

11. The IMC device according to claim 10: in, The control stage is further configured to generate at least a second master control mirror current in response to the first bit line current, compare the second master control mirror current to a second reference current, and generate said control signal, said control signal indicating a comparison of the first master control mirror current to the first reference current and a comparison of the second master control mirror current to the second reference current; wherein the counting selector comprises a first counting selector, a second counting selector and a third counting selector; wherein each count selector has: a respective first input coupled to the integration stage to receive the negated clock signal, a respective second input, a respective control input coupled to the control stage to receive a respective one of the control signals, and a respective output, the one or more count selectors being each configured to selectively couple the output to one of the first input and the second input in accordance with the control signal at the control input; wherein the second input of the first counter selector is configured to receive a predetermined logic signal; Wherein, the plurality of counting triggers include a first counting trigger, a second counting trigger, a third counting trigger and an Fth counting trigger which are cascaded with each other; Each counting flip-flop has a clock input, a data input, a first output, and a second output; wherein the second inputs of the second counter selector and the third counter selector are coupled to the second outputs of the first counter selector and the second counter selector, respectively; wherein the clock inputs of the first counting trigger, the second counting trigger and the third counting trigger are connected to the outputs of the first counting selector, the second counting selector and the third counting selector respectively, and the clock input of the Fth counting trigger is connected to the second output of the immediately preceding counting trigger, and the clock input of the counting trigger is configured to receive the trigger input signal; wherein the data inputs of the first counting trigger, the second counting trigger, the third counting trigger and the Fth counting trigger are connected to the second outputs of the first counting trigger, the second counting trigger, the third counting trigger and the Fth counting trigger respectively; and Wherein, the first output of the counting trigger is configured to generate the output signal.

12. The IMC device according to claim 1: in, The control stage is further configured to generate at least a second master control mirror current in response to the first bit line current, compare the second master control mirror current to a second reference current, and generate said control signal, said control signal indicating a comparison of the first master control mirror current to the first reference current and a comparison of the second master control mirror current to the second reference current; Wherein, the control stage is further configured to generate at least a third master control mirror current in response to the first bit line current, compare the third master control mirror current with at least a third reference current, and generate the control signal, which also indicates the comparison with the third reference current.

13. The IMC device of claim 1 , wherein the digital detector is configured to perform a plurality of successive sampling iterations, and in each sampling iteration: the integrating stage being configured to generate an integrated signal indicative of a time integral of the first total selected current, compare the integrated signal to a sampling threshold, and reset the integrated signal in response to the integrated signal reaching the sampling threshold; the integrating stage including a first inverter having an output providing an integrated signal and an integrating capacitive element coupled to the output of the first inverter, the first inverter being configured to receive a total select current indicative of a bit line current; as well as The charge counter stage is configured to update the output signal in response to the integrated signal reaching a sampling threshold.

14. The IMC device according to claim 1: wherein the bias circuit is configured to provide a bias voltage in response to a reference current; wherein the bias circuit includes a reference network having a variable reference impedance and configured to be passed through by a reference current, and the bias voltage is based on the reference voltage and the variable reference impedance; as well as Wherein the reference network includes a reference memory array configured to have a reference transconductance value, the variable reference impedance is based on the reference transconductance value, and the reference memory array represents a statistically significant sample of the memory array.

15. The IMC device according to claim 1: wherein the wordline activation circuit includes a timer configured to provide a timer signal, and a plurality of input-to-time converters electrically coupled to the timer and configured to receive the timer signal, each input-to-time converter comparing the timer signal to a respective one of the input values, and in response, each input-to-time converter providing a respective wordline activation signal; wherein the timer includes a corresponding integration stage; and The integrating stage of the digital detector has the same circuit diagram as the integrating stage of the timer.

16. The IMC device according to claim 1: wherein the memory array further comprises a plurality of second memory cells, the plurality of second memory cells are coupled to second bit lines, and each second memory cell is coupled to a corresponding word line among the word lines, the second bit lines are configured to receive a bias voltage, the second memory cells are configured to respectively store a corresponding calculation weight, and are configured to respectively receive a corresponding word line activation signal among the plurality of word line activation signals from the corresponding word line, the second memory cells are configured to be respectively traversed by a corresponding cell current according to the bias voltage, the corresponding word line activation signal and the corresponding calculation weight, the second bit lines are configured to be traversed by a second bit line current, the second bit line current being the sum of the cell currents of the second memory cells; wherein the IMC device further comprises a second digital detector coupled to the second bit line and configured to sample a second bit line current and provide the output signal in response to the second bit line current; as well as The second digital detector comprises: a respective control stage electrically coupled to the second bit line and configured to receive the second bit line current, generate at least a respective first master control mirror current in response to the second bit line current, compare the respective first master control mirror current to at least one respective first reference current, and generate one or more respective control signals indicative of the comparison; a corresponding selection stage electrically coupled to the control stage of the second digital detector and to the second bit line and configured to receive the second bit line current and the one or more corresponding control signals, and to generate a corresponding total selection current in response to the second bit line current and in accordance with the one or more corresponding control signals; a corresponding integrating stage electrically coupled to the select stage of the second digital detector and configured to receive and sample the corresponding total select current; and A corresponding charge counter stage is electrically coupled to the integration stage and to the control stage of the second digital detector and is configured to receive the sampled corresponding total selection current and the one or more corresponding control signals, and to generate the output signal according to the one or more corresponding control signals in response to the sampling of the second total selection current.

17. A method for controlling the IMC device according to claim 1, comprising: providing the plurality of word line activation signals to the first memory unit through a word line activation circuit; generating a bias voltage through a bias circuit and applying the bias voltage to a first bit line; generating, by a control stage, the at least first master control mirror current in response to the first bit line current; comparing, by a control stage, the at least first master control mirror current with the at least first reference current; generating, by a control stage, said one or more control signals indicative of said comparing; generating a total select current by the select stage in response to the first bit line current and in accordance with the one or more control signals; Sampling the total selection current through the integration stage; as well as The output signal is generated by the charge counter stage in response to sampling the first total selection current according to the one or more control signals.

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