System on chip, state information storage method, mainboard and electronic equipment
By setting up co-processing modules and nonvolatile memory in the on-chip system, the working status recording and saving problems caused by IP module abnormalities are solved, and the working status information of the IP module can still be recorded and saved after the on-chip system is down. , and retain exception information after reset.
Patent Information
- Application Number
- CN202411570098.4
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-11-05
- Publication Date
- 2025-02-14
AI Technical Summary
After the system on chip is down due to an abnormal IP module, the working status of each IP module is difficult to record and save, and the cause of the abnormality cannot be saved after reset.
A co-processing module is set up in the on-chip system, through which the module reads the working status information of the IP module and determines whether it is abnormal, and saves this information, including abnormal information, in the non-volatile memory.
Even if the system on chip is down due to an abnormal downtime due to an IP module, the co-processing module can still work normally, continuously record the working status information of the IP module, and retain this information in the non-volatile memory after reset, solving the problem of data being unable to be saved.
Smart Images
Figure CN119441132A_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the technical field of system on chip, and in particular to a system on chip, a state information storage method, a mainboard and an electronic device. Background Art
[0002] Currently, the working status of each IP module inside the system on chip is recorded in the status register or log. However, when the system on chip crashes due to an abnormal IP module inside the system on chip, the upper operating system will also crash, making it impossible to continue recording logs. In addition, after an abnormal crash, the system on chip will decide whether to trigger the reset process based on the severity of the abnormal IP module. Once the reset process is triggered, the data in the status register will be cleared after the reset, making it impossible for debuggers to check the cause of the abnormality before the system on chip is reset, which is not conducive to problem location. Summary of the invention
[0003] The purpose of the embodiments of the present application is to provide a system on chip, a status information storage method, a mainboard and an electronic device to solve the problem existing in the related art that after the system on chip crashes due to an IP module abnormality, the working status of each IP module is difficult to record and save.
[0004] The embodiment of the present application provides a system on chip, including a co-processing module, a non-volatile memory, and an IP module, wherein the co-processing module is connected to the non-volatile memory; wherein: the co-processing module is used to cyclically perform the following operations:
[0005] The working status information of the IP module is read out from the IP module; whether the IP module is abnormal is determined according to the working status information of the IP module; the working status information of the IP module is saved in the non-volatile memory, and the abnormal information is saved in the non-volatile memory for the IP module with abnormality.
[0006] In the above implementation scheme, a co-processing module is set in the system on chip, and the working status information of the IP module is read through the co-processing module to determine whether the IP module is abnormal, and the working status information of the IP module and the abnormal information of the IP module with abnormality are stored through a non-volatile memory. In this way, since the co-processing module is a processing module developed and applied to assist the central processing unit to complete the processing work that it cannot execute or executes inefficiently and ineffectively, it is independent of the central processing unit. After the central processing unit crashes, the co-processing module can still work independently, and it can be unaffected by whether other IP modules are abnormal, so it will not crash due to the abnormality of the IP module. This makes it possible that even if the system on chip crashes due to the abnormality of the IP module, the co-processing module can still work normally, thereby solving the problem that the working status information of the IP module inside the system on chip cannot be obtained in real time after the crash, so that after the system on chip crashes due to the abnormality of the IP module, the working status of the IP module can still be continuously recorded. Since the working status information and the abnormal information are stored in the non-volatile memory by the co-processing module, when the system on chip is reset, even if the data in the status register of the IP module is cleared, the working status information of the IP module and the abnormal information of the IP module with abnormality are still retained in the non-volatile memory, which solves the problem that the relevant data cannot be saved after the system on chip is reset abnormally. In summary, the solution of the embodiment of the present application solves the problem that the working status of the IP module is difficult to record and save after the system on chip crashes due to the abnormality of the IP module.
[0007] Furthermore, the abnormal information includes a first abnormal information identification value; the first abnormal information identification value is used to indicate an abnormality of the IP module.
[0008] In the above implementation, by storing the first abnormal information identification value for the IP module with the abnormality in the non-volatile memory, when subsequent engineers locate the abnormality, the abnormality can be located more easily, thereby improving the repair efficiency of relevant staff.
[0009] Furthermore, the co-processing module is also used to access the non-volatile memory to determine the target IP module that does not have the first exception information identification value before reading the working status information of the IP module from the IP module in each round of loop; correspondingly, in each round of loop, the co-processing module is specifically used to read the working status information of the target IP module from the target IP module, and determine whether the target IP module is abnormal based on the working status information of the target IP module, and save the working status information of the target IP module in the non-volatile memory, and save the exception information in the non-volatile memory for the target IP module with an abnormality.
[0010] In the above implementation, the co-processing module first accesses the non-volatile memory to identify all target IP modules in the IP module that do not have the first abnormal information identification value (i.e., normal IP modules that have not been recorded as abnormal), and then only obtains the working status information of the normal IP modules and determines whether they are abnormal. For the IP modules that have been determined to be abnormal before, the working status information is no longer obtained again. On the one hand, this reduces the workload of the co-processing module and improves the processing efficiency. On the other hand, since the working status information of the IP modules that have been determined to be abnormal is no longer obtained, the working status information of the abnormal IP module stored in the non-volatile memory is the working status information of the abnormal IP module when the abnormal IP module is just found to be abnormal by the co-processing module, which is beneficial for the relevant staff to obtain the on-site information when the abnormal IP module occurs abnormally when performing abnormal repair, which is more conducive to the relevant staff to perform abnormal repair.
[0011] Furthermore, any of the IP modules includes one or more working states, and the co-processing module is specifically used to read the working state information of all working states of the IP module from any of the IP modules; wherein, for any of the IP modules, when any working state information of the IP module is abnormal, it indicates that the IP module is abnormal.
[0012] An IP module may include one or more working states, for example, an IP module may have a data input state, a data processing state, and a data output state. The specific working states are determined by the IP module used. In the above implementation, when any working state information of the IP module is abnormal, it means that some work of the IP module has problems. Therefore, when any working state information of the IP module is abnormal, the IP module is determined to be abnormal, which can quickly and accurately determine the abnormal IP module.
[0013] Furthermore, the abnormal information also includes the abnormal time.
[0014] In the above implementation, by recording the abnormal time of the abnormal IP module in the non-volatile memory, when subsequent engineers locate the abnormality, they can obtain more abundant information, which is more conducive to locating the abnormality and improving the repair efficiency of relevant staff.
[0015] Furthermore, a state storage space corresponding to the IP module is pre-set in the non-volatile memory; each of the state storage spaces includes a state storage space size recording bit for recording size information of the state storage space corresponding to each of the IP modules; the size information recorded in the state storage space size recording bit is used to determine the address of the state storage space together with a preset starting address.
[0016] In the above implementation, by pre-setting the corresponding state storage space in the non-volatile memory for each IP module and recording the size of the state storage space, when the co-processing module reads and writes the non-volatile memory, it can quickly locate the address of the IP module currently to be accessed based on the preset starting address and the size of the state storage space, thereby realizing accurate reading and writing of the working status information and exception information of the IP module in the non-volatile memory.
[0017] Furthermore, any of the IP modules includes one or more working states, and each working state in the IP module corresponds to a record of working state information; each of the state storage spaces also includes one or more working state recording bits; wherein, for the same IP module, the number of working state recording bits is the same as the number of working states of the IP module, and the working state recording bits correspond one-to-one to the working states of the IP module, and are used to record the working state information of the corresponding working state.
[0018] In the above implementation, the working status information of the IP module in the working state is recorded by setting a working status recording bit for each IP module with the same number of working states and corresponding to the working state it has. In this way, when abnormal repair is required, the working status of the IP module in the working state can be known by reading the data of the working status recording bit, thereby facilitating relevant staff to locate and repair the abnormality.
[0019] Furthermore, each of the state storage spaces also includes an abnormal state identification bit and an abnormal time recording bit; the abnormal information includes a first abnormal information identification value to be written into the abnormal state identification bit and an abnormal time to be written into the abnormal time recording bit.
[0020] In the above implementation, by setting an abnormal status identification bit specifically for recording the abnormal information identification value and an abnormal time recording bit specifically for recording the abnormal time, when abnormal repair is required, the relevant staff can determine whether the data is the abnormal information identification value and the abnormal time by judging the location of the data, thereby facilitating the relevant staff to locate and repair the abnormality.
[0021] Furthermore, the co-processing module is also used to obtain a storage space clear flag value before reading the working status information of the IP module from the IP module in each cycle, and clear the working status information and exception information stored in the non-volatile memory when the storage space clear flag value is a preset clear value.
[0022] In the above implementation, the storage space clearing flag value is first obtained in each cycle, so that when the storage space clearing flag value is obtained to be a preset clearing value, the working state information and abnormality information stored in the non-volatile memory are cleared. In this way, when facing a situation where the abnormality has been repaired, the working state information and abnormality information stored in the non-volatile memory can be cleared and restored to the initial state by modifying the storage space clearing flag value, so that the subsequently recorded working state information and abnormality information can be adapted to the latest situation of the system on chip.
[0023] The embodiment of the present application further provides a state information preservation method, which is applied to a co-processing module in a system on chip, wherein the system on chip further includes a non-volatile memory and an IP module, and the co-processing module is connected to the non-volatile memory; wherein: the state information preservation method includes: cyclically performing the following operations:
[0024] The working status information of the IP module is read out from the IP module; whether the IP module is abnormal is determined according to the working status information of the IP module; the working status information of the IP module is saved in the non-volatile memory, and the abnormal information of the abnormal IP module is saved in the non-volatile memory.
[0025] In the above implementation scheme, a co-processing module is set in the system on chip, and the working state information of the IP module is read through the co-processing module to determine whether the IP module is abnormal, and the working state information of the IP module and the abnormal information of the IP module with abnormality are stored through the non-volatile memory. In this way, since the co-processing module will not be down due to the abnormality of the IP module, even if the system on chip is down due to the abnormality of the IP module, the co-processing module can still work normally, thereby solving the problem that the working state information of the IP module inside the system on chip cannot be obtained in real time after the downtime, so that after the system on chip is down due to the abnormality of the IP module, the working state of the IP module can still be continuously recorded. And because the working state information and the abnormality information are stored in the non-volatile memory by the co-processing module, when the system on chip is reset, even if the data in the status register of the IP module is cleared, the working state information of the IP module and the abnormality information of the IP module with abnormality are still retained in the non-volatile memory, which solves the problem that the relevant data cannot be saved after the abnormal reset of the system on chip. In summary, the solution of the embodiment of the present application can solve the problem that the working status of the IP module is difficult to record and save after the on-chip system crashes due to an IP module abnormality.
[0026] Furthermore, the abnormal information includes a first abnormal information identification value; the first abnormal information identification value is used to indicate an abnormality of the IP module.
[0027] Furthermore, in each round of the cycle, before reading the working status information of the IP module from the IP module, the method further includes: accessing the non-volatile memory to determine a target IP module that does not have the first abnormal information identification value; correspondingly, reading the working status information of the IP module from the IP module includes: reading the working status information of the target IP module from the target IP module; judging whether the IP module is abnormal according to the working status information of the IP module, including: judging whether the target IP module is abnormal according to the working status information of the target IP module; saving the working status information of the IP module in the non-volatile memory, and saving abnormal information in the non-volatile memory for an abnormal IP module with an abnormality, including: saving the working status information of the target IP module in the non-volatile memory, and saving abnormal information in the non-volatile memory for the target IP module with an abnormality.
[0028] Furthermore, any of the IP modules includes one or more working states, and the co-processing module is specifically used to read the working state information of all working states of the IP module from any of the IP modules; wherein, for any of the IP modules, when any working state information of the IP module is abnormal, it indicates that the IP module is abnormal.
[0029] Furthermore, in each cycle, before reading the working status information of the IP module from the IP module, the method also includes: obtaining a storage space clear flag value, and when the storage space clear flag value is a preset clear value, clearing the working status information and abnormal information stored in the non-volatile memory.
[0030] An embodiment of the present application also provides a mainboard, comprising any one of the above-mentioned systems on a chip.
[0031] An embodiment of the present application also provides an electronic device, including the above-mentioned mainboard. BRIEF DESCRIPTION OF THE DRAWINGS
[0032] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for use in the embodiments of the present application will be briefly introduced below. It should be understood that the following drawings only show certain embodiments of the present application and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other related drawings can be obtained based on these drawings without paying creative work.
[0033] Figure 1 A schematic diagram of the structure of a system on a chip provided in an embodiment of the present application;
[0034] Figure 2A flowchart of a method for storing status information provided in an embodiment of the present application;
[0035] Figure 3 A schematic diagram of the structure of a mainboard provided in an embodiment of the present application;
[0036] Figure 4 A schematic diagram of a more specific system-on-chip structure provided in an embodiment of the present application;
[0037] Figure 5 A flowchart of a more specific state information storage process provided in an embodiment of the present application;
[0038] Figure 6 A schematic diagram of a flow chart of an IP module anomaly detection performed by a coprocessor according to an embodiment of the present application. DETAILED DESCRIPTION
[0039] The technical solutions in the embodiments of the present application will be described below in conjunction with the drawings in the embodiments of the present application.
[0040] Embodiment 1:
[0041] In order to solve the problem in the related art that after the system on chip crashes due to an abnormal IP module, the working status of each IP module is difficult to record and save, an embodiment of the present application provides a system on chip, which can be referred to as Figure 1 As shown, it includes a co-processing module, a non-volatile memory, and an IP module. The co-processing module is connected to the non-volatile memory, and the co-processing module can access each IP module.
[0042] IP module is a general term for integrated circuit cores with intellectual property cores. It is an integrated circuit design macro module that is gradually separated from the SOC (system on chip) design link, has been repeatedly verified, has specific functions, can be reused, and contains specific core elements (such as instruction sets, function descriptions, codes, etc.), such as AHB (Advanced High Performance Bus, Advanced High Performance Bus) module, APB (Advanced Peripheral Bus, Peripheral Bus) module, USB (Universal Serial Bus, Serial Universal Bus) module, CPU (Central Processing Unit, Central Processing Unit), etc., which can reduce the cost of redundant design in the SOC design link, reduce the risk of errors, and improve the efficiency of SOC design. In the embodiment of the present application, IP module refers to other IP modules except the co-processing module and non-volatile memory described in the embodiment of the present application.
[0043] In the embodiments of the present application, non-volatile memory should be understood in a broad sense, and any memory in which data will not be lost due to reset after the on-chip system is powered on and shut down can be used as the non-volatile memory described in the embodiments of the present application. Exemplarily, the non-volatile memory described in the embodiments of the present application may adopt NVM (Non-Volatile Memory) in the traditional sense, such as EPROM (Erasable Programmable Read-Only Memory), EEPROM (Electrically Erasable Programmable Read-Only Memory), Flash Memory, MRAM (Magnetic Random Access Memory), FeRAM (Ferroelectric Random Access Memory), PCM (Phase Change Memory), etc., and may also adopt SRAM (Static Random-Access Memory) and other memories that do not have a reset function themselves, and can keep data unchanged as long as the power is turned on and no overwrite operation is actively performed. This type of memory will not cause data loss due to a reset of the on-chip system when the power is kept on. In a broad sense, it also has some characteristics of non-volatile storage and is also considered to be a non-volatile memory in the embodiments of the present application.
[0044] In the embodiment of the present application, the co-processing module refers to a processing module developed and applied to assist the central processing unit to complete the processing work that it cannot perform or performs inefficiently or ineffectively. It is independent of the central processing unit. After the central processing unit crashes, the co-processing module can still work independently, and it is a functional module that is not affected by whether other IP modules are abnormal. In the embodiment of the present application, the co-processing module can be various types of co-processors that have been repeatedly verified and can be reused, or it can be a chip function module that has been specially designed according to the functions to be implemented by the co-processing module introduced in the embodiment of the present application and has not been repeatedly verified. In the embodiment of the present application, the co-processing module is a chip that has the authority to access the working status information of each IP module in the non-volatile memory.
[0045] In the embodiment of the present application, the co-processing module is used to cyclically perform the following operations:
[0046] Read the working status information of the IP module from the IP module.
[0047] Determine whether the IP module is abnormal based on the working status information of the IP module.
[0048] The working state information of the IP module is saved in the non-volatile memory, and the abnormal information of the IP module with abnormality is saved in the non-volatile memory.
[0049] It is understood that in the embodiment of the present application, an IP module will have one or more working states, and the specific number of working states is determined by the IP module itself. It is understood that when designing an IP module, a corresponding status register will be set for each working state it has, which is used to record the working state information of each working state. Exemplarily, for some IP modules, it is determined during the design that it has three working states, namely, data input state, data processing state, and data output state. Correspondingly, three status registers will be set to record the working state information of the data input state, the working state information of the data processing state, and the working state information of the data output state.
[0050] In the embodiment of the present application, the working state information may include a first state value and a second state value, the first state value indicates that the corresponding working state is normal, and the second state value indicates that the corresponding working state is abnormal. For example, in the above example, assuming that the working state information corresponding to the data input state is the first state value, it indicates that the data input of the IP module is normal; on the contrary, assuming that the working state information corresponding to the data input state is the second state value, it indicates that the data input of the IP module is abnormal.
[0051] In an embodiment of the present application, when the co-processing module determines whether the IP module is abnormal based on the working status information of the IP module, the working status information of all working statuses of each IP module can be read from each IP module. If at least one working status information of a certain IP module is abnormal, that is, the second status value, it can be determined that the IP module is abnormal.
[0052] In the embodiment of the present application, when the working status information of the IP module is saved in the non-volatile memory, and when the abnormal information is saved in the non-volatile memory for the IP module with an abnormality, the storage can be performed based on the IP module. That is, the co-processing module can first store the working status information of an IP module in the non-volatile memory, and when the IP module has an abnormality, the abnormal information of the IP module is also stored in the non-volatile memory, and then the working status information of the next IP module (including the abnormal information when the abnormality occurs) is stored.
[0053] In the embodiment of the present application, the abnormal information of the IP module may include a first abnormal information identification value, and the first abnormal information identification value is used to characterize the abnormality of the IP module. In this way, by storing the first abnormal information identification value for the abnormal IP module in the non-volatile memory, when subsequent engineers perform abnormal location, it is easier to locate the abnormality, thereby improving the repair efficiency of relevant staff.
[0054] In a feasible implementation of the embodiment of the present application, the co-processing module can traverse all IP modules, read the working status information of the IP module from the status register of the IP module, and determine whether the IP module is abnormal based on the working status information of the IP module, and then save the working status information of the IP module in a non-volatile memory. For the IP module with an abnormality, if the abnormal information of the IP module has been recorded before, the abnormal information of the IP module may no longer be saved.
[0055] When the working status information of the IP module is saved in the non-volatile memory, the previously stored working status information can be retained and the time information can be added, so that subsequent engineers can determine the changes in the working status of the IP module based on the time information when checking.
[0056] In addition, when the working status information of the IP module is saved in the non-volatile memory, the previously stored working status information may not be retained, but the original working status information may be overwritten with the latest working status information.
[0057] In another feasible implementation of the embodiment of the present application, the co-processing module may be, in each round of the cycle, before reading the working status information of the IP module from the IP module, access the non-volatile memory to determine the target IP module that does not have the first exception information identification value, and then read the working status information of the target IP module from the target IP module, and determine whether the target IP module is abnormal based on the working status information of the target IP module, and save the working status information of the target IP module in the non-volatile memory, and save the exception information in the non-volatile memory for the target IP module with the exception.
[0058] In this way, the co-processing module first accesses the non-volatile memory to identify all target IP modules in the IP module that do not have the first abnormal information identification value (that is, normal IP modules that have not been recorded as abnormal), and then only obtains the working status information of the normal IP modules and determines whether they are abnormal. For the IP modules that have been determined to be abnormal before, the working status information is no longer obtained again. On the one hand, this reduces the workload of the co-processing module and improves the processing efficiency. On the other hand, since the working status information of the IP modules that have been determined to be abnormal is no longer obtained, the working status information of the abnormal IP module stored in the non-volatile memory is the working status information of the abnormal IP module when the abnormal IP module is just found to be abnormal by the co-processing module, which is beneficial for the relevant staff to obtain the on-site information when the abnormal IP module occurs abnormally when performing abnormal repair, which is more conducive to the relevant staff to perform abnormal repair.
[0059] In an embodiment of the present application, the abnormal information of the IP module may also include the abnormal time of the IP module, so that when subsequent engineers locate the abnormality, they can understand more abundant information, which is more conducive to locating the abnormality and improving the repair efficiency of relevant staff.
[0060] In the embodiment of the present application, the abnormal moment of the IP module may be the moment when the co-processing module determines that the IP module is abnormal based on the working status information of the IP module.
[0061] In a feasible implementation of the embodiment of the present application, a unique identifier can be assigned to each IP module, and then when the working status information and exception information of each IP module are saved in a non-volatile memory, the unique identifier of the IP module to which it belongs can be added to the working status information and exception information, so that the IP module corresponding to the working status information and exception information can be determined based on the unique identifier in the subsequent process.
[0062] In another feasible implementation of the embodiment of the present application, state storage spaces corresponding to each IP module may be pre-set in the non-volatile memory, and then the working status information and abnormal information of each IP module may be written into the designated position of the corresponding state storage space.
[0063] In order to facilitate the subsequent positioning of the state storage space of different IP modules, a state storage space size record bit can be set in each state storage space to record the size information of the state storage space corresponding to each IP module, and then the address of each state storage space can be determined based on the size information recorded in the state storage space size record bit and the preset starting address.
[0064] Exemplarily, the starting address of the state storage space corresponding to the nth IP module is: IPn_SIZE_addr=START_ADDR+IP0_SIZE+IP1_SIZE+…+IP(n-1)_SIZE; wherein START_ADDR is the preset starting address (that is, the starting address of the state storage space corresponding to all IP modules), IP0_SIZE is the state storage space size of IP module 0, IP1_SIZE is the state storage space size of IP module 1,…, +IP(n-1)_SIZE is the state storage space size of the nth IP module.
[0065] In the above feasible implementation, each state storage space may also include one or more working state recording bits. For the same IP module, the number of working state recording bits is the same as the number of working states of the IP module, and the working state recording bits correspond one-to-one to the working states of the IP module, and are used to record the working state information of the corresponding working state. In this way, when an abnormality repair is required, the working state of the IP module in each working state can be known by reading the data of each working state recording bit, so as to facilitate the relevant staff to locate and repair the abnormality.
[0066] In the above feasible implementation, each state storage space may also include an abnormal state identification bit and an abnormal time recording bit. The abnormal information includes a first abnormal information identification value to be written into the abnormal state identification bit and an abnormal time to be written into the abnormal time recording bit. In this way, when abnormal repair is required, the relevant staff can determine whether the data is an abnormal information identification value and an abnormal time by judging the location of the data, thereby facilitating the relevant staff to locate and repair the abnormality.
[0067] In the above feasible implementation, the abnormal information identification value recorded in the abnormal state identification bit can default to the second abnormal information identification value indicating that the IP module is normal. When the IP module is abnormal, the co-processing module can modify the second abnormal information identification value recorded in the abnormal state identification bit to the first abnormal information identification value.
[0068] It can be understood that in the above feasible implementation, the arrangement order of each record bit in the state storage space can be preset, and the size of each record bit can be preset. For example, since the abnormal identification information and each working state information only need to represent two situations, they can be represented by the values 0 and 1 respectively, so the size of the abnormal state identification bit and the working state record bit can be preset to 1 bit. The expression method of the abnormal time and the state storage space size of each IP module is consistent, so the size of the abnormal time record bit and the size of the state storage space size record bit corresponding to each IP module are also the same and can be preset.
[0069] Therefore, when performing read and write operations on each record bit, the address of each record bit can be determined based on the start address of the state storage space corresponding to each IP module, combined with the sorting and the size of each record bit.
[0070] Exemplarily, it is assumed that the arrangement order of the record bits in the state storage space is state storage space size record bit, abnormal state identification bit, abnormal time record bit, working state record bit 0, working state record bit 1, ..., working state record bit X.
[0071] Then, the abnormal state flag bit address of IP module n is: IPn_exception_flag_addr=IPn_SIZE_addr+SIZE(IPn SIZE), wherein IPn_SIZE_addr is the starting address of the state storage space corresponding to IP module n, and SIZE(IPn SIZE) is the size of the state storage space size record bit.
[0072] The abnormal time recording bit address of IP module n is: IPn_exception_time_addr=IPn_exception_flag_addr+SIZE(IPn_exception_flag), wherein SIZE(IPn_exception_flag) is the size of the abnormal state flag bit.
[0073] The address of the xth working status record bit of IP module n is: IPn_status_x_addr=IPn_exception_time_addr+SIZE(IPn status 0)+SIZE(IPn status 1)+…+SIZE(IPn status x-1). Among them, SIZE(IPn status 0) is the size of working status record bit 0, SIZE(IPn status 1) is the size of working status record bit 1, and SIZE(IPn status x-1) is the size of working status record bit x-1.
[0074] In an optional implementation of the embodiment of the present application, the co-processing module can also obtain the storage space clear flag value before reading the working status information of each IP module from each IP module in each round of cycle, and when the storage space clear flag value is a preset clear value, clear the working status information and exception information stored in the non-volatile memory.
[0075] It can be understood that after collecting the exception information, once the engineer actively intervenes or the on-chip system crashes due to IP exceptions, which leads to the intervention of engineers, the exception will be repaired at this time, and the engineer can use external tools (such as JTAG (Joint Test Action Group) debugging board) to set the storage space clear flag value to a preset clear value, so that the working status information and exception information stored in the non-volatile memory are cleared and restored to the initial state, so that the subsequently recorded working status information and exception information can be adapted to the latest situation of the on-chip system.
[0076] It can be understood that after clearing the working status information and exception information stored in the non-volatile memory, the co-processing module can modify the storage space clear flag value to the default value. When the co-processing module determines that the storage space clear flag value is the default value, it enters the operation of reading the working status information of each IP module from each IP module.
[0077] In the embodiment of the present application, the co-processing module can trigger each cycle by means of a timed interrupt trigger.
[0078] Exemplarily, a timer may be set in the co-processing module, and when the timer reaches a set time, an interrupt signal is generated to trigger the co-processing module to execute a new cycle.
[0079] Based on the same inventive concept, the present application also provides a method for preserving state information, which is applied to the co-processing module in the system on chip provided above. Figure 2 As shown, the method includes:
[0080] S201: Read the working status information of each IP module from the IP module.
[0081] S202: Determine whether the IP module is abnormal according to the working status information of the IP module.
[0082] S203: Save the working status information of the IP module in the non-volatile memory, and save the abnormal information of the abnormal IP module in the non-volatile memory.
[0083] In an embodiment of the present application, in each cycle, before reading the working status information of the IP module from the IP module, the method may further include: accessing a non-volatile memory to determine a target IP module that does not have a first abnormal information identification value.
[0084] Correspondingly, reading the working status information of the IP module from the IP module may include: reading the working status information of the target IP module from the target IP module.
[0085] Correspondingly, judging whether the IP module is abnormal according to the working status information of the IP module may include: judging whether the target IP module is abnormal according to the working status information of the target IP module.
[0086] Correspondingly, saving the working status information of the IP module in the non-volatile memory, and saving the abnormal information in the non-volatile memory for the abnormal IP module with the abnormality may include: saving the working status information of the target IP module in the non-volatile memory, and saving the abnormal information in the non-volatile memory for the target IP module with the abnormality.
[0087] In an embodiment of the present application, in each cycle, the process of determining whether the IP module is abnormal according to the working status information of the IP module may include: for each IP module, determining whether at least one working status information among all the working status information of the IP module is abnormal. If at least one working status information among all the working status information of the IP module is abnormal, then the IP module is determined to be abnormal. If all the working status information of the IP module is normal, then the IP module is determined to be normal.
[0088] In an embodiment of the present application, in each round of cycle, before reading the working status information of the IP module from the IP module, it may also include: obtaining a storage space clear flag value, and when the storage space clear flag value is a preset clear value, clearing the working status information and abnormal information stored in the non-volatile memory.
[0089] In the embodiment of the present application, the above method can be programmed into the firmware of the co-processing module so that the co-processing module can execute it.
[0090] Based on the scheme provided by the embodiment of the present application, by setting a co-processing module in the system on chip, the working state information of each IP module is read through the co-processing module and whether each IP module is abnormal, and the working state information of each IP module and the abnormal information of the IP module with abnormality are stored through the non-volatile memory. In this way, since the co-processing module will not crash due to the abnormality of the IP module, even if the system on chip crashes due to the abnormality of the IP module, the co-processing module can still work normally, thereby solving the problem that the working state information of each IP module inside the system on chip cannot be obtained in real time after the crash, so that after the system on chip crashes due to the abnormality of the IP module, the working state of each IP module can still be continuously recorded. And because the working state information and the abnormal information are stored in the non-volatile memory by the co-processing module, when the system on chip is reset, even if the data in the status register of each IP module is cleared, the working state information of each IP module and the abnormal information of the IP module with abnormality are still retained in the non-volatile memory, which solves the problem that the relevant data cannot be saved after the abnormal reset of the system on chip. In summary, the solution of the embodiments of the present application can solve the problem that the working status of each IP module is difficult to record and save after the on-chip system crashes due to an IP module abnormality.
[0091] Based on the same inventive concept, an embodiment of the present application further provides a mainboard, which includes the system on chip provided by the embodiment of the present application.
[0092] It can be understood that in the embodiment of the present application, the mainboard may also include devices such as an off-chip memory, for example Figure 3 As shown, off-chip memory can be connected to the on-chip system.
[0093] It can also be understood that in the embodiment of the present application, the IP module in the system on chip may also include a central processing unit and other IP modules besides the central processing unit, the co-processing module, and the non-volatile memory, such as Figure 4 shown.
[0094] It can also be understood that in the embodiments of the present application, the so-called system-on-chip crash mainly refers to the crash of the central processing unit. The crash of the central processing unit may be caused by abnormalities of other IP modules other than the central processing unit, the co-processing module, and the non-volatile memory, or may be caused by the central processing unit itself.
[0095] Based on the same inventive concept, an electronic device is also provided in an embodiment of the present application, which includes the mainboard provided in an embodiment of the present application.
[0096] The electronic device may also include more components. For example, it may also have an external communication interface, such as a USB interface, a CAN bus interface, etc.; for another example, it may also have an information display component such as a display screen, but this is not a limitation.
[0097] In the embodiments of the present application, the electronic device may be, but is not limited to, a computer, a tablet, a smart phone, a smart watch or other smart terminal device, or may be an intermediate device such as a server.
[0098] To facilitate understanding of the solution of the embodiment of the present application, the following takes a specific implementation method of a coprocessor as an example to exemplify the embodiment of the present application:
[0099] See also Figure 5 As shown, the overall process includes:
[0100] 1. The system on chip is powered on and the coprocessor starts working.
[0101] 2. The coprocessor starts the timing detection task and triggers this round of detection through the timing interrupt.
[0102] 3. After the coprocessor timing task is triggered, read the storage space clear flag value.
[0103] 4. If the clear flag is set to 1, the coprocessor clears the information stored in the non-volatile memory and proceeds to the next step. If the clear flag is set to 0, proceed to the next step.
[0104] 5. The detection task detects whether the IP module is abnormal.
[0105] 6. Record the working status information and abnormal time of the abnormal IP module in the non-volatile memory, and modify the abnormal information identification value of the abnormal IP module in the non-volatile memory to the first abnormal information identification value.
[0106] 7. Repeat steps 2-6.
[0107] 8. The on-chip system automatically resets after recovery from a crash.
[0108] 9. Use an external tool to set the fault storage space clear flag to 1 and go to step 2.
[0109] See also Figure 6 As shown, Figure 5 Steps 5 and 6 in include:
[0110] 1. Read the abnormal status flag of the nth IP from the non-volatile memory, and determine whether the abnormal status flag is set (ie, whether the value of the abnormal status flag is updated to the first abnormal information flag value).
[0111] 2. If the abnormal status flag is set, it means that the corresponding IP module has experienced an abnormality before and the working status information has been recorded, then no operation is performed on the IP module.
[0112] 3. If the abnormal status flag is not set, read the working status information of the IP module corresponding to the abnormal status flag.
[0113] 4. If the working status information of the IP module is abnormal, the abnormal status flag of the IP module is set, and the working status information and abnormal time of the IP module are recorded in the allocated status storage space of the IP module.
[0114] 5. Repeat steps 1-4 until the working status information of all IP modules is confirmed and recorded.
[0115] Based on the solution of the embodiment of the present application, the coprocessor can work independently and the non-volatile memory can store data for a long time. After the system on chip crashes, the coprocessor can continue to obtain the abnormal IP module's working status information and record it in the non-volatile memory. To a certain extent, the problem that the system on chip crash log cannot be recorded and the status register is cleared after reset is solved.
[0116] In the embodiments provided in this application, it should be understood that the disclosed devices and methods can be implemented in other ways. The device embodiments described above are only exemplary, for example, the connections shown or discussed may be indirect connections through some communication interfaces, devices or units, which may be electrical, mechanical or other forms.
[0117] In this document, relational terms such as first and second, etc. are used merely to distinguish one entity or operation from another entity or operation, but do not necessarily require or imply any such actual relationship or order between these entities or operations.
[0118] As used herein, a plurality refers to two or more than two.
[0119] The above description is only an embodiment of the present application and is not intended to limit the protection scope of the present application. For those skilled in the art, the present application may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included in the protection scope of the present application.
Claims
1. A system on chip, characterized in that: The system comprises a co-processing module, a non-volatile memory and an IP module, wherein the co-processing module is connected to the non-volatile memory; wherein: The co-processing module is used to perform the following operations in a loop: Reading the working status information of the IP module from the IP module; Determining whether the IP module is abnormal according to the working status information of the IP module; The working state information of the IP module is stored in the non-volatile memory, and the abnormal information of the IP module with abnormality is stored in the non-volatile memory.
2. The system on chip according to claim 1, wherein: The abnormal information includes a first abnormal information identification value; the first abnormal information identification value is used to indicate an abnormality of the IP module.
3. The system on chip according to claim 2, wherein: The co-processing module is further configured to access the non-volatile memory to determine a target IP module that does not have the first abnormal information identification value before reading the working status information of the IP module from the IP module in each cycle; Correspondingly, in each round of loop, the co-processing module is specifically used to read the working status information of the target IP module from the target IP module, and determine whether the target IP module is abnormal based on the working status information of the target IP module, and save the working status information of the target IP module in the non-volatile memory, and save the abnormal information in the non-volatile memory for the target IP module with an abnormality.
4. The system on chip according to claim 1, wherein: Any of the IP modules includes one or more working states, and the co-processing module is specifically used to read the working state information of all working states of the IP module from any of the IP modules; wherein, for any of the IP modules, when any working state information of the IP module is abnormal, it indicates that the IP module is abnormal.
5. The system on chip according to claim 1, wherein: The non-volatile memory is pre-set with a state storage space corresponding to the IP module; Each of the state storage spaces includes a state storage space size recording bit for recording size information of the state storage space corresponding to each of the IP modules; the size information recorded by the state storage space size recording bit is used to determine the address of the state storage space together with a preset starting address.
6. The system on chip according to claim 5, characterized in that Any of the IP modules includes one or more working states, and each working state in the IP module corresponds to a record of working state information; Each of the status storage spaces also includes one or more working status recording bits; wherein, for the same IP module, the number of working status recording bits is the same as the number of working states of the IP module, and the working status recording bits correspond one-to-one to the working states of the IP module, and are used to record the working status information of the corresponding working states.
7. The system on chip according to claim 5, characterized in that Each of the state storage spaces also includes an abnormal state identification bit and an abnormal time recording bit; the abnormal information includes a first abnormal information identification value to be written into the abnormal state identification bit and an abnormal time to be written into the abnormal time recording bit.
8. The system on chip according to any one of claims 1 to 7, characterized in that: The co-processing module is also used to obtain a storage space clear flag value in each cycle before reading the working status information of the IP module from the IP module, and clear the working status information and abnormal information stored in the non-volatile memory when the storage space clear flag value is a preset clear value.
9. A method for storing status information, characterized in that: In a co-processing module applied to a system on chip, the system on chip further includes a non-volatile memory and an IP module, and the co-processing module is connected to the non-volatile memory; wherein: the state information saving method includes: The loop does the following: Reading the working status information of the IP module from the IP module; Determining whether the IP module is abnormal according to the working status information of the IP module; The working state information of the IP module is stored in the non-volatile memory, and the abnormal information of the abnormal IP module with abnormality is stored in the non-volatile memory.
10. The method for storing status information according to claim 9, wherein: The abnormal information includes a first abnormal information identification value; the first abnormal information identification value is used to indicate an abnormality of the IP module.
11. The method for storing status information according to claim 9, wherein: In each cycle, before reading the working status information of the IP module from the IP module, the method further includes: accessing the non-volatile memory to determine a target IP module that does not have the first abnormal information identification value; Correspondingly, reading the working status information of the IP module from the IP module includes: reading the working status information of the target IP module from the target IP module; Judging whether the IP module is abnormal according to the working status information of the IP module includes: judging whether the target IP module is abnormal according to the working status information of the target IP module; The working status information of the IP module is saved in the non-volatile memory, and the abnormal information of the abnormal IP module with an abnormality is saved in the non-volatile memory, including: the working status information of the target IP module is saved in the non-volatile memory, and the abnormal information of the target IP module with an abnormality is saved in the non-volatile memory.
12. The method for storing status information according to claim 9, wherein: Any of the IP modules includes one or more working states, and the co-processing module is specifically used to read the working state information of all working states of the IP module from any of the IP modules; wherein, for any of the IP modules, when any working state information of the IP module is abnormal, it indicates that the IP module is abnormal.
13. The method for storing status information according to any one of claims 9 to 12 is characterized in that: In each cycle, before reading the working status information of each IP module from each IP module, the method further includes: A storage space clearing flag value is obtained, and when the storage space clearing flag value is a preset clearing value, the working status information and abnormality information stored in the non-volatile memory are cleared.
14. A motherboard, characterized in that: The method comprises a system on chip as claimed in any one of claims 1 to 8.
15. An electronic device, characterized in that: Comprising the mainboard as claimed in claim 14.