Sparse matrix operation method and apparatus, and computing device

Abstract

The embodiment of the invention belongs to the technical field of computing, and particularly relates to a sparse matrix operation method, a processor and computing equipment. The processor comprises a sparse matrix processing unit and a sparse vector operation unit. The operation method executed by the processor comprises the steps that the sparse matrix processing unit obtains a first numerical matrix and a first index matrix corresponding to the first sparse matrix and a second numerical matrix and a second index matrix corresponding to the second sparse matrix; the sparse vector operation unit determines target elements needing dot product operation in each row of elements of the first numerical matrix and each column of elements of the second numerical matrix based on each row of elements of the first index matrix and each column of elements included in the second index matrix; and performing dot product operation on the target element to obtain a first result matrix obtained by performing sparse multiplication operation on the first sparse matrix and the second sparse matrix. By adopting the method and the device, the number of zero elements participating in sparse matrix multiplication can be reduced, and the efficiency of executing the sparse matrix multiplication can be improved.

Description

[0001] This application is a divisional application. The application number of the original application is 202311240428.9, and the original application date is September 22, 2023. The entire contents of the original application are incorporated into this application by reference.

[0002] This application and the Chinese application with application number 202311240428.9 both claim the priority of the Chinese patent application with application number 202310781382.5 filed on June 28, 2023 and invention name “A sparse matrix multiplication method”, all contents of which are incorporated by reference into this application. Technical Field

[0003] The present application relates to the field of computing technology, and in particular to a sparse matrix operation method, processor and computing device. Background Art

[0004] Matrix multiplication is widely used in various scientific computing scenarios. Among them, the density of the matrix involved in different computing scenarios varies, and matrix multiplication is mainly divided into dense matrix multiplication and sparse matrix multiplication. Generally, dense matrix multiplication is mainly used in traditional machine learning, neural network model calculation and other scenarios, while sparse matrix multiplication is mainly used in graph computing, graph neural network and multi-grid solution and other scenarios.

[0005] Since a sparse matrix includes a large number of zero elements, a large number of zero elements will participate in the matrix multiplication operation during the sparse matrix multiplication process, which leads to low efficiency of the matrix operation. Summary of the invention

[0006] The embodiment of the present application provides a sparse matrix operation method, processor and computing device, which can improve the execution efficiency of sparse matrix multiplication. The corresponding technical solutions are as follows:

[0007] In a first aspect, a sparse matrix operation method is provided, the method being executed by a processor including a sparse matrix processing unit and a sparse vector operation unit, the method comprising:

[0008] The sparse matrix processing unit inputs the first numerical matrix and the first index matrix corresponding to the first sparse matrix obtained by the sparse matrix processing unit, and the second numerical matrix and the second index matrix corresponding to the second sparse matrix to the sparse vector operation unit, wherein each non-zero element in the first index matrix is ​​used to indicate the column number corresponding to the non-zero element at the same position in the first numerical matrix, and each non-zero element in the second index matrix is ​​used to indicate the row number corresponding to the non-zero element at the same position in the second numerical matrix. The sparse vector operation unit determines the target elements that need to be dot-producted among the non-zero elements in each row of the first numerical matrix and the non-zero elements in each column of the second numerical matrix based on the non-zero elements in each row of the first index matrix and the non-zero elements in each column of the second index matrix, and performs the dot product operation on the target elements to obtain the first result matrix of the sparse multiplication operation of the first sparse matrix and the second sparse matrix.

[0009] Among them, the first numerical matrix is ​​obtained by compressing the non-zero elements in the first sparse matrix in the row direction, and the second numerical matrix is ​​obtained by compressing the non-zero elements in the second sparse matrix in the column direction. In the scheme provided by the present application, the sparse matrix processing unit can determine the target elements in the first numerical matrix and the second data matrix that need to perform dot product operations according to the row numbers and column numbers indicated by the non-zero elements of each row of the first index matrix and each column of the second index matrix, and perform dot product operations on the target elements, thereby obtaining the first result matrix of the sparse multiplication operation performed by the first sparse matrix and the second sparse matrix. It can be seen that the scheme shown in the present application can avoid the operation of a large number of zero elements during the sparse multiplication operation, and can improve the efficiency of the processor in performing sparse multiplication operations.

[0010] In an implementable manner, the sparse vector operation unit determines the target elements that need to be subjected to the dot product operation in each row of elements in the first numerical matrix and the second numerical matrix based on each row of elements included in the first index matrix and the second index matrix, and performs the dot product operation on the target elements to obtain a first result matrix of the sparse multiplication operation performed on the first sparse matrix and the second sparse matrix, including:

[0011] The sparse vector operation unit determines the first position of the mth row and the second position of the nth column of the same non-zero elements included in the mth row of the first index matrix and the nth column of the second index matrix, respectively. A dot product operation is performed on the target element at the first position of the mth row of the first data matrix and the target element at the second position of the nth column of the second data matrix to obtain the element at the mth row and the nth column in the first result matrix.

[0012] In an implementable manner, the method further includes: the sparse matrix processing unit obtains a third numerical matrix and a third index matrix corresponding to the third sparse matrix, and a fourth numerical matrix and a fourth index matrix corresponding to the fourth sparse matrix, wherein the third numerical matrix includes a plurality of first numerical matrix blocks, the third index matrix includes a first index matrix block corresponding to each first numerical matrix block, the fourth numerical matrix includes a plurality of second numerical matrix blocks, and the fourth index matrix includes a plurality of second index matrix blocks corresponding to each second numerical matrix block. The sparse matrix processing unit determines the Cartesian product of the first numerical matrix block of the non-zero matrix block in the i-th row of the third numerical matrix and the second numerical matrix block of the non-zero matrix block in the j-th column of the fourth numerical matrix.

[0013] Before the sparse matrix processing unit inputs the first numerical matrix and the first index matrix corresponding to the first sparse matrix processed by the sparse matrix processing unit, and the second numerical matrix and the second index matrix corresponding to the second sparse matrix, the sparse matrix processing unit also includes: the sparse matrix processing unit determines that the first numerical matrix block and the second numerical matrix block included in a group of numerical matrix blocks in the Cartesian product are respectively the first numerical matrix and the second numerical matrix, determines that the first index matrix block corresponding to the first numerical matrix block is the first index matrix, and determines that the second index matrix block corresponding to the second numerical matrix block is the second index matrix.

[0014] In one implementable manner, the method further includes: a sparse matrix processing unit sums the first result matrix corresponding to each group of numerical matrix blocks included in the Cartesian product to obtain a matrix block in the i-th row and j-th column in the second result matrix where the third sparse matrix and the fourth sparse matrix perform sparse multiplication operations.

[0015] In the scheme shown in the present application, the sparse matrix processing unit compresses the third sparse matrix and the fourth sparse matrix that perform sparse multiplication operations into a third numerical matrix, a third index matrix, a fourth numerical matrix and a fourth index matrix, respectively, and divides the third numerical matrix, the third index matrix, the fourth numerical matrix and the fourth index matrix into blocks to obtain multiple first numerical matrix blocks, second numerical matrix blocks, first index matrix blocks and second index matrix blocks. In this way, the second result matrix is ​​calculated respectively by the above-mentioned numerical matrix blocks and index matrix blocks, which can avoid the zero matrix blocks from participating in the sparse multiplication operation process, and can improve the efficiency of the processor in performing sparse multiplication operations.

[0016] In addition, for each group of numerical matrix blocks included in the Cartesian product, that is, the first numerical matrix block and the second numerical matrix block for performing matrix multiplication operations, the first numerical matrix block is determined as the above-mentioned first numerical matrix, the second numerical matrix block is determined as the above-mentioned second numerical matrix, and the operations of the first numerical matrix block and the second numerical matrix block are performed according to the above-mentioned operation method for calculating the first numerical matrix and the second numerical matrix, which can further improve the efficiency of the processor in performing sparse multiplication operations.

[0017] In an implementable manner, the third numerical matrix includes L×M first numerical matrix areas, each of which includes at least one first numerical matrix block, the third index matrix includes L×M third index matrix areas, each of which includes at least one first index matrix block. The fourth numerical matrix includes M×N second numerical matrix areas, each of which includes at least one second numerical matrix block, and the fourth index matrix includes M×N second index matrix areas, each of which includes at least one second index matrix block.

[0018] In the solution shown in the present application, the third numerical matrix, the third index matrix, the fourth numerical matrix and the fourth index matrix can be partitioned, and then the second result matrix corresponding to the third sparse matrix and the fourth sparse matrix can be calculated according to the first numerical matrix area, the first index matrix area, the second numerical matrix area and the second index matrix area. The zero matrix area in the first numerical matrix area and the second numerical matrix area may not participate in the operation, thereby improving the efficiency of the processor in performing sparse multiplication operations.

[0019] In an implementable manner, the method further includes: the sparse matrix processing unit determines the number of non-zero matrix areas in the L×N matrix areas included in the second result matrix based on the first position of the zero matrix area in the third numerical matrix, the second position of the non-zero matrix area in the third numerical matrix, and the third position of the zero matrix area in the fourth numerical matrix and the fourth position of the non-zero matrix area in the fourth numerical matrix among the M×N second numerical matrix areas. Based on the number of non-zero matrix areas, storage space is applied for the second result matrix in the memory.

[0020] In the scheme shown in the present application, storage space is applied for the second result matrix in the memory according to the number of non-zero matrix areas included in the second result matrix. On the one hand, the storage space occupied by the second result matrix can be reduced. On the other hand, alignment judgment is performed according to the positions of the zero matrix areas and the non-zero matrix areas of the first numerical matrix area and the second numerical matrix area to determine the number of non-zero matrix areas included in the second result matrix, which can reduce the complexity of the alignment judgment.

[0021] In an implementable manner, the sparse matrix processing unit determines the Cartesian product of the first numerical matrix block of the non-zero matrix block in the i-th row of the third numerical matrix and the second numerical matrix block of the non-zero matrix block in the j-th column of the fourth numerical matrix, including: if the sparse matrix processing unit determines that the k-th first numerical matrix block group in the i-th row and the k-th second numerical matrix block group in the j-th column meet the operation condition, then determines the Cartesian product of the first numerical matrix block of each non-zero matrix block and the second numerical matrix block of each non-zero matrix block included in the k-th first numerical matrix block group and the k-th second numerical matrix block group. Wherein, the first numerical matrix block group includes the first numerical matrix block in the i-th row in the same first numerical matrix area, the second numerical matrix block group includes the second numerical matrix block in the j-th column in the same second numerical matrix area, and the operation condition is that both the first numerical matrix block group and the second numerical matrix block group include non-zero matrix blocks.

[0022] In the scheme shown in the present application, the sparse matrix processing unit can avoid the numerical matrix blocks that do not include non-zero numerical matrix blocks from participating in sparse multiplication operations by performing alignment judgment on the numerical matrix block groups, thereby improving the efficiency of the processor in performing sparse multiplication operations.

[0023] In a second aspect, a processor is provided, the processor comprising a sparse matrix processing unit and a sparse vector operation unit, wherein:

[0024] A sparse matrix processing unit, used for inputting into the sparse vector operation unit a first numerical matrix and a first index matrix corresponding to the first sparse matrix obtained by the sparse matrix processing unit, and a second numerical matrix and a second index matrix corresponding to the second sparse matrix, wherein each non-zero element in the first index matrix is ​​used to indicate a column number corresponding to a non-zero element at a same position in the first numerical matrix, and each non-zero element in the second index matrix is ​​used to indicate a row number corresponding to a non-zero element at a same position in the second numerical matrix;

[0025] The sparse vector operation unit is used to determine the target elements that need to be subjected to dot product operation in each row of elements in the first numerical matrix and the second numerical matrix based on each row of elements included in the first index matrix and the second index matrix, and perform dot product operation on the target elements to obtain a first result matrix of sparse multiplication operation performed on the first sparse matrix and the second sparse matrix.

[0026] In an implementable manner, the sparse vector operation unit is used to determine the first position in the mth row and the second position in the nth row of the same element included in the mth row of the first index matrix and the nth row of the second index matrix respectively;

[0027] The sparse vector operation unit is used to perform a dot product operation on the target element at the first position of the mth row of the first data matrix and the target element at the second position of the nth row of the second data matrix to obtain the element at the mth row and nth column in the first result matrix.

[0028] In an implementable manner, the sparse matrix processing unit is used to obtain a third numerical matrix and a third index matrix corresponding to the third sparse matrix, and a fourth numerical matrix and a fourth index matrix corresponding to the fourth sparse matrix, wherein the third numerical matrix includes a plurality of first numerical matrix blocks, the third index matrix includes a first index matrix block corresponding to each first numerical matrix block, the fourth numerical matrix includes a plurality of second numerical matrix blocks, and the fourth index matrix includes a plurality of second index matrix blocks corresponding to each second numerical matrix block;

[0029] The sparse matrix processing unit is used to determine the Cartesian product of the first numerical matrix block of the non-zero matrix blocks in the i-th row of the third numerical matrix and the second numerical matrix block of the non-zero matrix blocks in the j-th column of the fourth numerical matrix.

[0030] The sparse matrix processing unit is also used for the sparse matrix processing unit to determine that the first numerical matrix block and the second numerical matrix block included in a group of numerical matrix blocks in the Cartesian product are respectively the first numerical matrix and the second numerical matrix, determine that the first index matrix block corresponding to the first numerical matrix block is the first index matrix, and determine that the second index matrix block corresponding to the second numerical matrix block is the second index matrix.

[0031] The sparse matrix processing unit is also used to sum the first result matrix corresponding to each group of numerical matrix blocks included in the Cartesian product to obtain the matrix block of the i-th row and j-th column in the second result matrix of the third sparse matrix and the fourth sparse matrix performing sparse multiplication operation.

[0032] In an implementable manner, the third numerical matrix includes L×M first numerical matrix areas, each of which includes at least one first numerical matrix block, and the third index matrix includes L×M third index matrix areas, each of which includes at least one first index matrix block;

[0033] The fourth numerical matrix includes M×N second numerical matrix areas, each of which includes at least one second numerical matrix block. The fourth index matrix includes M×N second index matrix areas, each of which includes at least one second index matrix block.

[0034] In an implementable manner, the sparse matrix processing unit is used to determine the number of non-zero matrix areas in the L×N matrix areas included in the second result matrix based on the first position of the zero matrix area in the third numerical matrix, the second position of the non-zero matrix area in the third numerical matrix, and the third position of the zero matrix area in the fourth numerical matrix and the fourth position of the non-zero matrix area in the fourth numerical matrix among the M×N second numerical matrix areas;

[0035] The sparse matrix processing unit is used to apply for storage space for the second result matrix in the memory based on the number of non-zero matrix regions.

[0036] In one implementable manner, the sparse matrix processing unit is used to determine the Cartesian product of a first numerical matrix block of non-zero matrix blocks in the i-th row of the third numerical matrix and a second numerical matrix block of non-zero matrix blocks in the j-th column of the fourth numerical matrix, including:

[0037] A sparse matrix processing unit, configured to determine the Cartesian product of the first numerical matrix block of each non-zero matrix block and the second numerical matrix block of each non-zero matrix block included in the kth first numerical matrix block group and the kth second numerical matrix block group if it is determined that the kth first numerical matrix block group in the i-th row and the kth second numerical matrix block group satisfy the operation condition; wherein,

[0038] The first numerical matrix block group includes the first numerical matrix blocks in the same first numerical matrix area in the i-th row, and the second numerical matrix block group includes the second numerical matrix blocks in the same second numerical matrix area in the j-th column. The operation condition is that both the first numerical matrix block group and the second numerical matrix block group include non-zero matrix blocks.

[0039] In a third aspect, a computing device is provided, comprising a memory and a processor as described in the second aspect above, wherein the memory stores at least one instruction, and the processor executes at least one instruction to execute the method described in the first aspect above and / or any achievable method of the first aspect.

[0040] In a fourth aspect, a computer-readable storage medium is provided, wherein the computer-readable storage medium stores a computer program code. When the computer program code is executed by a computer device, the computer device executes the method described in the first aspect and / or any achievable method in the first aspect.

[0041] In a fifth aspect, a computer program product comprising instructions is provided, which, when executed on a computing device, enables the computing device to execute the method described in the first aspect and / or any achievable method of the first aspect. BRIEF DESCRIPTION OF THE DRAWINGS

[0042] Figure 1 It is a schematic diagram of performing matrix multiplication operation in the related art;

[0043] Figure 2 is a schematic diagram of the structure of a computing device provided in an embodiment of the present application;

[0044] Figure 3 is a schematic diagram of compressing a sparse matrix provided in an embodiment of the present application;

[0045] Figure 4 is a schematic diagram of compressing a sparse matrix provided in an embodiment of the present application;

[0046] Figure 5 It is a flow chart of a sparse matrix operation method provided in an embodiment of the present application;

[0047] Figure 6 is a structural diagram of a processor provided in an embodiment of the present application;

[0048] Figure 7 It is a flow chart of a sparse matrix operation method provided in an embodiment of the present application;

[0049] Figure 8 It is a schematic diagram of a sparse matrix operation method provided in an embodiment of the present application;

[0050] Fig. 9 It is a schematic diagram of a sparse matrix operation method provided in an embodiment of the present application;

[0051] Fig.10 It is a schematic diagram of a sparse matrix operation method provided in an embodiment of the present application. DETAILED DESCRIPTION

[0052] In order to make the objectives, technical solutions and advantages of the present application clearer, the implementation methods of the present application will be further described in detail below with reference to the accompanying drawings.

[0053] Matrix multiplication is widely used in various scientific computing scenarios. The density of the matrices involved in different computing scenarios varies, and matrix multiplication is mainly divided into dense matrix multiplication and sparse matrix multiplication. Generally, dense matrix multiplication is mainly used in traditional machine learning, neural network model calculation and other scenarios, while sparse matrix multiplication is mainly used in graph computing, graph neural network and multi-grid solution and other scenarios.

[0054] Dense matrix multiplication refers to the matrix used for matrix multiplication as a dense matrix, and sparse matrix multiplication refers to the matrix used for matrix multiplication as a sparse matrix. A sparse matrix refers to a matrix in which the percentage of non-zero elements in the matrix is ​​very small (e.g., less than 5%), and a dense matrix refers to a matrix in which the percentage of non-zero elements in the matrix is ​​relatively large.

[0055] Currently, the optimization method for matrix multiplication is only effective for dense matrix multiplication. For example, the matrix for matrix multiplication can be tiling (cut into blocks), and then the result matrix of the matrix multiplication operation is calculated through the tiling matrix after tiling. Figure 1 Schematic diagram of matrix multiplication in related technology. Figure 1 As shown, for matrix A and matrix B that perform matrix multiplication operations, matrix A can be divided into Tiling matrix A 0,0 , Tiling matrix A 0,1 , Tiling matrix A 1,0 , Tiling matrix A 1,1 , the matrix B can be divided into the Tiling matrix B 0,0 , Tiling matrix B 0,1 , Tiling matrix B 1,0 , Tiling matrix B 1,1 Among them, for the matrix C resulting from the matrix multiplication operation of matrix A and matrix B, the matrix C can be divided into the Tiling matrix C 0,0 , Tiling matrix C 0,1 , Tiling matrix C 1,0 , Tiling matrix C 1,1 To calculate the Tiling matrix C 0,0 For example, the Tiling matrix C 0,0 Equal to the Tiling matrix A 0,0 With the Tiling matrix B 0,0 The product of and the Tiling matrix A 0,1 With the Tiling matrix B 0,1 This can reduce the size of the matrix and thus reduce the complexity of the matrix multiplication operation, thereby improving the efficiency of the matrix multiplication operation.

[0056] However, for sparse matrices, since there are a large number of zero elements in the sparse matrix, even after Tiling, the obtained Tiling matrix still has a large number of zero elements, and there are even Tiling matrices that are zero matrices. In this way, during the process of matrix multiplication, there are always a large number of zero elements participating in the operation, which occupies a large amount of computing resources and storage resources, resulting in low execution efficiency of sparse matrix multiplication.

[0057] The embodiment of the present application provides a sparse matrix operation method, which can optimize sparse matrix multiplication by combining the characteristics of sparse matrices, and can further improve the execution efficiency of sparse matrix multiplication. Figure 2It is a computing device for executing a sparse matrix operation method provided in an embodiment of the present application. Figure 2 As shown, the computing device 200 may include: a bus 202, a processor 204, a memory 206, and the optional computing device 200 may also include a communication interface 208. The processor 204, the memory 206 and the communication interface 208 communicate through the bus 202. The computing device 200 may be a server or a terminal device. It should be understood that the present application does not limit the number of processors and memories in the computing device 200. The computing device 200 may be a device for running a model, a terminal or a server. When the computing device 200 is a terminal, the computing device 200 includes but is not limited to a desktop computer, a mobile phone, a notebook, a tablet computer, etc. When the computing device 200 is a server, the computing device 200 may be a separate server, or a server cluster composed of multiple servers, or may be a physical machine, or may be a virtual machine, a container, etc. virtualized by virtual technology.

[0058] The bus 202 may be a peripheral component interconnect (PCI) bus or an extended industry standard architecture (EISA) bus. The bus may be divided into an address bus, a value bus, a control bus, etc. For ease of representation, Figure 2 The bus 202 is represented by only one line, but it does not mean that there is only one bus or one type of bus. The bus 202 may include a path for transmitting information between various components of the computing device 200 (eg, the memory 206, the processor 204, and the communication interface 208).

[0059] The processor 204 may include any one or more of a central processing unit (CPU), a graphics processing unit (GPU), a microprocessor (MP), or a digital signal processor (DSP). The processor 204 may further include a vector operation unit and a matrix operation unit, and the vector operation unit may be a scalable vector extension (SVE), which may be used to perform vector operations involved in sparse matrix multiplication. The matrix operation unit may be a scalable matrix unit (SME), which may be used for matrix operations involved in sparse matrix multiplication.

[0060] Among them, the processor 204 includes a processor core (core) or multiple processor cores. Among them, the instructions that the processor core can process include SIMD instructions, SVE instructions and SME instructions, etc. The data types used and the calculations performed by the processor core when processing different instructions are different. For example, when the processor core processes SIMD instructions, it processes fixed-length data (such as integer data, floating-point data), and performs addition, subtraction or other calculations on the data. For another example, when the processor core processes SVE instructions, it processes variable-length data (such as integer data, floating-point data), and performs addition, subtraction or other calculations on the data. For another example, when the processor processes SME instructions, it performs matrix calculations on matrices (such as matrix inner product, matrix outer product). In an embodiment of the present application, the instructions that the processor can process may also include sparse scalable vector extension (SparseSVE, SPSVE) instructions. When the processor core processes SPSVE instructions, the sparse vector operation method provided in the embodiment of the present application can be implemented.

[0061] The memory 206 may include a volatile memory, such as a random access memory (RAM). The memory 206 may also include a non-volatile memory, such as a read-only memory (ROM), a flash memory, a hard disk drive (HDD) or a solid state drive (SSD). The memory 206 stores an executable program code, and the processor 204 executes the executable program code to implement the sparse matrix operation method provided in the embodiment of the present application.

[0062] The communication interface 208 uses a transceiver module such as, but not limited to, a network interface card or a transceiver to implement communication between the computing device 200 and other devices or a communication network.

[0063] To facilitate understanding of the sparse matrix calculation method provided in the embodiment of the present application, the sparse compressed Tile matrix used in the embodiment of the present application is first introduced below:

[0064] The sparse compressed tile matrix includes a data matrix and an index matrix. The data matrix is ​​obtained by sequentially arranging the zero elements and non-zero elements in the sparse matrix by row or column.

[0065] In one example, the non-zero elements and zero elements included in each row (column) in the sparse matrix can be rearranged continuously to obtain the numerical matrix corresponding to the sparse matrix. The index matrix and the numerical matrix have the same size, and the distribution of zero elements and non-zero elements in the index matrix is ​​consistent with the distribution of zero elements and non-zero elements in the numerical matrix. When the zero elements and non-zero elements in the sparse matrix are rearranged continuously according to the row to obtain the corresponding numerical matrix, each non-zero element in the index matrix is ​​used to indicate the column number of the non-zero elements at the same position in the data matrix in the sparse matrix. When the zero elements and non-zero elements in the sparse matrix are rearranged continuously according to the row and column to obtain the corresponding data matrix, each non-zero element in the index matrix is ​​used to indicate the row number of the non-zero elements at the same position in the data matrix in the sparse matrix. Wherein, the non-zero elements and zero elements are rearranged continuously respectively, and the non-zero elements can be arranged before the zero elements, or the non-zero elements can be arranged after the zero elements.

[0066] like Figure 3 As described, for the sparse matrix S, if the non-zero elements and zero elements are continuously rearranged by row, the corresponding data matrix A1 and the corresponding index matrix A2 can be obtained. If the non-zero elements and zero elements are continuously rearranged by column, the corresponding data matrix B1 and the corresponding index matrix B2 can be obtained. For example, the value of the 3rd row and 1st column in the index matrix A2 is used to indicate that the elements of the 3rd row and 1st column in the data matrix A1 are in the 2nd column of the sparse matrix S. For another example, the value of the 3rd row and 3rd column in the index matrix B2 is used to indicate that the elements of the 3rd row and 3rd column in the data matrix B1 are in the 4th row of the sparse matrix S.

[0067] In another example, the sparse matrix can be partitioned first, and then the non-zero elements and zero elements of each row (column) in the matrix area (block) corresponding to each partition are continuously rearranged to obtain the numerical matrix corresponding to the sparse matrix. The index matrix and the numerical matrix have the same size, and the distribution of zero elements and non-zero elements in the index matrix is ​​consistent with the distribution of zero elements and non-zero elements in the numerical matrix. When the zero elements and non-zero elements of the matrix area corresponding to each partition of the sparse matrix are continuously rearranged according to rows to obtain the corresponding data matrix, each non-zero element in the index matrix is ​​used to indicate the column number of the non-zero elements at the same position in the data matrix in the matrix area of ​​the sparse matrix. When the zero elements and non-zero elements of the matrix area corresponding to each partition of the sparse matrix are continuously rearranged according to columns to obtain the corresponding data matrix, each non-zero element in the index matrix is ​​used to indicate the row number of the non-zero elements at the same position in the data matrix in the matrix area of ​​the sparse matrix.

[0068] like Figure 4 As described above, for the sparse matrix S, the sparse matrix S can be divided into four partitions, and the matrix regions S corresponding to the four partitions are 0,0 , Matrix Area S0,1 , Matrix Area S 1,0 , Matrix Area S 1,1 If the non-zero elements and zero elements in each matrix region are continuously rearranged by row, the corresponding data matrix A3 and the corresponding index matrix A4 can be obtained. If the non-zero elements and zero elements in each matrix region are continuously rearranged by column, the corresponding data matrix B3 and the corresponding index matrix B4 can be obtained. For example, the value of the 5th row and 5th column in the index matrix A4 is used to indicate that the element of the 5th row and 5th column in the data matrix A3 is in the matrix region S. 1,1 For another example, the value of the 5th row and 6th column in the index matrix B4 is used to indicate that the element of the 5th row and 6th column in the data matrix A3 is in the matrix region S 1,1 2nd row of .

[0069] In the above two examples, before continuously rearranging the non-zero elements and zero elements by row, if there is a row in the sparse matrix that is all 0, the row of all 0 can be deleted to reduce the size of the generated data matrix and index matrix. Before continuously rearranging the non-zero elements and zero elements by column, if there is a column in the sparse matrix that is all 0, the column of all 0 can be deleted to reduce the size of the generated data matrix and index matrix.

[0070] Figure 5 is a flow chart of a sparse matrix operation method provided in an embodiment of the present application. Figure 2 The computing device 200 shown in the figure may be executed, and specifically may be executed by the processor 204. Figure 6 As shown, the processor 204 may include at least a sparse matrix processing unit and a sparse vector operation unit. The sparse matrix processing unit is a hardware part of the processor 204 for processing a sparse matrix for performing a sparse multiplication operation, such as a processor core. In addition, the sparse matrix processing unit may also refer to a software program that is run by the processor to process a sparse matrix. The sparse vector operation unit (SPSVE) is a vector operation unit in the processor 204 for performing operations on the sparse vectors in the present application. In an example, the sparse vector operation unit may be a vector operation unit improved on the basis of the vector operation unit for performing the sparse vector multiplication operation provided in the present application.

[0071] See also Figure 5 , the sparse matrix operation method provided in the embodiment of the present application includes:

[0072] Step 501: The sparse matrix processing unit inputs a first numerical matrix and a first index matrix corresponding to a first sparse matrix processed by the sparse matrix processing unit, and a second numerical matrix and a second index matrix corresponding to a second sparse matrix into a sparse vector operation unit.

[0073] In one example, an application involving sparse matrix multiplication may be run in a computing device, such as a high performance computing (HPC) application, an artificial intelligence (AI) application, a graph computing application, etc. During the running process, when the application needs to perform sparse matrix multiplication, it may send a matrix multiplication operation request to the processor. In response to the matrix multiplication operation request, the processor reads two sparse matrices to be multiplied from a memory (such as a hard disk).

[0074] The above two sparse matrices can be in formats such as CSC (Compressed Sparse Column Format), CSR (Compressed Sparse Row Format), COO (Coordinate Format), etc. Figure 3 or Figure 4 The sparse compressed Tile matrix shown in FIG. 1 can convert the two sparse matrices into the sparse compressed Tile matrix used in the embodiment of the present application. The specific conversion method can refer to the above Figure 3 or Figure 4 The content will not be introduced in detail this time.

[0075] Among them, each row element in the first numerical matrix corresponding to the first sparse matrix is ​​obtained by continuously arranging the zero elements and non-zero elements in each row element of the first sparse matrix, and the non-zero elements in the first index matrix are the column numbers of the non-zero elements with the same position in the first numerical matrix in the first sparse matrix. Each column element in the second numerical matrix corresponding to the second sparse matrix is ​​obtained by continuously arranging the zero elements and non-zero elements in each column element of the second sparse matrix, and the non-zero elements in the second index matrix are the row numbers of the non-zero elements with the same position in the second numerical matrix in the second sparse matrix.

[0076] After obtaining the first numerical matrix, the first index matrix, the second numerical matrix, and the second index matrix, the sparse matrix processing unit can sequentially input the first numerical matrix, the first index matrix including each row element, and the second numerical matrix and the second index matrix including each column element into the sparse vector operation unit to complete the sparse multiplication operation of the first sparse matrix and the second sparse matrix. In one example, the first numerical matrix, the elements of the mth row of the first index matrix, and the elements of the nth column of the second numerical matrix and the second index matrix can be input into the sparse vector operation unit, and the sparse vector operation unit inputs the elements of the mth row and the nth column in the first result matrix corresponding to the first sparse matrix and the second sparse matrix.

[0077] The operation method of the sparse matrix provided in the present application, the technician can write the corresponding processing program as a processing function of sparse matrix multiplication, and then add it to the mathematical library. The mathematical library can be stored in the computing device that executes the application, including a large number of processing functions, which can be used to implement various mathematical calculations involved in the application. When sparse matrix multiplication needs to be performed in the application, an execution request of sparse matrix multiplication can be sent to the processor, and then the processor can call the processing function of sparse matrix multiplication to implement the processing included and implicitly included in step 501 to step 502.

[0078] Step 502: The sparse vector operation unit determines the target elements that need to be dot-producted among the non-zero elements in each row of the first numerical matrix and the non-zero elements in each column of the second numerical matrix based on the non-zero elements in each row of the first index matrix and the non-zero elements in each column of the second index matrix, performs the dot-product operation on the target elements, and obtains a first result matrix of the sparse multiplication operation of the first sparse matrix and the second sparse matrix.

[0079] For the multiplication operation of any two matrices, the vector dot product operation can be performed by expressing the elements of the mth row of the first matrix and the elements of the nth column of the second matrix, and the elements of the mth row and nth column in the result matrix corresponding to the multiplication operation of the two matrices are obtained. In an embodiment of the present application, the non-zero elements in the first index matrix are the column numbers of the non-zero elements at the same position in the first data matrix in the first sparse matrix, and the non-zero elements in the second index matrix are the row numbers of the non-zero elements at the same position in the second data matrix in the second sparse matrix. If there are non-zero elements of the same value in one row of the first index matrix and one column of the second index matrix, it means that when the vector dot product operation is performed on the row elements of the corresponding first sparse matrix and the column elements of the second sparse matrix, there is a dot product operation of the non-zero elements in the corresponding position. The position of the non-zero elements in the first numerical matrix in the row is the same as the position of the non-zero elements of the same value in the first index matrix in the row, and the position of the non-zero elements in the second numerical matrix in the row is the same as the position of the non-zero elements of the same value in the second index matrix in the row.

[0080] like Figure 3 As shown, if the two first sparse matrices and the second sparse matrix for sparse multiplication operation are both sparse matrices S, then the numerical matrix A1 is the first numerical matrix, the index matrix A2 is the first index matrix, the numerical matrix B1 is the second numerical matrix, and the index matrix B2 is the second index matrix. Take the vector dot product operation of the first row element "11100000" of the first sparse matrix and the second column element "10010000" of the second sparse matrix as an example, where the first row element of the first index matrix is ​​"12300000" and the first column element of the second index matrix is ​​"13000000", it can be seen that the first non-zero element in the first row element of the first index matrix is ​​the same as the first non-zero element in the second column element of the second index matrix, and the third non-zero element in the first row element of the first index matrix is ​​the same as the second non-zero element in the second column element of the second index matrix. Therefore, the dot product operation can be performed on the first element and the third element in the first row element "11100000" of the first data matrix and the first element and the second element in the second column element "11000000" of the second data matrix, and the dot product operation result is "2", that is, the vector dot product operation result of the first row element of the first sparse matrix and the second column element of the second sparse matrix is ​​obtained.

[0081] In one example, the processing performed by the sparse vector operation unit in step 502 can be called a sparse vector multiplication operation, and the processor can execute an SPSVE instruction to instruct the sparse vector operation unit to implement the processing of step 502. Therefore, for the operation of the mth row of the first sparse matrix and the nth column of the second sparse matrix, the sparse vector operation unit is converted into: the sparse vector operation unit determines that the same non-zero elements included in the mth row of the first index matrix and the nth column of the second index matrix are respectively at the first position in the mth row and the second position in the nth column. The sparse vector operation unit performs a dot product operation on the target element at the first position of the mth row of the first data matrix and the target element at the second position of the nth column of the second data matrix to obtain the element of the mth row and the nth column in the first result matrix. After the processor obtains the elements corresponding to each row or column of the first result matrix, the obtained first result matrix can be returned to the corresponding application.

[0082] It can be seen that in the embodiment of the present application, the sparse vector operation unit can determine the non-zero elements in the first numerical matrix and the second numerical matrix that need to be subjected to the dot product operation through the first index matrix and the second index matrix, and perform the dot product operation on the corresponding non-zero elements, thereby obtaining the first result matrix of the sparse multiplication operation performed by the first sparse matrix and the second sparse matrix. Since the first sparse matrix and the second sparse matrix only include a small number of non-zero elements, the operation of a large number of zero elements can be avoided, thereby improving the efficiency of the processor in performing the sparse multiplication operation.

[0083] Figure 7 is a flow chart of another sparse matrix operation method provided in an embodiment of the present application. Figure 2 The computing device 200 shown in the figure may be executed by Figure 6 The processor 204 shown executes. Figure 7 Another sparse matrix operation method provided in an embodiment of the present application includes:

[0084] Step 701: The sparse matrix processing unit obtains a third numerical matrix and a third index matrix corresponding to the third sparse matrix, and a fourth numerical matrix and a fourth index matrix corresponding to the fourth sparse matrix.

[0085] The process of obtaining the third sparse matrix and the fourth sparse matrix in step 701 is similar to the process of obtaining the first sparse matrix and the second sparse matrix in step 701 above, and will not be repeated here. Figure 7 In the corresponding embodiment, the first sparse matrix may be a matrix block in the third sparse matrix, and the second sparse matrix may be a matrix block in the fourth sparse matrix.

[0086] Among them, each row element in the third numerical matrix corresponding to the third sparse matrix is ​​obtained by continuously arranging the zero elements and non-zero elements in each row element of the third sparse matrix, and the non-zero elements in the third index matrix are the column numbers of the non-zero elements with the same position in the third numerical matrix in the third sparse matrix. Each column element in the fourth numerical matrix corresponding to the fourth sparse matrix is ​​obtained by continuously arranging the zero elements and non-zero elements in each column element of the fourth sparse matrix, and the non-zero elements in the fourth index matrix are the row numbers of the non-zero elements with the same position in the fourth numerical matrix in the fourth sparse matrix.

[0087] After obtaining the third sparse matrix and the fourth sparse matrix, the third numerical matrix, the third index matrix, the fourth numerical matrix and the fourth index matrix can be Tiled according to the same size to obtain a plurality of first data matrix blocks corresponding to the third data matrix, a plurality of first index matrix blocks corresponding to the third index matrix, a plurality of second data matrix blocks corresponding to the fourth data matrix and a plurality of second index matrix blocks corresponding to the fourth index matrix. The first data matrix blocks, the first index matrix blocks, the second data matrix blocks and the second index matrix blocks are Tiling matrices.

[0088] For example, Figure 3 The numerical matrix A1 shown may be the third numerical matrix, the index matrix A2 may be the third index matrix, the numerical matrix B1 may be the fourth numerical matrix, and the index matrix B2 may be the fourth index matrix. Correspondingly, Figure 8The numerical matrix A1, index matrix A2, numerical matrix B1 and index matrix B2 shown in the figure can be arranged in a 2×2 size. Figure 3 The diagram shows the numerical matrix A1, index matrix A2, numerical matrix B1 and index matrix B2 after tiling. Figure 8 The second numerical matrix C shown refers to a second result matrix corresponding to the sparse multiplication operation performed on the third sparse matrix and the fourth sparse matrix.

[0089] In one example, there are a large number of zero matrix blocks in the first data matrix block, the first index matrix block, the second data matrix block and the second index matrix block. Therefore, when storing the first data matrix block, the first index matrix block, the second data matrix block and the second index matrix block corresponding to the third sparse matrix and the fourth sparse matrix, only the non-zero matrix blocks in the first data matrix block, the first index matrix block, the second data matrix block and the second index matrix block may be stored, thereby reducing the storage space occupied by storing the third sparse matrix and the fourth sparse matrix.

[0090] Step 702: The sparse matrix processing unit determines the Cartesian product of a first numerical matrix block of non-zero matrix blocks in the i-th row of the third numerical matrix and a second numerical matrix block of non-zero matrix blocks in the j-th column of the fourth numerical matrix.

[0091] Among them, the Cartesian product of the first numerical matrix block of the non-zero matrix block and the second numerical matrix block of the non-zero matrix block means that the first numerical matrix block of each non-zero matrix block is paired with the second numerical matrix block of each non-zero matrix block respectively to obtain multiple groups of numerical matrix blocks, each group of numerical matrix blocks includes a first numerical matrix block and a second numerical matrix block.

[0092] like Figure 8 As shown, the first numerical matrix block of the non-zero matrix blocks in the first row of the numerical matrix A1 includes A00_data: A01_data: The second numerical matrix block of non-zero matrix blocks in the first column of the numerical matrix B1 includes B01_data: Correspondingly, the Cartesian product of the first numerical matrix block of the non-zero matrix block in the first row of the numerical matrix A1 and the second numerical matrix block of the non-zero matrix block in the first column of the numerical matrix B1 includes: "A00_data, B01_data", "A01_data, B01_data".

[0093] The matrix obtained by performing the sparse multiplication operation on the third sparse matrix and the fourth sparse matrix can be referred to as the second result matrix. The Cartesian product of the first numerical matrix block of the non-zero matrix block in the i-th row of the third numerical matrix and the second numerical matrix block of the non-zero matrix block in the j-th column of the fourth numerical matrix is ​​determined. The matrix block in the i-th row and j-th column included in the second result matrix is ​​equal to the matrix block obtained by summing the result matrices obtained by performing matrix multiplication on each pair of numerical matrix blocks included in the determined Cartesian product and performing matrix multiplication on each pair of numerical matrix blocks.

[0094] Step 703: The sparse matrix processing unit determines that a first numerical matrix block and a second numerical matrix block included in a group of numerical matrix blocks in the Cartesian product are respectively the first numerical matrix and the second numerical matrix, determines that a first index matrix block corresponding to the first numerical matrix block is the first index matrix, and determines that a second index matrix block corresponding to the second numerical matrix block is the second index matrix.

[0095] In one example, the sparse matrix processing unit obtained in step 501 obtains the first numerical matrix and the first index matrix corresponding to the first sparse matrix, the second numerical matrix and the second index matrix corresponding to the second sparse matrix, which may be one of the numerical matrix blocks in the Cartesian product in step 703. That is, the first numerical matrix block included in a group of numerical matrix blocks in the Cartesian product may be used as the first numerical matrix in step 501, the second numerical matrix block included may be used as the second numerical matrix in step 501, the first index matrix block corresponding to the first numerical matrix block may be used as the first index matrix in step 501, and the second index matrix block corresponding to the second numerical matrix block may be obtained as the second index matrix in step 501.

[0096] The matrix multiplication operation corresponding to each group of numerical matrix blocks in the Cartesian product may adopt the sparse matrix operation method shown in the above steps 501 to 502, thereby obtaining a first result matrix corresponding to each group of numerical matrix blocks.

[0097] For example, for Figure 8 The first numerical matrix block A00_index corresponding to A00_data in: The second numerical matrix block B01_index corresponding to B01_data: Then the corresponding matrix multiplication operation of A00_data and B01_data includes: inputting the first row element [1, 2] corresponding to A00_index, the first column element [1, 4] corresponding to B01_index, the first row element [1, 1] corresponding to A00_data, and the first column element [1, 1] corresponding to B01_data into the sparse vector operation unit respectively, the sparse vector operation unit determines that the first row element of A00_index and the first column element of B01_index are both "1", and the sparse vector operation unit can multiply the first elements corresponding to the first row element of A00_data and the first column element of B01_data respectively, and then obtain the elements of the first row and the first column in the result matrix of the matrix multiplication operation of A00_data and B01_data. Referring to the above example, the elements of the first row and the second column, the second row and the first column, and the second row and the second column in the result matrix of the matrix multiplication operation of A00_data and B01_data can be calculated in sequence.

[0098] Step 704: The sparse matrix processing unit sums the first result matrix corresponding to each group of numerical matrix blocks included in the Cartesian product to obtain the matrix block of the i-th row and j-th column in the second result matrix of the sparse multiplication operation performed by the third sparse matrix and the fourth sparse matrix.

[0099] After obtaining the first result matrix corresponding to each group of numerical matrix blocks in the Cartesian product of the first numerical matrix block of the non-zero matrix block in the i-th row of the third numerical matrix and the second numerical matrix block of the non-zero matrix block in the j-th column of the fourth numerical matrix, the sparse matrix processing unit can sum the first result matrix corresponding to each group of numerical matrix blocks to obtain the matrix block in the i-th row and j-th column of the second result matrix of the sparse multiplication operation performed by the third sparse matrix and the fourth sparse matrix.

[0100] In this way, in the process of executing the sparse multiplication operation corresponding to the third sparse matrix and the fourth sparse matrix, on the one hand, the zero matrix blocks included in the first numerical matrix block and the second numerical matrix block can be screened out through the Cartesian product to avoid the zero matrix blocks from participating in the operation process. On the other hand, the sparse vector multiplication operation provided by the present application can be used to operate on each group of numerical matrix blocks in the Cartesian product, which can avoid the operation of a large number of zero elements and can further improve the efficiency of the processor in performing sparse multiplication operations.

[0101] In the embodiment of the present application, the third sparse matrix and the fourth sparse matrix obtained in step 701 are obtained according to Figure 4In the case of generating a third numerical matrix, a third index matrix, a fourth numerical matrix and a fourth index matrix by the conversion method shown, the third numerical matrix includes L×M first numerical matrix areas, each of which includes at least one first numerical matrix block, and the third index matrix includes L×M third index matrix areas, each of which includes at least one first index matrix block. The fourth numerical matrix includes M×N second numerical matrix areas, each of which includes at least one second numerical matrix block, and the fourth index matrix includes M×N second index matrix areas, each of which includes at least one second index matrix block. Wherein, the values ​​of L, M, and N may be equal or unequal.

[0102] In a possible implementation, the sparse matrix processing unit can record the first position of the zero matrix area in the third numerical matrix, the second position of the non-zero matrix area in the third numerical matrix, and the third position of the zero matrix area in the fourth numerical matrix and the fourth position of the non-zero matrix area in the fourth numerical matrix in the M×N second numerical matrix areas. Before executing step 701, the first position and the third position corresponding to the zero matrix area and the second position and the fourth position corresponding to the non-zero matrix area can be judged according to the alignment, and then the number of non-zero matrix areas in the L×N matrix areas included in the second result matrix can be determined, and then storage space is applied for the second result matrix according to the number.

[0103] like Fig. 9 As shown, the first numerical matrix can be a numerical matrix A3, and the second numerical matrix can be a numerical matrix B4. The non-zero matrix area corresponding to the numerical matrix A3 is in the 1st row and 1st column, and the 2nd row and 1st column of the numerical matrix A3, and the corresponding zero matrix area is in the 1st row and 2nd column, and the 2nd row and 1st column of the numerical matrix A3. The non-zero matrix area corresponding to the numerical matrix B3 is in the 1st row and 1st column, and the 2nd row and 1st column of the numerical matrix B3, and the corresponding zero matrix area is in the 1st row and 2nd column, and the 2nd row and 1st column of the numerical matrix B3. In one example, the first position, second position, third position, and fourth position corresponding to the corresponding first numerical matrix and the second numerical matrix can be recorded by a matrix. That is, the first position, second position, third position, and fourth position corresponding to the numerical matrix A3 and the numerical matrix B3 can be recorded as For example, if the first row and the first column of the first numerical matrix and the second numerical matrix are both non-zero matrix areas, then the matrix area of ​​the first row and the first column in the second result matrix is ​​a non-zero matrix area, and if the second row and the second column of the first numerical matrix and the second numerical matrix are both non-zero matrix areas, then the matrix area of ​​the second row and the second column in the second result matrix is ​​a non-zero matrix area. After the alignment judgment, it can be determined that the second result matrix includes two non-zero matrix areas, and then only the storage space corresponding to the two non-zero matrix areas can be applied in the memory.

[0104] It can be seen that in the embodiment of the present application, by applying for storage space for the result matrix in the memory by aligning the judgment results of the matrix blocks included in the stored numerical matrix, on the one hand, the storage space of the result matrix in the memory can be reduced, and on the other hand, compared with the traditional technology, the efficiency of the alignment judgment can also be improved.

[0105] In the embodiment of the present application, the third sparse matrix and the fourth sparse matrix obtained in step 701 are obtained according to Figure 4 In the case where the conversion method shown in the figure generates a third numerical matrix, a third index matrix, a fourth numerical matrix and a fourth index matrix, the processing of the above step 702 may include:

[0106] If the sparse matrix processing unit determines that the nth first numerical matrix block group in the ith row and the nth second numerical matrix block group in the jth column meet the operation condition, the sparse matrix processing unit determines the Cartesian product of the first numerical matrix block of each non-zero matrix block and the second numerical matrix block of each non-zero matrix block included in the nth first numerical matrix block group and the nth second numerical matrix block group. The first numerical matrix block group includes the first numerical matrix blocks in the same first numerical matrix region in the ith row, the second numerical matrix block group includes the second numerical matrix blocks in the same second numerical matrix region in the jth column, and the operation condition is that both the first numerical matrix block group and the second numerical matrix block group include non-zero matrix blocks.

[0107] After partitioning the third sparse matrix and the fourth sparse matrix, the sparse matrix processing unit can determine the Cartesian product of the non-zero matrix blocks in the i-th row of the third numerical matrix and the second numerical matrix blocks in the j-th column of the fourth numerical matrix, respectively, in units of numerical matrix areas, of the non-zero matrix blocks in the i-th row of the third numerical matrix located in each first data matrix area and the non-zero matrix blocks in the j-th column of the fourth numerical matrix located in the corresponding position.

[0108] For example, determine the Cartesian product corresponding to the non-zero matrix block located in the first first data matrix area in the i-th row of the third numerical matrix and the non-zero matrix block located in the first second data matrix area in the j-th row of the fourth numerical matrix. Determine the Cartesian product corresponding to the non-zero matrix block located in the second second data matrix area in the i-th row of the third numerical matrix and the non-zero matrix block located in the second second data matrix area in the j-th row of the fourth numerical matrix. Determine the Cartesian product corresponding to the non-zero matrix block located in the k-th first data matrix area in the i-th row of the third numerical matrix and the non-zero matrix block located in the k-th second data matrix area in the j-th row of the fourth numerical matrix. Then, add the first result matrix corresponding to each group of numerical matrix blocks included in the k Cartesian products to obtain the matrix block of the i-th row and the j-th column in the second result matrix of the sparse multiplication operation performed by the third sparse matrix and the fourth sparse matrix. Wherein, k is the number of data matrix areas corresponding to each row of the third numerical matrix or each column of the fourth numerical matrix.

[0109] Since the data matrix blocks located in the data matrix area may be zero matrix blocks, before determining the Cartesian product, the numerical matrix block groups included in each data matrix area can be judged in alignment, wherein the numerical matrix block group refers to the data matrix blocks located in the same numerical matrix area in a row or a column in the data matrix. If there is a numerical matrix block group in the first numerical matrix of the aligned position and the second numerical matrix block group in the second numerical matrix, both of which are zero matrix blocks, the Cartesian product of the first numerical matrix block group and the second numerical matrix block group can be determined. If there are non-zero matrix blocks in the first numerical matrix of the aligned position and the second numerical matrix block group in the second numerical matrix, the Cartesian product of the first numerical matrix block group and the second numerical matrix block group can be determined.

[0110] like Fig. 9 As shown, the first first data matrix block group in the first row of the numerical matrix A3 and the first second data matrix block group in the first column of the numerical matrix A4 both include non-zero matrix blocks, and the second first data matrix block group in the first row of the numerical matrix A3 and the second second data matrix block group in the first column of the numerical matrix A4 both include zero matrix blocks. Then, the Cartesian product corresponding to the first data matrix block in the first row of the numerical matrix A3 and the second data matrix block in the second row of the numerical matrix A4 can be determined only by the non-zero matrix blocks included in the first first data matrix block group in the first row of the numerical matrix A3 and the first second data matrix block group in the first column of the numerical matrix A4. In this way, by performing alignment judgment on the data matrix block groups, the process of zero matrix blocks participating in sparse multiplication operations can be reduced, thereby improving the execution efficiency of sparse multiplication operations.

[0111] In an example, the above result matrix (the first result matrix or the second result matrix) may also correspond to a result index matrix, wherein each non-zero element in the result index matrix is ​​used to indicate the column where each non-zero element in the result matrix is ​​located.

[0112] For the result index matrix, the value of each column corresponding to the element is the column number corresponding to each column of the index matrix (the second index matrix or the fourth index matrix mentioned above) corresponding to the data matrix in which the non-zero elements are compressed in the column direction. Fig.10 As shown, the fourth index matrix is ​​index matrix B4, and the result index matrix is ​​result index matrix C4. Fig.10 It can be seen that the values ​​corresponding to the elements in the first 4 columns of the result index matrix C4 are all the column numbers corresponding to the elements in the first 4 columns of the index matrix B4 in the corresponding second index matrix block, and the values ​​corresponding to the elements in the last 4 columns of the index matrix C4 are all the column numbers corresponding to the elements in the last 4 columns of the index matrix B4 in the corresponding second index matrix block. Fig.10 The column numbers in are arranged starting from "1", that is, the elements in the first column correspond to the column number "1". Optionally, the column numbers can also be arranged starting from other values, such as "0".

[0113] In one example, by Figure 3 and Figure 4 It can be seen from the corresponding embodiment that when converting a sparse matrix into a numerical matrix, if there is a column in the sparse matrix that is all zero before rearranging the non-zero elements and zero elements by column, the column that is all zero can be deleted. In this case, when setting the column number for each column of the numerical matrix block and the index matrix block, the column that is all zero can be skipped. For example, the sparse matrix corresponding to the index matrix B4 has the second column deleted and is all zero, then Fig.10 The column numbers corresponding to the first four columns of the index matrix B4 are 1, 3, 4, and 5 respectively.

[0114] All the above optional technical solutions can be combined in any way to form optional embodiments of the present application, and the embodiments of the present application will not be described in detail one by one.

[0115] The embodiment of the present application also provides a processor, which includes a sparse matrix processing unit and a sparse vector operation unit, such as Figure 6 As shown, the processor provided in the embodiment of the present application executes the sparse matrix operation method provided in the present application, including:

[0116] A sparse matrix processing unit, used for inputting into the sparse vector operation unit a first numerical matrix and a first index matrix corresponding to the first sparse matrix obtained by the sparse matrix processing unit, and a second numerical matrix and a second index matrix corresponding to the second sparse matrix, wherein each non-zero element in the first index matrix is ​​used to indicate a column number corresponding to a non-zero element at a same position in the first numerical matrix, and each non-zero element in the second index matrix is ​​used to indicate a row number corresponding to a non-zero element at a same position in the second numerical matrix;

[0117] The sparse vector operation unit is used to determine the target elements that need to be subjected to dot product operation in each row of elements in the first numerical matrix and the second numerical matrix based on each row of elements included in the first index matrix and the second index matrix, and perform dot product operation on the target elements to obtain a first result matrix of sparse multiplication operation performed on the first sparse matrix and the second sparse matrix.

[0118] In an implementable manner, the sparse vector operation unit is used to determine the first position in the mth row and the second position in the nth row of the same element included in the mth row of the first index matrix and the nth row of the second index matrix respectively;

[0119] The sparse vector operation unit is used to perform a dot product operation on the target element at the first position of the mth row of the first data matrix and the target element at the second position of the nth row of the second data matrix to obtain the element at the mth row and nth column in the first result matrix.

[0120] In an implementable manner, the sparse matrix processing unit is used to obtain a third numerical matrix and a third index matrix corresponding to the third sparse matrix, and a fourth numerical matrix and a fourth index matrix corresponding to the fourth sparse matrix, wherein the third numerical matrix includes a plurality of first numerical matrix blocks, the third index matrix includes a first index matrix block corresponding to each first numerical matrix block, the fourth numerical matrix includes a plurality of second numerical matrix blocks, and the fourth index matrix includes a plurality of second index matrix blocks corresponding to each second numerical matrix block;

[0121] The sparse matrix processing unit is used to determine the Cartesian product of the first numerical matrix block of the non-zero matrix blocks in the i-th row of the third numerical matrix and the second numerical matrix block of the non-zero matrix blocks in the j-th column of the fourth numerical matrix.

[0122] The sparse matrix processing unit is also used for the sparse matrix processing unit to determine that the first numerical matrix block and the second numerical matrix block included in a group of numerical matrix blocks in the Cartesian product are respectively the first numerical matrix and the second numerical matrix, determine that the first index matrix block corresponding to the first numerical matrix block is the first index matrix, and determine that the second index matrix block corresponding to the second numerical matrix block is the second index matrix.

[0123] The sparse matrix processing unit is also used to sum the first result matrix corresponding to each group of numerical matrix blocks included in the Cartesian product to obtain the matrix block of the i-th row and j-th column in the second result matrix of the third sparse matrix and the fourth sparse matrix performing sparse multiplication operation.

[0124] In an implementable manner, the third numerical matrix includes L×M first numerical matrix areas, each of which includes at least one first numerical matrix block, and the third index matrix includes L×M third index matrix areas, each of which includes at least one first index matrix block;

[0125] The fourth numerical matrix includes M×N second numerical matrix areas, each of which includes at least one second numerical matrix block. The fourth index matrix includes M×N second index matrix areas, each of which includes at least one second index matrix block.

[0126] In an implementable manner, the sparse matrix processing unit is used to determine the number of non-zero matrix areas in the L×N matrix areas included in the second result matrix based on the first position of the zero matrix area in the third numerical matrix, the second position of the non-zero matrix area in the third numerical matrix, and the third position of the zero matrix area in the fourth numerical matrix and the fourth position of the non-zero matrix area in the fourth numerical matrix among the M×N second numerical matrix areas;

[0127] The sparse matrix processing unit is used to apply for storage space for the second result matrix in the memory based on the number of non-zero matrix regions.

[0128] In one implementable manner, the sparse matrix processing unit is used to determine the Cartesian product of a first numerical matrix block of non-zero matrix blocks in the i-th row of the third numerical matrix and a second numerical matrix block of non-zero matrix blocks in the j-th column of the fourth numerical matrix, including:

[0129] A sparse matrix processing unit, configured to determine the Cartesian product of the first numerical matrix block of each non-zero matrix block and the second numerical matrix block of each non-zero matrix block included in the kth first numerical matrix block group and the kth second numerical matrix block group if it is determined that the kth first numerical matrix block group in the i-th row and the kth second numerical matrix block group satisfy the operation condition; wherein,

[0130] The first numerical matrix block group includes the first numerical matrix blocks in the same first numerical matrix area in the i-th row, and the second numerical matrix block group includes the second numerical matrix blocks in the same second numerical matrix area in the j-th column. The operation condition is that both the first numerical matrix block group and the second numerical matrix block group include non-zero matrix blocks.

[0131] The processor provided in the embodiment of the present application can be used to perform the operation method of the sparse matrix provided in the embodiment of the present application. For the specific execution process, the introduction content of the operation method of the sparse matrix in the above embodiment can be seen, and it will not be repeated here. The processor provided in the embodiment of the present application is used to perform sparse multiplication operations. The processor can determine the target elements that need to perform dot product operations in the first numerical matrix and the second data matrix according to the row number and column number indicated by the non-zero elements of each row of the first index matrix and each column of the second index matrix, and perform dot product operations on the target elements, thereby obtaining the first result matrix of the first sparse matrix and the second sparse matrix performing sparse multiplication operations. In this way, the operation of a large number of zero elements in the sparse multiplication process can be avoided, and the efficiency of the processor in performing sparse multiplication operations can be improved.

[0132] The present application embodiment also provides a computer program product comprising instructions. The computer program product may be a software or program product comprising instructions that can be run on a computing device or stored in any available medium. When the computer program product is run on at least one computing device, the at least one computing device executes the operation method for executing a sparse matrix provided in the present application embodiment.

[0133] The embodiment of the present application also provides a computer-readable storage medium. The computer-readable storage medium can be any available medium that can be stored by the computing device or a data storage device such as a data center containing one or more available media. The available medium can be a magnetic medium (e.g., a floppy disk, a hard disk, a tape), an optical medium (e.g., a DVD), or a semiconductor medium (e.g., a solid-state hard disk). The computer-readable storage medium includes instructions that instruct the computing device to execute the sparse matrix operation method of the embodiment of the present application.

[0134] In the present application, the words such as "first", "second", etc. are used to distinguish the same or similar items with basically the same effects and functions. It should be understood that there is no logical or temporal dependency between "first" and "second", nor is the quantity and execution order limited. It should also be understood that although the following description uses the terms first, second, etc. to describe various elements, these elements should not be limited by the terms. These terms are only used to distinguish one element from another. For example, without departing from the scope of various examples, the first data matrix can be referred to as the second data matrix, and similarly, the second data matrix can be referred to as the first data matrix. The first data matrix and the second data matrix can both be collectively referred to as data matrices, and in some cases, can be separate and different data matrices.

[0135] The term "at least one" in this application means one or more, and the term "plurality" in this application means two or more.

[0136] The above description is only a specific implementation of the present application, but the protection scope of the present application is not limited thereto. Any technician familiar with the technical field can easily think of various equivalent modifications or replacements within the technical scope disclosed in the present application, and these modifications or replacements should be included in the protection scope of the present application. Therefore, the protection scope of the present application should be based on the protection scope of the claims.

Claims

1. A sparse matrix operation method, characterized in that: The method is executed by a processor, the processor includes a sparse matrix processing unit and a sparse vector operation unit, and the method includes: The sparse vector operation unit obtains a first numerical matrix and a first index matrix, a second numerical matrix and a second index matrix, wherein the first numerical matrix and the first index matrix are obtained by the sparse matrix processing unit processing the first sparse matrix, and the second numerical matrix and the second index matrix are obtained by the sparse matrix processing unit processing the second sparse matrix; each non-zero element in the first index matrix is ​​used to indicate the column number of the column where the non-zero elements at the same position in the first numerical matrix are located, and each non-zero element in the second index matrix is ​​used to indicate the row number of the row where the non-zero elements at the same position in the second numerical matrix are located; The sparse vector operation unit determines the target elements that need to be subjected to dot product operation in each row of the first numerical matrix and in each column of the second numerical matrix based on the non-zero elements in each row of the first index matrix and the non-zero elements in each column of the second index matrix, wherein the target elements are all non-zero elements, performs dot product operation on the target elements, and obtains a first result matrix of sparse multiplication operation performed on the first sparse matrix and the second sparse matrix.

2. The method according to claim 1, characterized in that The sparse vector operation unit determines, based on the non-zero elements in each row of the first index matrix and the non-zero elements in each column of the second index matrix, target elements in each row of the first numerical matrix and in each column of the second numerical matrix that need to be subjected to dot product operation, wherein the target elements are all non-zero elements, performs dot product operation on the target elements, and obtains a first result matrix of sparse multiplication operation performed on the first sparse matrix and the second sparse matrix, including: The sparse vector operation unit determines that the same non-zero elements included in the mth row of the first index matrix and the nth column of the second index matrix are respectively located at a first position in the mth row and a second position in the nth column; The sparse vector operation unit performs a dot product operation on the target element at the first position in the mth row of the first data matrix and the target element at the second position in the nth column of the second data matrix to obtain the element at the mth row and nth column in the first result matrix.

3. The method according to claim 1 or 2, characterized in that: The method further includes: the sparse matrix processing unit obtains a third numerical matrix and a third index matrix corresponding to the third sparse matrix, and a fourth numerical matrix and a fourth index matrix corresponding to the fourth sparse matrix, wherein the third numerical matrix includes a plurality of first numerical matrix blocks, the third index matrix includes a first index matrix block corresponding to each first numerical matrix block, the fourth numerical matrix includes a plurality of second numerical matrix blocks, and the fourth index matrix includes a plurality of second index matrix blocks corresponding to each second numerical matrix block; The sparse matrix processing unit determines the Cartesian product of a first numerical matrix block of non-zero matrix blocks in the i-th row of the third numerical matrix and a second numerical matrix block of non-zero matrix blocks in the j-th column of the fourth numerical matrix; Before the sparse matrix processing unit inputs the first numerical matrix and the first index matrix corresponding to the first sparse matrix processed by the sparse matrix processing unit, and the second numerical matrix and the second index matrix corresponding to the second sparse matrix, the sparse matrix processing unit also includes: the sparse matrix processing unit determines that the first numerical matrix block and the second numerical matrix block included in a group of numerical matrix blocks in the Cartesian product are respectively the first numerical matrix and the second numerical matrix, determines that the first index matrix block corresponding to the first numerical matrix block is the first index matrix, and determines that the second index matrix block corresponding to the second numerical matrix block is the second index matrix.

4. The method according to claim 3, characterized in that The third numerical matrix includes L×M first numerical matrix areas, each of which includes at least one first numerical matrix block; the third index matrix includes L×M third index matrix areas, each of which includes at least one first index matrix block; The fourth numerical matrix includes M×N second numerical matrix areas, each of which includes at least one second numerical matrix block, and the fourth index matrix includes M×N second index matrix areas, each of which includes at least one second index matrix block.

5. The method according to claim 4, characterized in that The method further comprises: The sparse matrix processing unit determines the number of non-zero matrix areas in the L×N matrix areas included in the second result matrix based on the first position of the zero matrix area in the third numerical matrix, the second position of the non-zero matrix area in the third numerical matrix, and the third position of the zero matrix area in the fourth numerical matrix and the fourth position of the non-zero matrix area in the fourth numerical matrix among the M×N second numerical matrix areas; The sparse matrix processing unit applies for storage space for the second result matrix in a memory based on the number of the non-zero matrix regions.

6. The method according to any one of claims 3 to 5, characterized in that: The sparse matrix processing unit determines the Cartesian product of the first numerical matrix block of the non-zero matrix blocks in the i-th row of the third numerical matrix and the second numerical matrix block of the non-zero matrix blocks in the j-th column of the fourth numerical matrix, including: If the sparse matrix processing unit determines that the nth first numerical matrix block group in the i-th row and the nth second numerical matrix block group in the j-th column meet the operation condition, then determine the Cartesian product of the first numerical matrix block of each non-zero matrix block and the second numerical matrix block of each non-zero matrix block included in the k-th first numerical matrix block group and the k-th second numerical matrix block group; wherein, The first numerical matrix block group includes the first numerical matrix blocks in the same first numerical matrix area in the i-th row, and the second numerical matrix block group includes the second numerical matrix blocks in the same second numerical matrix area in the j-th column. The operation condition is that both the first numerical matrix block group and the second numerical matrix block group include non-zero matrix blocks.

7. A processor, characterized in that: The processor includes a sparse matrix processing unit and a sparse vector operation unit, wherein: The sparse vector operation unit obtains a first numerical matrix and a first index matrix, a second numerical matrix and a second index matrix, wherein the first numerical matrix and the first index matrix are obtained by the sparse matrix processing unit processing the first sparse matrix, and the second numerical matrix and the second index matrix are obtained by the sparse matrix processing unit processing the second sparse matrix; each non-zero element in the first index matrix is ​​used to indicate the column number of the column where the non-zero elements at the same position in the first numerical matrix are located, and each non-zero element in the second index matrix is ​​used to indicate the row number of the row where the non-zero elements at the same position in the second numerical matrix are located; The sparse vector operation unit is used to determine the target elements that need to perform dot product operation in each row of the first numerical matrix and in each column of the second numerical matrix based on the non-zero elements in each row of the first index matrix and the non-zero elements in each column of the second index matrix, wherein the target elements are all non-zero elements, perform dot product operation on the target elements, and obtain a first result matrix of sparse multiplication operation performed on the first sparse matrix and the second sparse matrix.

8. The processor according to claim 7, characterized in that The sparse vector operation unit is used to determine the first position in the mth row and the second position in the nth column of the same non-zero element included in the mth row of the first index matrix and the nth column of the second index matrix respectively; The sparse vector operation unit is used to perform a dot product operation on the target element at the first position in the mth row of the first data matrix and the target element at the second position in the nth column of the second data matrix to obtain the element at the mth row and nth column in the first result matrix.

9. The processor according to claim 7 or 8, characterized in that: The sparse matrix processing unit is used to obtain a third numerical matrix and a third index matrix corresponding to the third sparse matrix, and a fourth numerical matrix and a fourth index matrix corresponding to the fourth sparse matrix, wherein the third numerical matrix includes a plurality of first numerical matrix blocks, the third index matrix includes a first index matrix block corresponding to each first numerical matrix block, the fourth numerical matrix includes a plurality of second numerical matrix blocks, and the fourth index matrix includes a plurality of second index matrix blocks corresponding to each second numerical matrix block; The sparse matrix processing unit is used to determine the Cartesian product of a first numerical matrix block of non-zero matrix blocks in the i-th row of the third numerical matrix and a second numerical matrix block of non-zero matrix blocks in the j-th column of the fourth numerical matrix; The sparse matrix processing unit is also used for the sparse matrix processing unit to determine that the first numerical matrix block and the second numerical matrix block included in a group of numerical matrix blocks in the Cartesian product are respectively the first numerical matrix and the second numerical matrix, determine that the first index matrix block corresponding to the first numerical matrix block is the first index matrix, and determine that the second index matrix block corresponding to the second numerical matrix block is the second index matrix.

10. The processor according to claim 9, characterized in that The third numerical matrix includes L×M first numerical matrix areas, each of which includes at least one first numerical matrix block; the third index matrix includes L×M third index matrix areas, each of which includes at least one first index matrix block; The fourth numerical matrix includes M×N second numerical matrix areas, each of which includes at least one second numerical matrix block, and the fourth index matrix includes M×N second index matrix areas, each of which includes at least one second index matrix block.

11. The processor according to claim 10, characterized in that The sparse matrix processing unit is used to determine the number of non-zero matrix areas in the L×N matrix areas included in the second result matrix based on the first position of the zero matrix area in the third numerical matrix, the second position of the non-zero matrix area in the third numerical matrix, and the third position of the zero matrix area in the fourth numerical matrix and the fourth position of the non-zero matrix area in the fourth numerical matrix among the M×N second numerical matrix areas; The sparse matrix processing unit is used to apply for storage space for the second result matrix in the memory based on the number of the non-zero matrix regions.

12. The processor according to any one of claims 9 to 11, characterized in that: The sparse matrix processing unit is used to determine the Cartesian product of the first numerical matrix block of the non-zero matrix block in the i-th row of the third numerical matrix and the second numerical matrix block of the non-zero matrix block in the j-th column of the fourth numerical matrix, including: The sparse matrix processing unit is used to determine the Cartesian product of the first numerical matrix block of each non-zero matrix block and the second numerical matrix block of each non-zero matrix block included in the kth first numerical matrix block group and the kth second numerical matrix block group if it is determined that the nth first numerical matrix block group in the i-th row and the nth second numerical matrix block group in the j-th column meet the operation condition; wherein, The first numerical matrix block group includes the first numerical matrix blocks in the same first numerical matrix area in the i-th row, and the second numerical matrix block group includes the second numerical matrix blocks in the same second numerical matrix area in the j-th column. The operation condition is that both the first numerical matrix block group and the second numerical matrix block group include non-zero matrix blocks.

13. A computing device, characterized in that: The computing device comprises a memory and a processor as described in any one of claims 7 to 12 above, wherein the memory stores at least one instruction, and the processor executes the at least one instruction to execute the method as described in any one of claims 1 to 6.

14. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores a computer program code, and when the computer program code is executed by a computer device, the computer device executes the method according to any one of claims 1 to 6.

15. A computer program product comprising instructions, characterized in that When the computer program product is executed on a computing device, the computing device is caused to execute the method according to any one of claims 1 to 6.

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