Universal method for increasing EDA simulation speed

Abstract

The invention discloses a universal method for accelerating EDA (Electronic Design Automation) simulation speed, which comprises the following steps: S1, preparing information required by chip simulation or verification, the information comprising a design file, a process file and last-round simulation or verification data; s2, after the information preparation is completed, according to a simulation or verification type needing to be performed, determining a proper EDA tool, starting the tool, and reading information including a design file, a process file and previous simulation or verification data so as to perform chip simulation and verification; and S3, exporting a simulation or verification result, and exporting simulation or verification data of the round. The invention discloses a universal method for accelerating EDA (Electronic Design Automation) simulation speed, which is a new method for accelerating calculation or reducing calculation amount by introducing previous-round simulation or verification data in a current-round simulation or verification process, and exporting a database for accelerating next-round simulation or verification in the current-round simulation or verification process. And the simulation or verification time is greatly reduced.

Description

Technical Field

[0001] The invention belongs to the technical field of EDA simulation, and in particular relates to a universal method for accelerating EDA simulation speed. Background Art

[0002] EDA (Electronic Design Automation) refers to the design method of using computer software to complete large-scale integrated circuit design, simulation, verification and other processes, integrating graphics, computational mathematics, microelectronics, topological logic, materials science and artificial intelligence. With the development of the integrated circuit industry, the scale of chip design is getting larger and larger, and the manufacturing process is becoming more and more complicated. Designers cannot complete related work manually, and must rely on EDA tools to complete circuit design, layout design, layout verification, performance analysis and other tasks.

[0003] As an upstream basic tool in the field of integrated circuits, EDA software runs through the integrated circuit design, manufacturing, packaging and testing. Integrated circuit design can be divided into full custom design and semi-custom design based on the implementation method. Full custom design refers to the optimization of the circuit structure layout and wiring based on the transistor level, in which all devices and interconnection layouts are optimized according to the specified functions and performance requirements. It is usually used to design analog circuits and mixed analog and digital circuits; semi-custom design is based on functional blocks of certain specifications such as gate arrays, standard cells, programmable components, etc., and is generally used to design digital circuits. In the integrated circuit design process, EDA tools support every step of full custom design and semi-custom design.

[0004] In traditional full-custom and semi-custom design flows, there are many simulation or verification steps, such as Figure 1 Simulation, formal verification, layout verification, back-end simulation, etc. in the chip semi-custom design process. The single simulation or verification execution process in the chip design process can be summarized as follows: Figure 2 :

[0005] Step 1: Prepare the files required for chip simulation or verification. The files are divided into two categories.

[0006] The first category is the design files representing the chip. Common file formats include Verilog, VHDL, SPICE Netlist, SDC, UPF, DEF, LEF, GDS, SPEF, VCD, SDF, etc.

[0007] The second category is the process files provided by the chip foundry or third-party IP supplier, such as SPICE Model, Timing Model, Verilog Model, physical rule check files, electrical rule check files, antenna effect check files, etc.

[0008] Step 2: After data preparation is completed, determine the appropriate EDA tool based on the type of simulation or verification required. Start the tool, read the design file and process file, and perform chip simulation or verification.

[0009] Step 3: Export simulation or verification results.

[0010] In the traditional full-custom design and semi-custom design processes, each simulation or verification step needs to be iterated multiple times based on whether the current design meets the expected functions, design indicators (such as operating frequency, maximum power consumption, maximum area, etc.), physical rules, electrical rules, etc. As the current chip scale gradually increases, the time required for a single simulation or verification step is getting longer and longer, which makes the entire chip design cycle very long, seriously hindering the rapid listing of chips.

[0011] In addition, in the chip design process, chip simulation or verification requires multiple iterations. During the multiple iterations, the design file representing the chip only updates partial content each time, and most of the content remains unchanged. However, the traditional chip simulation or verification process will perform full simulation or verification of all the contents of the design file during each iteration. Secondly, in the traditional chip simulation or verification process, in order to obtain the final simulation or verification results, the EDA tool will perform a large amount of intermediate calculation data such as design data preprocessing, process data preprocessing, numerical calculation, numerical convergence iterative calculation, etc. These intermediate calculations are very time-consuming, but in the next round of simulation or verification process, the intermediate calculation data of the previous round of simulation or verification will be discarded.

[0012] Therefore, further improvements are made to the above problems. Summary of the invention

[0013] The main purpose of the present invention is to provide a general method for accelerating EDA simulation speed, introducing the previous round of simulation or verification data into the current round of simulation or verification process, a new method for calculating acceleration or reducing the amount of calculation, and exporting a database for accelerating the next round of simulation or verification in the current round of simulation or verification process, thereby greatly reducing the simulation or verification time.

[0014] To achieve the above objectives, the present invention provides a general method for accelerating EDA simulation speed, which is used for single-item simulation verification of chip design, and comprises the following steps:

[0015] Step S1: Prepare information required for chip simulation or verification, which includes design files, process files and previous round simulation or verification data;

[0016] Step S2: After the information is prepared, determine the appropriate EDA tool according to the type of simulation or verification to be performed, start the tool, and read the information including the design file, process file and the previous round of simulation or verification data to perform chip simulation and verification;

[0017] Step S3: Export simulation or verification results, and export the simulation or verification data of this round (export a database for accelerating the next round of simulation or verification).

[0018] As a further preferred technical solution of the above technical solution, for step S1:

[0019] Design files are chip design files. Common file formats include Verilog, VHDL, SPICE, Netlist, SDC, UPF, DEF, LEF, GDS, SPEF, VCD and SDF.

[0020] The process files are those provided by chip foundries or third-party IP suppliers, including SPICE, Model, Timing Model, Verilog Model, physical rule check files, electrical rule check files, and antenna effect check files;

[0021] The previous round of simulation or verification data is any data that can accelerate the current simulation or verification, which is saved by the EDA tool according to the type of simulation or verification performed (the specific content, type or form of the data is not limited and can be freely defined. For example, it can include the chip design files, design file presentation form, data format, compression method, etc. during the previous round of simulation or verification, which can be the same as or different from the original files. It can include the intermediate results of numerical calculations during the previous round of simulation or verification, and the convergence method of numerical iterative calculations. It can include the data preprocessing done on the chip design files during the previous round of simulation or verification. It can include the data preprocessing done on the process files during the previous round of simulation or verification. It can include the analysis process of simulation or verification during the previous round of simulation or verification, the analysis result data, etc.).

[0022] As a further preferred technical solution of the above technical solution, in step S2, if it is the first time to perform simulation or verification, it is not necessary to provide the simulation or verification data of the previous round.

[0023] As a further preferred technical solution of the above technical solution, in step S2, a simulation or verification data processing module for the previous round is designed in the EDA tool, so as to accelerate the current round of simulation or verification according to the simulation or verification data for the previous round (the functions that can be realized by the simulation or verification data processing module for the previous round are not limited and can be freely defined).

[0024] As a further preferred technical solution of the above technical solution, for the previous round simulation or verification data processing module, its functions include:

[0025] First: Compare the similarities and differences between the design files in the previous round of simulation or verification data and the design files in this round, and pass the similarities and differences information to the EDA tool in an appropriate form according to the simulation or verification type. Then the EDA tool only simulates or verifies the different parts according to the simulation or verification type, and directly uses the results of the previous round of simulation or verification for the simulation or verification of the same parts of the design files;

[0026] Second: Analyze the design file preprocessing data and process file preprocessing data in the previous round of simulation or verification data, and pass the preprocessing data to the current round of simulation or verification to accelerate the current round of simulation or verification;

[0027] Third: Analyze the intermediate results of the numerical calculation in the previous round of simulation or verification data (numerical iterative calculation convergence method), and then pass the intermediate data of the previous round of simulation or verification to the current round of simulation or verification to accelerate the current round of simulation or verification. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] Figure 1 It is a traditional full custom design and semi-custom design flow chart.

[0029] Figure 2 It is a single simulation or verification execution flow chart in the chip design process.

[0030] Figure 3 It is a flowchart of the chip design single-item simulation verification execution of the present invention.

[0031] Figure 4 It is a schematic diagram of the EDA tool of the present invention adding a previous round of simulation or verification data processing module. DETAILED DESCRIPTION

[0032] The following description is used to disclose the present invention so that those skilled in the art can implement the present invention. The preferred embodiments described below are only examples, and those skilled in the art can think of other obvious variations. The basic principles of the present invention defined in the following description can be applied to other embodiments, variations, improvements, equivalents, and other technical solutions that do not deviate from the spirit and scope of the present invention.

[0033] In the preferred embodiments of the present invention, those skilled in the art should note that the EDA tools and the like involved in the present invention may be regarded as prior art.

[0034] Preferred embodiments.

[0035] like Figure 3 As shown, the present invention discloses a general method for accelerating EDA simulation speed, which is used for single-item simulation verification of chip design, and includes the following steps:

[0036] Step S1: Prepare information required for chip simulation or verification, which includes design files, process files and previous round simulation or verification data;

[0037] Step S2: After the information is prepared, determine the appropriate EDA tool according to the type of simulation or verification to be performed, start the tool, and read the information including the design file, process file and the previous round of simulation or verification data to perform chip simulation and verification;

[0038] Step S3: Export simulation or verification results, and export the simulation or verification data of this round (export a database for accelerating the next round of simulation or verification).

[0039] Specifically, for step S1:

[0040] Design files are chip design files. Common file formats include Verilog, VHDL, SPICE, Netlist, SDC, UPF, DEF, LEF, GDS, SPEF, VCD and SDF.

[0041] The process files are those provided by chip foundries or third-party IP suppliers, including SPICE, Model, Timing Model, Verilog Model, physical rule check files, electrical rule check files, and antenna effect check files;

[0042] The previous round of simulation or verification data is any data that can accelerate the current simulation or verification, which is saved by the EDA tool according to the type of simulation or verification performed (the specific content, type or form of the data is not limited and can be freely defined. For example, it can include the chip design files, design file presentation form, data format, compression method, etc. during the previous round of simulation or verification, which can be the same as or different from the original files. It can include the intermediate results of numerical calculations during the previous round of simulation or verification, and the convergence method of numerical iterative calculations. It can include the data preprocessing done on the chip design files during the previous round of simulation or verification. It can include the data preprocessing done on the process files during the previous round of simulation or verification. It can include the analysis process of simulation or verification during the previous round of simulation or verification, the analysis result data, etc.).

[0043] More specifically, in step S2, if it is the first time to perform simulation or verification, it is not necessary to provide the simulation or verification data of the previous round.

[0044] Furthermore, if Figure 4 As shown, in step S2, a simulation or verification data processing module for the previous round is designed in the EDA tool, so as to accelerate the current round of simulation or verification according to the simulation or verification data for the previous round (the functions that can be realized by the simulation or verification data processing module for the previous round are not limited and can be freely defined).

[0045] Furthermore, for the last round of simulation or verification data processing module, its functions include:

[0046] First: Compare the similarities and differences between the design files in the previous round of simulation or verification data and the design files in this round, and pass the similarities and differences information to the EDA tool in an appropriate form according to the simulation or verification type. Then the EDA tool only simulates or verifies the different parts according to the simulation or verification type, and directly uses the results of the previous round of simulation or verification for the simulation or verification of the same parts in the design files (different design files need to do different similarities and differences analysis according to the design form described in the file, and different local results need to be updated according to different simulation or verification types, specifically:

[0047] For Verilog, VHDL and SPICE Netlist, these three design files are usually used to describe the logical functions of the circuit, circuit behavior, and the connection relationship between logic units. Therefore, it is necessary to compare whether the logical function of the circuit described in the design files of the two simulations or verifications has changed, whether the connection relationship of the basic devices in the circuit has changed, whether the driving strength, area, and power consumption of the devices in the circuit have changed, etc. After analyzing the similarities and differences between the two simulations, isolate the different parts into local circuits, and then update only the simulation or verification results of the local circuits according to the type of simulation or verification. For these three files, simulation or verification usually includes the following types: logic function simulation, logic equivalence verification, static timing analysis, layout and principle. Figure 1 Consistency verification, etc. For logic function simulation and logic equivalence verification, it is necessary to apply simulation test stimulus to the local difference circuit and its associated circuits, and record the simulation results, then merge the local simulation results with the last simulation results, and output a report. It should be noted that applying simulation test stimulus to the local difference circuit and its associated circuits is only one form of obtaining the simulation results of the local difference circuit. Any other method of obtaining the simulation results of the local circuit is within the scope of protection of this patent; for static timing analysis, it is necessary to recalculate the unit delay, path delay, path timing margin, maximum capacitance, maximum time conversion time, etc. of the local difference circuit and its associated circuits, then merge the local simulation results with the last simulation results, and output a report. For layout and principle Figure 1 Consistency verification requires re-comparing the consistency of the local difference circuit and its associated circuit with the layout file, then merging the local simulation results with the last simulation results and outputting a report.

[0048] For GDSII, DEF and LEF, these three design files are usually used to describe the layout information of the circuit, such as the wiring level of metal interconnects, metal line width, line spacing between metals, through-hole level, through-hole size, standard cell size, standard cell flip direction, standard cell wiring electrical position, etc. Therefore, it is necessary to compare whether the above layout information represented by the design files of the previous and subsequent simulations or verifications has changed. After analyzing the similarities and differences between the two simulations, the difference parts are isolated into local layouts, and then only the simulation or verification results of the local layouts are updated according to the simulation or verification type. For these three files, simulation or verification usually includes the following types: physical rule checking and parasitic parameter extraction. For physical rule checking, it is necessary to recheck the physical rules such as metal line width, metal line spacing, antenna effect, etc. for the local difference layout and the associated layout, and then record the verification results, then merge the local inspection results with the last inspection results, and output a report. For parasitic parameter extraction, it is necessary to re-extract the parasitic parameters of the local difference layout and the associated layout, and record the extraction results. Then, merge the local extraction results with the last extraction results, and output the final extraction results and report.

[0049] For SDC, SDC is a standard design constraint file, which defines the chip's working environment, operating frequency, input pin drive strength, output pin load size, multi-cycle path, false path, etc. Therefore, it is necessary to compare whether the above design constraint information represented by the design files of the two simulations or verifications has changed. After analyzing the similarities and differences between the two simulation standard design constraint files, the difference is written into an incremental SDC file for subsequent simulation or verification. Usually, the SDC file is not used as an independent simulation or verification input, but is simulated or verified together with the RTL or gate-level netlist. For SDC and RTL or gate-level netlist, co-simulation or verification usually includes: logic or physical synthesis, automatic layout and routing, static timing analysis, etc. For the above three types of simulation or verification, after the EDA tool reads the incremental SDC, it analyzes the impact of the incremental SDC on the design, such as whether the operating frequency, the drive strength of the input pin, the load size of the output pin, the multi-cycle path, the false path, etc. have changed. Then, the changed design constraints are re-analyzed, and the impact on the RTL or gate-level netlist is analyzed. Finally, the affected local circuits and related circuits are simulated or verified by logic or physical synthesis, automatic layout and routing, static timing analysis and other steps.

[0050] Second: Analyze the design file preprocessing data and process file preprocessing data in the previous round of simulation or verification data, and pass the preprocessing data to the current round of simulation or verification to accelerate the current round of simulation or verification, where:

[0051] After the standard design files and process files are usually read into the EDA tool, they cannot be used directly. A series of data preprocessing is required according to the simulation or verification type, and this data preprocessing often takes a lot of time to calculate. For example, for static timing analysis, it is necessary to unify the physical units of multiple Timing Models (libraries) and SPEF read in within the EDA tool to facilitate subsequent calculations; for physical verification, it is necessary to merge the GDSII data of each module read in into a full-chip GDSII to perform full-chip physical verification; for voltage drop simulation, it is necessary to merge the DEF data of each module read in into a full-chip DEF to perform full-chip voltage drop simulation; for functional simulation of digital chips, it is necessary to merge the Verilog data of each module into a full-chip Verilog to perform full-chip functional simulation, etc. The general method for accelerating EDA simulation introduced in the present invention can save the preprocessing data of the previous round of design files and the preprocessing data of the process files. Use it directly in this round of simulation or verification to reduce the time required for data preprocessing. In addition, if the design file or process file is partially changed, the unchanged pre-processed data can be partially used in the current round of simulation or verification.

[0052] Third: Analyze the intermediate results of the numerical calculation in the previous round of simulation or verification data (numerical iterative calculation convergence method), and then pass the intermediate data of the previous round of simulation or verification to the current round of simulation or verification to accelerate the current round of simulation or verification, where:

[0053] Different types of simulation or verification tools can also be used for different intermediate results or intermediate data of this round of simulation acceleration. For example, for static timing analysis, a key step is to reduce the model of the RC network, reducing the high-dimensional (dimension is usually greater than 5) RC network to a low-dimensional (dimension is usually less than 5) RC network. Model reduction usually requires a lot of time to calculate; for chip physical verification, it is necessary to perform graphic operations on all graphics of the GDSII file, such as graphic spacing (Space), graphic width (Width), graphic overlap (OverLap), graphic enclosure (Enclosure), graphic extension (Extension), etc. Graphic operations require a lot of time to calculate; for voltage drop simulation, it is necessary to calculate the resistance from the power supply point (Bump) to each standard device power and ground pin, and calculate the current of each standard device. The resistance and current require a lot of time to calculate; the general accelerated EDA simulation method introduced in the present invention can save such intermediate calculation data from the previous round and use it directly in the current round of simulation or verification to reduce the calculation time.

[0054] It is worth mentioning that the technical features such as EDA tools involved in the patent application of this invention should be regarded as prior art. The specific structure, working principle and possible control method and spatial layout method of these technical features can be selected by conventional methods in the field, and should not be regarded as the inventive point of the patent of this invention. The patent of this invention will not be further elaborated.

[0055] For those skilled in the art, it is still possible to modify the technical solutions described in the aforementioned embodiments, or to make equivalent substitutions for some of the technical features therein. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention should be included in the protection scope of the present invention.

Claims

1. A general method for accelerating EDA simulation speed, used for single-item simulation verification of chip design, characterized in that: The following steps are involved: Step S1: Prepare information required for chip simulation or verification, which includes design files, process files and previous round simulation or verification data; Step S2: After the information is prepared, determine the appropriate EDA tool according to the type of simulation or verification to be performed, start the tool, and read the information including the design file, process file and the previous round of simulation or verification data to perform chip simulation and verification; Step S3: Export the simulation or verification results, and export the simulation or verification data of this round.

2. A general method for accelerating EDA simulation speed according to claim 1, characterized in that: For step S1: Design files are chip design files. Common file formats include Verilog, VHDL, SPICE, Netlist, SDC, UPF, DEF, LEF, GDS, SPEF, VCD and SDF. The process files are those provided by chip foundries or third-party IP suppliers, including SPICE, Model, TimingModel, Verilog Model, physical rule check files, electrical rule check files, and antenna effect check files; The previous round of simulation or verification data is any data saved by the EDA tool based on the type of simulation or verification performed and can accelerate the current simulation or verification.

3. A general method for accelerating EDA simulation speed according to claim 2, characterized in that: In step S2, if it is the first time to perform simulation or verification, it is not necessary to provide the simulation or verification data of the previous round.

4. A general method for accelerating EDA simulation speed according to claim 3, characterized in that: In step S2, a module for processing the previous round of simulation or verification data is designed in an EDA tool, so as to accelerate the current round of simulation or verification based on the previous round of simulation or verification data.

5. A general method for accelerating EDA simulation speed according to claim 4, characterized in that: For the last round of simulation or verification data processing module, its functions include: First: Compare the similarities and differences between the design files in the previous round of simulation or verification data and the design files in this round, and pass the similarities and differences information to the EDA tool in an appropriate form according to the simulation or verification type. Then the EDA tool only simulates or verifies the different parts according to the simulation or verification type, and directly uses the results of the previous round of simulation or verification for the simulation or verification of the same parts of the design files; Second: Analyze the design file preprocessing data and process file preprocessing data in the previous round of simulation or verification data, and pass the preprocessing data to the current round of simulation or verification to accelerate the current round of simulation or verification; Third: Analyze the intermediate results of the numerical calculations in the previous round of simulation or verification data, and then pass the intermediate data of the previous round of simulation or verification to the current round of simulation or verification to accelerate the current round of simulation or verification.

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