Pixel circuit, driving method thereof and display panel

Abstract

The invention discloses a pixel circuit and a driving method thereof and a display panel, the pixel circuit comprises a time control module, a current control module, a potential holding module and a light emitting module, and the current control module is used for driving the light emitting module to emit light according to a first data voltage in a light emitting stage; the time control module is used for outputting a time control signal according to the second data voltage and the sweep frequency signal and controlling the potential of the control end of the current control module; the control end of the potential maintaining module is connected with the output end of the time control module, the output end of the potential maintaining module is connected with the control end of the current control module, and the potential maintaining module is used for maintaining the voltage of the control end of the current control module at the turn-off voltage according to the time control signal in the light emitting stage. According to the scheme, the potential of the control end of the current control module can be quickly and stably kept at the turn-off voltage when the light emitting module finishes emitting light, so that the stability of the potential of the control end of the current control module is kept, and the current control module is quickly turned off.

Description

Technical Field

[0001] The embodiments of the present invention relate to the field of display technology, and in particular to a pixel circuit and a driving method thereof, and a display panel. Background Art

[0002] With the continuous development of display technology, people have higher and higher requirements on the display effects of display devices.

[0003] Display driving methods include PWM (Pulse Width Modulation), PAM (Pulse Amplitude Modulation) and a mixture of the two. Currently, in the existing digital-analog hybrid driving method, there is a problem of poor display effect. Summary of the invention

[0004] The embodiment of the present invention provides a pixel circuit and a driving method thereof and a display panel to improve display effect.

[0005] According to one aspect of the present invention, there is provided a pixel circuit, comprising: a time control module, a current control module and a light emitting module;

[0006] The current control module and the light emitting module are connected between the first power line and the second power line, and the current control module is used to drive the light emitting module to emit light according to the first data voltage in the light emitting stage;

[0007] The time control module is used to output a time control signal according to the second data voltage and the frequency sweep signal to control the potential of the control terminal of the current control module;

[0008] It also includes a potential holding module, the control end of the potential holding module is connected to the output end of the time control module, the output end of the potential holding module is connected to the control end of the current control module, and the potential holding module is used to keep the voltage of the control end of the current control module at the shutdown voltage according to the time control signal during the light-emitting stage.

[0009] Optionally, the potential maintaining module includes a first switch unit, a second switch unit and a third switch unit;

[0010] The control end of the first switch unit is connected to the output end of the time control module, the first end of the first switch unit is connected to the third power line, and the second end of the first switch unit is connected to the second end of the second switch unit; the first end of the second switch unit is connected to the first initialization signal line, and the control end of the second switch unit is connected to the output end of the time control module, or the control end of the second switch unit is connected to the first scan line;

[0011] The control end of the third switch unit is connected to the second end of the first switch unit, the first end of the third switch unit is connected to the third power line, and the second end of the third switch unit is connected to the control end of the current control module;

[0012] The third power line is used to transmit the shutdown voltage, and the third switch unit is used to transmit the shutdown voltage to the control end of the current control module in response to the potential of the second end of the first switch unit;

[0013] Optionally, the first initialization signal line is multiplexed as a first scan line.

[0014] Optionally, the first switch unit includes a first transistor, the second switch unit includes a second transistor, and the third switch unit includes a third transistor; the gate of the first transistor is the control end of the first switch unit, the first pole of the first transistor is the first end of the first switch unit, and the second pole of the first transistor is the second end of the first switch unit; the gate of the second transistor is the control end of the second switch unit, the first pole of the second transistor is the first end of the second switch unit, and the second pole of the second transistor is the second end of the second switch unit; the gate of the third transistor is the control end of the third switch unit, the first pole of the third transistor is the first end of the third switch unit, and the second pole of the third transistor is the second end of the third switch unit;

[0015] Optionally, a width-to-length ratio of the first transistor is greater than a width-to-length ratio of the second transistor.

[0016] Optionally, the potential holding module further includes a fourth switch unit, a control end of the fourth switch unit is connected to the second scan line, a first end of the fourth switch unit is connected to the first initialization signal line, a second end of the fourth switch unit is connected to the control end of the current control module, and the fourth switch unit is used to transmit the first initialization voltage on the first initialization signal line to the control end of the current control module in response to the signal on the second scan line when the third switch unit is turned off;

[0017] Optionally, the first initialization signal line is multiplexed as a second scan line;

[0018] Optionally, the fourth switch unit includes a fourth transistor, the gate of the fourth transistor is the control end of the fourth switch unit, the first pole of the fourth transistor is the first end of the fourth switch unit, and the second pole of the fourth transistor is the second end of the fourth switch unit; the width-to-length ratio of the third transistor is greater than the width-to-length ratio of the fourth transistor.

[0019] Optionally, the potential holding module further includes a reset unit, a control end of the reset unit is connected to the reset signal line, a first end of the reset unit is connected to the second initialization signal line, and a second end of the reset unit is connected to the control end of the current control module;

[0020] Optionally, the first initialization signal line is multiplexed as a second initialization signal line.

[0021] Optionally, the potential holding module further includes a first storage unit, a first end of the first storage unit is connected to the first initialization signal line, and a second end of the first storage unit is connected to the control end of the current control module;

[0022] The potential holding module further includes a first initialization unit, a control end of the first initialization unit is connected to the third scan line, a first end of the first initialization unit is connected to the first initialization signal line, and a second end of the first initialization unit is connected to the control end of the first switch unit.

[0023] Optionally, the current control module includes a first driving unit, a first data writing unit and a current control unit; the current control unit and the first driving unit are connected between the first power line and the first end of the light emitting module, the second end of the light emitting module is connected to the second power line, the first data writing unit is connected to the first driving unit, and the first data writing unit is used to write the first data voltage to the control end of the first driving unit;

[0024] Optionally, the current control module further includes a first compensation unit, the first compensation unit is connected between the second end and the control end of the first driving unit, the first data writing unit is connected to the first end of the first driving unit, and the control end of the first data writing unit and the control end of the first compensation unit are both connected to the third scan line;

[0025] Optionally, the current control module further includes a first light-emitting control unit, a second light-emitting control unit and a third light-emitting control unit, wherein the first end of the first light-emitting control unit is connected to the first power line, the second end of the first light-emitting control unit is connected to the first end of the current control unit, the first end of the second light-emitting control unit is connected to the second end of the current control unit, the second end of the second light-emitting control unit is connected to the first end of the first driving unit, the first end of the third light-emitting control unit is connected to the second end of the first driving unit, and the second end of the third light-emitting control unit is connected to the first end of the light-emitting module; the control end of the second light-emitting control unit and the control end of the third light-emitting control unit are both connected to the first light-emitting control signal line, and the control end of the first light-emitting control unit is connected to the second light-emitting control signal line;

[0026] Optionally, the current control module also includes a second storage unit and a third storage unit, the second storage unit is connected between the control end of the first driving unit and the first power line, and the third storage unit is connected between the control end of the current control unit and the first power line; the current control module also includes a second initialization unit, the first end of the second initialization unit is connected to the third initialization signal line, the second end of the second initialization unit is connected to the control end of the first driving unit, and the control end of the second initialization unit is connected to the fourth scan line.

[0027] Optionally, the time control module includes a second driving unit, a second data writing unit, a third initialization unit and a coupling unit; the second driving unit is connected between the fourth power line and the control end of the potential holding module, and the second data writing unit is used to write the second data voltage to the control end of the second driving unit; the third initialization unit is connected between the fourth initialization signal line and the control end of the second driving unit, and the control end of the third initialization unit is connected to the third scanning line; the coupling unit is connected to the control end of the second driving unit, and the coupling unit is used to control the potential of the control end of the second driving unit according to the frequency sweep signal;

[0028] Optionally, the time control module further includes a second compensation unit, the second compensation unit is connected between the control end and the second end of the second driving unit, and the control end of the second compensation unit and the control end of the second data writing unit are both connected to the fifth scan line;

[0029] Optionally, the time control module also includes a fourth light-emitting control unit and a fifth light-emitting control unit, the control end of the fourth light-emitting control unit and the control end of the fifth light-emitting control unit are both connected to the second light-emitting control signal line, the first end of the fourth light-emitting control unit is connected to the fourth power line, the second end of the fourth light-emitting control unit is connected to the first end of the second driving unit, the first end of the fifth light-emitting control unit is connected to the second end of the second driving unit, and the second end of the fifth light-emitting control unit is connected to the control end of the potential holding module.

[0030] According to another aspect of the present invention, a method for driving a pixel circuit is provided, wherein the pixel circuit includes a time control module, a current control module and a light emitting module, wherein the current control module and the light emitting module are connected between a first power line and a second power line, and further includes a potential holding module, wherein a control end of the potential holding module is connected to an output end of the time control module, and an output end of the potential holding module is connected to a control end of the current control module; the method for driving the pixel circuit includes:

[0031] In the light-emitting stage, the current control module is controlled to drive the light-emitting module to emit light according to the first data voltage of its own control end, and the time control module is controlled to output a time control signal to the output end of the current control module according to the second data voltage and the sweep signal, and the potential holding module is controlled to keep the voltage of the control end of the current control module at the shutdown voltage according to the time control signal.

[0032] According to another aspect of the present invention, a display panel is provided, comprising the pixel circuit provided by any embodiment of the present invention.

[0033] The technical solution provided by the embodiment of the present invention is to control the potential of the control end of the current control module by outputting the time control signal according to the second data voltage and the frequency sweep signal through the time control module, so as to control the duration of the driving current generated by the current control module, thereby controlling the light-emitting time of the light-emitting module. In addition, a potential holding module is connected in series between the output end of the time control module and the control end of the current control module, so that the potential of the control end of the current control module can be quickly and stably maintained at the turn-off voltage when the light-emitting module ends, thereby maintaining the stability of the potential of the control end of the current control module, and can quickly turn off the current control module, effectively avoiding the phenomenon of unstable light emission, thereby facilitating the improvement of the flickering or uneven display caused by the unstable output signal of the time control module when the pixel circuit is turned off, and facilitating the improvement of the display effect.

[0034] It should be understood that the contents described in this section are not intended to identify the key or important features of the embodiments of the present invention, nor are they intended to limit the scope of the present invention. Other features of the present invention will become easily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0036] Figure 1 A schematic structural diagram of a pixel circuit provided by an embodiment of the present invention;

[0037] Figure 2 A schematic diagram of the structure of another pixel circuit provided by an embodiment of the present invention;

[0038] Figure 3 A schematic diagram of the structure of another pixel circuit provided by an embodiment of the present invention;

[0039] Figure 4 A schematic diagram of the structure of another pixel circuit provided by an embodiment of the present invention;

[0040] Figure 5 A schematic diagram of the structure of another pixel circuit provided by an embodiment of the present invention;

[0041] Figure 6 A schematic diagram of the structure of another pixel circuit provided by an embodiment of the present invention;

[0042] Figure 7 A schematic diagram of the structure of another pixel circuit provided by an embodiment of the present invention;

[0043] Figure 8 A schematic diagram of the structure of another pixel circuit provided by an embodiment of the present invention;

[0044] Fig. 9 A schematic diagram of the structure of another pixel circuit provided by an embodiment of the present invention;

[0045] Fig.10 A schematic diagram of the structure of another pixel circuit provided by an embodiment of the present invention;

[0046] Fig.11 A schematic diagram of the structure of a current control module provided by an embodiment of the present invention;

[0047] Fig.12 A schematic diagram of the structure of a time control module provided by an embodiment of the present invention;

[0048] Fig.13 A schematic diagram of the structure of another pixel circuit provided by an embodiment of the present invention;

[0049] Fig.14 A driving timing diagram of a pixel circuit provided by an embodiment of the present invention;

[0050] Fig.15 A schematic structural diagram of a display panel provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0051] In order to enable those skilled in the art to better understand the scheme of the present invention, the technical scheme in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the present invention.

[0052] It should be noted that the terms "first", "second", etc. in the specification and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged where appropriate, so that the embodiments of the present invention described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units that are clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0053] As described in the background technology, the existing analog-digital hybrid driving method has the problem of poor display effect. The inventors have found that the reason for the above problem is that for the existing pixel circuit adopting the analog-digital hybrid driving method, the pixel circuit usually includes a PWM driving module and a PAM driving module, wherein the PWM driving module is used to convert the analog grayscale voltage through PWM modulation to control the switching time of the PAM driving module to generate a driving current, thereby controlling the light-emitting time of the light-emitting element. However, the time control signal output by the PWM driving module is easily affected by the leakage of the PWM driving module itself, resulting in signal attenuation, node potential instability and other phenomena, which leads to poor uniformity of light-emitting brightness and reduces the display effect.

[0054] In view of the above problems, an embodiment of the present invention provides a pixel circuit. Figure 1 A schematic diagram of a pixel circuit according to an embodiment of the present invention is provided. Figure 1 The pixel circuit provided in this embodiment includes a time control module 10, a current control module 20 and a light-emitting module 30. The current control module 20 and the light-emitting module 30 are connected between the first power line L1 and the second power line L2. The current control module 20 is used to drive the light-emitting module 30 to emit light according to the first data voltage Vdata_I in the light-emitting stage; the time control module 10 is used to output a time control signal to the control end of the current control module 20 according to the second data voltage Vdata_t and the sweep signal SWEEP to control the light-emitting time of the light-emitting module 30.

[0055] The first power line L1 is used to provide a first power supply voltage VDDA, and the second power line L2 is used to provide a second power supply voltage VSS. The current control module 20 can generate a driving current when the connection path between the first power line L1 and the second power line L2 is turned on, so as to drive the light-emitting module 30 to emit light. The magnitude of the driving current is related to the magnitude of the first data voltage Vdata_I connected to the current control module 20. The time control module 10 outputs a time control signal according to the second data voltage Vdata_t and the sweep signal SWEEP to control the potential of the control terminal of the current control module 20, thereby controlling the light-emitting time of the light-emitting module 30.

[0056] In this embodiment, the pixel circuit further includes a potential holding module 40. The control end of the potential holding module 40 is connected to the output end of the time control module 10, and the output end of the potential holding module 40 is connected to the control end of the current control module 20. The potential holding module 40 is used to keep the voltage of the control end of the current control module 20 at the off voltage according to the time control signal during the light emitting stage.

[0057] Specifically, the potential holding module 40 is connected between the output end of the time control module 10 and the control end of the current control module 20, so that the time control module 10 and the current control module 20 are not directly connected, that is, the time control signal output by the time control module 10 does not directly control the potential of the control end of the current control module 20. Therefore, even if the time control signal of the time control module 10 is unstable due to its own leakage, the potential holding module 40 can still stabilize the potential of the control end of the current control module 20 at the shutdown voltage (for example, the shutdown voltage can be the third power supply voltage VDDW; in other embodiments, the shutdown voltage can be any voltage that can shut down the current control module 20), preventing the potential of the control end of the current control module 20 from attenuating and other unstable problems, thereby ensuring that the current control module 20 can be quickly shut down at the end of light emission, reducing the driving current attenuation phenomenon caused by the unstable potential of the control end of the current control module 20, improving the difference in driving current between different pixels, improving the uniformity of the driving current, effectively avoiding the difference in light emission time between different pixels, and helping to improve the display effect.

[0058] The technical solution provided by the embodiment of the present invention is to control the potential of the control end of the current control module by outputting the time control signal according to the second data voltage and the frequency sweep signal through the time control module, so as to control the duration of the driving current generated by the current control module, thereby controlling the light-emitting time of the light-emitting module. In addition, a potential holding module is connected in series between the output end of the time control module and the control end of the current control module, so that the potential of the control end of the current control module can be quickly and stably maintained at the turn-off voltage when the light-emitting module ends, thereby maintaining the stability of the potential of the control end of the current control module, and can quickly turn off the current control module, effectively avoiding the phenomenon of unstable light emission, thereby facilitating the improvement of the flickering or uneven display caused by the unstable output signal of the time control module when the pixel circuit is turned off, and facilitating the improvement of the display effect.

[0059] Figure 2 A schematic diagram of another pixel circuit provided by an embodiment of the present invention, referring to Figure 2On the basis of the above technical solution, optionally, the potential holding module 40 includes a first switch unit 401, a second switch unit 402 and a third switch unit 403. The control end of the first switch unit 401 is connected to the N1 node as the control end of the potential holding module 40 and the output end of the time control module 10. The first end of the first switch unit 401 is connected to the third power line L3. The third power line L3 is used to transmit the third power voltage VDDW, and the third power voltage VDDW is used as the shutdown voltage. The second end of the first switch unit 401 and the second end of the second switch unit 402 are connected to the N2 node. The first end of the second switch unit 402 is connected to the first initialization signal line. The control end of the second switch unit 402 is connected to the first scan line. The second switch unit 402 is used to respond to the first scan signal S1 on the first scan line to turn on, so as to transmit the first initialization voltage Vinit1 on the first initialization signal line to the node N2. The control end of the third switch unit 403 is connected to the second end of the first switch unit 401, that is, connected to the N2 node. The first end of the third switch unit 403 is connected to the third power line L3. The second end of the third switch unit 403 is connected to the N3 node as the output end of the potential holding module 40 and the control end of the current control module 20.

[0060] The third switch unit 403 is used to transmit the shutdown voltage to the control end of the current control module 20 in response to the potential of the second end of the first switch unit 401 , so as to control the current control module 20 to be shut down.

[0061] Figure 3 A schematic diagram of another pixel circuit structure provided by an embodiment of the present invention, specifically: Figure 2 The potential holding module 40 in the pixel circuit shown in FIG. 4 is further refined into a schematic diagram of the structure of the device, referring to FIG. Figure 3 The first switch unit 401 includes a first transistor M1, the second switch unit 402 includes a second transistor M2, and the third switch unit 403 includes a third transistor M3. The gate of the first transistor M1 is the control end of the first switch unit 401, the first pole of the first transistor M1 is the first end of the first switch unit 401, and the second pole of the first transistor M1 is the second end of the first switch unit 401; the gate of the second transistor M2 is the control end of the second switch unit 402, the first pole of the second transistor M2 is the first end of the second switch unit 402, and the second pole of the second transistor M2 is the second end of the second switch unit 402; the gate of the third transistor M3 is the control end of the third switch unit 403, the first pole of the third transistor M3 is the first end of the third switch unit 403, and the second pole of the third transistor M3 is the second end of the third switch unit 403.

[0062] Specifically, Figure 3In the pixel circuit shown, the first transistor M1, the second transistor M2, and the third transistor M3 are all P-type transistors, and the low-level signals of their corresponding gates are turned on. Before entering the light-emitting stage, a low level can be transmitted to the N1 node, so that the first transistor M1 is in a conducting state. When the first transistor M1 is turned on, the second transistor M2 can be turned off by the first scanning signal S1, and the potential of the N2 node is controlled by the first transistor M1. At this time, the potential of the N2 node is a high level (the third power supply voltage VDDW), and the third transistor M3 is turned off, and the third transistor M3 does not control the potential of the N3 node.

[0063] In the light-emitting stage, a low level is transmitted to the N3 node to control the current control module 20 to be turned on. The current control module 20 generates a driving current according to the first data voltage Vdata_I connected to drive the light-emitting module 30 to emit light. Under the action of the sweep signal SWEEP, the time control module 10 gradually outputs a time control signal to the N1 node. When the potential of the N1 node causes the first transistor M1 to be turned off, the potential of the N2 node is controlled by the second transistor M2. The second transistor M2 transmits the first initialization voltage Vinit1 to the N2 node in response to the first scan signal S1, and the third transistor M3 is turned on in response to the potential of the N2 node, and transmits the third power supply voltage VDDW to the N3 node, so that the control end of the current control module 20 is quickly maintained at the potential of the turn-off voltage, avoiding the potential of the control end of the current control module 20 to gradually change with the time control signal of the N1 node, ensuring the stability of the potential of the control end of the current control module 20, and then ensuring the stability of the light emission.

[0064] Optionally, when the first transistor M1 is turned on, the second transistor M2 may also be controlled to be turned on by the first scan signal S1. Figure 4 A schematic diagram of another pixel circuit provided by an embodiment of the present invention, Figure 3 The difference between the pixel circuits shown is that Figure 4 In the pixel circuit shown, the first initialization signal line is multiplexed as the first scan line, that is, the gate of the second transistor M2 is short-circuited with the first electrode and connected between the first initialization signal line and the N2 node in a diode structure. Here, the second transistor M2 is always in the on state.

[0065] The width-to-length ratio of the first transistor M1 is greater than that of the second transistor M2, so that the control capability of the first transistor M1 over the N2 node is stronger than that of the second transistor M2 over the N2 node. Therefore, when both the first transistor M1 and the second transistor M2 are turned on, the potential of the N2 node is dominated by the first transistor M1. The working principle of this circuit is similar to Figure 3 The circuits shown are the same and will not be described in detail. By multiplexing the first initialization signal line as the first scan line, the number of signal lines can be reduced, which is beneficial to improving the PPI.

[0066] Figure 5 A schematic diagram of another pixel circuit provided by an embodiment of the present invention, Figure 3 The pixel circuit shown differs in that Figure 5 In the potential holding module 40 shown, the control end of the second switch unit 402 is connected to the output end of the time control module 10. Specifically, the second transistor M2 included in the second switch unit 402 is an N transistor, and the first transistor M1 and the third transistor M3 are P transistors. Since the gate of the first transistor M1 and the gate of the second transistor M2 are both connected to the N1 node, the first transistor M1 and the second transistor M2 are not turned on at the same time, and the specific working process is the same as Figure 3 The working process of the pixel circuit shown is similar and will not be repeated here.

[0067] Figure 6 A schematic diagram of another pixel circuit provided by an embodiment of the present invention, referring to Figure 6 On the basis of the above technical solutions, optionally, the potential holding module 40 also includes a fourth switch unit 404, the control end of the fourth switch unit 404 is connected to the second scan line, the first end of the fourth switch unit 404 is connected to the first initialization signal line, and the second end of the fourth switch unit 404 is connected to the control end of the current control module 20. The fourth switch unit 404 is used to respond to the second scan signal S2 on the second scan line to transmit the first initialization voltage Vinit1 on the first initialization signal line to the control end of the current control module 20 when the third switch unit 403 is turned off, so as to prevent the control end of the current control module 20 from floating, which is beneficial to improving the stability and anti-interference ability of the potential of the control end of the current control module 20.

[0068] Figure 7 A schematic diagram of another pixel circuit structure provided by an embodiment of the present invention, specifically: Figure 6 The potential holding module 40 in the pixel circuit shown is refined into a schematic diagram of the structure of the device, the fourth switch unit 404 includes a fourth transistor M4, the gate of the fourth transistor M4 is the control end of the fourth switch unit 404, the first pole of the fourth transistor M4 is the first end of the fourth switch unit 404, and the second pole of the fourth transistor M4 is the second end of the fourth switch unit 404. Figure 3 On the basis of the potential holding module 40 shown, when the first transistor M1 is turned on, the third transistor M3 is turned off in response to the voltage of the N2 node. At this time, the fourth transistor M4 can be turned on by the second scanning signal S2 to transmit the first initialization voltage Vinit1 to the N3 node to lower the potential of the control end of the current control module 20 to prevent the control end of the current control module 20 from floating. At the same time, the fourth transistor M4 can also be set to initialize the control end of the current control module 20.

[0069] When the third transistor M3 is turned on in response to the voltage of the N2 node, the fourth transistor M4 may be controlled to be turned off by the second scan signal S2.

[0070] In another optional implementation, when the third transistor M3 is turned on in response to the voltage at the N2 node, the fourth transistor M4 may still remain in the turned-on state. Figure 8 A schematic diagram of another pixel circuit provided by an embodiment of the present invention, referring to Figure 8 , the first initialization signal line can be multiplexed as the second scan line, that is, the gate of the fourth transistor M4 is short-circuited with the first electrode. In this embodiment, the width-to-length ratio of the third transistor M3 is greater than the width-to-length ratio of the fourth transistor M4, so that the control capability of the third transistor M3 over the N3 node is stronger than the control capability of the fourth transistor M4 over the N3 node. When the third transistor M3 is turned on in response to the voltage of the N2 node, the potential of the N3 node is dominated by the third transistor M3, and the third transistor M3 transmits the third power supply voltage VDDW to the N3 node, thereby maintaining the potential of the N3 node at the turn-off voltage of the current control module 20 to quickly turn off the current control module 20.

[0071] Fig. 9 A schematic diagram of another pixel circuit provided by an embodiment of the present invention, referring to Fig. 9 ,exist Figure 3 On the basis of the technical solution shown, the potential holding module 40 further includes a reset unit 405, the control end of the reset unit 405 is connected to the reset signal line, the first end of the reset unit 405 is connected to the second initialization signal line, and the second end of the reset unit 405 is connected to the control end of the current control module 20. The reset unit 405 is used to respond to the reset signal Set on the reset signal line in the reset stage before light emission, transmit the second initialization voltage Vinit2 on the second initialization signal line to the control end of the current control module 20, and initialize the control end of the current control module 20.

[0072] In this embodiment, the first initialization signal line can be multiplexed as the second initialization signal line to reduce the number of signal lines.

[0073] Optionally, continue to refer to Fig. 9 The potential holding module 40 further includes a first storage unit 407, a first end of the first storage unit 407 is connected to the first initialization signal line, and a second end of the first storage unit 407 is connected to the control end of the current control module 20. The first storage unit 407 may be a capacitor, which is used to store the potential of the control end of the current control module 20 and maintain the stability of the potential of the control end of the current control module 20 when the current control module 20 is turned off, so that the current control module 20 can be turned off more reliably.

[0074] Continue to refer Fig. 9 The potential holding module 40 further includes a first initialization unit 406, a control end of the first initialization unit 406 is connected to the third scan line, a first end of the first initialization unit 406 is connected to the first initialization signal line, and a second end of the first initialization unit 406 is connected to the control end of the first switch unit 401. The first initialization unit 406 is used to transmit the first initialization voltage Vinit1 to the N1 node before the time control module 10 outputs the time control signal, so as to turn on the first switch unit 401, thereby keeping the third switch unit 403 in the off state.

[0075] Fig.10 A schematic diagram of another pixel circuit provided by an embodiment of the present invention, referring to Fig.10 ,exist Figure 6 Based on the technical solution shown in FIG. 1 , the potential holding module 40 further includes a first storage unit 407, a reset unit 405 and a first initialization unit 406. The specific working process is similar to that of FIG. 1 . Fig. 9 The working process of the pixel circuit shown is the same and will not be repeated here.

[0076] Fig.11 A schematic diagram of a current control module according to an embodiment of the present invention is provided. Fig.11 On the basis of the above technical solutions, optionally, the current control module 20 includes a first driving unit 201, a first data writing unit 202 and a current control unit 203, the current control unit 203 and the first driving unit 201 are connected between the first power line L1 and the first end of the light emitting module 30, the second end of the light emitting module 30 is connected to the second power line L2, the first data writing unit 202 is connected to the first driving unit 201, and the first data writing unit 202 is used to write the first data voltage Vdata_I to the control end of the first driving unit 201. Among them, the control end of the current control unit 203 is connected to the N3 node as the control end of the current control module 20. In the light emitting stage, by controlling the on-off state of the current control unit 203, the light emitting time of the light emitting module 30 can be controlled.

[0077] Further, the current control module 20 further includes a first compensation unit 204, the first compensation unit 204 is connected between the second end and the control end of the first driving unit 201, the first data writing unit 202 is connected to the first end of the first driving unit 201, and the control end of the first data writing unit 202 and the control end of the first compensation unit 204 are both connected to the third scan line. The first compensation unit 204 is used to compensate for the threshold voltage of the first driving unit 201 to improve the problem of poor uniformity of the driving current caused by the change of the threshold characteristic of the first driving unit 201.

[0078] Optionally, the current control module 20 further includes a first light-emitting control unit 206, a second light-emitting control unit 207, and a third light-emitting control unit 208, wherein the first end of the first light-emitting control unit 206 is connected to the first power line L1, the second end of the first light-emitting control unit 206 is connected to the first end of the current control unit 203, the first end of the second light-emitting control unit 207 is connected to the second end of the current control unit 203, the second end of the second light-emitting control unit 207 is connected to the first end of the first driving unit 201, the first end of the third light-emitting control unit 208 is connected to the second end of the first driving unit 201, and the second end of the third light-emitting control unit 208 is connected to the first end of the light-emitting module 30; the control end of the second light-emitting control unit 207 and the control end of the third light-emitting control unit 208 are both connected to the first light-emitting control signal line, and the control end of the first light-emitting control unit 206 is connected to the second light-emitting control signal line. The first light-emitting control unit 206 can cut off the connection between the first power line L1 and the current control unit 203 in the non-light-emitting stage to prevent the current control unit 203 from being mis-conducted. The second light-emitting control unit 207 is used to cut off the connection between the current control unit 203 and the first driving unit 201 in the non-light-emitting stage to prevent the first power supply voltage VDDA from interfering with the first data voltage Vdata_I when the first data voltage Vdata_I is transmitted to the first end of the first driving unit 201, thereby affecting the light-emitting quality.

[0079] The current control module 20 also includes a second storage unit 210 and a third storage unit 211, the second storage unit 210 is connected between the control end of the first driving unit 201 and the first power line L1, and the third storage unit 211 is connected between the control end of the current control unit 203 and the first power line L1; the current control module 20 also includes a second initialization unit 205, the first end of the second initialization unit 205 is connected to the third initialization signal line, the second end of the second initialization unit 205 is connected to the control end of the first driving unit 201, and the control end of the second initialization unit 205 is connected to the fourth scan line.

[0080] Fig.12 A schematic diagram of a time control module provided by an embodiment of the present invention, referring to Fig.12On the basis of the above technical solutions, optionally, the time control module 10 includes a second driving unit 101, a second data writing unit 102, a third initialization unit 103 and a coupling unit 104, the second driving unit 101 is connected between the fourth power line L4 and the control end of the potential holding module 40, the second data writing unit 102 is used to write the second data voltage Vdata_t to the control end of the second driving unit 101; the third initialization unit 103 is connected between the fourth initialization signal line and the control end of the second driving unit 101, the control end of the third initialization unit 103 is connected to the third scanning line; the coupling unit 104 is connected to the control end of the second driving unit 101, and the coupling unit 104 is used to control the potential of the control end of the second driving unit 101 according to the sweep signal SWEEP.

[0081] Exemplarily, before the light-emitting stage, the third initialization unit 103 transmits the fourth initialization voltage Vinit4 on the fourth initialization signal line to the control end of the second driving unit 101 in response to the third scan signal S3 on the third scan line, initializes the control end of the second driving unit 101, and turns on the second driving unit 101. Afterwards, the second data voltage Vdata_t is transmitted to the control end of the second driving unit 101 via the second data writing unit 102, and a constant voltage difference is maintained across the coupling unit 104. In the light-emitting stage, the current control module 20 can generate a driving current in the light-emitting stage according to the voltage state of its control end to drive the light-emitting module 30 to emit light. Among them, the sweep signal SWEEP is used to perform signal scanning from a high level to a low level, or from a low level to a high level in the light-emitting stage, so as to control the voltage of the output end (node ​​N1) of the time control module 10, thereby controlling the voltage of the control end of the current control module 20, and then controlling the working state (on or off) of the current control module 20, so as to control the light-emitting time of the light-emitting module 30.

[0082] Optionally, the time control module 10 further includes a second compensation unit 105, which is connected between the control end and the second end of the second driving unit 101, and the control end of the second compensation unit 105 and the control end of the second data writing unit 102 are both connected to the fifth scan line. The second data writing unit 102 is connected to the first end of the second driving unit 101.

[0083] In this embodiment, the power supply voltage transmitted on the fourth power supply line L4 can be set according to actual needs, and can be the same as the third power supply voltage VDDW or different from the third power supply voltage VDDW. When the third power supply voltage VDDW is the same as the third power supply voltage VDDW, the third power supply line L3 can be reused as the fourth power supply line L4.

[0084] Optionally, the time control module 10 also includes a fourth light-emitting control unit 106 and a fifth light-emitting control unit 107, the control end of the fourth light-emitting control unit 106 and the control end of the fifth light-emitting control unit 107 are both connected to the second light-emitting control signal line, the first end of the fourth light-emitting control unit 106 is connected to the fourth power line L4, the second end of the fourth light-emitting control unit 106 is connected to the first end of the second driving unit 101, the first end of the fifth light-emitting control unit 107 is connected to the second end of the second driving unit 101, and the second end of the fifth light-emitting control unit 107 is connected to the control end of the potential holding module 40.

[0085] As a preferred implementation provided in this embodiment, Fig.13 A schematic diagram of another pixel circuit provided by an embodiment of the present invention, referring to Fig.13 On the basis of the above technical solutions, the reset unit 405 includes a fifth transistor M5, the gate of the fifth transistor M5 is connected to the reset signal line, the first electrode of the fifth transistor M5 is connected to the second initialization signal line, and the second electrode of the fifth transistor M5 is connected to the N3 node. The first initialization unit 406 includes a sixth transistor M6, the gate of the sixth transistor M6 is connected to the third scan line, the first electrode of the sixth transistor M6 is connected to the first initialization signal line, and the second electrode of the sixth transistor M6 is connected to the N1 node. The first storage unit 407 includes a fourth capacitor C4, the first electrode of the fourth capacitor C4 is connected to the first initialization signal line, and the second electrode of the fourth capacitor C4 is connected to the N3 node.

[0086] The first driving unit 201 includes a seventh transistor M7, the current control unit 203 includes an eighth transistor M8, the first data writing unit includes a ninth transistor M9, the first compensation unit 204 includes a tenth transistor M10, the first light-emitting control unit 206 includes an eleventh transistor M11, the second light-emitting control unit 207 includes a twelfth transistor M12, the third light-emitting control unit 208 includes a thirteenth transistor M13, the second initialization unit 205 includes a fourteenth transistor M14, the second storage unit 210 includes a second capacitor C2, and the third storage unit 211 includes a third capacitor C3. The light-emitting module 30 includes a light-emitting diode D1, which may be an LED, an OLED, a Micro LED, or a Mini LED.

[0087] The second driving unit 101 includes a fifteenth transistor M15, the second data writing unit 102 includes a sixteenth transistor M16, the second compensation unit 105 includes a seventeenth transistor M17, the third initializing unit 103 includes an eighteenth transistor M18, the fourth light emitting control unit 106 includes a nineteenth transistor M19, and the fifth light emitting control unit 107 includes a second transistor M20.

[0088] Fig.14 A driving timing diagram of a pixel circuit provided by an embodiment of the present invention can be applied to Fig.13 As shown in the pixel circuit. Taking all transistors as P tubes as an example, combined with Fig.13 and Fig.14 The specific operation of the pixel circuit provided in this embodiment includes a voltage writing stage T1, a reset stage T2 and a light emitting stage T3, wherein the voltage writing stage T1 includes an initialization stage t1, a first data writing stage t2 and a second data writing stage t3.

[0089] In the initialization stage t1, the third scan signal line is configured to transmit a high-level third scan signal S3, the fourth scan signal line is configured to transmit a low-level fourth scan signal S4, the fifth scan signal line is configured to transmit a high-level fifth scan signal S5, the reset signal line is configured to transmit a high-level reset signal Set, the first light-emitting control signal line is configured to transmit a high-level first light-emitting control signal EM1, and the second light-emitting control signal line is configured to transmit a high-level second light-emitting control signal EM2. Therefore, the fourteenth transistor M14 is turned on, and the third initialization voltage Vinit3 transmitted on the third initialization signal line is written to the gate of the seventh transistor M7, so as to initialize the gate potential of the seventh transistor M7 and turn on the seventh transistor M7.

[0090] In the first data writing phase t2, the third scan signal line is configured to transmit a low-level third scan signal S3, the fourth scan signal line is configured to transmit a high-level fourth scan signal S4, the fifth scan signal line is configured to transmit a high-level fifth scan signal S5, the reset signal line is configured to transmit a high-level reset signal Set, the first light-emitting control signal line is configured to transmit a high-level first light-emitting control signal EM1, and the second light-emitting control signal line is configured to transmit a high-level second light-emitting control signal EM2. Therefore, the sixth transistor M6, the ninth transistor M9, the tenth transistor M10, and the eighteenth transistor M18 are turned on. The first data voltage Vdata_I is transmitted to the gate of the seventh transistor M7 via the ninth transistor M9, the seventh transistor M7, and the tenth transistor M10, and the gate potential of the seventh transistor M7 is Vdata_I+Vth7, and is stored on the second capacitor C2, where Vth7 is the threshold voltage of the seventh transistor M7, and the threshold compensation of the seventh transistor M7 is realized.

[0091] The fourth initialization voltage Vinit4 transmitted on the fourth initialization signal line is transmitted to the gate of the fifteenth transistor M15 via the eighteenth transistor M18, so as to initialize the gate potential of the fifteenth transistor M15 and turn on the fifteenth transistor M15. At the same time, the first initialization voltage Vinit1 on the first initialization signal line is transmitted to the N1 node via the sixth transistor M6, so that the first transistor M1 is turned on. Since the width-to-length ratio of the first transistor M1 is greater than the width-to-length ratio of the second transistor M2, the potential of the N2 node is controlled by the first transistor M1, the potential of the N2 node is VDDW, the third transistor M3 is turned off, and the N3 node maintains the first initialization voltage Vinit1 under the action of the fourth transistor M4.

[0092] In the second data writing phase t3, the third scan signal line is configured to transmit a high-level third scan signal S3, the fourth scan signal line is configured to transmit a high-level fourth scan signal S4, the fifth scan signal line is configured to transmit a low-level fifth scan signal S5, the reset signal line is configured to transmit a high-level reset signal Set, the first light-emitting control signal line is configured to transmit a high-level first light-emitting control signal EM1, and the second light-emitting control signal line is configured to transmit a high-level second light-emitting control signal EM2. Therefore, the sixteenth transistor M16 and the seventeenth transistor M17 are turned on, and the second data voltage Vdata_t is transmitted to the gate of the fifteenth transistor M15 through the sixteenth transistor M16, the fifteenth transistor M15, and the seventeenth transistor M17, until the gate potential of the fifteenth transistor M15 is Vdata_t+Vth15, and the fifteenth transistor M15 is turned off, wherein Vth15 is the threshold voltage of the fifteenth transistor M15. A constant voltage difference is maintained across the first capacitor C1.

[0093] In this embodiment, during the threshold compensation of the fifteenth transistor M15, the twentieth transistor M20 is provided to improve the instability of the gate potential of the fifteenth transistor M15 due to the leakage of the sixth transistor M6, which is beneficial to improving the accuracy of the time control signal output by the time control module 10.

[0094] Phase t4 is the time period during which the voltage writing phase T1 is performed row by row for the remaining rows of sub-pixels, so as to complete the data writing of all the pixel rows.

[0095] In the reset phase T2, the third scan signal line is configured to transmit a high-level third scan signal S3, the fourth scan signal line is configured to transmit a high-level fourth scan signal S4, the fifth scan signal line is configured to transmit a high-level fifth scan signal S5, the reset signal line is configured to transmit a low-level reset signal Set, the first light-emitting control signal line is configured to transmit a high-level first light-emitting control signal EM1, and the second light-emitting control signal line is configured to transmit a high-level second light-emitting control signal EM2. Therefore, the fifth transistor M5 is turned on, the second initialization voltage Vinit2 on the second initialization signal line is transmitted to the N3 node via the fifth transistor M5, the third capacitor C3 and the fourth capacitor C4 maintain the potential of the N3 node, and the eighth transistor M8 is turned on.

[0096] In the light-emitting stage T3, the third scan signal line is configured to transmit a high-level third scan signal S3, the fourth scan signal line is configured to transmit a high-level fourth scan signal S4, the fifth scan signal line is configured to transmit a high-level fifth scan signal S5, the reset signal line is configured to transmit a high-level reset signal Set, the first light-emitting control signal line is configured to transmit a low-level first light-emitting control signal EM1, and the second light-emitting control signal line is configured to transmit a low-level second light-emitting control signal EM2. Therefore, the eleventh transistor M11, the twelfth transistor M12, the thirteenth transistor N13, the nineteenth transistor M19, and the twentieth transistor M20 are turned on, the first power supply voltage VDDA on the first power supply line L1 is transmitted to the first electrode of the seventh transistor M7, and the seventh transistor M7 generates a driving current under the control of its gate voltage to drive the light-emitting diode D1 to emit light.

[0097] At the same time, the sweep signal SWEEP gradually changes from a high level SWEEP-H to a low level SWEEP-L, and due to the coupling effect of the first capacitor C1, the potential of the gate of the fifteenth transistor M15 changes synchronously. When the potential of the gate of the fifteenth transistor M15 turns on the fifteenth transistor M15, the third power supply voltage VDDW is transmitted to the N1 node through the nineteenth transistor M19, the fifteenth transistor M15 and the twentieth transistor M20, and the first transistor M1 is controlled to turn on. The third power supply voltage VDDW is transmitted to the N2 node, and the third transistor M3 is turned on in response to the voltage of the N2 node. The width-to-length ratio of the third transistor M3 is greater than the width-to-length ratio of the fourth transistor M4, and the potential of the N3 node is dominated by the third transistor M3. The third transistor M3 transmits the third power supply voltage VDDW to the N3 node, thereby maintaining the potential of the N3 node at the off voltage of the current control module 20. Therefore, the eighth transistor M8 is turned off in response to the potential of the N3 node, the first electrode of the seventh transistor M7 is disconnected from the first power line L1, the driving current is zero, the light emitting diode D1 is extinguished, and the light emitting time is controlled. When the eighth transistor M8 is turned off, the fourth capacitor C4 can maintain the stability of the potential of the N3 node, so that the eighth transistor M8 is quickly turned off.

[0098] Optionally, an embodiment of the present invention further provides a driving method for a pixel circuit, and the driving method can be applied to the pixel circuit provided by any of the above technical solutions. Figure 1 Specifically, the driving method of the pixel circuit includes:

[0099] In the light-emitting stage, the current control module is controlled to drive the light-emitting module to emit light according to the first data voltage of its own control end, and the time control module is controlled to output a time control signal to the output end of the current control module according to the second data voltage and the sweep signal, and the potential holding module is controlled to keep the voltage of the control end of the current control module at the shutdown voltage according to the time control signal.

[0100] The driving method of the pixel circuit provided in the present embodiment connects a potential holding module in series between the output end of the time control module and the control end of the current control module, so that when the light-emitting module stops emitting light, the potential of the control end of the current control module can be quickly and stably maintained at the shutdown voltage, thereby maintaining the stability of the potential of the control end of the current control module, and being able to quickly shut down the current control module, effectively avoiding the phenomenon of unstable light emission, which is beneficial to improving the flickering or uneven display caused by the unstable output signal of the time control module when the pixel circuit is turned off, and is beneficial to improving the display effect.

[0101] An embodiment of the present invention further provides a display panel, the display panel comprising the pixel circuit provided by any embodiment of the present invention, Fig.15A schematic diagram of a display panel according to an embodiment of the present invention is provided. The display panel 200 can be Fig.15 The mobile phone panel shown can also be a display panel in electronic devices such as tablets, mobile phones, watches, wearable devices, and vehicle displays, camera displays, televisions, and computer screens. Since the display panel includes the pixel circuit provided by any embodiment of the present invention, the display panel provided by the embodiment of the present invention also has the beneficial effects described in any embodiment of the present invention.

[0102] It should be understood that the various forms of processes shown above can be used to reorder, add or delete steps. For example, the steps described in the present invention can be executed in parallel, sequentially or in different orders, as long as the desired results of the technical solution of the present invention can be achieved, and this document does not limit this.

[0103] The above specific implementations do not constitute a limitation on the protection scope of the present invention. It should be understood by those skilled in the art that various modifications, combinations, sub-combinations and substitutions can be made according to design requirements and other factors. Any modification, equivalent substitution and improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims

1. A pixel circuit, characterized in that: include: Time control module, current control module and light emitting module; The current control module and the light emitting module are connected between a first power line and a second power line, and the current control module is used to drive the light emitting module to emit light according to a first data voltage in a light emitting stage; The time control module is used to output a time control signal according to the second data voltage and the frequency sweep signal, so as to control the potential of the control terminal of the current control module; It also includes a potential holding module, the control end of the potential holding module is connected to the output end of the time control module, the output end of the potential holding module is connected to the control end of the current control module, and the potential holding module is used to keep the voltage of the control end of the current control module at the shutdown voltage according to the time control signal during the light-emitting stage.

2. The pixel circuit according to claim 1, characterized in that: The potential maintaining module includes a first switch unit, a second switch unit and a third switch unit; The control end of the first switch unit is connected to the output end of the time control module, the first end of the first switch unit is connected to the third power line, and the second end of the first switch unit is connected to the second end of the second switch unit; the first end of the second switch unit is connected to the first initialization signal line, and the control end of the second switch unit is connected to the output end of the time control module, or the control end of the second switch unit is connected to the first scan line; The control end of the third switch unit is connected to the second end of the first switch unit, the first end of the third switch unit is connected to the third power line, and the second end of the third switch unit is connected to the control end of the current control module; The third power line is used to transmit the shutdown voltage, and the third switch unit is used to transmit the shutdown voltage to the control end of the current control module in response to the potential of the second end of the first switch unit; Preferably, the first initialization signal line is multiplexed as the first scan line.

3. The pixel circuit according to claim 2, characterized in that: The first switch unit includes a first transistor, the second switch unit includes a second transistor, and the third switch unit includes a third transistor; The gate of the first transistor is the control end of the first switch unit, the first pole of the first transistor is the first end of the first switch unit, and the second pole of the first transistor is the second end of the first switch unit; the gate of the second transistor is the control end of the second switch unit, the first pole of the second transistor is the first end of the second switch unit, and the second pole of the second transistor is the second end of the second switch unit; the gate of the third transistor is the control end of the third switch unit, the first pole of the third transistor is the first end of the third switch unit, and the second pole of the third transistor is the second end of the third switch unit; Preferably, a width-to-length ratio of the first transistor is greater than a width-to-length ratio of the second transistor.

4. The pixel circuit according to claim 3, characterized in that: The potential holding module further includes a fourth switch unit, a control end of the fourth switch unit is connected to the second scan line, a first end of the fourth switch unit is connected to the first initialization signal line, and a second end of the fourth switch unit is connected to the control end of the current control module, and the fourth switch unit is used to transmit the first initialization voltage on the first initialization signal line to the control end of the current control module in response to the signal on the second scan line when the third switch unit is turned off; Preferably, the first initialization signal line is multiplexed as the second scan line; Preferably, the fourth switch unit includes a fourth transistor, the gate of the fourth transistor is the control end of the fourth switch unit, the first pole of the fourth transistor is the first end of the fourth switch unit, and the second pole of the fourth transistor is the second end of the fourth switch unit; the width-to-length ratio of the third transistor is greater than the width-to-length ratio of the fourth transistor.

5. The pixel circuit according to claim 2 or 4, characterized in that: The potential holding module further includes a reset unit, a control end of the reset unit is connected to a reset signal line, a first end of the reset unit is connected to a second initialization signal line, and a second end of the reset unit is connected to a control end of the current control module; Preferably, the first initialization signal line is multiplexed as the second initialization signal line.

6. The pixel circuit according to claim 5, characterized in that: The potential holding module further includes a first storage unit, a first end of the first storage unit is connected to the first initialization signal line, and a second end of the first storage unit is connected to the control end of the current control module; The potential holding module further includes a first initialization unit, a control end of the first initialization unit is connected to the third scan line, a first end of the first initialization unit is connected to the first initialization signal line, and a second end of the first initialization unit is connected to the control end of the first switch unit.

7. The pixel circuit according to claim 1, characterized in that: The current control module includes a first driving unit, a first data writing unit and a current control unit; The current control unit and the first driving unit are connected between the first power line and the first end of the light emitting module, the second end of the light emitting module is connected to the second power line, the first data writing unit is connected to the first driving unit, and the first data writing unit is used to write the first data voltage to the control end of the first driving unit; Preferably, the current control module further includes a first compensation unit, the first compensation unit is connected between the second end and the control end of the first driving unit, the first data writing unit is connected to the first end of the first driving unit, and the control end of the first data writing unit and the control end of the first compensation unit are both connected to the third scan line; Preferably, the current control module further includes a first light-emitting control unit, a second light-emitting control unit and a third light-emitting control unit, wherein a first end of the first light-emitting control unit is connected to the first power line, a second end of the first light-emitting control unit is connected to the first end of the current control unit, a first end of the second light-emitting control unit is connected to the second end of the current control unit, a second end of the second light-emitting control unit is connected to the first end of the first driving unit, a first end of the third light-emitting control unit is connected to the second end of the first driving unit, and a second end of the third light-emitting control unit is connected to the first end of the light-emitting module; a control end of the second light-emitting control unit and a control end of the third light-emitting control unit are both connected to the first light-emitting control signal line, and a control end of the first light-emitting control unit is connected to the second light-emitting control signal line; Preferably, the current control module further includes a second storage unit and a third storage unit, the second storage unit is connected between the control end of the first driving unit and the first power line, and the third storage unit is connected between the control end of the current control unit and the first power line; Preferably, the current control module further includes a second initialization unit, a first end of the second initialization unit is connected to the third initialization signal line, a second end of the second initialization unit is connected to the control end of the first driving unit, and the control end of the second initialization unit is connected to the fourth scan line.

8. The pixel circuit according to claim 1, characterized in that: The time control module includes a second driving unit, a second data writing unit, a third initialization unit and a coupling unit; The second driving unit is connected between the fourth power line and the control end of the potential holding module, and the second data writing unit is used to write the second data voltage to the control end of the second driving unit; the third initialization unit is connected between the fourth initialization signal line and the control end of the second driving unit, and the control end of the third initialization unit is connected to the third scan line; The coupling unit is connected to the control end of the second driving unit, and the coupling unit is used to control the potential of the control end of the second driving unit according to the sweep signal; Preferably, the time control module further comprises a second compensation unit, the second compensation unit is connected between the control end and the second end of the second driving unit, and the control end of the second compensation unit and the control end of the second data writing unit are both connected to the fifth scanning line; Preferably, the time control module also includes a fourth light-emitting control unit and a fifth light-emitting control unit, the control end of the fourth light-emitting control unit and the control end of the fifth light-emitting control unit are both connected to the second light-emitting control signal line, the first end of the fourth light-emitting control unit is connected to the fourth power line, the second end of the fourth light-emitting control unit is connected to the first end of the second driving unit, the first end of the fifth light-emitting control unit is connected to the second end of the second driving unit, and the second end of the fifth light-emitting control unit is connected to the control end of the potential holding module.

9. A method for driving a pixel circuit, characterized in that: The pixel circuit includes a time control module, a current control module and a light-emitting module, wherein the current control module and the light-emitting module are connected between a first power line and a second power line, and further includes a potential holding module, wherein a control end of the potential holding module is connected to an output end of the time control module, and an output end of the potential holding module is connected to a control end of the current control module; The driving method of the pixel circuit includes: In the light-emitting stage, the current control module is controlled to drive the light-emitting module to emit light according to the first data voltage at its own control end, and the time control module is controlled to output a time control signal to the output end of the current control module according to the second data voltage and the sweep signal, and the potential holding module is controlled to keep the voltage at the control end of the current control module at the shutdown voltage according to the time control signal.

10. A display panel, characterized in that: Comprising the pixel circuit as described in any one of claims 1-8.

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