Driver chip, display panel, and driving method of display panel

Abstract

This application discloses a driver chip, a display panel, and a driving method for the display panel. The driver chip includes a fast discharge circuit, which comprises an input port for receiving a fast discharge signal, a judgment sub-circuit, a buffer sub-circuit, and an electronic shutdown circuit. The judgment sub-circuit, responding to the falling edge of the fast discharge signal, generates a judgment signal based on a target signal within a preset time. The buffer sub-circuit, responding to the judgment signal, generates a control signal and sends it to the electronic shutdown circuit. The electronic shutdown circuit, responding to the control signal, controls the driver chip to perform or not perform a power-off operation. By setting a preset time as a buffer phase, and adding judgment conditions during the buffer phase, it is further determined whether the fast discharge signal is valid, thereby determining whether to perform a power-off operation.

Description

Technical Field

[0001] This application relates to the field of display technology, specifically to a driver chip, a display panel, and a driving method for the display panel. Background Technology

[0002] In-Plane Switching Panels (IPS Panels) have relatively stable total capacitance, resulting in good stability during driving, and are therefore widely used in the current display panel industry. However, IPS Panels discharge slowly when the driver chip is powered off, which can cause flickering or screen noise. By setting a fast discharge pin (XON pin) on the driver chip, the timing controller outputs a fast discharge signal (XON signal) to the driver chip. This allows all the output signals of the driving circuits to be short-circuited to the common voltage signal at the moment the driver chip is powered off, thus achieving rapid discharge of the panel. However, the presence of other interference on the XON pin can easily lead to malfunctions. Summary of the Invention

[0003] The embodiments of this application provide a driver chip, a display panel, and a driving method for the display panel, so as to at least solve the problem that malfunctions are likely to occur when there are other interferences on the XON pin.

[0004] In a first aspect, embodiments of this application provide a driver chip, including a fast discharge circuit. The fast discharge circuit includes: an access port configured to receive a fast discharge signal, wherein the fast discharge signal is used to indicate that the driver chip is powered off; a sensing sub-circuit connected to the access port and a power supply voltage, the sensing sub-circuit configured to sense the falling edge of the fast discharge signal; a buffer sub-circuit connected to the sensing sub-circuit, a judgment sub-circuit, and a power-off circuit, the buffer sub-circuit configured to, after the sensing sub-circuit senses the falling edge of the fast discharge signal, generate a control signal and send it to the power-off circuit within a preset time in response to a judgment signal output by the judgment sub-circuit; the judgment sub-circuit connected to the buffer sub-circuit configured to generate the judgment signal based on the state of a target signal within the preset time and send it to the buffer sub-circuit; and the power-off circuit connected to the buffer sub-circuit configured to control the driver chip to perform or not perform a power-off operation in response to the control signal.

[0005] In some embodiments, the judgment sub-circuit is further configured to: generate a first judgment signal and send it to the buffer sub-circuit in response to the rising edge of the target signal within the preset time period.

[0006] In some embodiments, the judgment sub-circuit is further configured to: generate the first judgment signal and send it to the buffer sub-circuit in response to the rising edge of the fast discharge signal within the preset time period; or generate the first judgment signal and send it to the buffer sub-circuit in response to the rising edge of the scan drive start pulse signal within the preset time period; wherein the scan drive start pulse signal is used to indicate the start of transmission of a frame image signal.

[0007] In some embodiments, the buffer sub-circuit is further configured to: generate a first control signal in response to the first judgment signal within the preset time period and send it to the power-off circuit; the power-off circuit is further configured to: control the driver chip not to perform a power-off operation in response to the first control signal.

[0008] In some embodiments, the judgment sub-circuit is further configured to: generate a second judgment signal and send it to the buffer sub-circuit in response to the continuous low-level state of the target signal within the preset time.

[0009] In some embodiments, the judgment sub-circuit is further configured to: generate the second judgment signal and send it to the buffer sub-circuit in response to the continuous low level state of the fast discharge signal within the preset time; or generate the second judgment signal and send it to the buffer sub-circuit in response to the continuous low level state of the scan drive start pulse signal within the preset time; wherein the scan drive start pulse signal is used to indicate the start of transmission of a frame image signal.

[0010] In some embodiments, the buffer sub-circuit is further configured to: generate a second control signal in response to the second judgment signal within the preset time period, and send it to the power-off circuit; the power-off circuit is further configured to: control the driver chip to perform a power-off operation in response to the second control signal.

[0011] In some embodiments, the driver chip is adapted to the CSPI transmission protocol.

[0012] Secondly, embodiments of this application also provide a display panel, including the driver chip described in any of the above embodiments.

[0013] Thirdly, embodiments of this application also provide a driving method for a display panel, applied to a driver chip. The driver chip includes a fast discharge circuit, which includes an input port for receiving a fast discharge signal, a judgment sub-circuit, a buffer sub-circuit, and an electronic power-off circuit. The method includes: the judgment sub-circuit responding to the falling edge of the fast discharge signal to generate a judgment signal based on a target signal within a preset time; the buffer sub-circuit responding to the judgment signal to generate a control signal and sending it to the electronic power-off circuit; and the electronic power-off circuit responding to the control signal to control the driver chip to perform or not perform a power-off operation.

[0014] In some embodiments, the judgment sub-circuit, in response to the falling edge of the fast discharge signal, generates a judgment signal based on the target signal within a preset time period, including: within the preset time period, in response to the rising edge of the target signal, generating a first judgment signal and sending it to the buffer sub-circuit.

[0015] In some embodiments, generating a first judgment signal and sending it to the buffer sub-circuit in response to the rising edge of the target signal within the preset time period includes: generating the first judgment signal and sending it to the buffer sub-circuit in response to the rising edge of the fast discharge signal within the preset time period; or generating the first judgment signal and sending it to the buffer sub-circuit in response to the rising edge of the scan drive start pulse signal within the preset time period; wherein the scan drive start pulse signal is used to indicate the start of transmission of a frame image signal.

[0016] In some embodiments, the method further includes: within the preset time period, the buffer sub-circuit generates a first control signal in response to the first judgment signal and sends it to the power-off circuit; the power-off circuit controls the driver chip not to perform a power-off operation in response to the first control signal.

[0017] In some embodiments, the judgment sub-circuit responds to the falling edge of the fast discharge signal and generates a judgment signal based on the target signal within a preset time period, including: within the preset time period, in response to the continuous low level state of the target signal, generating a second judgment signal and sending it to the buffer sub-circuit.

[0018] In some embodiments, generating a second judgment signal and sending it to the buffer sub-circuit in response to a continuous low-level state of the target signal within the preset time period includes: generating the second judgment signal and sending it to the buffer sub-circuit in response to a continuous low-level state of the fast discharge signal within the preset time period; or generating the second judgment signal and sending it to the buffer sub-circuit in response to a continuous low-level state of the scan drive start pulse signal within the preset time period; wherein the scan drive start pulse signal is used to indicate the start of transmission of a frame image signal.

[0019] In some embodiments, the method further includes: within the preset time period, the buffer sub-circuit generates a second control signal in response to the second judgment signal and sends it to the power-off circuit; the power-off circuit controls the driver chip to perform a power-off operation in response to the second control signal.

[0020] In some embodiments, the driving method is applicable to the CSPI transmission protocol.

[0021] The beneficial effects provided by the embodiments of this application include at least the following:

[0022] This application provides a driver chip, a display panel, and a driving method for the display panel. The driver chip includes a fast discharge circuit, which comprises an input port for receiving a fast discharge signal, a judgment sub-circuit, a buffer sub-circuit, and an electronic shutdown circuit. The judgment sub-circuit, responding to the falling edge of the fast discharge signal, generates a judgment signal based on a target signal within a preset time. The buffer sub-circuit, responding to the judgment signal, generates a control signal and sends it to the electronic shutdown circuit. The electronic shutdown circuit, responding to the control signal, controls the driver chip to perform or not perform a power-off operation. By setting a preset time as a buffer phase and adding a judgment condition during the buffer phase to further determine whether the fast discharge signal is valid, and thus determining whether to perform a power-off operation, this approach at least solves the problem of erroneous operation when there is interference on the XON pin, effectively improving the accuracy of fast power-off based on the XON signal.

[0023] Other beneficial effects of the embodiments of this application will be further explained in the following specific embodiments. Attached Figure Description

[0024] Figure 1 This is a schematic diagram of the structure of a display panel provided in an optional embodiment of this application;

[0025] Figure 2 This is a signal timing diagram provided in an optional embodiment of this application;

[0026] Figure 3This is a schematic diagram of the structure of a fast discharge circuit provided in an optional embodiment of this application;

[0027] Figure 4 This is an iSTB signal timing diagram provided in an optional embodiment of this application;

[0028] Figure 5 This is yet another iSTB signal timing diagram provided in an optional embodiment of this application;

[0029] Figure 6 This is an XON signal timing diagram provided in an optional embodiment of this application;

[0030] Figure 7 This is yet another XON signal timing diagram provided in an optional embodiment of this application;

[0031] Figure 8 This is a schematic flowchart of the display panel driving method provided in an optional embodiment of this application. Detailed Implementation

[0032] The technical solutions in the embodiments of this application will now be described with reference to the accompanying drawings. The described technical solutions are for illustrative purposes only and should not be construed as limiting the scope of protection of this application.

[0033] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the stated features. In the description of this application, "a plurality of" means two or more, unless otherwise explicitly specified.

[0034] In the description of this application, it should be noted that, unless otherwise expressly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection, an electrical connection, or a connection that allows communication between them; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication between two components or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in this application according to the specific circumstances.

[0035] The following disclosure provides many different embodiments or examples for implementing different structures of this application. To simplify the disclosure, specific examples of components and arrangements are described below. Of course, these are merely examples and are not intended to limit the scope of this application. Furthermore, reference numerals and / or letters may be repeated in different examples; such repetition is for simplification and clarity and does not in itself indicate a relationship between the various embodiments and / or arrangements discussed. In addition, various specific examples of processes and materials are provided in this application, but those skilled in the art will recognize the application of other processes and / or the use of other materials.

[0036] In describing some embodiments, the terms "coupled" and "connected," and their derivative expressions, may be used. For example, the term "connected" may be used in describing some embodiments to indicate that two or more components have direct physical or electrical contact with each other. Similarly, the term "coupled" may be used in describing some embodiments to indicate that two or more components have direct physical or electrical contact. However, the terms "coupled" or "communicatively coupled" may also refer to two or more components that do not have direct contact with each other but still cooperate or interact with each other. The embodiments disclosed herein are not necessarily limited to the embodiments of this application.

[0037] The various embodiments provided in this application are similar, and features in different embodiments can be combined with each other.

[0038] The use of “configured to” in this application embodiment implies an open and inclusive language, which does not exclude the applicability to or configuration of devices to perform additional tasks or steps.

[0039] The order in which the following embodiments are described is not intended to limit the preferred order of the embodiments.

[0040] Reference Figure 1As shown, this application embodiment provides a display panel 1000, which can be integrated into a display device, such as a television, smartphone, tablet computer, laptop computer, desktop computer, smart speaker, smartwatch, etc., but is not limited thereto. A display panel refers to a component used to display images, which may include many pixel units, each of which can emit light, display color, or reflect light to generate an image. The type of display panel can be set according to actual conditions; for example, the display panel can be a Liquid Crystal Display (LCD), an Organic Light-Emitting Diode (OLED) panel, a Mini-LED panel, or a Micro-LED panel. This application embodiment does not limit this specific type. The pixel units included in the display panel can exist in a row and / or column form.

[0041] The display panel 1000 includes an effective display area AA and a peripheral area NA surrounding the effective display area AA. A circuit board 1100 is disposed in the peripheral area of ​​the display panel 1000 to provide clock signals to the circuitry inside the display panel 1000. The effective display area AA includes a plurality of sub-pixels 1500. For ease of explanation, the plurality of sub-pixels 1500 are described in this application as arranged in a matrix. In this case, sub-pixels arranged in a row along the first direction (X direction) are called a row of sub-pixels, and sub-pixels arranged in a row along the second direction (Y direction) are called a column of sub-pixels. A row of sub-pixels can be connected to a gate signal line GL and a light emission control signal line EM, and a column of sub-pixels can be connected to a data line DL. The X direction and the Y direction intersect perpendicularly.

[0042] Each subpixel 1500 may include a pixel driving circuit 1510 and a light-emitting device 1520. The light-emitting device 1520 may emit at least three primary colors, such as red (R), green (G), and blue (B) light.

[0043] The display panel 1000 also includes a gate driving circuit 1200, a data driving circuit 1300, and a light-emitting control circuit 1400 disposed in the NA area. The gate driving circuit 1200 includes multiple cascaded gate driving sub-circuits 1210, and the light-emitting control circuit 1400 includes multiple cascaded light-emitting control sub-circuits 1410. Each column of sub-pixels is connected to the data driving circuit 1300 via at least one DL (vertical line), each row of sub-pixels is connected to at least one gate driving sub-circuit 1210 via at least one GL (vertical line), and each row of sub-pixels is connected to at least one light-emitting control sub-circuit 1410 via at least one EM (electrical line). It should be noted that, depending on the specific circuit application, a row of sub-pixels can be connected to two or three or more gate driving sub-circuits via two or three or more GLs, and a row of sub-pixels can be connected to two or three or more light-emitting control sub-circuits via two or three or more EMs. Figure 1 The example described uses only one signal line and is not intended to limit the scope of this application.

[0044] In some embodiments, the light-emitting device 1520 can be an organic light-emitting diode (OLED), and its luminous efficiency is positively correlated with the magnitude or current density of the current flowing through it. That is, when the current flowing through the light-emitting device 1520 is small, its luminous efficiency is low; when the current flowing through it is large, its luminous efficiency is high. To improve the luminous efficiency of the light-emitting device 1520 when displaying low grayscale, the emission time of the light-emitting device 1520 can be modulated using the emission control signal EM, i.e., pulse width modulation (PWM), to change the emission duty cycle of the light-emitting device 1520 within a frame, thereby shortening its emission time. By shortening the emission time of the light-emitting device 1520 and increasing the current flowing through it during emission, the luminous efficiency of the light-emitting device 1520 can be improved.

[0045] The pixel driving circuit 1510, gate driving circuit 1200, and data driving circuit 1300 in this embodiment can be implemented using any circuit in the art capable of performing the corresponding functions, and will not be described in detail here. It should be noted that the gate driving circuit 1200 and data driving circuit 1300 can both be integrated on the driver chip.

[0046] Because IPS panels discharge slowly when powered off, there may be visible flickering or screen noise. To address this issue, an XON input pin is provided on the driver chip to receive the XON signal. (See reference...) Figure 2As shown, during the period without data signal input, all data output signals Y1 to Yn are connected to the common voltage signal Vcom. Under normal operating conditions, XON is at a high potential, and the Yn signal changes periodically. When power is cut off and data input is not received, a falling edge appears on the XON signal, and all data output signals are shorted to Vcom and connected to a preset low potential (usually VSS or GND). In general or experimental situations, when noise or interference occurs on the XON pin, the XON pin will perceive it as a falling edge, thus causing malfunction. For example, the phenomenon of the driver chip suddenly losing power during electrostatic discharge (ESD) evaluation, or during other evaluation tests. This malfunction is caused by the XON pin perceiving the driver chip's GND jitter or external signal noise as a falling edge.

[0047] To address the aforementioned problems, one embodiment of this application provides a driver chip, including a fast discharge circuit 100. (See also...) Figure 3 As shown, the fast discharge circuit 100 includes an access port 110, a sensing sub-circuit 120, a buffer sub-circuit 130, a judgment sub-circuit 140, and an electronic disconnection circuit 150.

[0048] The system includes: an access port 110 configured to receive an XON signal; a sensing sub-circuit 120 connected to the access port 110 and the power supply voltage VDD, configured to sense the falling edge of a fast discharge signal; a buffer sub-circuit 130 connected to the sensing sub-circuit 120, the judgment sub-circuit 140, and the power-off circuit 150, configured to generate a control signal and send it to the power-off circuit 150 within a preset time T in response to the judgment signal output by the judgment sub-circuit 140 after the sensing sub-circuit 120 senses the falling edge of the fast discharge signal; the judgment sub-circuit 140 connected to the buffer sub-circuit 130 configured to generate a judgment signal based on the state of the target signal within a preset time and send it to the buffer sub-circuit 130; and the power-off circuit 150 connected to the buffer sub-circuit 130 configured to control the driver chip to perform or not perform a power-off operation in response to the control signal.

[0049] By determining the response of the sub-circuit to the falling edge of the fast discharge signal, a judgment signal is generated based on the target signal within a preset time. The buffer sub-circuit, responding to the judgment signal, generates a control signal and sends it to the power-off circuit. The power-off circuit, in response to the control signal, controls the driver chip to perform or not perform a power-off operation. By setting a preset time as a buffer phase, and adding judgment conditions during the buffer phase to further determine whether it is a valid fast discharge signal, and thus determining whether to perform a power-off operation, this approach at least solves the problem of erroneous operation when there is other interference on the XON pin, effectively improving the accuracy of performing fast power-off based on the XON signal.

[0050] In some embodiments, the judgment sub-circuit 140 is further configured to: generate a first judgment signal and send it to the buffer sub-circuit 130 in response to the rising edge of the target signal within a preset time. The preset time here can be a time longer than one frame, for example, one frame, two frames, three frames, or 1.5 frames, 2.5 frames. This application embodiment does not limit this.

[0051] In some embodiments, the buffer sub-circuit 130 is further configured to: acquire a first judgment signal output by the judgment sub-circuit 140 within a preset buffer time; generate a first control signal in response to the first judgment signal and send it to the power-off circuit 150; the power-off circuit 150 is further configured to: control the driver chip not to perform a power-off operation in response to the first control signal.

[0052] The target signal can be a Scan Driver Start Pulse (STB or STV), used to indicate the start of a frame of image signal transmission. The STB signal is generally used in the new high-speed point-to-point interface transmission (China Standard Point-to-Point Interface, CSPI) protocol to mark the start of each frame of signal transmission. The iSTB (Internal STB function) is an internal signal of the CSPI driver chip used to inform the CSPI protocol of the start of a frame. The target signal can also be an XON signal, which will be described in detail in subsequent embodiments.

[0053] In some embodiments, the judgment sub-circuit 140 is further configured to: generate a first judgment signal and send it to the buffer sub-circuit 130 in response to the rising edge of the fast discharge signal within a preset time; or, generate a first judgment signal and send it to the buffer sub-circuit in response to the rising edge of the scan drive start pulse signal within a preset time; wherein the scan drive start pulse signal is used to indicate that a frame of image signal has started to be transmitted.

[0054] Reference Figure 4 As shown, when the target signal is an iSTB signal, within the preset buffer time, it is determined whether the iSTB signal has a rising edge, that is, whether there is a new frame signal input. If a rising edge occurs, the judgment sub-circuit 140 generates a first judgment signal and sends it to the buffer sub-circuit 130. The buffer sub-circuit 130 resets the XON signal and restores it to a high potential, so that the electronic circuit does not perform a power-off operation.

[0055] Reference Figure 6As shown, when the target signal is the XON signal, within the preset buffer time, it is determined whether the XON signal has a rising edge, that is, whether there is a new frame signal input. If a rising edge occurs, the judgment sub-circuit 140 generates the first judgment signal and sends it to the buffer sub-circuit 130. The buffer sub-circuit 130 resets the XON signal and restores it to a high potential, so that the electronic circuit does not perform the power-off operation.

[0056] In some embodiments, the judgment sub-circuit 140 is further configured to: generate a second judgment signal and send it to the buffer sub-circuit in response to the continuous low level state of the fast discharge signal within a preset time; or, generate a second judgment signal and send it to the buffer sub-circuit in response to the continuous low level state of the scan drive start pulse signal within a preset time; wherein the scan drive start pulse signal is used to indicate the start of transmission of a frame image signal.

[0057] When the target signal is an iSTB signal, within the preset buffer time, it is determined whether the iSTB signal has a rising edge, that is, whether there is a new frame signal input. If no rising edge appears, it remains in a low level state. The judgment sub-circuit 140 generates a second judgment signal and sends it to the buffer sub-circuit 130. The buffer sub-circuit 130 sends a second control signal to make the power-off circuit perform a power-off operation.

[0058] When the target signal is the XON signal, within the preset buffer time, it is determined whether the XON signal has a rising edge, that is, whether a new frame signal is input. If no rising edge appears, it remains in a low level state. The judgment sub-circuit 140 generates a second judgment signal and sends it to the buffer sub-circuit 130. The buffer sub-circuit 130 sends a second control signal to make the power-off circuit perform a power-off operation.

[0059] The following example illustrates the concept of an iSTB signal as the target signal. (Refer to...) Figure 4 As shown, when the XON signal experiences a falling edge, a preset buffer time T is set to prevent immediate power-off upon the XON signal's falling edge, i.e., to prevent all data output signals from being immediately short-circuited to Vcom upon the XON signal's falling edge. This preset time T is greater than the transmission time of one frame of display data; for example, it could be the transmission time of 1, 2, 3, 1.5, or 2.5 frames of display data. This embodiment does not limit this. Within the preset buffer time T, it is determined whether the iSTB signal experiences a rising edge, i.e., whether a new frame signal is input. If a rising edge occurs, the buffer sub-circuit resets the XON signal to a high potential, and the data output signals are not short-circuited to Vcom, thus preventing the power-off circuit from performing a power-off operation. For example... Figure 4 As shown, a rising edge of iSTB occurred within the preset time T, so no power-off operation was performed, and the driver chip continued to work normally.

[0060] Reference Figure 5 As shown, in the CSPI data transmission protocol, the rising edge of each iSTB marks the start of the next frame. During data frame transmission, the Lock signal remains high to ensure the display panel can receive data normally. Here, BK (Blanking Time) represents the blank information (invalid information) of each frame during data transmission, BAC (Begin active command) indicates the start of execution of various signal commands in a frame, POL (Polarity) is used to confirm the polarity of the data in this frame, and EOL (End Command) indicates the end command signal. (Refer to...) Figure 5 As shown, the first three frames are initialization information, the fourth frame transmits the first column of data information, i.e., 1st line data, and so on, with the next frame being the 2nd line data.

[0061] In some embodiments, the target signal can be the fast discharge signal XON. If the XON pin is falsely triggered, the XON signal can automatically recover to a high level within a preset time T.

[0062] The following example illustrates the concept of a target signal being an XON signal. (Refer to...) Figure 6 As shown, a buffering function is added when the XON pin input falls, which can be a preset buffering time. This preset time T can be greater than one frame, for example, 1 frame, 2 frames, 3 frames, or 1.5 frames, 2.5 frames. This embodiment does not limit this. It prevents immediate power-off upon the falling edge of the XON input, i.e., immediately shorting all data output signals to Vcom. Within the preset buffering time, it determines whether a rising edge appears on the XON signal, i.e., whether a new frame signal is input. If a rising edge appears, all data output signals are not shorted to Vcom, thus preventing the electronic circuit from performing a power-off operation. For example... Figure 6 As shown, a rising edge of XON appeared within the preset time T, so no power-off operation was performed, and the driver chip continued to work normally.

[0063] Reference Figure 7 As shown, within the preset buffer time, it is determined whether a rising edge appears on the XON signal, i.e., whether a new frame of signal input is available. If a rising edge appears on the XON signal, the data output signal is not shorted to Vcom, thus the electronic circuit does not perform a power-off operation. If no rising edge appears on the XON signal, the XON signal is considered valid, and a power-off operation is performed. For example... Figure 7 As shown, no rising edge of XON appeared within the preset time T, ruling out the possibility of XON being falsely triggered, and the power-off operation was determined to be performed.

[0064] In some embodiments, the fast discharge circuit further includes an electrostatic discharge (ESD) protection sub-circuit 160 connected to the access port 110 and the sensing sub-circuit 120, wherein the ESD protection sub-circuit 160 is configured to perform ESD discharge on the driver chip.

[0065] In some embodiments, the electrostatic discharge protection sub-circuit 160 includes: a diode, including a positive terminal connected to a preset low potential and a negative terminal connected to the access port 110 and the sensing sub-circuit 120; and a MOSFET, including a control terminal connected to a preset low potential, a first terminal connected to a preset low potential, and a second terminal connected to the access port 110 and the sensing sub-circuit 120.

[0066] It should be noted that the transistors used in all embodiments of this application may be thin film transistors (TFTs), metal oscillating transistors (MOSs), or other devices with the same characteristics. This application does not limit the types of transistors used.

[0067] For example, the transistor can be a TFT. TFTs can be fabricated using a-Si technology, oxide semiconductor technology, low-temperature polysilicon (LTPS) technology, or high-temperature polysilicon (HTPS) technology. The embodiments of this application do not limit this.

[0068] The embodiments of this application do not limit the type of transistor. The transistor can be an N-type transistor, a P-type transistor, an enhancement-mode transistor, or a depletion-mode transistor. In the embodiments of this application, all transistors are assumed to be P-type transistors for illustrative purposes. A P-type transistor is turned on under a low-level voltage signal and turned off under a high-level voltage signal; that is, the operating voltage of a P-type transistor is a low-level voltage, and the turn-off voltage is a high-level voltage.

[0069] In the embodiments of this application, the gate of the transistor is the control electrode. To distinguish the two electrodes of the transistor other than the gate, one electrode is directly described as the first electrode, and the other as the second electrode. In this case, the first electrode of the transistor can be either the source or the drain, and the second electrode can be either the source or the drain. Since the source and drain of a transistor can be structurally symmetrical, they can be structurally indistinguishable.

[0070] In some embodiments, the power-off circuit 150 includes: a latch unit 151 configured to generate a latch signal in response to a control signal and send it to a power-off unit 152; and a power-off unit 152 configured to perform or not perform a power-off operation in response to the latch signal.

[0071] This application also provides a display panel, including the driver chip described in any of the above embodiments, and the contents already stated will not be repeated here.

[0072] This application also provides a driving method for a display panel, applied to a driver chip. The driver chip includes a fast discharge circuit, which includes an input port for receiving a fast discharge signal, a judgment sub-circuit, a buffer sub-circuit, and an electron-disconnecting circuit. This driving method can be applied to the driver chip described in any of the above embodiments; details already described will not be repeated here. (Refer to...) Figure 8 As shown, the method includes:

[0073] Step S801: Determine the sub-circuit's response to the falling edge of the fast discharge signal, and generate a judgment signal based on the target signal within a preset time.

[0074] In step S802, the buffer sub-circuit, in response to the judgment signal, generates a control signal and sends it to the disconnect circuit; and

[0075] In step S803, the electronic circuit responds to the control signal to control the driver chip to perform or not perform a power-off operation.

[0076] In some embodiments, the judgment sub-circuit generates a judgment signal based on the target signal within a preset time period in response to the falling edge of the fast discharge signal, including: generating a first judgment signal and sending it to the buffer sub-circuit within the preset time period in response to the rising edge of the target signal.

[0077] In some embodiments, within a preset time period, in response to the rising edge of the target signal, a first judgment signal is generated and sent to the buffer sub-circuit, including: within a preset time period, in response to the rising edge of the fast discharge signal, generating the first judgment signal and sending it to the buffer sub-circuit; or within a preset time period, in response to the rising edge of the scan drive start pulse signal, generating the first judgment signal and sending it to the buffer sub-circuit; wherein, the scan drive start pulse signal is used to indicate that a frame of image signal has started transmission.

[0078] In some embodiments, the above-described display panel driving method further includes: within a preset time period, a buffer sub-circuit generates a first control signal in response to a first judgment signal and sends it to an electronic disconnection circuit; the electronic disconnection circuit controls the driving chip not to perform a power-off operation in response to the first control signal.

[0079] In some embodiments, the judgment sub-circuit responds to the falling edge of the fast discharge signal and generates a judgment signal based on the target signal within a preset time, including: within the preset time, responding to the continuous low level state of the target signal, generating a second judgment signal and sending it to the buffer sub-circuit.

[0080] In some embodiments, within a preset time period, in response to a continuous low-level state of the target signal, a second judgment signal is generated and sent to the buffer sub-circuit, including: within a preset time period, in response to a continuous low-level state of the fast discharge signal, generating a second judgment signal and sending it to the buffer sub-circuit; or within a preset time period, in response to a continuous low-level state of the scan drive start pulse signal, generating a second judgment signal and sending it to the buffer sub-circuit; wherein, the scan drive start pulse signal is used to indicate the start of transmission of a frame image signal.

[0081] In some embodiments, the method further includes: within a preset time period, a buffer sub-circuit generates a second control signal in response to a second judgment signal and sends it to an electronic disconnection circuit; the electronic disconnection circuit controls the driver chip to perform a power-off operation in response to the second control signal.

[0082] In some embodiments, this driving method is applicable to the CSPI transport protocol.

[0083] In this embodiment, a preset time is set as a buffer stage, and a judgment condition is added during the buffer stage to further determine whether it is a valid fast discharge signal, and then determine whether to perform a power-off operation. This can at least solve the problem that misoperation is easy to occur when there are other interferences on the XON pin, and effectively improve the accuracy of performing fast power-off based on the XON signal.

[0084] This application also provides a non-transitory computer-readable storage medium storing a computer program thereon, which, when executed by a processor, implements the steps of the above-described display panel driving method. This non-transitory computer-readable storage medium possesses all the beneficial effects of the above-described display panel driving method, which will not be elaborated upon further herein.

[0085] This application also provides an electronic device, including a memory and a processor. The memory stores a computer program; the processor executes the computer program in the memory to implement the steps of the above-described display panel driving method. This electronic device has all the beneficial effects of the above-described display panel driving method, which will not be elaborated further here.

[0086] Computer-readable storage media can be, for example, electrical, magnetic, optical, electromagnetic, infrared, or semiconductor systems, apparatuses, or devices, or any combination thereof, without particular limitation herein. More specific examples of computer-readable storage media may include, but are not limited to: electrical connections having one or more wires, portable computer disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fiber, portable compact disk read-only memory (CD-ROM), optical storage devices, magnetic storage devices, or any suitable combination thereof.

[0087] In some embodiments of this application, a computer-readable storage medium may be any tangible medium that contains or stores a program that may be used or combined with an instruction execution system, apparatus, or device.

[0088] The aforementioned computer-readable storage medium may be included in the aforementioned electronic device or may exist independently without being assembled into the electronic device.

[0089] Computer program code for performing operations of some embodiments of this application can be written in one or more programming languages ​​or a combination thereof. These programming languages ​​include object-oriented programming languages ​​such as Java, Smalltalk, and C++, as well as conventional procedural programming languages ​​such as the "C" language or similar programming languages. The program code can be executed entirely on the user's computer, partially on the user's computer, as a standalone software package, partially on the user's computer and partially on a remote computer, or entirely on a remote computer or server. In cases involving remote computers, the remote computer can be connected to the user's computer via any type of network (including a local area network (LAN) or a wide area network (WAN)), or it can be connected to an external computer (e.g., via the Internet using an Internet service provider).

[0090] The flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of this application. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of code containing one or more executable instructions for implementing a specified logical function.

[0091] It should also be noted that in some alternative implementations, the functions marked in the box may occur in a different order than those marked in the attached figures.

[0092] This application uses specific examples to illustrate the principles and implementation methods of this application. The description of the above embodiments is only for the purpose of helping to understand the method and core ideas of this application. At the same time, for those skilled in the art, there will be changes in the specific implementation methods and application scope based on the ideas of this application. Therefore, the content of this specification should not be construed as a limitation of this application.

[0093] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A driver chip, characterized in that, The driver chip includes a fast discharge circuit, which includes: The access port is configured to receive a fast discharge signal; wherein the fast discharge signal is used to indicate that the driver chip is powered off. A sensing sub-circuit is connected to the access port and the power supply voltage, and the sensing sub-circuit is configured to sense the falling edge of the fast discharge signal; A buffer sub-circuit is connected to the sensing sub-circuit, the judgment sub-circuit, and the electron disconnection circuit. The buffer sub-circuit is configured to generate a control signal and send it to the electron disconnection circuit within a preset time after the sensing sub-circuit senses the falling edge of the fast discharge signal and responds to the judgment signal output by the judgment sub-circuit. The judgment sub-circuit, connected to the buffer sub-circuit, is configured to generate the judgment signal based on the state of the target signal within a preset time period, and send it to the buffer sub-circuit; and The power-off circuit is connected to the buffer sub-circuit and is configured to control the driver chip to perform or not perform a power-off operation in response to the control signal. The target signal is either a rapid discharge signal or a scan drive start pulse signal.

2. The driver chip according to claim 1, characterized in that, The judgment sub-circuit is further configured as follows: Within the preset time period, in response to the rising edge of the fast discharge signal, a first judgment signal is generated and sent to the buffer sub-circuit; or Within the preset time period, in response to the rising edge of the scan drive start pulse signal, the first judgment signal is generated and sent to the buffer sub-circuit; wherein, the scan drive start pulse signal is used to indicate the start of transmission of a frame image signal.

3. The driver chip according to claim 2, characterized in that, The buffer sub-circuit is further configured to: Within the preset time period, a first control signal is generated in response to the first judgment signal and sent to the electronic circuit. The electronic circuit is also configured as follows: In response to the first control signal, the driver chip is controlled not to perform a power-off operation.

4. The driver chip according to claim 1, characterized in that, The judgment sub-circuit is further configured as follows: Within the preset time period, in response to the continuous low-level state of the rapid discharge signal, a second judgment signal is generated and sent to the buffer sub-circuit; or Within the preset time period, in response to the continuous low level state of the scan drive start pulse signal, the second judgment signal is generated and sent to the buffer sub-circuit; wherein, the scan drive start pulse signal is used to indicate the start of transmission of a frame image signal.

5. The driver chip according to claim 4, characterized in that, The buffer sub-circuit is further configured to: Within the preset time period, a second control signal is generated in response to the second judgment signal and sent to the electronic circuit. The electronic circuit is also configured as follows: In response to the second control signal, the driver chip is controlled to perform a power-off operation.

6. The driver chip according to claim 1, characterized in that, The driver chip is compatible with the CSPI transmission protocol.

7. A display panel, characterized in that, Includes the driver chip as described in any one of claims 1 to 6.

8. A driving method for a display panel, characterized in that, Applied to a driver chip, the driver chip includes a fast discharge circuit, the fast discharge circuit includes an input port for receiving a fast discharge signal, a judgment sub-circuit, a buffer sub-circuit, and an electron-disconnecting circuit, the method includes: The judgment sub-circuit responds to the falling edge of the fast discharge signal and generates a judgment signal based on the target signal within a preset time. The buffer sub-circuit responds to the judgment signal, generates a control signal, and sends it to the electronic disconnection circuit; and The power-off circuit responds to the control signal to control the driver chip to perform or not perform a power-off operation; The target signal is either a rapid discharge signal or a scan drive start pulse signal.

9. The driving method for a display panel according to claim 8, characterized in that, The step of generating a judgment signal based on the target signal within a preset time period includes: Within the preset time period, in response to the rising edge of the fast discharge signal, a first judgment signal is generated and sent to the buffer sub-circuit; or Within the preset time period, in response to the rising edge of the scan drive start pulse signal, the first judgment signal is generated and sent to the buffer sub-circuit; wherein, the scan drive start pulse signal is used to indicate the start of transmission of a frame image signal.

10. The driving method for a display panel according to claim 9, characterized in that, The method further includes: Within the preset time period, the buffer sub-circuit generates a first control signal in response to the first judgment signal and sends it to the electronic disconnection circuit; The power-off circuit responds to the first control signal by controlling the driver chip not to perform a power-off operation.

11. The driving method for a display panel according to claim 8, characterized in that, The step of generating a judgment signal based on the target signal within a preset time period includes: Within the preset time period, in response to the continuous low-level state of the rapid discharge signal, a second judgment signal is generated and sent to the buffer sub-circuit; or Within the preset time period, in response to the continuous low level state of the scan drive start pulse signal, the second judgment signal is generated and sent to the buffer sub-circuit; wherein, the scan drive start pulse signal is used to indicate the start of transmission of a frame image signal.

12. The driving method for a display panel according to claim 11, characterized in that, The method further includes: Within the preset time period, the buffer sub-circuit generates a second control signal in response to the second judgment signal and sends it to the electronic disconnection circuit; The power-off circuit responds to the second control signal by controlling the driver chip to perform a power-off operation.

13. The driving method for a display panel according to claim 8, characterized in that, The driving method described is applicable to the CSPI transmission protocol.

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