Driving compensation circuit, driving circuit, display panel and display device

Abstract

The invention provides a driving compensation circuit, a driving circuit, a display panel and a display device. Relates to the technical field of display, the drive compensation circuit comprises a high level signal end, a plurality of drive signal ends and a first sub-circuit, the drive signal ends are used for transmitting drive signals, and the drive signals comprise a first drive signal and a second drive signal; the first sub-circuit is electrically connected with a high-level signal end, a first driving signal end and a second driving signal end, and the first sub-circuit is used for being switched on or switched off under the action of a first driving signal and a second driving signal; when the first sub-circuit is in a conducting state, a high-level signal received by the high-level signal end is transmitted to the first driving signal end, and the potential of the first driving signal end is the high-level signal. The high-level signal is used for compensating the attenuation of the first driving signal, so that the abnormal problem caused by insufficient opening degree of the thin film transistor device due to the attenuation of the first driving signal is avoided, and the display effect can be improved.

Description

Technical Field

[0001] The present invention relates to the field of display technology, and more specifically, to a driving compensation circuit, a driving circuit, a display panel and a display device. Background Art

[0002] Generally, for the pixel circuit in the display device, multiple driving signals are required for driving control. In order to generate these driving signals that are turned on / off in sequence, GOA (Gate On Array) circuits are set on both sides of the AA (Active Area) area. The gate signal (Gate) that the GOA circuit can provide to the pixel circuit can control the state of, for example, a TFT (Thin Film Transistor). For a normal Gate signal, signal attenuation may occur during the transmission process to the TFT gate, thereby affecting the opening degree of the TFT, resulting in abnormal display of the display panel and affecting the display effect.

[0003] Therefore, a new technical solution is urgently needed to solve the above technical problems. Summary of the invention

[0004] A series of simplified concepts are introduced in the Summary of the Invention, which will be further described in detail in the Detailed Description of the Invention. The Summary of the Invention does not mean to attempt to define the key features and essential technical features of the claimed technical solution, nor does it mean to attempt to determine the scope of protection of the claimed technical solution.

[0005] In a first aspect, the present invention provides a driving compensation circuit, which is applied to a display panel. The display panel includes a pixel circuit. The driving compensation circuit includes:

[0006] A high-level signal terminal, a plurality of drive signal terminals and a first sub-circuit, the drive signal terminal is used to transmit a drive signal, different drive signals are used to drive the operation of different pixel circuits, the drive signal includes a first drive signal and a second drive signal, and the second drive signal drives the pixel circuit before the first drive signal drives the pixel circuit;

[0007] The driving signal terminal includes a first driving signal terminal and a second driving signal terminal, the first driving signal terminal is used to transmit a first driving signal, the second driving signal terminal is used to transmit a second driving signal, and the first driving signal terminal is used to electrically connect to a corresponding driven pixel circuit;

[0008] The first sub-circuit is electrically connected to the high-level signal terminal, the first drive signal terminal and the second drive signal terminal respectively, and the first sub-circuit is used to be turned on or off under the action of the first drive signal and the second drive signal;

[0009] When the first sub-circuit is turned on, the high-level signal received by the high-level signal terminal is transmitted to the first drive signal terminal, and the potential of the first drive signal terminal is a high-level signal.

[0010] In some embodiments, a first capacitor and a second capacitor are further included, and the first sub-circuit includes a first transistor;

[0011] The first end of the first capacitor is electrically connected to the second drive signal end, the second end of the first capacitor is electrically connected to the gate of the first transistor via the first node, the first end of the second capacitor is electrically connected to the first drive signal end, the second end of the second capacitor is electrically connected to the first node, the first electrode of the first transistor is electrically connected to the high level signal end, and the second electrode of the first transistor is electrically connected to the first drive signal end, wherein the first electrode is one of the source and the drain of the first transistor, and the second electrode is the other of the source and the drain of the first transistor.

[0012] In some implementations, the drive compensation circuit further includes:

[0013] a second sub-circuit, wherein a first end of the second sub-circuit is electrically connected to the first node, a second end of the second sub-circuit is electrically connected to a third drive signal end among the plurality of drive signal ends, the second sub-circuit is configured to be turned on or off under the action of a third drive signal, the third drive signal end is configured to transmit a third drive signal, and a driving time of the third drive signal on the pixel circuit is later than a driving time of the first drive signal on the pixel circuit;

[0014] When the second sub-circuit is in an on state, the first driving signal is transmitted to the first capacitor.

[0015] In some embodiments, the second subcircuit includes a second transistor, a gate of the second transistor is electrically connected to the third drive signal terminal, a first electrode of the second transistor is electrically connected to the first node, a second electrode of the second transistor is electrically connected to the first drive signal terminal via the second node, a first end of the second capacitor is electrically connected to the first node, and a second end of the second capacitor is electrically connected to the second node.

[0016] In some embodiments, the driving compensation circuit includes N stages, the second sub-circuit in the N-th stage driving compensation circuit is electrically connected to the reset signal terminal, the second sub-circuit in the N-th stage driving compensation circuit is used to be turned on or off under the action of the reset signal, and the reset signal terminal is used to transmit the reset signal, wherein N is a natural number greater than 0;

[0017] The first driving signal corresponding to the n-th level driving compensation circuit is used to drive the pixel circuit of the n-th row, the second driving signal corresponding to the n-th level driving compensation circuit is used to drive the pixel circuit of the n-1-th row, and the third driving signal corresponding to the n-th level driving compensation circuit is used to drive the pixel circuit of the n+x-th row, where n and x are natural numbers greater than 0, and n+x≤N.

[0018] In a second aspect, a driving circuit is also proposed, comprising:

[0019] a plurality of driving sub-circuits;

[0020] As for the driving compensation circuit as above, the driving compensation circuit is electrically connected to the driving sub-circuit, and the multiple driving sub-circuits are used to provide multiple driving signals to the driving compensation circuit, and different driving signals are output by different driving sub-circuits.

[0021] In some embodiments, the driving compensation circuit and the driving sub-circuit are connected via a driving signal line, and the driving signal line is used to be electrically connected to the pixel circuit.

[0022] In some implementations, a voltage value of the first driving signal output from the driving sub-circuit transmitted to the first driving signal terminal via the driving signal line is smaller than a voltage value of the high-level signal.

[0023] In some embodiments, the effective level start point of the first driving signal is before the effective level end point of the second driving signal, and the effective level end point of the first driving signal is after the effective level end point of the second driving signal.

[0024] In some embodiments, the effective level end point of the second drive signal is located at the first position moment of the effective level of the first drive signal, the duration of the effective level of the first drive signal before the first position moment is the first duration, and the duration of the effective level of the first drive signal after the first moment position is the second duration.

[0025] In some embodiments, the sum of the first duration and the second duration is a third duration, the ratio of the third duration to the scanning duration of a row of pixel circuits is a first value, and the number of clock signals in the driving circuit is twice the first value.

[0026] In some implementations, the effective level start point of the third driving signal is the effective level end point of the first driving signal.

[0027] In a third aspect, a display panel is also proposed, comprising:

[0028] a plurality of pixel circuits;

[0029] As the driving circuit above, the driving circuit is electrically connected to the pixel circuit.

[0030] In some embodiments, comprising:

[0031] A display area, wherein the display area is provided with a plurality of pixel circuits arranged in rows and columns;

[0032] The driving sub-circuit is arranged on one side of the display area, and the driving compensation circuit electrically connected to the driving sub-circuit is arranged on the other side of the display area.

[0033] In a fourth aspect, a display device is also proposed, comprising the display panel as above.

[0034] According to the above technical solution, a first subcircuit electrically connected to the drive signal terminal and a high-level signal terminal electrically connected to the first subcircuit are provided, and the state of the first subcircuit is controlled by using the first drive signal and the second drive signal transmitted by the drive signal terminal. When the first subcircuit is in the on state, the high-level signal terminal transmits the received high-level signal to the first drive signal terminal, so that the potential of the first drive signal terminal changes from the original first drive signal to the high-level signal. Thus, it is achieved that by controlling the state of the first subcircuit, it is controlled whether the high-level signal is connected, and the attenuation of the first drive signal is compensated by the high-level signal, so as to avoid the abnormal problem caused by the insufficient opening of the TFT device due to the attenuation of the first drive signal, and the display effect can be improved.

[0035] The driving compensation circuit of the present invention, other advantages, objectives and features of the present invention will be reflected in part through the following description, and in part will be understood by those skilled in the art through research and practice of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present application and, together with the description, serve to explain the principles of the present application.

[0037] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, for ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative labor.

[0038] Various other advantages and benefits will become apparent to those of ordinary skill in the art by reading the detailed description of the exemplary embodiments below. The accompanying drawings are only for the purpose of illustrating exemplary embodiments and are not to be considered as limiting the present application. Also, the same reference symbols are used throughout the accompanying drawings to represent the same components. In the accompanying drawings:

[0039] Figure 1 A schematic block diagram of a drive compensation circuit provided in an embodiment of the present application;

[0040] Figure 2 A schematic structural diagram of a drive compensation circuit provided in an embodiment of the present application;

[0041] Figure 3 A timing diagram of a driving circuit provided in an embodiment of the present application;

[0042] Figure 4 A schematic comparison diagram before and after voltage compensation provided in an embodiment of the present application;

[0043] Figure 5 A schematic block diagram of another drive compensation circuit provided in an embodiment of the present application;

[0044] Figure 6 A schematic block diagram of a driving circuit provided in an embodiment of the present application;

[0045] Figure 7 A schematic block diagram of a display panel provided in an embodiment of the present application;

[0046] Figure 8 A schematic block diagram of another display panel provided in an embodiment of the present application;

[0047] Fig. 9 A schematic block diagram of another display panel provided in an embodiment of the present application;

[0048] Fig.10 A schematic block diagram of a display device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0049] In order to more clearly understand the above-mentioned purposes, features and advantages of the present application, the scheme of the present application will be further described below. It should be noted that the embodiments of the present application and the features in the embodiments can be combined with each other without conflict.

[0050] The terms "first", "second", "third", "fourth", etc. (if any) in the specification and claims of the present application and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchangeable where appropriate, so that the embodiments described herein can be implemented in an order other than that illustrated or described herein. In addition, the terms "including" and "having" and any of their variations are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units that are clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices. The technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all of the embodiments.

[0051] In the following description, many specific details are set forth to facilitate a full understanding of the present application, but the present application may also be implemented in other ways different from those described herein; obviously, the embodiments in the specification are only part of the embodiments of the present application, rather than all of the embodiments.

[0052] In panel design, the Gate signal is generated by the GOA circuit and transmitted to the pixel circuit. If there is foreign matter in the GOA area causing a short circuit, or if the device characteristics are abnormal, it may affect the generation and transmission of the Gate signal, causing the TFT device in the pixel circuit to work abnormally, thereby causing display abnormalities, black screens, etc. Among them, the abnormalities generated during the production process can be detected in the lighting inspection link. For products with confirmed GOA abnormalities, the routing of the GOA signal input end on the abnormal side can be cut off by methods such as laser cutting, thereby shielding the abnormal GOA, and using the normal side GOA for unilateral driving to ensure normal display. However, this shielding method cannot meet the requirements of a variety of products, and after the original double-sided drive is changed to a single-sided drive, the normal Gate signal will attenuate during the transmission to the non-driven side, thereby affecting the degree of opening of the TFT device, and also causing display abnormalities. Among them, the non-driven side is the GOA abnormal side or the side without GOA.

[0053] In order to solve the above technical problem, according to a first aspect of the present application, a driving compensation circuit is proposed, which is applied to a display panel, and the display panel includes a pixel circuit. Figure 1 A schematic block diagram of a drive compensation circuit provided in an embodiment of the present application. For example, Figure 1 As shown, the driving compensation circuit 100 may include a high-level signal terminal 110 , a plurality of driving signal terminals 120 and a first sub-circuit 130 .

[0054] For example, Figure 1 As shown, the driving signal terminal 120 is used to transmit a driving signal. Different driving signals are used to drive the operation of different pixel circuits 200. For example, Figure 1 As shown, the driving signal may include a first driving signal G2 and a second driving signal G1. The second driving signal G1 drives the pixel circuit 200 before the first driving signal G1 drives the pixel circuit 200. For example, for a row scanning pixel circuit, the first driving signal G2 may be used to drive the pixel circuit of the current row, and the second driving signal G1 may be used to drive the pixel circuit of the previous row of the pixel circuit of the current row, so that the second driving signal G1 drives the pixel circuit 200 before. For example, Figure 1 As shown, when the current row of pixel circuits is the second row of pixel circuits, the previous row of pixel circuits of the current row of pixel circuits is the first row of pixel circuits. It should be noted that Figure 1 The corresponding connection relationship between the driving signal terminal and the row pixel circuit shown is only exemplary and does not mean a limitation on the connection relationship between the two.

[0055] For example, Figure 1 As shown, the drive signal terminal may include a first drive signal terminal 122 and a second drive signal terminal 121. The first drive signal terminal 122 is used to transmit the first drive signal G2, and the second drive signal terminal 121 is used to transmit the second drive signal G1. In the case of compensating the drive circuit corresponding to the pixel circuit of the current row, the first drive signal terminal is electrically connected to the corresponding driven pixel circuit, that is, the first drive signal terminal is connected to the pixel circuit of the current row ( Figure 1 The first sub-circuit 130 is electrically connected to the high-level signal terminal 110, the first drive signal terminal 122, and the second drive signal terminal 121, respectively. The first sub-circuit 130 can be turned on or off under the action of the first drive signal G2 and the second drive signal G1. When the first sub-circuit 130 is turned on, the high-level signal received by the high-level signal terminal 110 is transmitted to the first drive signal terminal 122, and the potential of the first drive signal terminal 122 is a high-level signal.

[0056] Exemplarily, the high-level signal terminal can be used to receive a high-level signal such as VGH (Gate High Voltage). The high-level signal terminal can be realized by the VGH routing retained when cutting the abnormal end GOA routing. For the drive signal terminal, the voltage of the drive signal transmitted by it is generally equal to the voltage of the high-level signal. GOA can be used to generate a drive signal, which is used to be transmitted to the pixel circuit via the drive signal line. In the process of GOA transmitting the drive signal to the drive signal terminal via the drive signal line, the drive signal is prone to signal attenuation, and the voltage of the drive signal on the non-driving side is less than the voltage of the high-level signal. In order to avoid the attenuated drive signal driving the gate of the TFT, a first sub-circuit electrically connected to the drive signal terminal and a high-level signal terminal electrically connected to the first sub-circuit are added. Among them, the first sub-circuit can be used as a switch for whether the high-level signal is written. For example, when the first sub-circuit is in a conducting state, the high-level signal terminal can transmit the high-level signal to the first drive signal terminal via the first sub-circuit that is turned on, and the potential of the first drive signal terminal is the written high-level signal. Among them, the first subcircuit can be turned on or off under the joint action of the first drive signal and the second drive signal. It should be noted that, in an ideal state, the voltages of the first drive signal and the second drive signal are equal. When the first drive signal or the second drive signal acts on the first subcircuit alone, the first subcircuit cannot be turned on and is still in a cut-off state, and the high-level signal cannot be connected at this time. Only when the first drive signal and the second drive signal act on the first subcircuit together, the first subcircuit can be turned on. When the first subcircuit is in the on state, the high-level signal end is electrically connected to the first drive signal end. Combined with the foregoing, before the high-level signal is written, the potential of the first drive signal end is less than or equal to the high-level signal. After the high-level signal is written, the potential of the first drive signal end is pulled up or maintained as a high-level signal, and then the high-level signal can be used as the gate drive signal of the TFT to ensure the normal operation of the TFT. That is, it can be understood that the high-level signal can reset or cover the potential of the first drive signal end to ensure that the pixel circuit connected to the first drive signal end obtains sufficient drive voltage to work and ensure the normal operation of the pixel circuit.

[0057] According to the above technical solution, a first subcircuit electrically connected to the drive signal terminal and a high-level signal terminal electrically connected to the first subcircuit are provided, and the state of the first subcircuit is controlled by using the first drive signal and the second drive signal transmitted by the drive signal terminal. When the first subcircuit is in the on state, the high-level signal terminal transmits the received high-level signal to the first drive signal terminal, so that the potential of the first drive signal terminal changes from the original first drive signal to the high-level signal. Thus, it is achieved that by controlling the state of the first subcircuit, whether the high-level signal is connected is controlled, and the attenuation of the first drive signal is compensated by the high-level signal to avoid the abnormal problem caused by the insufficient opening of the TFT device due to the attenuation of the first drive signal, so as to improve the display effect.

[0058] Figure 2 A schematic structural diagram of a drive compensation circuit provided in an embodiment of the present application. In some implementations, Figure 2 As shown, the drive compensation circuit also includes a first capacitor C1 and a second capacitor C2. The first subcircuit 130 includes a first transistor T1. The first end a of the first capacitor C1 is electrically connected to the second drive signal terminal Gn-1, and the second end b of the first capacitor C1 is electrically connected to the gate g of the first transistor T1 via the first node N1. The first end c of the second capacitor C2 is electrically connected to the first drive signal terminal Gn, and the second end d of the second capacitor C2 is electrically connected to the first node N1. The first electrode 1 of the first transistor T1 is electrically connected to the high level signal terminal 110, and the second electrode 2 of the first transistor T1 is electrically connected to the first drive signal terminal Gn. Among them, the first electrode 1 can be the source of the first transistor T1, and correspondingly, the second electrode 2 is the drain of the first transistor T1. Alternatively, the first electrode 1 can be the drain of the first transistor T1, and correspondingly, the second electrode 2 is the source of the first transistor T1.

[0059] Figure 3 A timing diagram of a driving circuit provided in an embodiment of the present application. Exemplarily, in combination with the foregoing, the driving time of the second driving signal Gn-1 on the pixel circuit is before the driving time of the first driving signal Gn on the pixel circuit, such as Figure 3 As shown, the effective level starting point t1 of the second driving signal Gn-1 can be regarded as the starting point of the driving time of the second driving signal Gn-1 on the pixel circuit. The effective level starting point t2 of the first driving signal Gn can be regarded as the starting point of the driving time of the first driving signal Gn on the pixel circuit, where t1 is before t2. Figure 2 and Figure 3As shown, the second drive signal Gn-1 starts to be high level at time t1. When the second drive signal Gn-1 is high level, the gate voltage of the first transistor T1 is raised by the first capacitor C1. Exemplarily, the first terminal a of the first capacitor C1 receives the high level signal. According to the capacitance characteristics, the signal output by the second terminal b of the first capacitor C1 is different from the signal received by the first terminal a. Therefore, the voltage V1 received by the gate of the first transistor T1 is less than the second drive signal V Gn-1 , and combined with the above, VGH ≥ V Gn-1 Therefore, V1<VGH, at this time, the first transistor T1 cannot be turned on normally and is in the cut-off state. Figure 2 and Figure 3 As shown, at time t2, when the first drive signal Gn and the second drive signal Gn-1 are both high-level signals, the first drive signal Gn can further raise the gate voltage of the first transistor T1 to V2 through the second capacitor C2, and V2>V1. Combined with the above, the voltages of the first drive signal Gn and the second drive signal Gn-1 are equal, and the two give the voltage to the gate g of the first transistor T1 in a superimposed manner. At this time, the voltage V2 of the gate g>VGH, and the first transistor T1 is turned on. The high-level signal terminal 110 is connected to the first drive signal terminal, and the high-level signal terminal 110 can give the high-level signal VGH to the first drive signal terminal to achieve voltage compensation at the first drive signal terminal.

[0060] Therefore, adding the first capacitor and the second capacitor in the driving compensation circuit can realize the voltage compensation of the driving signal terminal adjacent to the driving signal terminal controlled by the driving signal terminal transmitted therefrom, and avoid the connection between adjacent driving signal terminals, which may lead to the occurrence of problems such as timing disorder. The circuit structure is simple, and the complex circuit structure may avoid the increase of the border of the display panel to which the driving compensation circuit is applied, thereby affecting the display effect.

[0061] In some embodiments, Figure 2 As shown, the drive compensation circuit may further include a second subcircuit 140. A first end of the second subcircuit 140 is electrically connected to the first node N1, and a second end of the second subcircuit 140 is electrically connected to a third drive signal terminal 123 among a plurality of drive signal terminals. The second subcircuit 140 is used to be turned on or off under the action of the third drive signal Gn+4, and the third drive signal terminal 123 is used to transmit the third drive signal Gn+4, and the driving time of the third drive signal Gn+4 to the pixel circuit is later than the driving time of the first drive signal Gn to the pixel circuit. When the second subcircuit 140 is in the on state, the first drive signal Gn is transmitted to the first capacitor C1.

[0062] It should be noted that the third driving signal may be any signal that drives the pixel circuit later than the first driving signal. Figure 2The third driving signal Gn+4 shown is only exemplary, and the third driving signal may be Gn+x, where x may be set according to the number of clock signals in the driving circuit, for example, when the number of clock signals is 8, x=8÷2=4. Figure 2 For example, the first driving signal is Gn, and the third driving signal is Gn+4. If Gn is used to drive the pixel circuit of the nth row, then Gn+4 is used to drive the pixel circuit of the n+4th row. Figure 2 and Figure 3 As shown, the time t3 is the effective level end point of the second drive signal Gn-1, and the second drive signal Gn-1 begins to enter a low level. At this time, the gate voltage of the first transistor T1 is pulled down to V1, and the first transistor T1 is turned off, and the connection between the high-level signal terminal 110 and the first drive signal terminal 122 is disconnected. The first drive signal terminal 122 is not connected to other loads, so the potential of the high-level signal can be maintained. The time t4 is the effective level end point of the first drive signal Gn, and it is also the effective level starting point of the third drive signal Gn+4. In addition, before the time t4, the second drive signal Gn-1 is a low-level signal. Figure 2 As shown, when the third drive signal Gn+4 is a high level signal, the second subcircuit 140 is turned on, and the first drive signal Gn is a low level signal. The first drive signal terminal 122 is connected to the second terminal b of the first capacitor C1 via the second subcircuit 140, and the voltage of the second terminal b of the first capacitor C1 is pulled down to VGL (Gate Low Voltage). At the same time, the second terminal b of the first capacitor C1 and the gate g of the first transistor T1 are equipotential, that is, the gate voltage of the first transistor T1 is pulled down to VGL. The t5 moment is the effective level end point of the third drive signal Gn+4, after which the third drive signal Gn+4 is converted to a low level signal, the second transistor T2 is turned off, and the gate reset of the first transistor T1 is completed, and then the next round of voltage compensation can be started.

[0063] Thus, the first transistor T1 is reset, and the influence on the opening degree of the first transistor T1 caused by the superposition of the next written driving signal is avoided, thereby affecting the voltage compensation effect of the first driving signal terminal.

[0064] In some embodiments, Figure 3As shown, the effective level starting point (t2) of the first drive signal is before the effective level end point (t3) of the second drive signal, and the effective level end point (t4) of the first drive signal is after the effective level end point (t3) of the second drive signal. That is, the t3 moment is between the t2 moment and the t4 moment, and the first drive signal Gn and the second drive signal Gn-1 have a high level period (t2-t3) at the same time, thereby ensuring that the opening time of the first transistor is sufficient, providing sufficient time for voltage compensation, and ensuring effective compensation of the potential of the first drive signal end. Figure 4 A schematic comparison diagram before and after voltage compensation provided in an embodiment of the present application. For example, Figure 4 (a) is the potential change during the transmission of the driving signal to the TFT under ideal conditions, such as Figure 4 As shown in (a), VGL quickly changes to VGH and keeps VGH unchanged, and the required time is 4H, where H can represent the scanning time of a row of pixel circuits. In 4H, the first 3H is the pre-charging process for TFT, that is, before the driving signal is given to the TFT gate, the driving signal has prepared a high-level signal VGH. The last 1H is to give the prepared VGH to the TFT gate to drive the TFT to turn on. Figure 4 (b) is the potential change during the process of the single-side driving signal being transmitted to the TFT corresponding to the non-driving side. Figure 4 As shown in (b), signal attenuation occurs when the driving signal is transmitted to the non-driving side. Therefore, the potential of the driving signal cannot reach VGH in the pre-charging stage, affecting the opening degree of the TFT device in the charging stage, thereby causing display abnormality. Figure 4 (c) is the potential change of the driving signal given to the TFT after adding the driving compensation circuit. Figure 4 (a) Compared with Figure 4 (c) also achieves pre-charging for 3 hours and charging for 1 hour, and the potential is kept at VGH before the charging stage. Figure 4 (a) Compared with Figure 4 (c) The process of the potential changing from VGL to VGH is relatively gentle, avoiding device breakdown damage.

[0065] In some embodiments, Figure 3As shown, the effective level end point of the second drive signal Gn-1 is located at the first position of the effective level of the first drive signal Gn, that is, the t3 moment. The duration of the effective level of the first drive signal before the t3 moment is the first duration, that is, the t2-t3 period, and the duration of the effective level of the first drive signal after the t3 moment is the second duration, that is, the t3-t4 period. The sum of the first duration t2-t3 period and the second duration t3-t4 period is the third duration, that is, the total effective level duration t2-t4 period of the first drive signal. The ratio of the third duration to the scanning duration H of a row of pixel circuits is a first value, and the number of clock signals in the drive circuit is twice the first value. Exemplarily, if the number of clock signals in the drive circuit is 8, the first value is 4, that is, the third duration is 4H. In order to ensure that the compensation time is sufficient, the pre-charge (compensation) time can be set to 3H, and the charging (driving TFT) time can be set to 1H.

[0066] In some embodiments, Figure 2 As shown, the second sub-circuit 140 may include a second transistor T2. The gate of the second transistor T2 is electrically connected to the third drive signal terminal 123, the first electrode of the second transistor T2 is electrically connected to the first node N1, and the second electrode of the second transistor T2 is electrically connected to the first drive signal terminal 122 via the second node N2. The first terminal d of the second capacitor C2 is electrically connected to the first node N1, and the second terminal c of the second capacitor C2 is electrically connected to the second node N2. Figure 2 As shown, the second transistor T2 is connected in parallel with the second capacitor C2. When the third drive signal is a high-level signal, the second transistor starts to conduct under the action of the high-level signal. When the second transistor is turned on, the first drive signal terminal can be connected to the second terminal of the first capacitor and the gate of the first transistor via the second transistor. When the first drive signal is a low-level signal, the second terminal of the first capacitor and the gate voltage of the first transistor can be pulled down to achieve the reset of the first transistor.

[0067] The above circuit structure is simple, and avoids the problems of introducing too many devices leading to signal delay and widening of the border of the display panel, thereby effectively ensuring the display effect.

[0068] Figure 5 A schematic block diagram of another drive compensation circuit provided in an embodiment of the present application. For example, Figure 5As shown, the driving compensation circuit may include N stages, the second sub-circuit 120 in the N-th driving compensation circuit is electrically connected to the reset signal terminal, the second sub-circuit in the N-th driving compensation circuit is used to be turned on or off under the action of the reset signal CLR, and the reset signal terminal is used to transmit the reset signal CLR, wherein N is a natural number greater than 0; the first driving signal corresponding to the n-th driving compensation circuit is used to drive the pixel circuit of the n-th row, the second driving signal corresponding to the n-th driving compensation circuit is used to drive the pixel circuit of the n-1-th row, and the third driving signal corresponding to the n-th driving compensation circuit is used to drive the pixel circuit of the n+x-th row, n and x are natural numbers greater than 0, n+x≤N, for example, reference Figure 2 and Figure 3 , x=4. Exemplarily, x can also be 2, 3, 5 or other corresponding values ​​according to the number of clock signals in the driving circuit.

[0069] Exemplarily, the drive compensation circuit is used to perform voltage compensation on the drive signal, so the drive compensation circuit can be set one-to-one with the drive circuit used to generate the drive signal. Figure 1 As shown, the first drive signal can be voltage compensated by the first-level drive compensation circuit, so that the first row pixel circuit can be driven by the compensated first drive signal. For the second drive signal G1 in the first-level drive compensation circuit, it can be an initial signal preset according to experience or actual needs. Under the action of this initial signal, the first drive signal G2 generated by the first-level drive circuit can be voltage compensated. The specific compensation process is as described above and will not be repeated here, so that the first row pixel circuit can be driven by the compensated first drive signal G2. After the first drive signal G2 is voltage compensated, the first sub-circuit can be reset by the third drive signal G6 to ensure the accuracy of voltage compensation for the next frame drive signal. At the same time, the first drive signal G2 can also be used as the second drive signal in the next-level drive compensation circuit, and is used to act on the first sub-circuit in the next-level drive compensation circuit together with the first drive signal G3 in the next-level drive compensation circuit to achieve voltage compensation of the first drive signal G3 of the next level. By analogy, the compensation of multi-level drive signals can be achieved in a cascade manner to reduce signal input. For the last-stage driving compensation circuit, the reset signal CLR can be used as the control signal of the second sub-circuit. Compared with its own third driving signal, the driving compensation circuit can be reset by external input, which can realize the double insurance of the reset operation together with the third driving signal, and further ensure the reliability of the reset result.

[0070] According to a second aspect of the present application, a driving circuit is also provided. Figure 6 A schematic block diagram of a driving circuit provided in an embodiment of the present application. Figure 6As shown, the driving circuit 300 may include: a plurality of driving sub-circuits 310 and the driving compensation circuit 100 as described above. The driving compensation circuit 100 is electrically connected to the driving sub-circuit 310, and the plurality of driving sub-circuits 310 are used to provide a plurality of driving signals to the driving compensation circuit 100, and different driving signals are output by different driving sub-circuits 310.

[0071] It should be noted that the driving subcircuit may include a circuit for providing a driving signal to the pixel circuit, and may also include circuits for other purposes. Therefore, the number of driving subcircuits is greater than or equal to the number of driving compensation circuits, and the driving compensation circuit is electrically connected one-to-one with the driving subcircuit for providing a driving signal to the pixel circuit. The driving compensation circuit performs voltage compensation on the driving signal provided by the driving subcircuit, and then transmits the compensated driving signal back to the driving signal terminal of the driving subcircuit, and the driving signal terminal can provide the pixel circuit with the voltage-compensated driving signal.

[0072] For example, Figure 6 As shown, in some embodiments, the driving compensation circuit 100 and the driving sub-circuit 310 are connected via a driving signal line 320, and the driving signal line 320 is used to be electrically connected to the pixel circuit. The driving signal line can be used for the driving sub-circuit to transmit the driving signal to the pixel circuit. For each level of driving sub-circuit, it can be connected to the same driving signal line as the corresponding driving compensation circuit. For each row of pixel circuits, it is electrically connected to a driving signal line and is driven and controlled by the driving signal generated by the first-level driving sub-circuit. Exemplarily, for the first-level driving sub-circuit, after it generates the driving signal, the driving signal can be transmitted to the driving compensation circuit via the driving signal line. According to the above technical solution, the driving compensation circuit performs voltage compensation on the driving signal. Afterwards, the compensated driving signal can be transmitted to the pixel circuit via the driving signal line, and the pixel circuit can drive the display under the action of the compensated driving signal.

[0073] Thus, the driving sub-circuit, the driving compensation circuit and the pixel circuit are all connected to the driving signal line, so that multiple signals flow on the driving signal line, the wiring is simple, the production is convenient, and it is not easy to make mistakes.

[0074] In some embodiments, the voltage value of the first driving signal output from the driving subcircuit transmitted to the first driving signal terminal via the driving signal line is less than the voltage value of the high-level signal. Exemplarily, as described above, the voltage value of the first driving signal output from the driving subcircuit is substantially equal to the voltage value of the high-level signal, but due to the signal attenuation of the first driving signal during transmission on the driving signal line, combined with Figure 6 , the driving sub-circuit 310 generates a driving signal, which is transmitted to the driving compensation circuit 100 via the driving signal line 320. Figure 2 and Figure 3, the driving signal terminal in the driving compensation circuit 100 transmits the driving signal received from the driving signal line 320 to the gate of the first transistor T1, and uses the first driving signal Gn and the second driving signal Gn-1 to act on the gate of the first transistor T1 to turn on the first transistor T1. The high-level signal terminal 110 is connected to the first driving signal terminal to compensate the attenuated driving signal received by the first driving signal terminal with VGH. Afterwards, the compensated high-level signal is transmitted to the pixel circuit via the driving signal line 320, completing the compensation action of the driving compensation circuit on the driving signal and improving the display effect.

[0075] According to a third aspect of the present application, a display panel is also provided. Figure 7 A schematic block diagram of a display panel provided in an embodiment of the present application. For example, Figure 7 As shown, the display panel 700 may include: a plurality of pixel circuits 200 and the driving circuit 300 as described above, and the driving circuit 300 is electrically connected to the pixel circuits 200 .

[0076] Figure 8 A schematic block diagram of another display panel provided in an embodiment of the present application. For example, Figure 8 As shown, the display panel 700 may further include: a display area 710 and a non-display area 720, wherein the display area 710 is provided with a plurality of pixel circuits 200 arranged in rows and columns. The non-display area 720 is arranged to surround the display area 710. The driving sub-circuit and the driving compensation circuit may both be arranged in the non-display area. Figure 8 The pixel circuit 200 in the figure is merely exemplary and does not imply a specific limitation on the arrangement and number of pixel circuits. For a display panel 700 driven on one side, that is, the driving sub-circuit 310 is disposed only in the non-display area 720 on one side of the display area 710 of the display panel 700, the driving sub-circuit 310 may be disposed as follows: Figure 8 On the left side of the display area 710, the driving compensation circuit 100 can be arranged on the opposite side of the display area 710, or on the adjacent side, and the driving sub-circuit 310 is electrically connected to the driving compensation circuit 100. In some embodiments, the driving sub-circuit can also be arranged on the right side of the display area, and the driving compensation circuit electrically connected to the driving sub-circuit is correspondingly arranged on the opposite side of the display area, or on the adjacent side.

[0077] Fig. 9 A schematic block diagram of another display panel provided in an embodiment of the present application. Fig. 9As shown, for a double-sided driven display panel 700, that is, a driving sub-circuit 310 is disposed in the non-display area 720 on both sides of the display area 710 of the display panel 700, a driving compensation circuit 100 is also disposed on both sides of the display area 710, and the driving compensation circuit 100 on each side is electrically connected to the driving sub-circuit 310 on the opposite side. That is, the driving compensation circuit 100 on the right side is electrically connected to the driving sub-circuit 310 on the left side, and the driving compensation circuit 100 on the left side is electrically connected to the driving sub-circuit 310 on the right side.

[0078] for Figure 8 In the single-side driven display panel shown, the side where the driving sub-circuit is located can be the driving side, and the other side can be regarded as the non-driving side, or the side opposite to the driving side can be regarded as the non-driving side. When there is no driving signal output on the non-driving side and the signal output from the driving side is attenuated when transmitted to the non-driving side, potential compensation can be performed on the driving signal transmitted to the non-driving side. Fig. 9 The double-side driven display panel shown can use the driving compensation circuit electrically connected to the opposite side to perform potential compensation on the driving signal when a fault occurs at one driving signal end, thereby ensuring the display effect of the display panel.

[0079] According to a fourth aspect of the present application, a display device is also proposed. Fig.10 A schematic block diagram of a display device provided in an embodiment of the present application is shown in FIG. Fig.10 As shown, the display device 800 may include the display panel 700 as described above.

[0080] Exemplarily, the display device 800 of the embodiment of the present application can be applied to scenarios such as vehicle-mounted display, smart phones, computers, medical monitors, televisions, smart wearable displays, etc. Smart wearable devices may include smart watches, AR (augmented reality) devices, and VR (virtual reality) devices, etc.

[0081] In combination with the above, the drive compensation circuit of the display panel can compensate the potential of the drive signal attenuated due to the transmission process in the display device, avoid the abnormal problem caused by insufficient opening of the TFT device, and improve the display effect of the display device.

[0082] A person skilled in the art may understand the specific details and beneficial effects of the display panel and the display device by reading the above descriptions of the driving compensation circuit and the driving circuit, which will not be described here for the sake of brevity.

[0083] In the several embodiments provided in the present application, it should be understood that the disclosed devices and / or equipment can be implemented in other ways. For example, the device embodiments described above are only schematic, for example, the division of units is only a logical function division, and there may be other division methods in actual implementation, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, indirect coupling or communication connection of devices or units, which can be electrical, mechanical or other forms.

[0084] The units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0085] In addition, each functional unit in each embodiment of the present application may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit. The above-mentioned integrated unit may be implemented in the form of hardware or in the form of software functional units.

[0086] The above embodiments are only used to illustrate the technical solutions of the present application, rather than to limit them. Although the present application has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or replace some of the technical features therein by equivalents. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present application.

Claims

1. A drive compensation circuit, characterized in that: Applied to a display panel, the display panel includes a pixel circuit, and the driving compensation circuit includes: A high-level signal terminal, a plurality of drive signal terminals and a first sub-circuit, the drive signal terminal is used to transmit a drive signal, different drive signals are used to drive the operation of different pixel circuits, the drive signal includes a first drive signal and a second drive signal, and the second drive signal drives the pixel circuit before the first drive signal drives the pixel circuit; The driving signal terminal includes a first driving signal terminal and a second driving signal terminal, the first driving signal terminal is used to transmit a first driving signal, the second driving signal terminal is used to transmit a second driving signal, and the first driving signal terminal is used to electrically connect to a corresponding driven pixel circuit; The first sub-circuit is electrically connected to the high-level signal terminal, the first drive signal terminal and the second drive signal terminal respectively, and the first sub-circuit is used to be turned on or off under the action of the first drive signal and the second drive signal; When the first sub-circuit is turned on, the high-level signal received by the high-level signal terminal is transmitted to the first drive signal terminal, and the potential of the first drive signal terminal is a high-level signal.

2. The drive compensation circuit according to claim 1, characterized in that: Also includes a first capacitor and a second capacitor, the first sub-circuit includes a first transistor; The first end of the first capacitor is electrically connected to the second drive signal end, the second end of the first capacitor is electrically connected to the gate of the first transistor via the first node, the first end of the second capacitor is electrically connected to the first drive signal end, the second end of the second capacitor is electrically connected to the first node, the first electrode of the first transistor is electrically connected to the high level signal end, and the second electrode of the first transistor is electrically connected to the first drive signal end, wherein the first electrode is one of the source and the drain of the first transistor, and the second electrode is the other of the source and the drain of the first transistor.

3. The drive compensation circuit according to claim 2, characterized in that: Also includes: a second sub-circuit, wherein a first end of the second sub-circuit is electrically connected to the first node, a second end of the second sub-circuit is electrically connected to a third drive signal end among the plurality of drive signal ends, the second sub-circuit is configured to be turned on or off under the action of a third drive signal, the third drive signal end is configured to transmit a third drive signal, and a driving time of the third drive signal on the pixel circuit is later than a driving time of the first drive signal on the pixel circuit; When the second sub-circuit is in an on state, the first driving signal is transmitted to the first capacitor.

4. The drive compensation circuit according to claim 3, characterized in that: The second subcircuit includes a second transistor, a gate of the second transistor is electrically connected to the third drive signal terminal, a first electrode of the second transistor is electrically connected to the first node, a second electrode of the second transistor is electrically connected to the first drive signal terminal via the second node, a first end of the second capacitor is electrically connected to the first node, and a second end of the second capacitor is electrically connected to the second node.

5. The drive compensation circuit according to claim 3, characterized in that: The driving compensation circuit includes N stages, the second sub-circuit in the N-th stage driving compensation circuit is electrically connected to the reset signal terminal, the second sub-circuit in the N-th stage driving compensation circuit is used to be turned on or off under the action of the reset signal, and the reset signal terminal is used to transmit the reset signal, wherein N is a natural number greater than 0; The first driving signal corresponding to the n-th level driving compensation circuit is used to drive the pixel circuit of the n-th row, the second driving signal corresponding to the n-th level driving compensation circuit is used to drive the pixel circuit of the n-1-th row, and the third driving signal corresponding to the n-th level driving compensation circuit is used to drive the pixel circuit of the n+x-th row, where n and x are natural numbers greater than 0, and n+x≤N.

6. A driving circuit, characterized in that: include: a plurality of driving sub-circuits; According to any one of claims 1 to 5, the drive compensation circuit is electrically connected to the drive sub-circuit, and the plurality of drive sub-circuits are used to provide a plurality of drive signals to the drive compensation circuit, and different drive signals are output by different drive sub-circuits.

7. The driving circuit according to claim 6, characterized in that The driving compensation circuit and the driving sub-circuit are connected via a driving signal line, and the driving signal line is used to be electrically connected to the pixel circuit.

8. The driving circuit according to claim 7, characterized in that The voltage value of the first driving signal output from the driving sub-circuit transmitted to the first driving signal terminal via the driving signal line is smaller than the voltage value of the high level signal.

9. The driving circuit according to claim 6, characterized in that The effective level starting point of the first driving signal is before the effective level ending point of the second driving signal, and the effective level ending point of the first driving signal is after the effective level ending point of the second driving signal.

10. The driving circuit according to claim 9, characterized in that The effective level end point of the second driving signal is located at the first position moment of the effective level of the first driving signal, the duration of the effective level of the first driving signal before the first position moment is the first duration, and the duration of the effective level of the first driving signal after the first moment position is the second duration.

11. The driving circuit according to claim 10, characterized in that The sum of the first duration and the second duration is the third duration, the ratio of the third duration to the scanning duration of a row of pixel circuits is a first value, and the number of clock signals in the driving circuit is twice the first value.

12. The driving circuit according to claim 6, characterized in that The effective level starting point of the third driving signal is the effective level ending point of the first driving signal.

13. A display panel, characterized in that: include: a plurality of pixel circuits; The driving circuit according to any one of claims 6 to 12, wherein the driving circuit is electrically connected to the pixel circuit.

14. The display panel according to claim 13, characterized in that include: A display area, wherein the display area is provided with a plurality of pixel circuits arranged in rows and columns; The driving sub-circuit is arranged on one side of the display area, and the driving compensation circuit electrically connected to the driving sub-circuit is arranged on the other side of the display area.

15. A display device, characterized in that: Comprising a display panel as claimed in claim 13 or 14.

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