Driving compensation circuit, driving circuit, display panel and display device

Abstract

The application provides a driving compensation circuit, a driving circuit, a display panel and a display device. The application relates to the technical field of display, and the driving compensation circuit comprises a high-level signal end, a plurality of driving signal ends and a first sub-circuit. The driving signal ends are used for transmitting driving signals, the driving signals comprise first driving signals and second driving signals; the first sub-circuit is electrically connected with the high-level signal end, the first driving signal end and the second driving signal end respectively, and the first sub-circuit is used for being turned on or turned off under the action of the first driving signals and the second driving signals; in the state that the first sub-circuit is turned on, the high-level signal received by the high-level signal end is transmitted to the first driving signal end, and the potential of the first driving signal end is the high-level signal. The high-level signal is used for compensating the attenuation of the first driving signal, so that abnormal problems caused by the insufficient opening degree of a thin film transistor device opened due to the attenuation of the first driving signal can be avoided, and the display effect can be improved.

Description

Technical Field

[0001] This invention relates to the field of display technology, and more specifically, to a drive compensation circuit, a drive circuit, a display panel, and a display device. Background Technology

[0002] Typically, pixel circuits in display devices require multiple drive signals for control. To generate these sequentially on / off drive signals, GOA (Gate On Array) circuits are placed on both sides of the AA (Active Area) region. The GOA circuits can provide gate signals to the pixel circuits, which can control, for example, the state of TFTs (Thin Film Transistors). For a normal gate signal, signal attenuation may occur during transmission to the TFT gate, thus affecting the degree of TFT activation, leading to display abnormalities and impacting the display effect.

[0003] Therefore, a new technical solution is urgently needed to solve the above-mentioned technical problems. Summary of the Invention

[0004] The summary section introduces a series of simplified concepts, which will be further explained in detail in the detailed description section. The summary section of this invention is not intended to limit the key features and essential technical features of the claimed technical solution, nor is it intended to determine the scope of protection of the claimed technical solution.

[0005] In a first aspect, the present invention proposes a driving compensation circuit for use in a display panel, the display panel including pixel circuitry, the driving compensation circuit comprising:

[0006] The circuit includes a high-level signal terminal, multiple drive signal terminals, and a first sub-circuit. The drive signal terminals are used to transmit drive signals. Different drive signals are used to drive the operation of different pixel circuits. The drive signals include a first drive signal and a second drive signal. The second drive signal drives the pixel circuit before the first drive signal drives the pixel circuit.

[0007] The driving signal terminal includes a first driving signal terminal and a second driving signal terminal. The first driving signal terminal is used to transmit a first driving signal, and the second driving signal terminal is used to transmit a second driving signal. The first driving signal terminal is used to electrically connect to the corresponding driven pixel circuit.

[0008] The first sub-circuit is electrically connected to the high-level signal terminal, the first driving signal terminal, and the second driving signal terminal, respectively. The first sub-circuit is used to turn on or off under the action of the first driving signal and the second driving signal.

[0009] When the first sub-circuit is turned on, the high-level signal received at the high-level signal terminal is transmitted to the first drive signal terminal, and the potential of the first drive signal terminal is a high-level signal.

[0010] In some implementations, a first capacitor and a second capacitor are also included, and the first sub-circuit includes a first transistor;

[0011] The first terminal of the first capacitor is electrically connected to the second driving signal terminal, the second terminal of the first capacitor is electrically connected to the gate of the first transistor via the first node, the first terminal of the second capacitor is electrically connected to the first driving signal terminal, the second terminal of the second capacitor is electrically connected to the first node, the first electrode of the first transistor is electrically connected to the high-level signal terminal, and the second electrode of the first transistor is electrically connected to the first driving signal terminal. The first electrode is one of the source and drain of the first transistor, and the second electrode is the other of the source and drain of the first transistor.

[0012] In some implementations, the drive compensation circuit further includes:

[0013] The second sub-circuit has a first terminal electrically connected to the first node and a second terminal electrically connected to the third driving signal terminal among multiple driving signal terminals. The second sub-circuit is used to turn on or off under the action of the third driving signal. The third driving signal terminal is used to transmit the third driving signal. The driving time of the third driving signal on the pixel circuit is after the driving time of the first driving signal on the pixel circuit.

[0014] When the second sub-circuit is in the on state, the first drive signal is transmitted to the first capacitor.

[0015] In some embodiments, the second sub-circuit includes a second transistor, the gate of which is electrically connected to a third drive signal terminal, the first electrode of which is electrically connected to a first node, the second electrode of which is electrically connected to the first drive signal terminal via a second node, the first terminal of which is electrically connected to the first node, and the second terminal of which is electrically connected to the second node.

[0016] In some implementations, the drive compensation circuit includes N stages. The second sub-circuit in the Nth stage drive compensation circuit is electrically connected to the reset signal terminal. The second sub-circuit in the Nth stage drive compensation circuit is used to turn on or off under the action of the reset signal. The reset signal terminal is used to transmit the reset signal. Here, N is a natural number greater than 0.

[0017] The first driving signal corresponding to the nth-level driving compensation circuit is used to drive the pixel circuit in the nth row, the second driving signal corresponding to the nth-level driving compensation circuit is used to drive the pixel circuit in the (n-1)th row, and the third driving signal corresponding to the nth-level driving compensation circuit is used to drive the pixel circuit in the (n+x)th row, where n and x are natural numbers greater than 0, and n+x≤N.

[0018] Secondly, a driving circuit is also proposed, including:

[0019] Multiple driver sub-circuits;

[0020] The drive compensation circuit described above is electrically connected to the drive sub-circuit. Multiple drive sub-circuits are used to provide multiple drive signals to the drive compensation circuit, and different drive signals are output by different drive sub-circuits.

[0021] In some implementations, the drive compensation circuit and the drive sub-circuit are connected via a drive signal line, which is used to electrically connect to the pixel circuit.

[0022] In some implementations, the voltage value of the first drive signal output from the drive sub-circuit transmitted to the first drive signal terminal via the drive signal line is less than the voltage value of the high-level signal.

[0023] In some implementations, the effective level start point of the first drive signal is before the effective level end point of the second drive signal, and the effective level end point of the first drive signal is after the effective level end point of the second drive signal.

[0024] In some implementations, the effective level endpoint of the second driving signal is located at a first position time of the effective level of the first driving signal, the duration of the effective level of the first driving signal before the first position time is the first duration, and the duration of the effective level of the first driving signal after the first position time is the second duration.

[0025] In some implementations, the sum of the first duration and the second duration is the third duration, the ratio of the third duration to the scanning duration of a row of pixel circuits is the first value, and the number of clock signals in the driving circuit is twice the first value.

[0026] In some implementations, the effective level start point of the third driving signal is the effective level end point of the first driving signal.

[0027] Thirdly, a display panel is also proposed, including:

[0028] Multiple pixel circuits;

[0029] The driving circuit described above is electrically connected to the pixel circuit.

[0030] In some implementations, the following are included:

[0031] The display area has multiple rows and columns of pixel circuits.

[0032] The driving sub-circuit is located on one side of the display area, and the driving compensation circuit, which is electrically connected to the driving sub-circuit, is located on the other side of the display area.

[0033] Fourthly, a display device is also proposed, including the display panel as described above.

[0034] According to the above technical solution, a first sub-circuit electrically connected to the drive signal terminal and a high-level signal terminal electrically connected to the first sub-circuit are configured. The state of the first sub-circuit is controlled by a first drive signal and a second drive signal transmitted from the drive signal terminal. When the first sub-circuit is in the on state, the high-level signal terminal transmits its received high-level signal to the first drive signal terminal, causing the potential of the first drive signal terminal to change from the original first drive signal to a high-level signal. Thus, by controlling the state of the first sub-circuit, the connection of the high-level signal is controlled, achieving compensation for the attenuation of the first drive signal using the high-level signal. This avoids abnormal problems caused by insufficient opening of the TFT device due to the attenuation of the first drive signal, thereby improving the display effect.

[0035] The driving compensation circuit of the present invention, other advantages, objectives and features of the present invention will be apparent in part from the following description, and in part will be understood by those skilled in the art through study and practice of the present invention. Attached Figure Description

[0036] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this application and, together with the description, serve to explain the principles of this application.

[0037] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, for those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0038] Various other advantages and benefits will become apparent to those skilled in the art upon reading the following detailed description of exemplary embodiments. The accompanying drawings are for illustrative purposes only and are not intended to limit the scope of this application. Furthermore, the same reference numerals denote the same parts throughout the drawings. In the drawings:

[0039] Figure 1 A schematic block diagram of a drive compensation circuit provided for an embodiment of this application;

[0040] Figure 2 A schematic structural diagram of a drive compensation circuit provided in an embodiment of this application;

[0041] Figure 3 A timing diagram of a driving circuit provided in an embodiment of this application;

[0042] Figure 4 A schematic comparison diagram of voltage compensation before and after is provided for an embodiment of this application;

[0043] Figure 5 A schematic block diagram of another drive compensation circuit provided in an embodiment of this application;

[0044] Figure 6 A schematic block diagram of a driving circuit provided for an embodiment of this application;

[0045] Figure 7 A schematic block diagram of a display panel provided for an embodiment of this application;

[0046] Figure 8 A schematic block diagram of another display panel provided in an embodiment of this application;

[0047] Figure 9 A schematic block diagram of yet another display panel provided in an embodiment of this application;

[0048] Figure 10 This is a schematic block diagram of a display device provided in an embodiment of this application. Detailed Implementation

[0049] To better understand the above-mentioned objectives, features, and advantages of this application, the solution of this application will be further described below. It should be noted that, unless otherwise specified, the embodiments and features described in these embodiments can be combined with each other.

[0050] The terms "first," "second," "third," "fourth," etc. (if present) in the specification, claims, and accompanying drawings of this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus. The technical solutions of the embodiments of this application will now be clearly and completely described in conjunction with the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them.

[0051] Many specific details are set forth in the following description in order to provide a full understanding of this application, but this application may also be implemented in other ways different from those described herein; obviously, the embodiments in the specification are only some embodiments of this application, and not all embodiments.

[0052] In panel design, the Gate signal is generated by the GOA circuit and transmitted to the pixel circuit. If foreign objects exist in the GOA area causing a short circuit, or if the device characteristics are abnormal, it may affect the generation and transmission of the Gate signal, causing the TFT devices in the pixel circuit to malfunction, resulting in display abnormalities, black screens, etc. Abnormalities occurring during the production process can be detected during the lamp inspection stage. For products with confirmed GOA abnormalities, the traces at the GOA signal input terminal on the abnormal side can be cut off using methods such as laser cutting, thereby shielding the abnormal GOA and using the normal side GOA for single-sided driving to ensure normal display. However, this shielding method cannot meet the requirements of many products, and after the original dual-sided driving is changed to single-sided driving, the normal Gate signal will experience signal attenuation during transmission to the non-driving side, thus affecting the opening degree of the TFT devices and also causing display abnormalities. The non-driving side is the GOA abnormal side or the side without a GOA.

[0053] To address the aforementioned technical problems, according to a first aspect of this application, a drive compensation circuit is proposed for use in a display panel, the display panel including pixel circuitry. Figure 1 This is a schematic block diagram of a drive compensation circuit provided in an embodiment of this application. For example, as shown... Figure 1 As shown, the drive compensation circuit 100 may include a high-level signal terminal 110, multiple drive signal terminals 120, and a first sub-circuit 130.

[0054] For example, such as Figure 1 As shown, the drive signal terminal 120 is used to transmit drive signals. Different drive signals are used to drive the operation of different pixel circuits 200. For example, as... Figure 1 As shown, the driving signal may include a first driving signal G2 and a second driving signal G1. The second driving signal G1 drives the pixel circuit 200 before the first driving signal G1 drives the pixel circuit 200. For example, for a row scanning pixel circuit, the first driving signal G2 can drive the current row pixel circuit, and the second driving signal G1 can drive the row pixel circuit preceding the current row pixel circuit, so that the second driving signal G1 drives the pixel circuit 200 first. For example, as... Figure 1 As shown, when the current row of pixel circuits is the second row of pixel circuits, the row of pixel circuits preceding the current row of pixel circuits is the first row of pixel circuits. It should be noted that... Figure 1 The corresponding connection between the driving signal terminal and the row pixel circuit shown is merely exemplary and does not imply any limitation on the connection between the two.

[0055] For example, such as Figure 1 As shown, the driving signal terminal may include a first driving signal terminal 122 and a second driving signal terminal 121. The first driving signal terminal 122 is used to transmit a first driving signal G2, and the second driving signal terminal 121 is used to transmit a second driving signal G1. When compensating the driving circuit corresponding to the current row pixel circuit, the first driving signal terminal is electrically connected to the corresponding driven pixel circuit, that is, the first driving signal terminal is connected to the current row ( Figure 1 The pixel circuits in the second row shown are electrically connected. The first sub-circuit 130 is electrically connected to the high-level signal terminal 110, the first driving signal terminal 122, and the second driving signal terminal 121, respectively. The first sub-circuit 130 can be turned on or off under the action of the first driving signal G2 and the second driving signal G1. When the first sub-circuit 130 is turned on, the high-level signal received by the high-level signal terminal 110 is transmitted to the first driving signal terminal 122, and the potential of the first driving signal terminal 122 is a high-level signal.

[0056] For example, a high-level signal terminal can be used to receive a high-level signal, such as VGH (Gate High Voltage). The high-level signal terminal can be implemented using a VGH trace preserved when cutting the abnormal terminal GOA trace. For the drive signal terminal, the voltage of the transmitted drive signal is generally equal to the voltage of the high-level signal. The GOA can be used to generate a drive signal, which is transmitted to the pixel circuit via the drive signal line. During the transmission of the drive signal from the GOA to the drive signal terminal via the drive signal line, the drive signal is prone to attenuation, at which point the voltage of the drive signal on the non-drive side is less than the voltage of the high-level signal. To prevent the attenuated drive signal from driving the TFT gate, a first sub-circuit electrically connected to the drive signal terminal and a high-level signal terminal electrically connected to the first sub-circuit are added. The first sub-circuit can act as a switch for whether the high-level signal is written. For example, when the first sub-circuit is in the on state, the high-level signal terminal can transmit the high-level signal to the first drive signal terminal via the on-state first sub-circuit, at which point the potential of the first drive signal terminal is the high-level signal being written. The first sub-circuit can be turned on or off under the combined action of the first and second driving signals. It should be noted that, ideally, the voltages of the first and second driving signals are equal. When either the first or second driving signal acts alone on the first sub-circuit, the first sub-circuit cannot conduct and remains in the off state, preventing the high-level signal from being connected. The first sub-circuit can only conduct when both the first and second driving signals act together. When the first sub-circuit is in the conducting state, the high-level signal terminal is electrically connected to the first driving signal terminal. Referring to the preceding text, before the high-level signal is written, the potential of the first driving signal terminal is less than or equal to the high-level signal. After the high-level signal is written, the potential of the first driving signal terminal is pulled high or maintained at a high level, thus allowing the high-level signal to be used as the gate driving signal for the TFT, ensuring the normal operation of the TFT. In other words, the high-level signal can reset or overwrite the potential of the first driving signal terminal to ensure that the pixel circuit connected to the first driving signal terminal receives sufficient driving voltage, guaranteeing the normal operation of the pixel circuit.

[0057] According to the above technical solution, a first sub-circuit electrically connected to the drive signal terminal and a high-level signal terminal electrically connected to the first sub-circuit are configured. The state of the first sub-circuit is controlled by a first drive signal and a second drive signal transmitted from the drive signal terminal. When the first sub-circuit is in the on state, the high-level signal terminal transmits its received high-level signal to the first drive signal terminal, causing the potential of the first drive signal terminal to change from the original first drive signal to a high-level signal. Thus, by controlling the state of the first sub-circuit, the connection of the high-level signal is controlled. The compensation of the attenuation of the first drive signal by the high-level signal is used to avoid abnormal problems caused by insufficient opening of the TFT device due to the attenuation of the first drive signal, thereby improving the display effect.

[0058] Figure 2 This is a schematic structural diagram of a drive compensation circuit provided in an embodiment of this application. In some implementations, such as... Figure 2 As shown, the drive compensation circuit also includes a first capacitor C1 and a second capacitor C2. The first sub-circuit 130 includes a first transistor T1. The first terminal a of the first capacitor C1 is electrically connected to the second drive signal terminal Gn-1, and the second terminal b of the first capacitor C1 is electrically connected to the gate g of the first transistor T1 via the first node N1. The first terminal c of the second capacitor C2 is electrically connected to the first drive signal terminal Gn, and the second terminal d of the second capacitor C2 is electrically connected to the first node N1. The first electrode 1 of the first transistor T1 is electrically connected to the high-level signal terminal 110, and the second electrode 2 of the first transistor T1 is electrically connected to the first drive signal terminal Gn. The first electrode 1 can be the source of the first transistor T1, and correspondingly, the second electrode 2 is the drain of the first transistor T1. Alternatively, the first electrode 1 can be the drain of the first transistor T1, and correspondingly, the second electrode 2 is the source of the first transistor T1.

[0059] Figure 3 This is a timing diagram of a driving circuit provided in an embodiment of this application. For example, as described above, the driving time of the second driving signal Gn-1 for the pixel circuit is before the driving time of the first driving signal Gn for the pixel circuit, such as... Figure 3 As shown, the effective level start point t1 of the second driving signal Gn-1 can be regarded as the start point of the driving time of the second driving signal Gn-1 on the pixel circuit. The effective level start point t2 of the first driving signal Gn can be regarded as the start point of the driving time of the first driving signal Gn on the pixel circuit, where t1 precedes t2. Figure 2 and Figure 3As shown, the second driving signal Gn-1 starts at a high level at time t1. When the second driving signal Gn-1 is high, the gate voltage of the first transistor T1 is raised due to the influence of the first capacitor C1. For example, the first terminal a of the first capacitor C1 receives this high-level signal. According to the capacitance characteristics, the signal output from the second terminal b of the first capacitor C1 is different from the signal received by the first terminal a. Therefore, the gate voltage V1 of the first transistor T1 is less than that of the second driving signal V. Gn-1 Furthermore, in conjunction with the preceding text, VGH≥V Gn-1 Therefore, V1 < VGH, and the first transistor T1 cannot be turned on normally and is in the off state. Figure 2 and Figure 3 As shown, at time t2, when both the first driving signal Gn and the second driving signal Gn-1 are high-level signals, the first driving signal Gn can further raise the gate voltage of the first transistor T1 to V2 through the second capacitor C2, where V2 > V1. Combining this with the preceding description, the voltages of the first driving signal Gn and the second driving signal Gn-1 are equal, and they are superimposed to provide voltage to the gate g of the first transistor T1. At this time, the voltage of gate g, V2 > VGH, and the first transistor T1 is turned on. The high-level signal terminal 110 is connected to the first driving signal terminal, and the high-level signal terminal 110 can provide the high-level signal VGH to the first driving signal terminal, achieving voltage compensation for the first driving signal terminal.

[0060] Therefore, by adding a first capacitor and a second capacitor to the drive compensation circuit, the voltage compensation of the drive signal transmitted through the drive signal terminal can be achieved by controlling the drive signal of the adjacent drive signal terminal. This avoids the connection between adjacent drive signal terminals, which could lead to timing errors and other problems. The circuit structure is simple, avoiding the increase in the bezel of the display panel where the drive compensation circuit is applied due to a complex circuit structure, thus affecting the display effect.

[0061] In some implementations, such as Figure 2 As shown, the drive compensation circuit may further include a second sub-circuit 140. A first terminal of the second sub-circuit 140 is electrically connected to the first node N1, and a second terminal of the second sub-circuit 140 is electrically connected to a third drive signal terminal 123 among a plurality of drive signal terminals. The second sub-circuit 140 is used to be turned on or off under the action of the third drive signal Gn+4. The third drive signal terminal 123 is used to transmit the third drive signal Gn+4, and the driving time of the third drive signal Gn+4 on the pixel circuit is after the driving time of the first drive signal Gn on the pixel circuit. When the second sub-circuit 140 is in the on state, the first drive signal Gn is transmitted to the first capacitor C1.

[0062] It should be noted that the third driving signal can be any signal that drives the pixel circuit later than the first driving signal. Figure 2The third drive signal shown as Gn+4 is merely an example; the third drive signal can be Gn+x, where x can be set according to the number of clock signals in the drive circuit. For example, when the number of clock signals is 8, x = 8 ÷ 2 = 4. Figure 2 For example, the first driving signal is Gn, and the third driving signal is Gn+4. If Gn is used to drive the nth row of pixel circuits, then Gn+4 is used to drive the (n+4)th row of pixel circuits. Figure 2 and Figure 3 As shown, time t3 marks the end of the effective level of the second drive signal Gn-1. The second drive signal Gn-1 begins to enter a low level, at which point the gate voltage of the first transistor T1 is pulled low back to V1, the first transistor T1 is turned off, and thus the connection between the high-level signal terminal 110 and the first drive signal terminal 122 is broken. Since no other load is connected to the first drive signal terminal 122, it can maintain a high-level signal potential. Time t4 marks the end of the effective level of the first drive signal Gn and is also the start of the effective level of the third drive signal Gn+4. Furthermore, before time t4, the second drive signal Gn-1 is a low-level signal. Figure 2 As shown, when the third driving signal Gn+4 is high, the second sub-circuit 140 is turned on, and the first driving signal Gn is low. The first driving signal terminal 122 is connected to the second terminal b of the first capacitor C1 via the second sub-circuit 140, pulling the voltage at the second terminal b of the first capacitor C1 down to VGL (Gate Low Voltage). At the same time, the second terminal b of the first capacitor C1 is at the same potential as the gate g of the first transistor T1, that is, pulling the gate voltage of the first transistor T1 down to VGL. Time t5 is the effective end point of the third driving signal Gn+4. After this, the third driving signal Gn+4 is converted to a low-level signal, the second transistor T2 is turned off, the gate reset of the first transistor T1 is completed, and the next round of voltage compensation can begin.

[0063] This achieves the reset of the first transistor T1, preventing it from being superimposed on the drive signal of the next write operation and affecting the opening degree of the first transistor T1, thereby affecting the voltage compensation effect of the first drive signal terminal.

[0064] In some implementations, such as Figure 3As shown, the effective start point of the first driving signal (time t2) is before the effective end point of the second driving signal (time t3), and the effective end point of the first driving signal (time t4) is after the effective end point of the second driving signal (time t3). That is, time t3 is located between time t2 and time t4, and the first driving signal Gn and the second driving signal Gn-1 have a simultaneous high-level period (t2-t3). This ensures that the first transistor has sufficient turn-on time, providing enough time for voltage compensation and ensuring effective compensation of the potential at the first driving signal terminal. Figure 4 This is a schematic comparison diagram showing the voltage compensation process before and after, as provided in an embodiment of this application. For example, Figure 4 (a) represents the potential change during the transmission of the drive signal to the TFT under ideal conditions, such as Figure 4 As shown in (a), VGL rapidly changes to VGH and remains constant for 4H, where H can represent the scan time of a row of pixel circuits. Within 4H, the first 3H is the pre-charging process for the TFT, meaning the drive signal is prepared with a high-level signal VGH before being sent to the TFT gate. The last 1H is the process of sending the prepared VGH to the TFT gate, driving the TFT to turn on. Figure 4 (b) shows the potential change during the transmission of the drive signal from one side to the TFT corresponding to the non-driven side. For example... Figure 4 As shown in (b), the driving signal is attenuated when it is transmitted to the non-driving side. Therefore, the potential of the driving signal cannot reach VGH during the pre-charging stage, which affects the degree of opening of the TFT device during the charging stage and causes display abnormalities. Figure 4 (c) The potential change of the drive signal supplied to the TFT after the addition of the drive compensation circuit. Figure 4 (a) In comparison, Figure 4 (c) It also achieved a 3-hour pre-charge, 1-hour charge, and maintained the potential at VGH before the charging phase. Furthermore, compared with... Figure 4 (a) In comparison, Figure 4 (c) The process of the potential changing from VGL to VGH is relatively gentle, which avoids the device from being damaged by breakdown.

[0065] In some implementations, such as Figure 3As shown, the effective level endpoint of the second driving signal Gn-1 is located at the first position time of the effective level of the first driving signal Gn, i.e., time t3. The duration of the effective level of the first driving signal before time t3 is the first duration, i.e., the t2-t3 period. The duration of the effective level of the first driving signal after time t3 is the second duration, i.e., the t3-t4 period. The sum of the first duration t2-t3 and the second duration t3-t4 is the third duration, i.e., the total effective level duration of the first driving signal t2-t4. The ratio of the third duration to the scan duration H of a row of pixel circuits is the first value, and the number of clock signals in the driving circuit is twice the first value. For example, if the number of clock signals in the driving circuit is 8, then the first value is 4, i.e., the third duration is 4H. To ensure sufficient compensation time, the pre-charge (compensation) time can be set to 3H, and the charging (driving TFT) time can be set to 1H.

[0066] In some implementations, such as Figure 2 As shown, the second sub-circuit 140 may include a second transistor T2. The gate of the second transistor T2 is electrically connected to the third drive signal terminal 123, the first electrode of the second transistor T2 is electrically connected to the first node N1, and the second electrode of the second transistor T2 is electrically connected to the first drive signal terminal 122 via the second node N2. The first terminal d of the second capacitor C2 is electrically connected to the first node N1, and the second terminal c of the second capacitor C2 is electrically connected to the second node N2. Figure 2 As shown, the second transistor T2 is connected in parallel with the second capacitor C2. When the third drive signal is a high-level signal, the second transistor starts to conduct under the influence of the high-level signal. When the second transistor is conducting, the first drive signal terminal can be connected to the second terminal of the first capacitor and the gate of the first transistor through the second transistor. When the first drive signal is a low-level signal, the voltage of the second terminal of the first capacitor and the gate voltage of the first transistor can be pulled low, thereby resetting the first transistor.

[0067] The circuit structure described above is simple, avoiding problems such as signal delay and widening of the display panel bezel caused by introducing too many components, thus effectively ensuring the display effect.

[0068] Figure 5 This is a schematic block diagram of another drive compensation circuit provided in an embodiment of this application. Exemplary examples include... Figure 5As shown, the drive compensation circuit can include N stages. The second sub-circuit 120 in the Nth stage drive compensation circuit is electrically connected to the reset signal terminal. The second sub-circuit in the Nth stage drive compensation circuit is used to turn on or off under the action of the reset signal CLR. The reset signal terminal is used to transmit the reset signal CLR, where N is a natural number greater than 0. The first drive signal corresponding to the nth stage drive compensation circuit is used to drive the pixel circuit in the nth row, the second drive signal corresponding to the nth stage drive compensation circuit is used to drive the pixel circuit in the (n-1)th row, and the third drive signal corresponding to the nth stage drive compensation circuit is used to drive the pixel circuit in the (n+x)th row, where n and x are natural numbers greater than 0, and n+x≤N. For example, refer to... Figure 2 and Figure 3 x = 4. For example, x can also take the value of 2, 3 or 5, etc., depending on the number of clock signals in the driving circuit.

[0069] For example, the drive compensation circuit is used to compensate the voltage of the drive signal, therefore the drive compensation circuit can be configured one-to-one with the drive circuit used to generate the drive signal. For example... Figure 1 As shown, the first-stage drive compensation circuit can be used to compensate the voltage of the first drive signal, thereby driving the first row of pixel circuits with the compensated first drive signal. The second drive signal G1 in the first-stage drive compensation circuit can be an initial signal preset based on experience or actual needs. Under the action of this initial signal, the voltage of the first drive signal G2 generated by the first-stage drive circuit can be compensated. The specific compensation process is as described above and will not be repeated here. Thus, the first row of pixel circuits can be driven with the compensated first drive signal G2. After voltage compensation of the first drive signal G2, the first sub-circuit can be reset using the third drive signal G6 to ensure the accuracy of voltage compensation for the next frame's drive signal. Simultaneously, the first drive signal G2 can also serve as the second drive signal in the next-stage drive compensation circuit, acting together with the first drive signal G3 in the next-stage drive compensation circuit to achieve voltage compensation for the first drive signal G3 in the next stage. Similarly, multi-stage drive signal compensation can be achieved through cascading, reducing signal input. For the last stage drive compensation circuit, the reset signal CLR can be used as the control signal for the second sub-circuit. Compared with its own third drive signal, the drive compensation circuit can be reset by external input. This can achieve double protection for the reset operation together with the third drive signal, further ensuring the reliability of the reset result.

[0070] According to a second aspect of this application, a driving circuit is also proposed. Figure 6 This is a schematic block diagram of a driving circuit provided in an embodiment of this application. For example, as shown... Figure 6As shown, the drive circuit 300 may include: multiple drive sub-circuits 310 and the drive compensation circuit 100 as described above. The drive compensation circuit 100 is electrically connected to the drive sub-circuits 310, and the multiple drive sub-circuits 310 are used to provide multiple drive signals to the drive compensation circuit 100. Different drive signals are output by different drive sub-circuits 310.

[0071] It should be noted that the driving sub-circuit may include circuitry for providing driving signals to the pixel circuit, and may also include circuitry for other purposes. Therefore, the number of driving sub-circuits is greater than or equal to the number of driving compensation circuits. The driving compensation circuit is electrically connected one-to-one with the driving sub-circuit for providing driving signals to the pixel circuit. The driving compensation circuit performs voltage compensation on the driving signal provided by the driving sub-circuit, and then transmits the compensated driving signal back to the driving signal terminal of the driving sub-circuit, which can then provide the voltage-compensated driving signal to the pixel circuit.

[0072] For example, such as Figure 6 As shown, in some embodiments, the drive compensation circuit 100 and the drive sub-circuit 310 are connected via a drive signal line 320, which is used for electrical connection with the pixel circuit. The drive signal line can be used to transmit drive signals from the drive sub-circuit to the pixel circuit. For each stage of the drive sub-circuit, it can be connected to the corresponding drive compensation circuit on the same drive signal line. For each row of pixel circuits, it is electrically connected to a drive signal line and is driven and controlled by the drive signal generated by the first-stage drive sub-circuit. For example, for the first-stage drive sub-circuit, after generating the drive signal, it can transmit the drive signal to the drive compensation circuit via the drive signal line. According to the above technical solution, the drive compensation circuit performs voltage compensation on the drive signal. Then, the compensated drive signal can be transmitted to the pixel circuit via the drive signal line, and the pixel circuit can drive the display under the action of the compensated drive signal.

[0073] Therefore, the driver sub-circuit, driver compensation circuit and pixel circuit are all connected to the driver signal line, so that multiple signals flow on the driver signal line. The wiring is simple, easy to produce and less prone to errors.

[0074] In some implementations, the voltage value of the first drive signal output from the driver sub-circuit, transmitted to the first drive signal terminal via the drive signal line, is less than the voltage value of the high-level signal. For example, as described above, the voltage values ​​of the first drive signal output from the driver sub-circuit are substantially equal to those of the high-level signal, but due to signal attenuation during transmission on the drive signal line, combined with… Figure 6 The drive sub-circuit 310 generates a drive signal, which is transmitted to the drive compensation circuit 100 via the drive signal line 320. (See also...) Figure 2 and Figure 3In the drive compensation circuit 100, the drive signal terminal receives the drive signal from the drive signal line 320 and transmits it to the gate of the first transistor T1. The first drive signal Gn and the second drive signal Gn-1 work together on the gate of the first transistor T1 to turn it on. This connects the high-level signal terminal 110 to the first drive signal terminal, allowing VGH to compensate for the attenuated drive signal received at the first drive signal terminal. Afterward, the compensated high-level signal is transmitted to the pixel circuit via the drive signal line 320, completing the compensation operation of the drive signal and improving the display effect.

[0075] According to a third aspect of this application, a display panel is also proposed. Figure 7 This is a schematic block diagram of a display panel provided in an embodiment of this application. For example, as shown... Figure 7 As shown, the display panel 700 may include: a plurality of pixel circuits 200 and a driving circuit 300 as described above, wherein the driving circuit 300 is electrically connected to the pixel circuits 200.

[0076] Figure 8 A schematic block diagram of another display panel provided in an embodiment of this application. Exemplary, such as... Figure 8 As shown, the display panel 700 may further include: a display area 710 and a non-display area 720. The display area 710 is provided with multiple pixel circuits 200 arranged in rows and columns. The non-display area 720 surrounds the display area 710. The driving sub-circuit and the driving compensation circuit can both be located within the non-display area. Figure 8 The pixel circuit 200 in the text is merely exemplary and does not imply a specific limitation on the arrangement or number of pixel circuits. For a single-sided driven display panel 700, i.e., when the driving sub-circuit 310 is only provided in the non-display area 720 on one side of the display area 710 of the display panel 700, the driving sub-circuit 310 can be arranged as follows: Figure 8 On the left side of the display area 710, the drive compensation circuit 100 can be located on the opposite side of the display area 710 or on an adjacent side, and the drive sub-circuit 310 is electrically connected to the drive compensation circuit 100. In some embodiments, the drive sub-circuit can also be located on the right side of the display area, and the drive compensation circuit electrically connected to the drive sub-circuit can be located on the opposite side of the display area or on an adjacent side.

[0077] Figure 9 This is a schematic block diagram of yet another display panel provided in an embodiment of this application. For example, as shown... Figure 9As shown, for a dual-sided driven display panel 700, where driving sub-circuits 310 are provided in the non-display areas 720 on both sides of the display area 710 of the display panel 700, driving compensation circuits 100 are also provided on both sides of the display area 710. Each driving compensation circuit 100 is electrically connected to the driving sub-circuit 310 on the opposite side. That is, the driving compensation circuit 100 on the right side is electrically connected to the driving sub-circuit 310 on the left side, and the driving compensation circuit 100 on the left side is electrically connected to the driving sub-circuit 310 on the right side.

[0078] for Figure 8 The single-sided driven display panel shown can be configured such that the side containing the driving sub-circuit is the driving side, while other sides can be considered non-driving sides, or the side opposite the driving side can be considered a non-driving side. Potential compensation can be performed on the driving signal transmitted to the non-driving side when there is no driving signal output on the non-driving side and the signal output from the driving side attenuates upon transmission to the non-driving side. For Figure 9 The dual-side driven display panel shown can compensate for the potential of the drive signal by using the drive compensation circuit electrically connected to the other side in the event of a failure on one side of the drive signal terminal, thereby ensuring the display effect of the display panel.

[0079] According to the fourth aspect of this application, a display device is also proposed. Figure 10 This is a schematic block diagram of a display device provided in an embodiment of this application. For example, as shown... Figure 10 As shown, the display device 800 may include the display panel 700 as described above.

[0080] For example, the display device 800 of this application embodiment can be applied to scenarios such as in-vehicle displays, smartphones, computers, medical displays, televisions, and smart wearable displays. Smart wearable devices may include smartwatches, AR (augmented reality) devices, and VR (virtual reality) devices.

[0081] The embodiments in this application are not specifically limited. In conjunction with the foregoing, the drive compensation circuit of the display panel described above can compensate for the potential of the drive signal that has attenuated due to the transmission process in the display device, thereby avoiding abnormal problems caused by insufficient opening of the TFT device and improving the display effect of the display device.

[0082] Those skilled in the art can understand the specific details and beneficial effects of the display panel and display device by reading the above description of the drive compensation circuit and drive circuit, which will not be repeated here for the sake of brevity.

[0083] In the several embodiments provided in this application, it should be understood that the disclosed apparatus and / or device can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative; for instance, the division of units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be through some interfaces; the indirect coupling or communication connection between apparatuses or units may be electrical, mechanical, or other forms.

[0084] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0085] Furthermore, the functional units in the various embodiments of this application can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or as a software functional unit.

[0086] The above embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit it. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this application.

Claims

1. A drive compensation circuit, characterized in that, Applied to display panels, the display panels include pixel circuitry, and the drive compensation circuitry includes: The circuit includes a high-level signal terminal, multiple drive signal terminals, and a first sub-circuit. The drive signal terminals are used to transmit drive signals. Different drive signals are used to drive the operation of different pixel circuits. The drive signals include a first drive signal and a second drive signal. The second drive signal drives the pixel circuit before the first drive signal drives the pixel circuit. The driving signal terminal includes a first driving signal terminal and a second driving signal terminal. The first driving signal terminal is used to transmit a first driving signal, and the second driving signal terminal is used to transmit a second driving signal. The first driving signal terminal is used to electrically connect to the corresponding driven pixel circuit. The first sub-circuit is electrically connected to the high-level signal terminal, the first driving signal terminal, and the second driving signal terminal, respectively. The first sub-circuit is used to turn on or off under the action of the first driving signal and the second driving signal. When the first sub-circuit is turned on, the high-level signal received at the high-level signal terminal is transmitted to the first drive signal terminal, and the potential of the first drive signal terminal is a high-level signal.

2. The drive compensation circuit according to claim 1, characterized in that, It also includes a first capacitor and a second capacitor, and the first sub-circuit includes a first transistor; The first terminal of the first capacitor is electrically connected to the second driving signal terminal, the second terminal of the first capacitor is electrically connected to the gate of the first transistor via the first node, the first terminal of the second capacitor is electrically connected to the first driving signal terminal, the second terminal of the second capacitor is electrically connected to the first node, the first electrode of the first transistor is electrically connected to the high-level signal terminal, and the second electrode of the first transistor is electrically connected to the first driving signal terminal. The first electrode is one of the source and drain of the first transistor, and the second electrode is the other of the source and drain of the first transistor.

3. The drive compensation circuit according to claim 2, characterized in that, Also includes: The second sub-circuit has a first terminal electrically connected to the first node and a second terminal electrically connected to the third driving signal terminal among multiple driving signal terminals. The second sub-circuit is used to turn on or off under the action of the third driving signal. The third driving signal terminal is used to transmit the third driving signal. The driving time of the third driving signal on the pixel circuit is after the driving time of the first driving signal on the pixel circuit. When the second sub-circuit is in the on state, the first drive signal is transmitted to the first capacitor.

4. The drive compensation circuit according to claim 3, characterized in that, The second sub-circuit includes a second transistor, the gate of which is electrically connected to a third drive signal terminal, the first electrode of which is electrically connected to a first node, the second electrode of which is electrically connected to the first drive signal terminal via a second node, the first terminal of which is electrically connected to the first node, and the second terminal of which is electrically connected to the second node.

5. The drive compensation circuit according to claim 3, characterized in that, The drive compensation circuit includes N stages. The second sub-circuit in the Nth stage drive compensation circuit is electrically connected to the reset signal terminal. The second sub-circuit in the Nth stage drive compensation circuit is used to turn on or off under the action of the reset signal. The reset signal terminal is used to transmit the reset signal. Here, N is a natural number greater than 0. The first driving signal corresponding to the nth-level driving compensation circuit is used to drive the pixel circuit in the nth row, the second driving signal corresponding to the nth-level driving compensation circuit is used to drive the pixel circuit in the (n-1)th row, and the third driving signal corresponding to the nth-level driving compensation circuit is used to drive the pixel circuit in the (n+x)th row, where n and x are natural numbers greater than 0, and n+x≤N.

6. A driving circuit, characterized in that, include: Multiple driver sub-circuits; The drive compensation circuit according to any one of claims 1 to 5 is electrically connected to the drive sub-circuit, and the multiple drive sub-circuits are used to provide multiple drive signals to the drive compensation circuit, and the different drive signals are output by different drive sub-circuits.

7. The driving circuit according to claim 6, characterized in that, The drive compensation circuit and the drive sub-circuit are connected via drive signal lines, which are used to electrically connect to the pixel circuit.

8. The driving circuit according to claim 7, characterized in that, The voltage value of the first drive signal output from the driver sub-circuit is less than the voltage value of the high-level signal when it is transmitted to the first drive signal terminal via the drive signal line.

9. The driving circuit according to claim 6, characterized in that, The effective level start point of the first driving signal is before the effective level end point of the second driving signal, and the effective level end point of the first driving signal is after the effective level end point of the second driving signal.

10. The driving circuit according to claim 9, characterized in that, The effective level endpoint of the second driving signal is located at the first position time of the effective level of the first driving signal. The duration of the effective level of the first driving signal before the first position time is the first duration, and the duration of the effective level of the first driving signal after the first position time is the second duration.

11. The driving circuit according to claim 10, characterized in that, The sum of the first duration and the second duration is the third duration. The ratio of the third duration to the scanning duration of a row of pixel circuits is the first value. The number of clock signals in the driving circuit is twice the first value.

12. The driving circuit according to claim 6, characterized in that, The effective level start point of the third driving signal is the effective level end point of the first driving signal.

13. A display panel, characterized in that, include: Multiple pixel circuits; The driving circuit according to any one of claims 6 to 12 is electrically connected to the pixel circuit.

14. The display panel according to claim 13, characterized in that, include: The display area has multiple rows and columns of pixel circuits. The driving sub-circuit is located on one side of the display area, and the driving compensation circuit, which is electrically connected to the driving sub-circuit, is located on the other side of the display area.

15. A display device, characterized in that, Including the display panel as claimed in claim 13 or 14.

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