Pixel circuit, driving method and display device

Abstract

The application provides a pixel circuit, a driving method and a display device. The pixel circuit comprises a light emitting element, a first light emitting control circuit, a second light emitting control circuit and a light emitting control voltage control circuit; under the control of input signals, reset signals and light emitting control signals, the light emitting control voltage control circuit controls a light emitting control voltage provided by a light emitting control voltage terminal according to a light emitting control data voltage provided by a light emitting control data voltage terminal, a on-off data voltage provided by a on-off data voltage terminal and a control data voltage provided by a control data terminal. The pixel circuit provided by the embodiment of the application can realize full gray scale PWM (pulse width modulation) driving, completely replace PAM (pulse amplitude modulation) and greatly reduce power consumption and heat generation.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of display, in particular to a pixel circuit, a driving method and a display device. BACKGROUND

[0002] The related pixel circuit cannot realize full gray scale PWM (pulse width modulation) driving, cannot completely replace PAM (pulse amplitude modulation), and has high power consumption and high heat generation. SUMMARY

[0003] In one aspect, the embodiments of the present application provide a pixel circuit, comprising a light emitting element, a first light emitting control circuit, a second light emitting control circuit and a light emitting control voltage control circuit.

[0004] The first light emitting control circuit is electrically connected with a light emitting control voltage end, a power voltage end and a first node respectively, and is used for controlling the communication between the power voltage end and the first node under the control of a light emitting control voltage provided by the light emitting control voltage end.

[0005] The second light emitting control circuit is electrically connected with a light emitting control end, the first node and a first electrode of the light emitting element respectively, and is used for controlling the communication between the first node and the first electrode of the light emitting element under the control of a light emitting control signal provided by the light emitting control end; a second electrode of the light emitting element is electrically connected with a first voltage end.

[0006] The light emitting control voltage control circuit is electrically connected with the light emitting control voltage end, a light emitting control input end, a light emitting control reset end, the light emitting control end, a light emitting control data voltage end, a on-off data voltage end and a control data end respectively, and is used for controlling the light emitting control voltage provided by the light emitting control voltage end under the control of an input signal provided by the light emitting control input end, a reset signal provided by the light emitting control reset end and a light emitting control signal provided by the light emitting control end, according to a light emitting control data voltage provided by the light emitting control data voltage end, a on-off data voltage provided by the on-off data voltage end and a control data voltage provided by the control data end.

[0007] Optionally, the light emitting control voltage control circuit comprises an input circuit, a reset circuit, a on-off control circuit, a first control circuit, a second control circuit and a first control node control circuit.

[0008] The input circuit is electrically connected with the light emitting control input end, a second voltage end and the light emitting control voltage end respectively, and is used for controlling the communication between the light emitting control voltage end and the second voltage end under the control of an input signal provided by the light emitting control input end.

[0009] The reset circuit is electrically connected with the light-emitting control reset end and the on-off control node respectively, and is used for controlling the potential of the on-off control node under the control of a reset signal provided by the light-emitting control reset end.

[0010] The on-off control circuit is electrically connected with the on-off control node, the third voltage end and the light-emitting control voltage end respectively, and is used for controlling the communication between the light-emitting control voltage end and the third voltage end under the control of the potential of the on-off control node.

[0011] The first control circuit is electrically connected with the light-emitting control reset end, the on-off control node and the first intermediate node respectively, and is used for controlling the communication between the on-off control node and the first intermediate node under the control of the reset signal.

[0012] The second control circuit is electrically connected with the first control node, the first intermediate node and the fourth voltage end respectively, and is used for controlling the communication between the first intermediate node and the fourth voltage end under the control of the potential of the first control node.

[0013] The first control node control circuit is electrically connected with the first control node, the light-emitting control end, a light-emitting control data voltage end, an on-off data voltage end and a control data end respectively, and is used for controlling the potential of the first control node according to the light-emitting control data voltage, the on-off data voltage and the control data voltage under the control of a light-emitting control signal provided by the light-emitting control end.

[0014] Optionally, the pixel circuit further comprises a first intermediate node control circuit.

[0015] The first intermediate node control circuit is electrically connected with the light-emitting control voltage end, the first intermediate node and the fourth voltage end respectively, and is used for controlling the communication between the first intermediate node and the fourth voltage end under the control of a light-emitting control voltage provided by the light-emitting control voltage end.

[0016] Optionally, the pixel circuit further comprises a first energy storage circuit and a second energy storage circuit.

[0017] The first energy storage circuit is electrically connected with the light-emitting control voltage end, and is used for maintaining the potential of the light-emitting control voltage end.

[0018] The second energy storage circuit is electrically connected with the on-off control node, and is used for maintaining the potential of the on-off control node.

[0019] Optionally, the first control node control circuit comprises a third control circuit, a fourth control circuit and a second control node control circuit.

[0020] The third control circuit is electrically connected with the second control node, the fifth voltage terminal and the first control node respectively, and is configured to control the communication between the first control node and the fifth voltage terminal under the control of the potential of the second control node.

[0021] The fourth control circuit is electrically connected with the sixth voltage terminal and the first control node respectively, and is configured to control the potential of the first control node.

[0022] The second control node control circuit is electrically connected with the second control node, the light-emitting control terminal, the light-emitting control data voltage terminal, the on-off data voltage terminal and the control data terminal respectively, and is configured to control the potential of the second control node according to the light-emitting control data voltage, the on-off data voltage and the control data voltage under the control of the light-emitting control signal provided by the light-emitting control terminal.

[0023] Optionally, the second control node control circuit comprises a first data writing circuit, a second data writing circuit, a fifth control circuit, a sixth control circuit and a seventh control circuit.

[0024] The first data writing circuit is electrically connected with the light-emitting control terminal, the light-emitting control data voltage terminal and the second control node respectively, and is configured to write the light-emitting control data voltage into the second control node under the control of the light-emitting control signal.

[0025] The second data writing circuit is electrically connected with the light-emitting control terminal, the on-off data voltage terminal and the third control node respectively, and is configured to write the on-off data voltage provided by the on-off data voltage terminal into the third control node under the control of the light-emitting control signal.

[0026] The fifth control circuit is electrically connected with the third control node, the control data terminal and the fourth control node respectively, and is configured to write the control data voltage into the fourth control node under the control of the potential of the third control node.

[0027] The sixth control circuit is electrically connected with the third control node, the sixth voltage terminal, the fourth control node and the sixth voltage terminal.

[0028] The seventh control circuit is electrically connected with the fourth control node, the fifth voltage terminal and the second control node respectively, and is configured to control the communication between the second control node and the fifth voltage terminal under the control of the potential of the fourth control node.

[0029] Optionally, the first control node control circuit comprises an eighth control circuit and the second control node control circuit.

[0030] The eighth control circuit is electrically connected with the light emitting control end, the second control node and the first control node respectively, and is used for controlling the communication between the first control node and the second control node under the control of the light emitting control signal provided by the light emitting control end.

[0031] The second control node control circuit is electrically connected with the light emitting control end, the driving control end, the light emitting control data voltage end, the on-off data voltage end and the control data end respectively, and is used for controlling the potential of the second control node according to the light emitting control data voltage, the on-off data voltage and the control data voltage under the control of the light emitting control signal provided by the light emitting control end and the driving control signal provided by the driving control end.

[0032] Optionally, the second control node control circuit comprises a first data writing circuit, a second data writing circuit, a fifth control circuit, a sixth control circuit and a seventh control circuit.

[0033] The first data writing circuit is electrically connected with the driving control end, the light emitting control data voltage end and the second control node respectively, and is used for writing the light emitting control data voltage into the second control node under the control of the driving control signal.

[0034] The second data writing circuit is electrically connected with the light emitting control end, the on-off data voltage end and the third control node respectively, and is used for writing the on-off data voltage provided by the on-off data voltage end into the third control node under the control of the light emitting control signal.

[0035] The fifth control circuit is electrically connected with the third control node, the control data end and the fourth control node respectively, and is used for writing the control data voltage into the fourth control node under the control of the potential of the third control node.

[0036] The sixth control circuit is electrically connected with the third control node, the sixth voltage end and the fourth control node respectively, and is used for controlling the communication between the fourth control node and the sixth voltage end under the control of the potential of the third control node.

[0037] The seventh control circuit is electrically connected with the fourth control node, the sixth voltage end and the second control node respectively, and is used for controlling the communication between the second control node and the sixth voltage end under the control of the potential of the fourth control node.

[0038] Optionally, the pixel circuit further comprises a third energy storage circuit and a fourth energy storage circuit.

[0039] The third energy storage circuit is electrically connected with the second control node, and is used for maintaining the potential of the second control node.

[0040] The fourth energy storage circuit is electrically connected with the third control node, and is used for maintaining the potential of the third control node.

[0041] Optionally, the input circuit comprises a first transistor, the reset circuit comprises a second transistor, the on-off control circuit comprises a third transistor, the first control circuit comprises a fourth transistor, and the second control circuit comprises a fifth transistor.

[0042] The gate of the first transistor is electrically connected with the light-emitting control input end, the first pole of the first transistor is electrically connected with the second voltage end, and the second pole of the first transistor is electrically connected with the light-emitting control voltage end.

[0043] The gate of the second transistor and the first pole of the second transistor are both electrically connected with the light-emitting control reset end, and the second pole of the second transistor is electrically connected with the on-off control node.

[0044] The gate of the third transistor is electrically connected with the on-off control node, the first pole of the third transistor is electrically connected with the third voltage end, and the second pole of the third transistor is electrically connected with the light-emitting control voltage end.

[0045] The gate of the fourth transistor is electrically connected with the light-emitting control reset end, the first pole of the fourth transistor is electrically connected with the on-off control node, and the second pole of the fourth transistor is electrically connected with the first intermediate node.

[0046] The gate of the fifth transistor is electrically connected with the first control node, the first pole of the fifth transistor is electrically connected with the first intermediate node, and the second pole of the fifth transistor is electrically connected with the fourth voltage end.

[0047] Optionally, the first intermediate node control circuit comprises a sixth transistor.

[0048] The gate of the sixth transistor is electrically connected with the light-emitting control voltage end, the first pole of the sixth transistor is electrically connected with the fourth voltage end, and the second pole of the sixth transistor is electrically connected with the first intermediate node.

[0049] Optionally, the third control circuit comprises a seventh transistor, and the fourth control circuit comprises an eighth transistor.

[0050] The gate of the seventh transistor is electrically connected with the second control node, the first pole of the seventh transistor is electrically connected with the fifth voltage end, and the second pole of the seventh transistor is electrically connected with the first control node.

[0051] The gate of the eighth transistor and the first pole of the eighth transistor are electrically connected with the sixth voltage terminal, and the second pole of the eighth transistor is electrically connected with the first control node.

[0052] Optionally, the first data writing circuit comprises a ninth transistor, the second data writing circuit comprises a tenth transistor, the fifth control circuit comprises an eleventh transistor, the sixth control circuit comprises a twelfth transistor, and the seventh control circuit comprises a thirteenth transistor.

[0053] The gate of the ninth transistor is electrically connected with the light-emitting control terminal, the first pole of the ninth transistor is electrically connected with the light-emitting control data voltage terminal, and the second pole of the ninth transistor is electrically connected with the second control node.

[0054] The gate of the tenth transistor is electrically connected with the light-emitting control terminal, the first pole of the tenth transistor is electrically connected with the on-off data voltage terminal, and the second pole of the tenth transistor is electrically connected with the third control node.

[0055] The gate of the eleventh transistor is electrically connected with the third control node, the first pole of the eleventh transistor is electrically connected with the control data terminal, and the second pole of the eleventh transistor is electrically connected with the fourth control node.

[0056] The gate of the twelfth transistor is electrically connected with the third control node, the first pole of the twelfth transistor is electrically connected with the sixth voltage terminal, and the second pole of the twelfth transistor is electrically connected with the fourth control node.

[0057] The gate of the thirteenth transistor is electrically connected with the fourth control node, the first pole of the thirteenth transistor is electrically connected with the fifth voltage terminal, and the second pole of the thirteenth transistor is electrically connected with the second control node.

[0058] Optionally, the eighth control circuit comprises a fourteenth transistor.

[0059] The gate of the fourteenth transistor is electrically connected with the light-emitting control terminal, the first pole of the fourteenth transistor is electrically connected with the second control node, and the second pole of the fourteenth transistor is electrically connected with the first control node.

[0060] Optionally, the first data writing circuit comprises a ninth transistor, the second data writing circuit comprises a tenth transistor, the fifth control circuit comprises an eleventh transistor, the sixth control circuit comprises a twelfth transistor, and the seventh control circuit comprises a thirteenth transistor.

[0061] The gate of the ninth transistor is electrically connected with the driving control end, the first pole of the ninth transistor is electrically connected with the light-emitting control data voltage end, and the second pole of the ninth transistor is electrically connected with the second control node;

[0062] The gate of the tenth transistor is electrically connected with the light-emitting control end, the first pole of the tenth transistor is electrically connected with the on-off data voltage end, and the second pole of the tenth transistor is electrically connected with the third control node;

[0063] The gate of the eleventh transistor is electrically connected with the third control node, the first pole of the eleventh transistor is electrically connected with the control data end, and the second pole of the eleventh transistor is electrically connected with the fourth control node;

[0064] The gate of the twelfth transistor is electrically connected with the third control node, the first pole of the twelfth transistor is electrically connected with the sixth voltage end, and the second pole of the twelfth transistor is electrically connected with the fourth control node;

[0065] The gate of the thirteenth transistor is electrically connected with the fourth control node, the first pole of the thirteenth transistor is electrically connected with the sixth voltage end, and the second pole of the thirteenth transistor is electrically connected with the second control node.

[0066] Optionally, the first light-emitting control circuit comprises a fifteenth transistor, and the second light-emitting control circuit comprises a sixteenth transistor;

[0067] The gate of the fifteenth transistor is electrically connected with the light-emitting control voltage end, the first pole of the fifteenth transistor is electrically connected with the power voltage end, and the second pole of the fifteenth transistor is electrically connected with the first node;

[0068] The gate of the sixteenth transistor is electrically connected with the light-emitting control end, the first pole of the sixteenth transistor is electrically connected with the first node, and the second pole of the sixteenth transistor is electrically connected with the first pole of the light-emitting element.

[0069] In a second aspect, an embodiment of the present application provides a driving method applied to the pixel circuit, and the driving method comprises the following steps:

[0070] The first light-emitting control circuit controls the communication between the power voltage end and the first node under the control of the light-emitting control voltage;

[0071] The second light-emitting control circuit controls the communication between the first node and the first pole of the light-emitting element under the control of the light-emitting control signal;

[0072] The light emitting control voltage control circuit controls the light emitting control voltage provided by the light emitting control voltage terminal according to the light emitting control data voltage provided by the light emitting control data voltage terminal, the on-off data voltage provided by the on-off data voltage terminal and the control data voltage provided by the control data terminal under the control of the input signal provided by the light emitting control input terminal, the reset signal provided by the light emitting control reset terminal and the light emitting control signal provided by the light emitting control terminal.

[0073] In a third aspect, the embodiment of the present application provides a display device comprising the pixel circuit. BRIEF DESCRIPTION OF DRAWINGS

[0074] Figure 1 is a structural diagram of the pixel circuit according to at least one embodiment of the present application;

[0075] Figure 2 is a structural diagram of the pixel circuit according to at least one embodiment of the present application;

[0076] Figure 3 is a structural diagram of the pixel circuit according to at least one embodiment of the present application;

[0077] Figure 4 is a structural diagram of the pixel circuit according to at least one embodiment of the present application;

[0078] Figure 5 is a structural diagram of the pixel circuit according to at least one embodiment of the present application;

[0079] Figure 6 is a structural diagram of the pixel circuit according to at least one embodiment of the present application;

[0080] Figure 7 is a structural diagram of the pixel circuit according to at least one embodiment of the present application;

[0081] Figure 8A is a structural diagram of the pixel circuit according to at least one embodiment of the present application;

[0082] Figure 8B is Figure 8A is a simulation working timing diagram of at least one embodiment of the pixel circuit shown in

[0083] Figure 8C and Figure 8D is a simulation working timing diagram of at least one embodiment of the pixel circuit shown in Figure 8A

[0084] Figure 9A is a structural diagram of the pixel circuit according to at least one embodiment of the present application;

[0085] Figure 9B is Figure 9A ​At least one embodiment of the pixel circuit shown in operation, the simulation working timing diagram when high gray scale display;

[0086] Figure 9C is Figure 8A At least one embodiment of the pixel circuit shown in operation, the simulation working timing diagram when low gray scale display;

[0087] Figure 10A is the circuit diagram of the pixel circuit described in at least one embodiment of the application;

[0088] Figure 10B is Figure 10A At least one embodiment of the pixel circuit shown in operation, the simulation working timing diagram when high gray scale display;

[0089] Figure 10C and Figure 10D is Figure 10A At least one embodiment of the pixel circuit shown in operation, the simulation working timing diagram when low gray scale display;

[0090] Figure 11A is the circuit diagram of the pixel circuit described in at least one embodiment of the application;

[0091] Figure 11B is Figure 11A At least one embodiment of the pixel circuit shown in operation, the simulation working timing diagram when high gray scale display;

[0092] Figure 11C is Figure 11A At least one embodiment of the pixel circuit shown in operation, the simulation working timing diagram when low gray scale display;

[0093] Figure 12A is the circuit diagram of the pixel circuit described in at least one embodiment of the application;

[0094] Figure 12B is Figure 12A At least one embodiment of the pixel circuit shown in operation, the simulation working timing diagram when high gray scale display;

[0095] Figure 12C is Figure 12A At least one embodiment of the pixel circuit shown in operation, the simulation working timing diagram when low gray scale display;

[0096] Figure 13A is the circuit diagram of the pixel circuit described in at least one embodiment of the application;

[0097] Figure 13B is Figure 13A At least one embodiment of the pixel circuit shown in operation, the simulation working timing diagram when high gray scale display;

[0098] Figure 13C is Figure 13A the simulation working timing diagram of at least one embodiment of the pixel circuit shown in FIG. 6 when displaying a low gray scale;

[0099] Figure 14A is a circuit diagram of the pixel circuit described in at least one embodiment of the present application;

[0100] Figure 14B is Figure 14A the simulation working timing diagram of at least one embodiment of the pixel circuit shown in FIG. 6 when displaying a high gray scale;

[0101] Figure 14C is Figure 14A the simulation working timing diagram of at least one embodiment of the pixel circuit shown in FIG. 6 when displaying a low gray scale;

[0102] Figure 15A is a circuit diagram of the pixel circuit described in at least one embodiment of the present application;

[0103] Figure 15B is Figure 15A the simulation working timing diagram of at least one embodiment of the pixel circuit shown in FIG. 6 when displaying a high gray scale;

[0104] Figure 15C is Figure 15A the simulation working timing diagram of at least one embodiment of the pixel circuit shown in FIG. 6 when displaying a low gray scale. DETAILED DESCRIPTION

[0105] The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only some of the embodiments of the present application, but not all the embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative work fall within the protection scope of the present application.

[0106] The transistors used in all the embodiments of the present application can be thin film transistors or field effect transistors or other devices with the same characteristics. In the embodiments of the present application, in order to distinguish the two poles of the transistor except the gate, one pole is called the first pole and the other pole is called the second pole.

[0107] In actual operation, when the transistor is a thin film transistor or a field effect transistor, the first pole can be a drain and the second pole can be a source, or the first pole can be a source and the second pole can be a drain.

[0108] As Figure 1As shown, the pixel circuit in the embodiment of the present application comprises a light emitting element E1, a first light emitting control circuit 11, a second light emitting control circuit 12 and a light emitting control voltage control circuit 13.

[0109] The first light emitting control circuit 11 is electrically connected with a light emitting control voltage terminal HFO, a power voltage terminal ELVDD and a first node N1 respectively, and is used for controlling the communication between the power voltage terminal ELVDD and the first node N1 under the control of the light emitting control voltage provided by the light emitting control voltage terminal HFO.

[0110] The second light emitting control circuit 12 is electrically connected with a light emitting control terminal EM, the first node N1 and a first pole of the light emitting element E1 respectively, and is used for controlling the communication between the first node N1 and the first pole of the light emitting element E1 under the control of a light emitting control signal provided by the light emitting control terminal EM; a second pole of the light emitting element E1 is electrically connected with a first voltage terminal V1.

[0111] The light emitting control voltage control circuit 13 is electrically connected with the light emitting control voltage terminal HFO, a light emitting control input terminal HFI, a light emitting control reset terminal HFR, the light emitting control terminal EM, a light emitting control data voltage terminal DE, a on-off data voltage terminal DS and a control data terminal DC respectively, and is used for controlling the light emitting control voltage provided by the light emitting control voltage terminal HFO under the control of an input signal provided by the light emitting control input terminal HFI, a reset signal provided by the light emitting control reset terminal HFR and a light emitting control signal provided by the light emitting control terminal EM, according to a light emitting control data voltage provided by the light emitting control data voltage terminal DE, a on-off data voltage provided by the on-off data voltage terminal DS and a control data voltage provided by the control data terminal DC.

[0112] In the working process of the pixel circuit in the embodiment of the present application, the light emitting control voltage control circuit can control the duty cycle of the light emitting control voltage according to the light emitting control data voltage, the on-off data voltage and the control data voltage under the control of the input signal, the reset signal and the light emitting control signal, and then control the second light emitting control circuit 12 to control the communication time between the first node N1 and the first pole of the light emitting element E1, and further control the light emitting brightness of the light emitting element E1. The pixel circuit in the embodiment of the present application can realize full gray scale PWM (pulse width modulation) driving, completely replace PAM (pulse amplitude modulation), and greatly reduce power consumption and heat generation.

[0113] Optionally, the first voltage terminal can be a low level terminal, but is not limited thereto.

[0114] As shown in Figure 2 the first node N1 is electrically connected with a second voltage terminal V2, and the second voltage terminal V2 is electrically connected with a second node N2. Figure 1Based on the embodiment of the pixel circuit shown, in the pixel circuit according to at least one embodiment of the present application, the light-emitting control voltage control circuit comprises an input circuit 21, a reset circuit 22, a pass-through control circuit 23, a first control circuit 24, a second control circuit 25 and a first control node control circuit 26.

[0115] The input circuit 21 is electrically connected with the light-emitting control input terminal HFI, the second voltage terminal V2 and the light-emitting control voltage terminal HFO respectively, for controlling the communication between the light-emitting control voltage terminal HFO and the second voltage terminal V2 under the control of the input signal provided by the light-emitting control input terminal HFI.

[0116] The reset circuit 22 is electrically connected with the light-emitting control reset terminal HFR and the pass-through control node Q respectively, for controlling the potential of the pass-through control node Q under the control of the reset signal provided by the light-emitting control reset terminal HFR.

[0117] The pass-through control circuit 23 is electrically connected with the pass-through control node Q, the third voltage terminal V3 and the light-emitting control voltage terminal HFO respectively, for controlling the communication between the light-emitting control voltage terminal HFO and the third voltage terminal V3 under the control of the potential of the pass-through control node Q.

[0118] The first control circuit 24 is electrically connected with the light-emitting control reset terminal HFR, the pass-through control node Q and the first intermediate node NZ1 respectively, for controlling the communication between the pass-through control node Q and the first intermediate node NZ1 under the control of the reset signal.

[0119] The second control circuit 25 is electrically connected with the first control node S, the first intermediate node NZ1 and the fourth voltage terminal V4 respectively, for controlling the communication between the first intermediate node NZ1 and the fourth voltage terminal V4 under the control of the potential of the first control node S.

[0120] The first control node control circuit 26 is electrically connected with the first control node S, the light-emitting control terminal EM, the light-emitting control data voltage terminal DE, the pass-through data voltage terminal DS and the control data terminal DC respectively, for controlling the potential of the first control node S according to the light-emitting control data voltage, the pass-through data voltage and the control data voltage under the control of the light-emitting control signal provided by the light-emitting control terminal EM.

[0121] Optionally, the second voltage terminal can be a low voltage terminal, the third voltage terminal can be a high voltage terminal, and the fourth voltage terminal can be a low voltage terminal.

[0122] The pixel circuit according to at least one embodiment of the present application further comprises a first intermediate node control circuit.

[0123] The first intermediate node control circuit is electrically connected with the light-emitting control voltage terminal, the first intermediate node and the fourth voltage terminal respectively, and is configured to control the communication between the first intermediate node and the fourth voltage terminal under the control of the light-emitting control voltage provided by the light-emitting control voltage terminal.

[0124] In a specific implementation, the pixel circuit further includes a first intermediate node control circuit configured to control the communication between the first intermediate node and the fourth voltage terminal under the control of the light-emitting control voltage provided by the light-emitting control voltage terminal.

[0125] As shown in Figure 3 As shown in Figure 2 Based on at least one embodiment of the pixel circuit shown in

[0126] The first intermediate node control circuit 31 is electrically connected with the light-emitting control voltage terminal HFO, the first intermediate node NZ1 and the fourth voltage terminal V4 respectively, and is configured to control the communication between the first intermediate node NZ1 and the fourth voltage terminal V4 under the control of the light-emitting control voltage provided by the light-emitting control voltage terminal HFO.

[0127] The pixel circuit according to at least one embodiment of the present application further includes a first energy storage circuit and a second energy storage circuit.

[0128] The first energy storage circuit is electrically connected with the light-emitting control voltage terminal, and is configured to maintain the potential of the light-emitting control voltage terminal.

[0129] The second energy storage circuit is electrically connected with the on-off control node, and is configured to maintain the potential of the on-off control node.

[0130] In a specific implementation, the pixel circuit further includes a first energy storage circuit and a second energy storage circuit, the first energy storage circuit maintains the potential of the light-emitting control voltage terminal, and the second energy storage circuit maintains the potential of the on-off control node.

[0131] Optionally, the first control node control circuit includes a third control circuit, a fourth control circuit and a second control node control circuit.

[0132] The third control circuit is electrically connected with the second control node, a fifth voltage terminal and the first control node respectively, and is configured to control the communication between the first control node and the fifth voltage terminal under the control of the potential of the second control node.

[0133] The fourth control circuit is electrically connected with a sixth voltage terminal and the first control node respectively, and is configured to control the potential of the first control node.

[0134] The control circuit of the second control node is electrically connected to the second control node, the light emission control terminal, the light emission control data voltage terminal, the on / off data voltage terminal, and the control data terminal, respectively. It is used to control the potential of the second control node according to the light emission control data voltage, the on / off data voltage, and the control data voltage under the control of the light emission control signal provided by the light emission control terminal.

[0135] In a specific implementation, the first control node control circuit may include a third control circuit, a fourth control circuit, and a second control node control circuit; the third control circuit controls the potential of the first control node under the control of the potential of the second control node; the fourth control circuit controls the potential of the first control node; and the second control node control circuit controls the potential of the second control node under the control of the light emission control signal, according to the light emission control data voltage, the on / off data voltage, and the control data voltage.

[0136] like Figure 4 As shown, in Figure 3 Based on at least one embodiment of the pixel circuit shown, the pixel circuit of at least one embodiment of the present invention further includes a first energy storage circuit 41 and a second energy storage circuit 42;

[0137] The first energy storage circuit 41 is electrically connected to the light-emitting control voltage terminal HFO and is used to maintain the potential of the light-emitting control voltage terminal HFO;

[0138] The second energy storage circuit 42 is electrically connected to the on / off control node Q and is used to maintain the potential of the on / off control node Q;

[0139] The first control node control circuit includes a third control circuit 43, a fourth control circuit 44, and a second control node control circuit 45.

[0140] The third control circuit 43 is electrically connected to the second control node R, the fifth voltage terminal V5 and the first control node S respectively, and is used to control the connection between the first control node S and the fifth voltage terminal V5 under the control of the potential of the second control node R.

[0141] The fourth control circuit 44 is electrically connected to the sixth voltage terminal V6 and the first control node S respectively, and is used to control the potential of the first control node S.

[0142] The second control node control circuit 45 is electrically connected with the second control node R, the light emitting control end EM, the light emitting control data voltage end DE, the on-off data voltage end DS and the control data end DC respectively, for controlling the potential of the second control node R according to the light emitting control data voltage, the on-off data voltage and the control data voltage under the control of the light emitting control signal provided by the light emitting control end EM.

[0143] Optionally, the fifth voltage end can be a control voltage end and the sixth voltage end can be a low voltage end, but not limited thereto.

[0144] In at least one embodiment of the present application, the second control node control circuit comprises a first data writing circuit, a second data writing circuit, a fifth control circuit, a sixth control circuit and a seventh control circuit.

[0145] The first data writing circuit is electrically connected with the light emitting control end, the light emitting control data voltage end and the second control node respectively, for writing the light emitting control data voltage into the second control node under the control of the light emitting control signal.

[0146] The second data writing circuit is electrically connected with the light emitting control end, the on-off data voltage end and the third control node respectively, for writing the on-off data voltage provided by the on-off data voltage end into the third control node under the control of the light emitting control signal.

[0147] The fifth control circuit is electrically connected with the third control node, the control data end and the fourth control node respectively, for writing the control data voltage into the fourth control node under the control of the potential of the third control node.

[0148] The sixth control circuit is electrically connected with the third control node, the sixth voltage end and the fourth control node respectively, for controlling the communication between the fourth control node and the sixth voltage end under the control of the potential of the third control node.

[0149] The seventh control circuit is electrically connected with the fourth control node, the fifth voltage end and the second control node respectively, for controlling the communication between the second control node and the fifth voltage end under the control of the potential of the fourth control node.

[0150] In a specific implementation, the second control node control circuit may include a first data writing circuit, a second data writing circuit, a fifth control circuit, a sixth control circuit, and a seventh control circuit; the first data writing circuit, under the control of the light emission control signal, writes the light emission control data voltage into the second control node; the second data writing circuit, under the control of the light emission control signal, writes the on / off data voltage into the third control node; the fifth control circuit, under the control of the potential of the third control node, writes the control data voltage into the fourth control node; the sixth control circuit, under the control of the potential of the third control node, controls the connection between the fourth control node and the sixth voltage terminal; the seventh control circuit, under the control of the potential of the fourth control node, controls the connection between the second control node and the fifth voltage terminal.

[0151] The pixel circuit described in at least one embodiment of the present invention further includes a third energy storage circuit and a fourth energy storage circuit;

[0152] The third energy storage circuit is electrically connected to the second control node and is used to maintain the potential of the second control node;

[0153] The fourth energy storage circuit is electrically connected to the third control node and is used to maintain the potential of the third control node.

[0154] In a specific implementation, the pixel circuit may include a third energy storage circuit and a fourth energy storage circuit, wherein the third energy storage circuit maintains the potential of the second control node; and the fourth energy storage circuit maintains the potential of the third control node.

[0155] like Figure 5 As shown, in Figure 4 Based on at least one embodiment of the pixel circuit shown, the second control node control circuit includes a first data writing circuit 51, a second data writing circuit 52, a fifth control circuit 53, a sixth control circuit 54, and a seventh control circuit 55; the pixel circuit described in at least one embodiment of the present invention also includes a third energy storage circuit 71 and a fourth energy storage circuit 72.

[0156] The first data writing circuit 51 is electrically connected to the light-emitting control terminal EM, the light-emitting control data voltage terminal DE, and the second control node R, respectively, and is used to write the light-emitting control data voltage into the second control node R under the control of the light-emitting control signal;

[0157] The second data writing circuit 52 is connected to the light-emitting control terminal EM, the on / off data voltage terminal DS, and the third control node NC3, respectively, and is used to write the on / off data voltage provided by the on / off data voltage terminal DS into the third control node NC3 under the control of the light-emitting control signal.

[0158] The fifth control circuit 53 is electrically connected with the third control node NC3, the control data terminal DC and the fourth control node NC4 respectively, and is configured to write the control data voltage into the fourth control node NC4 under the control of the potential of the third control node NC3.

[0159] The sixth control circuit 54 is electrically connected with the third control node NC3, the sixth voltage terminal V6 and the fourth control node NC4 respectively, and is configured to control the communication between the fourth control node NC4 and the sixth voltage terminal V6 under the control of the potential of the third control node NC3.

[0160] The seventh control circuit 55 is electrically connected with the fourth control node NC4, the fifth voltage terminal V5 and the second control node R respectively, and is configured to control the communication between the second control node R and the fifth voltage terminal V5 under the control of the potential of the fourth control node NC4.

[0161] The third energy storage circuit 71 is electrically connected with the second control node R, and is configured to maintain the potential of the second control node R.

[0162] The fourth energy storage circuit 72 is electrically connected with the third control node NC3, and is configured to maintain the potential of the third control node NC3.

[0163] In at least one embodiment of the present application, the first control node control circuit comprises an eighth control circuit and a second control node control circuit.

[0164] The eighth control circuit is electrically connected with the light-emitting control terminal, the second control node and the first control node respectively, and is configured to control the communication between the first control node and the second control node under the control of the light-emitting control signal provided by the light-emitting control terminal.

[0165] The second control node control circuit is electrically connected with the light-emitting control terminal, the driving control terminal, the light-emitting control data voltage terminal, the on-off data voltage terminal and the control data terminal respectively, and is configured to control the potential of the second control node according to the light-emitting control data voltage, the on-off data voltage and the control data voltage under the control of the light-emitting control signal provided by the light-emitting control terminal and the driving control signal provided by the driving control terminal.

[0166] In a specific implementation, the first control node control circuit can include an eighth control circuit and a second control node control circuit; the eighth control circuit controls the communication between the first control node and the second control node under the control of the light emission control signal; and the second control node control circuit controls the potential of the second control node according to the light emission control data voltage, the on-off data voltage and the control data voltage under the control of the light emission control signal and the drive control signal.

[0167] As shown in Figure 6 As shown in Figure 3 Based on at least one embodiment of the pixel circuit shown in

[0168] The first energy storage circuit 41 is electrically connected with the light emission control voltage terminal HFO, and is used for maintaining the potential of the light emission control voltage terminal HFO.

[0169] The second energy storage circuit 42 is electrically connected with the on-off control node Q, and is used for maintaining the potential of the on-off control node Q.

[0170] The first control node control circuit includes an eighth control circuit 61 and a second control node control circuit 62.

[0171] The eighth control circuit 61 is electrically connected with the light emission control terminal EM, the second control node R and the first control node S respectively, and is used for controlling the communication between the first control node S and the second control node R under the control of the light emission control signal provided by the light emission control terminal EM.

[0172] The second control node control circuit 62 is electrically connected with the second control node R, the light emission control terminal EM, the drive control terminal GA, the light emission control data voltage terminal DE, the on-off data voltage terminal DS and the control data terminal DC respectively, and is used for controlling the potential of the second control node R according to the light emission control data voltage, the on-off data voltage and the control data voltage under the control of the light emission control signal provided by the light emission control terminal EM and the drive control signal provided by the drive control terminal GA.

[0173] In at least one embodiment of the present application, the second control node control circuit includes a first data writing circuit, a second data writing circuit, a fifth control circuit, a sixth control circuit and a seventh control circuit.

[0174] The first data writing circuit is electrically connected with the drive control terminal, the light emission control data voltage terminal and the second control node respectively, and is used for writing the light emission control data voltage into the second control node under the control of the drive control signal.

[0175] The second data writing circuit is connected to the light-emitting control terminal, the on / off data voltage terminal, and the third control node, respectively, and is used to write the on / off data voltage provided by the on / off data voltage terminal to the third control node under the control of the light-emitting control signal;

[0176] The fifth control circuit is electrically connected to the third control node, the control data terminal, and the fourth control node, respectively, and is used to write the control data voltage into the fourth control node under the control of the potential of the third control node;

[0177] The sixth control circuit is electrically connected to the third control node, the sixth voltage terminal and the fourth control node respectively, and is used to control the connection between the fourth control node and the sixth voltage terminal under the control of the potential of the third control node;

[0178] The seventh control circuit is electrically connected to the fourth control node, the sixth voltage terminal, and the second control node, respectively, and is used to control the connection between the second control node and the sixth voltage terminal under the control of the potential of the fourth control node.

[0179] In specific implementation, the second control node control circuit includes a first data writing circuit, a second data writing circuit, a fifth control circuit, a sixth control circuit, and a seventh control circuit; the first data writing circuit, under the control of the driving control signal, writes the light emission control data voltage into the second control node; the second data writing circuit, under the control of the light emission control signal, writes the on / off data voltage into the third control node; the fifth control circuit, under the control of the potential of the third control node, writes the control data voltage into the fourth control node; the sixth control circuit, under the control of the potential of the third control node, controls the connection between the fourth control node and the sixth voltage terminal; the seventh control circuit, under the control of the potential of the fourth control node, controls the connection between the second control node and the sixth voltage terminal.

[0180] like Figure 7 As shown, in Figure 6 Based on at least one embodiment of the pixel circuit shown, the second control node control circuit includes a first data writing circuit 73, a second data writing circuit 74, a fifth control circuit 75, a sixth control circuit 76, and a seventh control circuit 77; the pixel circuit described in at least one embodiment of the present invention also includes a third energy storage circuit 71 and a fourth energy storage circuit 72.

[0181] The first data writing circuit 73 is electrically connected with the driving control end GA, the light-emitting control data voltage end DE and the second control node R respectively, and is configured to write the light-emitting control data voltage into the second control node R under the control of the driving control signal;

[0182] The second data writing circuit 74 is electrically connected with the light-emitting control end EM, the on-off data voltage end DS and the third control node NC3 respectively, and is configured to write the on-off data voltage provided by the on-off data voltage end DS into the third control node NC3 under the control of the light-emitting control signal;

[0183] The fifth control circuit 75 is electrically connected with the third control node NC3, the control data end DC and the fourth control node NC4 respectively, and is configured to write the control data voltage into the fourth control node NC4 under the control of the potential of the third control node NC3;

[0184] The sixth control circuit 76 is electrically connected with the third control node NC3, the sixth voltage end V6 and the fourth control node NC4 respectively, and is configured to control the communication between the fourth control node NC4 and the sixth voltage end V6 under the control of the potential of the third control node NC3;

[0185] The seventh control circuit 77 is electrically connected with the fourth control node NC4, the sixth voltage end V6 and the second control node R respectively, and is configured to control the communication between the second control node R and the sixth voltage end V6 under the control of the potential of the fourth control node NC4;

[0186] The third energy storage circuit 71 is electrically connected with the second control node R, and is configured to maintain the potential of the second control node R;

[0187] The fourth energy storage circuit 72 is electrically connected with the third control node NC3, and is configured to maintain the potential of the third control node NC3.

[0188] Optionally, the input circuit comprises a first transistor, the reset circuit comprises a second transistor, the on-off control circuit comprises a third transistor, the first control circuit comprises a fourth transistor, and the second control circuit comprises a fifth transistor;

[0189] The gate of the first transistor is electrically connected with the light-emitting control input end, the first pole of the first transistor is electrically connected with the second voltage end, and the second pole of the first transistor is electrically connected with the light-emitting control voltage end;

[0190] The gate of the second transistor and the first pole of the second transistor are electrically connected with the light-emitting control reset end, and the second pole of the second transistor is electrically connected with the on-off control node;

[0191] The gate of the third transistor is electrically connected with the on-off control node, the first pole of the third transistor is electrically connected with the third voltage end, and the second pole of the third transistor is electrically connected with the light-emitting control voltage end;

[0192] The gate of the fourth transistor is electrically connected with the light-emitting control reset end, the first pole of the fourth transistor is electrically connected with the on-off control node, and the second pole of the fourth transistor is electrically connected with the first intermediate node;

[0193] The gate of the fifth transistor is electrically connected with the first control node, the first pole of the fifth transistor is electrically connected with the first intermediate node, and the second pole of the fifth transistor is electrically connected with the fourth voltage end.

[0194] Optionally, the first intermediate node control circuit comprises a sixth transistor;

[0195] The gate of the sixth transistor is electrically connected with the light-emitting control voltage end, the first pole of the sixth transistor is electrically connected with the fourth voltage end, and the second pole of the sixth transistor is electrically connected with the first intermediate node.

[0196] Optionally, the third control circuit comprises a seventh transistor, and the fourth control circuit comprises an eighth transistor;

[0197] The gate of the seventh transistor is electrically connected with the second control node, the first pole of the seventh transistor is electrically connected with the fifth voltage end, and the second pole of the seventh transistor is electrically connected with the first control node;

[0198] The gate of the eighth transistor and the first pole of the eighth transistor are electrically connected with the sixth voltage end, and the second pole of the eighth transistor is electrically connected with the first control node.

[0199] Optionally, the first data write-in circuit comprises a ninth transistor, the second data write-in circuit comprises a tenth transistor, the fifth control circuit comprises an eleventh transistor, the sixth control circuit comprises a twelfth transistor, and the seventh control circuit comprises a thirteenth transistor;

[0200] The gate of the ninth transistor is electrically connected with the light-emitting control end, the first pole of the ninth transistor is electrically connected with the light-emitting control data voltage end, and the second pole of the ninth transistor is electrically connected with the second control node;

[0201] The gate of the tenth transistor is electrically connected with the light-emitting control end, the first pole of the tenth transistor is electrically connected with the on-off data voltage end, and the second pole of the tenth transistor is electrically connected with the third control node;

[0202] The gate of the eleventh transistor is electrically connected with the third control node, the first pole of the eleventh transistor is electrically connected with the control data end, and the second pole of the eleventh transistor is electrically connected with the fourth control node;

[0203] The gate of the twelfth transistor is electrically connected with the third control node, the first pole of the twelfth transistor is electrically connected with the sixth voltage end, and the second pole of the twelfth transistor is electrically connected with the fourth control node;

[0204] The gate of the thirteenth transistor is electrically connected with the fourth control node, the first pole of the thirteenth transistor is electrically connected with the fifth voltage end, and the second pole of the thirteenth transistor is electrically connected with the second control node.

[0205] Optionally, the eighth control circuit comprises a fourteenth transistor;

[0206] The gate of the fourteenth transistor is electrically connected with the light-emitting control end, the first pole of the fourteenth transistor is electrically connected with the second control node, and the second pole of the fourteenth transistor is electrically connected with the first control node.

[0207] Optionally, the first data write-in circuit comprises a ninth transistor, the second data write-in circuit comprises a tenth transistor, the fifth control circuit comprises an eleventh transistor, the sixth control circuit comprises a twelfth transistor, and the seventh control circuit comprises a thirteenth transistor;

[0208] The gate of the ninth transistor is electrically connected with the driving control end, the first pole of the ninth transistor is electrically connected with the light-emitting control data voltage end, and the second pole of the ninth transistor is electrically connected with the second control node;

[0209] The gate of the tenth transistor is electrically connected with the light-emitting control end, the first pole of the tenth transistor is electrically connected with the on-off data voltage end, and the second pole of the tenth transistor is electrically connected with the third control node;

[0210] The gate of the eleventh transistor is electrically connected with the third control node, the first pole of the eleventh transistor is electrically connected with the control data end, and the second pole of the eleventh transistor is electrically connected with the fourth control node;

[0211] A gate of the twelfth transistor is electrically connected with the third control node, a first pole of the twelfth transistor is electrically connected with the sixth voltage terminal, and a second pole of the twelfth transistor is electrically connected with the fourth control node.

[0212] A gate of the thirteenth transistor is electrically connected with the fourth control node, a first pole of the thirteenth transistor is electrically connected with the sixth voltage terminal, and a second pole of the thirteenth transistor is electrically connected with the second control node.

[0213] Optionally, the first light-emitting control circuit comprises a fifteenth transistor, and the second light-emitting control circuit comprises a sixteenth transistor.

[0214] A gate of the fifteenth transistor is electrically connected with the light-emitting control voltage terminal, a first pole of the fifteenth transistor is electrically connected with the power voltage terminal, and a second pole of the fifteenth transistor is electrically connected with the first node.

[0215] A gate of the sixteenth transistor is electrically connected with the light-emitting control terminal, a first pole of the sixteenth transistor is electrically connected with the first node, and a second pole of the sixteenth transistor is electrically connected with the first pole of the light-emitting element.

[0216] As shown in Figure 8A on the basis of at least one embodiment of the pixel circuit shown in Figure 5 The light-emitting element is an organic light-emitting diode.

[0217] The input circuit comprises a first transistor M1, the reset circuit comprises a second transistor M2, the on-off control circuit comprises a third transistor M3, the first control circuit comprises a fourth transistor M4, and the second control circuit comprises a fifth transistor M5.

[0218] A gate of the first transistor M1 is electrically connected with the light-emitting control input terminal HFI, a source of the first transistor M1 is electrically connected with the low voltage terminal VSS, and a drain of the first transistor M1 is electrically connected with the light-emitting control voltage terminal HFO.

[0219] A gate of the second transistor M2 and a source of the second transistor M2 are both electrically connected with the light-emitting control reset terminal HFR, and a drain of the second transistor M2 is electrically connected with the on-off control node Q.

[0220] A gate of the third transistor M3 is electrically connected with the on-off control node Q, a source of the third transistor M3 is electrically connected with the high voltage terminal VDD, and a drain of the third transistor M3 is electrically connected with the light-emitting control voltage terminal HFO.

[0221] A gate of the fourth transistor M4 is electrically connected with the light-emitting control reset end HFR, a source of the fourth transistor M4 is electrically connected with the on-off control node Q, and a drain of the fourth transistor M4 is electrically connected with the first intermediate node NZ1;

[0222] A gate of the fifth transistor M5 is electrically connected with the first control node S, a source of the fifth transistor M5 is electrically connected with the first intermediate node NZ1, and a drain of the fifth transistor M5 is electrically connected with the low voltage end VSS;

[0223] The first intermediate node control circuit comprises a sixth transistor M6;

[0224] A gate of the sixth transistor M6 is electrically connected with the light-emitting control voltage end HFO, a source of the sixth transistor M6 is electrically connected with the low voltage end VSS, and a drain of the sixth transistor M6 is electrically connected with the first intermediate node NZ1;

[0225] The third control circuit comprises a seventh transistor M7, and the fourth control circuit comprises an eighth transistor M8;

[0226] A gate of the seventh transistor M7 is electrically connected with the second control node R, a source of the seventh transistor M7 is electrically connected with the control voltage end VSM, and a drain of the seventh transistor M7 is electrically connected with the first control node S;

[0227] A gate of the eighth transistor M8 and a source of the eighth transistor M8 are both electrically connected with the low voltage end VSS, and a drain of the eighth transistor M8 is electrically connected with the first control node S;

[0228] The first data write-in circuit comprises a ninth transistor M9, the second data write-in circuit comprises a tenth transistor M10, the fifth control circuit comprises an eleventh transistor M11, the sixth control circuit comprises a twelfth transistor M12, and the seventh control circuit comprises a thirteenth transistor M13;

[0229] A gate of the ninth transistor M9 is electrically connected with the light-emitting control end EM, a source of the ninth transistor M9 is electrically connected with the light-emitting control data voltage end DE, and a drain of the ninth transistor M9 is electrically connected with the second control node R;

[0230] A gate of the tenth transistor M10 is electrically connected with the light-emitting control end EM, a source of the tenth transistor M10 is electrically connected with the on-off data voltage end DS, and a drain of the tenth transistor M10 is electrically connected with the third control node NC3;

[0231] A gate of the eleventh transistor M11 is electrically connected with the third control node NC3, a source of the eleventh transistor M11 is electrically connected with the control data end DC, and a drain of the eleventh transistor M11 is electrically connected with the fourth control node NC4;

[0232] A gate of the twelfth transistor M12 is electrically connected with the third control node NC3, a source of the twelfth transistor M12 is electrically connected with the low voltage end VSS, and a drain of the twelfth transistor M12 is electrically connected with the fourth control node NC4;

[0233] A gate of the thirteenth transistor M13 is electrically connected with the fourth control node NC4, a source of the thirteenth transistor M13 is electrically connected with the control voltage end VSM, and a drain of the thirteenth transistor M13 is electrically connected with the second control node R;

[0234] The first light emitting control circuit comprises a fifteenth transistor M15, and the second light emitting control circuit comprises a sixteenth transistor M16;

[0235] A gate of the fifteenth transistor M15 is electrically connected with the light emitting control voltage end HFO, a source of the fifteenth transistor M15 is electrically connected with the power voltage end ELVDD, and the fifteenth transistor M15 is electrically connected with the first node N1;

[0236] A gate of the sixteenth transistor M16 is electrically connected with the light emitting control end EM, a source of the sixteenth transistor M16 is electrically connected with the first node N1, and a drain of the sixteenth transistor M16 is electrically connected with an anode of the organic light emitting diode O1; a cathode of the organic light emitting diode O1 is electrically connected with the low voltage end ELVSS;

[0237] The first energy storage circuit comprises a first capacitor C1, and the second energy storage circuit comprises a second capacitor C2;

[0238] A first end of the first capacitor C1 is electrically connected with the light emitting control voltage end HFO, and a second end of the first capacitor C1 is electrically connected with the low voltage end VSS;

[0239] A first end of the second capacitor C2 is electrically connected with the on-off control node Q, and a second end of the second capacitor C2 is electrically connected with the low voltage end VSS;

[0240] The third energy storage circuit comprises a third capacitor C3, and the fourth energy storage circuit comprises a fourth capacitor C4;

[0241] A first end of the third capacitor C3 is electrically connected with the second control node R, and a second end of the third capacitor C3 is electrically connected with the control voltage end VSM;

[0242] The first terminal of the fourth capacitor C4 is electrically connected to the third control node NC3, and the second terminal of the fourth capacitor C4 is electrically connected to the low voltage terminal VSS.

[0243] exist Figure 8A In at least one embodiment shown, M1 is a p-type transistor, M2 is an n-type transistor, M3 is a p-type transistor, M4 is a p-type transistor, M5 is an n-type transistor, M6 is an n-type transistor, M7 is a p-type transistor, M8 is a p-type transistor, M9 is a p-type transistor, M10 is a p-type transistor, M11 is a p-type transistor, M12 is an n-type transistor, M13 is a p-type transistor, M15 is an n-type transistor, and M16 is an n-type transistor.

[0244] exist Figure 8A In at least one of the embodiments shown, the control voltage terminal VSM can provide a negative voltage signal, for example, VSM can provide a -4V voltage signal.

[0245] exist Figure 8A In at least one embodiment shown, the second voltage terminal is a low voltage terminal VSS, the third voltage terminal is a high voltage terminal VDD, the fourth voltage terminal is a low voltage terminal VSS, the fifth voltage terminal is a control voltage terminal VSM, and the sixth voltage terminal is a low voltage terminal VSS.

[0246] exist Figure 8A In at least one embodiment shown, the high voltage terminal VDD can provide a 14V voltage signal, the low voltage terminal VSS can provide a -14V voltage signal, VSM can provide a -4V voltage signal, ELVDD can provide a 5V voltage signal, and ELVSS can provide a 0V voltage signal.

[0247] The high voltage value of the input signal provided by HFI is 16V, the low voltage value of the input signal provided by HFI is -16V, the input signal provided by HFI is a square wave signal, the period of the input signal provided by HFI is 100μs, and the ratio of the time the potential of the input signal is maintained at low voltage to the time the potential of the input signal is maintained at high voltage is 5 / 95.

[0248] The high voltage value of the reset signal provided by HFR is 25V, the low voltage value of the reset signal provided by HFR is -16V, the reset signal provided by HFR is a square wave signal, the period of the reset signal provided by HFR is 100μs, and the ratio of the time the potential of the reset signal is maintained at low voltage to the time the potential of the reset signal is maintained at high voltage is 96 / 4.

[0249] DE can provide -4.694V, -4.7V, -4.8V, -4.9V, and -5V voltage signals sequentially.

[0250] The DS can provide a -14V voltage signal or a 14V voltage signal;

[0251] Taking a display frequency of 60Hz as an example, when low gray scale display is performed, the high voltage value of the control data voltage provided by the DC can be 14V, the low voltage value of the control data voltage can be -14V, the control data voltage can be a square wave voltage, the period of the control data voltage can be 16667μs, and the ratio of the time during which the voltage value of the control data voltage is low to the time during which the voltage value of the control data voltage is high can be 300 / 16367;

[0252] Taking a display frequency of 60Hz as an example, the high voltage value of the light-emitting control signal provided by the EM can be 16V, the low voltage value of the light-emitting control signal can be -16V, the period of the light-emitting control signal can be 16667μs, and the ratio of the time during which the potential of the light-emitting control signal is low to the time during which the potential of the light-emitting control signal is high can be 200 / 16467;

[0253] The capacitance value of C1 is 50fF, the capacitance value of C2 is 50fF, the capacitance value of C3 is 50Ff, and the capacitance value of C4 is 50fF;

[0254] M1 and M2 are digital trigger TFTs (thin film transistors) and constitute a first-order digital trigger; M3, M4, M5 and M6 are duty ratio adjustment control TFTs, M9, M7 and M8 are data voltage writing and holding TFTs, and M15 and M16 are light-emitting control TFTs.

[0255] The present application Figure 8A At least one embodiment of the pixel circuit shown is in operation,

[0256] Before the start of a period (the period can last for 100μs, but is not limited thereto), the HR provides a high voltage signal, opens M2, closes M4, and resets the potential of Q to 25V, and M3 is closed;

[0257] After the start of the period, the HR provides a low voltage signal, closes M2, opens M4, the HFI opens M1, the low voltage signal provided by VSS is written to C1, the HFO outputs a low voltage signal, and M6 is closed at the same time, the Q point is discharged to VSS, and the voltage of S is written to the gate of M5, so as to control the discharging speed of the Q point by controlling the size of the saturation current Id of M5;

[0258] After a time t elapses, when the gate-source voltage Vgs discharged to M3 is less than the threshold voltage of M3, M3 is opened, the high voltage signal provided by VDD is written to C1, the HF outputs a high voltage signal, and M6 is opened at the same time, and the potential of Q is quickly discharged to a low voltage;

[0259] Before the end of the period (i.e. in the last 5us of the period), HR provides a high voltage signal, opens M2, closes M4, the potential of Q is reset to 25V, M3 is closed, C1 keeps high voltage, and HFO continuously outputs a high voltage signal;

[0260] The next period starts, and the above process is repeated.

[0261] The present application Figure 8A At least one embodiment of the pixel circuit shown in the present application works as follows: after the start of a period, the voltage of S is written to the gate of M5, the discharging speed of Q is controlled by controlling the size of the saturation current Id of M5, the time t required for the potential of Q to discharge to Vgs less than the threshold voltage of M3 is the time during which HFO continuously provides a low voltage, and by adjusting the potential of S, a light-emitting control voltage with different duty cycles can be obtained.

[0262] In the present application Figure 8A In at least one embodiment of the pixel circuit shown in the present application, M1 is a p-type transistor, at the start of a period, HFI provides a low voltage signal to open M1 and write a low voltage signal provided by VSS, after the writing is completed, HFI provides a high voltage signal to close M1, and due to the influence of the parasitic capacitance of M1, the voltage value of the light-emitting control voltage provided by HFO is pulled up, and finally the voltage value of the light-emitting control voltage is slightly higher than the voltage value of the low voltage signal provided by VSS, which causes the gate-source voltage of M6 to be greater than 0, resulting in the risk of incomplete closing of M6 and thus leakage. Based on this, in the present application Figure 9A In at least one embodiment of the pixel circuit shown in the present application, M1 is set to an n-type transistor, at the start of a period, HFI provides a high voltage signal to open M1 and write a low voltage signal, after the writing is completed, HFI provides a low voltage signal to close M1, and due to the influence of the parasitic capacitance of M1, the voltage value of the light-emitting control voltage provided by HFO is pulled down, at this time, the gate-source voltage of M6 is less than 0, solving the risk of opening of M6.

[0263] The present application Figure 8A At least one embodiment of the pixel circuit shown in the present application works as follows: at the start of a period, M7, M8 and M9 are responsible for writing and maintaining data voltage, in the data writing stage (which can last for 200us, for example), EM provides a low voltage signal to open M9, and the light-emitting control data voltage provided by DE is written to R, the potential of R controls the opening degree of M7, based on the principle of voltage division of a series circuit, the potential of S is controlled by the ratio between the resistance of M7 and the resistance of M8, and then the opening degree of M5 is controlled, and the duty cycle of the light-emitting control voltage provided by HFO is controlled.

[0264] M13, M11, M12 and M10 form a high-low gray scale switching module.

[0265] When displaying high gray scale, the duty cycle adjusting circuit works all the time, EM provides low voltage signal to open M10, DS provides 14V voltage signal to close M11, open M12, VSS provides low voltage signal to write into the gate of M13, and close M13;

[0266] When displaying low gray scale, the duty cycle adjusting circuit works only one cycle, EM provides low voltage to open M10, DS provides -14V voltage signal to open M11, close M12, DC provides control data voltage to write into the gate of M13, after EM provides high voltage signal to close M10, DC continues to provide low voltage signal to close M13 for one cycle, then DC provides high voltage signal to open M13, VSM provides control voltage to write into R, close M7, S is low voltage, close M5, cut off the path of discharging Q, M3 keeps closed, HFO continuously outputs low voltage signal.

[0267] In the specific implementation, when using PWM (pulse width modulation) driving, N gray scale duty cycle equals 255 gray scale duty cycle x (N / 255) ga ;

[0268] Wherein, ga is gamma value, for example, ga can be greater than or equal to 2.2 and less than or equal to 2.5;

[0269] The following takes the display frequency of 60Hz and the time of one display cycle of 16667μs as an example to explain the realization method of high and low gray scale.

[0270] Suppose 255 gray scale duty cycle is 100%, that is, the working time in one display cycle is 16667μs, according to the above calculation formula, 1 gray scale duty cycle equals 0.000508%, in one display cycle, the working time corresponding to 1 gray scale is 16667 x 0.000508%, that is, the working time corresponding to 1 gray scale is 0.1μs.

[0271] In at least one embodiment of the present invention, the period of the light emission control voltage provided by the HFO is 100μs. The light emission control data voltage is adjusted so that the duty cycle of the light emission control voltage provided by the HFO is 0.1%, i.e., the single-cycle working time is 0.1μs. Controlled by DC, after the EM provides a high voltage signal to open M16, the HFO only outputs a high voltage signal within 0.1μs, thus achieving 0.1μs of light emission from O1 within one display cycle, realizing a 1-grayscale display. The maximum duty cycle of the light emission control voltage provided by the HFO within a single cycle is 95%, meaning that grayscales with a working time less than or equal to 95μs can be achieved through DC control. Based on the above formula, grayscales from 1 to 24 can all be achieved through DC control. When displaying grayscales from 25 to 255, the control data voltage provided by DC needs to be turned off, and the light emission control voltage output by the HFO needs to operate at full load within the display cycle.

[0272] The above distinction between high and low grayscale is derived based on the example that the period of the light emission control voltage provided by HFO is 10000Hz and the display period is 60Hz. When the above two periods change, the distinction between high and low grayscale will also change.

[0273] In at least one embodiment of the present invention, M15 and M16 are light-emitting control transistors. When grayscale is switched, DE and DS write signals, and then EM provides a high voltage signal. The working time of M15 is controlled by the light-emitting control voltage provided by HFO, and the light-emitting time of O1 is controlled to realize grayscale display.

[0274] Figure 8B yes Figure 8A The diagram shows the timing of operation of at least one embodiment of the pixel circuit when performing high grayscale display.

[0275] like Figure 8B As shown, S1 is the first time period, S2 is the second time period, S3 is the third time period, S4 is the fourth time period, and S5 is the fifth time period.

[0276] The durations of S1, S2, S3, S4, and S5 are all 200 μs.

[0277] In S1, DE provides a -4.694V voltage signal, and the duty cycle of the light emission control voltage provided by HFO is 0.2%.

[0278] In S2, DE provides a -4.7V voltage signal, and the duty cycle of the light emission control voltage provided by HFO is 2.7%.

[0279] In S3, DE provides a -4.8V voltage signal, and the duty cycle of the light emission control voltage provided by HFO is 35.8%.

[0280] In S4, DE provides a -4.9V voltage signal, and the duty cycle of the light emission control voltage provided by HFO is 55.3%.

[0281] In S5, DE provides a -5V voltage signal, and the duty cycle of the light control voltage provided by HFO is 67.6%.

[0282] Figure 8C and Figure 8D yes Figure 8A The timing diagram of at least one embodiment of the pixel circuit shown in operation during low grayscale display is shown.

[0283] exist Figure 8C and Figure 8D In the process, the first 200μs is the data writing time, and the 200μs to 300μs is the working time. During the working time, M15 is turned on or off according to the light emission control voltage provided by HFO. After 300μs, DC provides a high voltage signal to control M13 to turn on, connecting R and VSM. M7 is turned on, connecting S and VSM. M5 is turned off. At this time, the discharge path of Q point is turned off, M3 remains in the off state, and HFO continuously outputs a low voltage signal.

[0284] exist Figure 8D In the diagram, SW represents the data writing stage, and SC represents the low grayscale working stage; SW lasts for 200μs, and SC lasts for 100μs.

[0285] Figure 9A The difference between at least one embodiment of the pixel circuit shown and at least one embodiment of the pixel circuit shown in FIG8 is that M1 is an n-type transistor.

[0286] exist Figure 9A In at least one embodiment of the pixel circuit shown, the high voltage value of the input signal provided by the HFI is 16V, the low voltage value of the input signal provided by the HFI is -14V, the input signal provided by the HFI is a square wave signal, the period of the input signal provided by the HFI is 100μs, and the ratio of the time the potential of the input signal is maintained at a high voltage to the time the potential of the input signal is maintained at a low voltage is 5 / 95.

[0287] In at least one embodiment of the present invention, the active layer material of the TFT is not limited, and various types such as a-Si (amorphous silicon), oxide (oxide), LTPS (low temperature polycrystalline silicon), and organic materials can be used.

[0288] Figure 9B yes Figure 9A The diagram shows the timing of operation of at least one embodiment of the pixel circuit when performing high grayscale display.

[0289] As shown in Figure 9B , S1 is a first time period, S2 is a second time period, S3 is a third time period, S4 is a fourth time period, and S5 is a fifth time period.

[0290] Figure 9C As shown in Figure 8A , at least one embodiment of the pixel circuit is in operation, and the working timing diagram when displaying a low gray scale.

[0291] As shown in Figure 10A , on the basis of at least one embodiment of the pixel circuit shown in Figure 5 , the light emitting element is an organic light emitting diode O1;

[0292] The input circuit includes a first transistor M1, the reset circuit includes a second transistor M2, the on-off control circuit includes a third transistor M3, the first control circuit includes a fourth transistor M4, and the second control circuit includes a fifth transistor M5.

[0293] The gate of the first transistor M1 is electrically connected with the light emitting control input end HFI, the source of the first transistor M1 is electrically connected with the high voltage end VDD, and the drain of the first transistor M1 is electrically connected with the light emitting control voltage end HFO.

[0294] The gate of the second transistor M2 and the source of the second transistor M2 are both electrically connected with the light emitting control reset end HFR, and the drain of the second transistor M2 is electrically connected with the on-off control node Q.

[0295] The gate of the third transistor M3 is electrically connected with the on-off control node Q, the source of the third transistor M3 is electrically connected with the low voltage end VSS, and the drain of the third transistor M3 is electrically connected with the light emitting control voltage end HFO.

[0296] The gate of the fourth transistor M4 is electrically connected with the light emitting control reset end HFR, the source of the fourth transistor M4 is electrically connected with the on-off control node Q, and the drain of the fourth transistor M4 is electrically connected with the first intermediate node NZ1.

[0297] The gate of the fifth transistor M5 is electrically connected with the first control node S, the source of the fifth transistor M5 is electrically connected with the first intermediate node NZ1, and the drain of the fifth transistor M5 is electrically connected with the high voltage signal end VDDL.

[0298] The first intermediate node control circuit includes a sixth transistor M6.

[0299] A gate of the sixth transistor M6 is electrically connected with the light-emitting control voltage terminal HFO, a source of the sixth transistor M6 is electrically connected with the high voltage signal terminal VDDL, and a drain of the sixth transistor M6 is electrically connected with the first intermediate node NZ1;

[0300] The third control circuit comprises a seventh transistor M7, and the fourth control circuit comprises an eighth transistor M8;

[0301] A gate of the seventh transistor M7 is electrically connected with the second control node R, a source of the seventh transistor M7 is electrically connected with the control voltage terminal VSM, and a drain of the seventh transistor M7 is electrically connected with the first control node S;

[0302] A gate of the eighth transistor M8 and a source of the eighth transistor M8 are electrically connected with the high voltage terminal VDD, and a drain of the eighth transistor M8 is electrically connected with the first control node S;

[0303] The first data write-in circuit comprises a ninth transistor M9, the second data write-in circuit comprises a tenth transistor M10, the fifth control circuit comprises an eleventh transistor M11, the sixth control circuit comprises a twelfth transistor M12, and the seventh control circuit comprises a thirteenth transistor M13;

[0304] A gate of the ninth transistor M9 is electrically connected with the light-emitting control terminal EM, a source of the ninth transistor M9 is electrically connected with the light-emitting control data voltage terminal DE, and a drain of the ninth transistor M9 is electrically connected with the second control node R;

[0305] A gate of the tenth transistor M10 is electrically connected with the light-emitting control terminal EM, a source of the tenth transistor M10 is electrically connected with the on-off data voltage terminal DS, and a drain of the tenth transistor M10 is electrically connected with the third control node NC3;

[0306] A gate of the eleventh transistor M11 is electrically connected with the third control node NC3, a source of the eleventh transistor M11 is electrically connected with the control data terminal DC, and a drain of the eleventh transistor M11 is electrically connected with the fourth control node NC4;

[0307] A gate of the twelfth transistor M12 is electrically connected with the third control node NC3, a source of the twelfth transistor M12 is electrically connected with the low voltage terminal VSS, and a drain of the twelfth transistor M12 is electrically connected with the fourth control node NC4;

[0308] The gate of the thirteenth transistor M13 is electrically connected with the fourth control node NC4, the source of the thirteenth transistor M13 is electrically connected with the control voltage terminal VSM, and the drain of the thirteenth transistor M13 is electrically connected with the second control node R;

[0309] The first light emitting control circuit comprises a fifteenth transistor M15, and the second light emitting control circuit comprises a sixteenth transistor M16;

[0310] The gate of the fifteenth transistor M15 is electrically connected with the light emitting control voltage terminal HFO, the source of the fifteenth transistor M15 is electrically connected with the power voltage terminal ELVDD, and the fifteenth transistor M15 is electrically connected with the first node N1;

[0311] The gate of the sixteenth transistor M16 is electrically connected with the light emitting control terminal EM, the source of the sixteenth transistor M16 is electrically connected with the first node N1, and the drain of the sixteenth transistor M16 is electrically connected with the anode of the organic light emitting diode O1; the cathode of the organic light emitting diode O1 is electrically connected with the low voltage terminal ELVSS;

[0312] The first energy storage circuit comprises a first capacitor C1, and the second energy storage circuit comprises a second capacitor C2;

[0313] The first end of the first capacitor C1 is electrically connected with the light emitting control voltage terminal HFO, and the second end of the first capacitor C1 is electrically connected with the high voltage terminal VDD;

[0314] The first end of the second capacitor C2 is electrically connected with the on-off control node Q, and the second end of the second capacitor C2 is electrically connected with the high voltage terminal VDD;

[0315] The third energy storage circuit comprises a third capacitor C3, and the fourth energy storage circuit comprises a fourth capacitor C4;

[0316] The first end of the third capacitor C3 is electrically connected with the second control node R, and the second end of the third capacitor C3 is electrically connected with the control voltage terminal VSM;

[0317] The first end of the fourth capacitor C4 is electrically connected with the third control node NC3, and the second end of the fourth capacitor C4 is electrically connected with the high voltage terminal VDD.

[0318] In Figure 10A In at least one embodiment shown in the figure, the second voltage terminal is the high voltage terminal VDD, the third voltage terminal is the low voltage terminal, the fourth voltage terminal is the high voltage signal terminal VDDL, the fifth voltage terminal is the control voltage terminal VSM, and the sixth voltage terminal is the high voltage terminal VDD.

[0319] Optionally, the high voltage signal end VDDL provides a high voltage signal with a voltage value slightly less than the voltage value of the high voltage signal provided by the high voltage end.

[0320] In Figure 10A In at least one embodiment shown, the control voltage end VSM can provide a positive voltage signal, for example, VSM can provide a +4V voltage signal.

[0321] In Figure 10A In at least one embodiment shown, M1 is an n-type transistor, M2 is a p-type transistor, M3 is an n-type transistor, M4 is an n-type transistor, M5 is a p-type transistor, M6 is a p-type transistor, M7 is an n-type transistor, M8 is an n-type transistor, M9 is an n-type transistor, M10 is an n-type transistor, M11 is an n-type transistor, M12 is a p-type transistor, M13 is a p-type transistor, M15 is a p-type transistor, and M16 is a p-type transistor.

[0322] In Figure 10A In at least one embodiment shown, VDD provides a 14V voltage signal, VSS provides a -14V voltage signal, VSM provides a 4V voltage signal, ELVDD provides a 5V voltage signal, and ELVSS provides a 0V voltage signal.

[0323] The high voltage value of the input signal provided by the HFI is 16V, the low voltage value of the input signal provided by the HFI is -16V, the input signal provided by the HFI is a square wave signal, the period of the input signal provided by the HFI is 100μs, and the ratio of the time during which the potential of the input signal is maintained at a high voltage to the time during which the potential of the input signal is at a low voltage is 5 / 95.

[0324] The high voltage value of the reset signal provided by the HFR is 16V, the low voltage value of the reset signal provided by the HFR is -25V, the reset signal provided by the HFR is a square wave signal, the period of the reset signal provided by the HFR is 100μs, and the ratio of the time during which the potential of the reset signal is maintained at a low voltage to the time during which the potential of the input signal is at a high voltage is 4 / 96.

[0325] The DE can provide a 6.86V voltage signal, a 6.95V voltage signal, a 7V voltage signal, a 7.1V voltage signal, a 7.2V voltage signal, and a 7.3V voltage signal in sequence.

[0326] The DS provides a -14V voltage signal or a 14V voltage signal.

[0327] Taking a display frequency of 60Hz as an example, when low gray scale display is performed, the high voltage value of the control data voltage provided by the DC can be 14V, the low voltage value of the control data voltage can be -14V, the control data voltage can be a square wave voltage, the period of the control data voltage can be 16667μs, and the ratio of the time during which the voltage value of the control data voltage is low to the time during which the voltage value of the control data voltage is high can be 300 / 16367;

[0328] Taking a display frequency of 60Hz as an example, the high voltage value of the light-emitting control signal provided by the EM can be 16V, the low voltage value of the light-emitting control signal can be -16V, the period of the light-emitting control signal can be 16667μs, and the ratio of the time during which the potential of the light-emitting control signal is high to the time during which the potential of the light-emitting control signal is low can be 200 / 16467;

[0329] The capacitance value of C1 is 50fF, the capacitance value of C2 is 50fF, the capacitance value of C3 is 50fF, and the capacitance value of C4 is 50fF.

[0330] The pixel circuit shown in the present application Figure 10A At least one embodiment of the pixel circuit shown in the present application works,

[0331] Before the start of a period (the period can last for 100μs, but is not limited thereto), the HFR provides a low voltage signal, M2 is turned on, M4 is turned off, and the potential of Q is reset to -25V, and M3 is turned off;

[0332] After the start of the period, the HFR provides a high voltage signal, M2 is turned off, M4 is turned on, the HFI provides a high voltage signal, M1 is turned on, the high voltage signal provided by VDD is written to C1, the HFO signal outputs a high voltage signal, M6 is turned off at the same time, Q is charged by VDD, the voltage at the S point is written to the gate of M5, and the charging speed of Q is controlled by controlling the saturation current Id of M5;

[0333] After a time t elapses, when the gate-source voltage Vgs charged to M3 is greater than the threshold voltage of M3, M3 is turned on, the low voltage signal provided by VSS is written to C1, the HFO outputs a low voltage signal, and M6 is turned on at the same time, and the potential of Q is raised to a high voltage by rapid charging;

[0334] Before the end of the period (i.e., in the last 5μs included in the period), the HFR provides a low voltage signal, M2 is turned on, M4 is turned off, the potential of Q is reset to -25V, M3 is turned off, C1 remains at a low voltage, and the HFO continuously outputs a low voltage signal;

[0335] The next period is started, and the above process is repeated.

[0336] The pixel circuit shown in the present applicationFigure 10A At least one embodiment of the pixel circuit shown in operation, the S point voltage is written to the gate of M5, by controlling the size of the saturation current Id of M5, the charging speed of Q point is controlled, and the time required for Q point to charge to the gate-source voltage of M3 greater than the threshold voltage of M3 is the time for HFO to continuously output a high voltage signal. By adjusting the potential of S, a light emitting control voltage with different duty cycles can be obtained.

[0337] In at least one embodiment of the pixel circuit shown in the present application Figure 10A In at least one embodiment of the pixel circuit shown in the present application

[0338] Compared with at least one embodiment of the pixel circuit shown in the present application Figure 10A In at least one embodiment of the pixel circuit shown in the present application Figure 11A In at least one embodiment of the pixel circuit shown in the present application

[0339] In at least one embodiment of the pixel circuit shown in the present application Figure 10A In at least one embodiment of the pixel circuit shown in the present application

[0340] M13, M11, M12 and M10 constitute high-low gray scale switching module, when displaying high gray scale, duty cycle adjustment circuit works all the time, EM provides high voltage signal, opens M10, DS provides-14V voltage signal, closes M11, opens M12, high voltage signal provided by VDD is written to the gate of M10, and M10 is closed; when displaying low gray scale, duty cycle adjustment circuit only works for one period, when EM provides high voltage signal, DS provides 14V voltage signal, opens M11, closes M12, DC writes control data voltage to the gate of M13, after EM provides low voltage signal, DC continues to provide high voltage signal to close M13 for one period, then DC provides low voltage signal to open M10, control voltage provided by VSM is written to R, M7 is closed, the potential of S becomes high voltage to close M5, and Q point discharge circuit is cut off, M3 is always kept closed, and HFO continuously outputs high voltage.

[0341] In the specific implementation, when PWM (pulse width modulation) driving is adopted, N gray scale duty cycle equals 255 gray scale duty cycle x (N / 255) ga ;

[0342] Wherein, ga is gamma value, for example, ga can be greater than or equal to 2.2 and less than or equal to 2.5;

[0343] The following takes the display frequency of 60Hz and the time of one display period of 16667us as an example to illustrate the realization method of high-low gray scale.

[0344] Suppose that 255 gray scale duty cycle is 100%, that is, the working time in the display period is 16667us, and the 13 gray scale duty cycle calculated by the above formula is 0.14%, and the working time corresponding to 13 gray scale in the display period is 16667*0.14%=23.9us.

[0345] In at least one embodiment of the present application, the period of the light emitting control voltage output by HFO is 100us, the voltage of the light emitting control data provided by the adjustment DE is adjusted, and the duty cycle of the light emitting control voltage output by HFO is adjusted to 23.9%, that is, the single period working time is 100us*23.9%=23.9us, and the control voltage provided by DC is controlled, after EM provides low voltage signal to open M16, in the first period, the duty cycle of the light emitting control voltage provided by HFO is 23.9%, that is, in one display period of 16667us, the light emitting circuit only works for 23.9us, and 13 gray scale display is realized.

[0346] In the present application as Figure 10AIn at least one embodiment of the pixel circuit shown, M15 and M16 are light emitting control transistors, when the gray scale is switched, DE and DS write signals, and then EM provides a low voltage signal, the light emitting control voltage provided by HFO controls the working time of M15, controls the light emitting time of O1, and realizes gray scale display.

[0347] Figure 10B is Figure 10A In at least one embodiment of the pixel circuit shown, when working, the simulation working timing diagram when high gray scale display is performed.

[0348] As Figure 10B As shown, S1 is a first time period, S2 is a second time period, S3 is a third time period, S4 is a fourth time period, and S5 is a fifth time period;

[0349] The duration of S1, the duration of S2, the duration of S3, the duration of S4, and the duration of S5 are all 200μs;

[0350] In S1, DE provides a 6.86V voltage signal, and the duty cycle of the light emitting control voltage provided by HFO is 23.9%;

[0351] In S2, DE provides a 6.95V voltage signal, and the duty cycle of the light emitting control voltage provided by HFO is 57.3%;

[0352] In S3, DE provides a 7V voltage signal, and the duty cycle of the light emitting control voltage provided by HFO is 66.9%;

[0353] In S4, DE provides a 7.1V voltage signal, and the duty cycle of the light emitting control voltage provided by HFO is 78.9%;

[0354] In S5, DE provides a 7.2V voltage signal, and the duty cycle of the light emitting control voltage provided by HFO is 85.1%.

[0355] Figure 10B It is only a simulation working timing diagram.

[0356] In actual operation, Figure 10A In at least one embodiment of the pixel circuit shown, when working, a data write stage lasting 200μs is provided before S1, in the data write stage, EM controls M16 to be turned off; and in a display period (when the display frequency is 60Hz, the display period lasts for 16667μs), DE can only provide a data voltage in the data write stage, M16 is turned on after the time period provided after the data write stage in the display period, and M15 is controlled to be turned on or turned off by the light emitting control voltage provided by HFO.

[0357] Figure 10B is simulated to illustrate the relationship between the voltage value of the light emitting control voltage provided by DE and the duty cycle of the light emitting control voltage provided by HFO.

[0358] Figure 10C and Figure 10D is Figure 10A At least one embodiment of the pixel circuit shown in

[0359] In Figure 10C and Figure 10D , the first 200μs is the data writing time, the 200th to 300thμs is the working time, during the working time, M15 is opened or closed according to the light emitting control voltage provided by HFO, after 300μs, DC provides a low voltage signal to control M13 to open, R is communicated with VSM, M7 is opened, S is communicated with VSM, M5 is closed, at this time, the discharge path of Q point is closed, M3 remains closed, and HFO continuously outputs a low voltage signal.

[0360] In Figure 10D , the label SW is the data writing stage, and the label SC is the low gray scale working stage; the duration of SW is 200μs, and the duration of SC is 100μs.

[0361] Figure 11A At least one embodiment of the pixel circuit shown in Figure 10A is different from at least one embodiment of the pixel circuit shown in

[0362] In Figure 11A , the high voltage value of the input signal provided by HFI is 16V, the low voltage value of the input signal provided by HFI is -16V, the input signal provided by HFI is a square wave signal, the period of the input signal provided by HFI is 100μs, and the ratio of the time during which the potential of the input signal is maintained at a low voltage to the time during which the potential of the input signal is at a high voltage is 5 / 95.

[0363] Figure 11B At least one embodiment of the pixel circuit shown in Figure 11A is working, and the working timing diagram during high gray scale display is shown.

[0364] As shown in Figure 11B , the label S1 is the first time period, the label S2 is the second time period, the label S3 is the third time period, the label S4 is the fourth time period, and the label S5 is the fifth time period.

[0365] Figure 11C isFigure 11A At least one embodiment of the pixel circuit shown is in operation, the working timing diagram when low gray scale display.

[0366] As Figure 12A shown, in Figure 7 At least one embodiment of the pixel circuit shown is based on, the light emitting element is organic light emitting diode O1;

[0367] The input circuit includes a first transistor M1, the reset circuit includes a second transistor M2, the on-off control circuit includes a third transistor M3, the first control circuit includes a fourth transistor M4, and the second control circuit includes a fifth transistor M5;

[0368] The gate of the first transistor M1 is electrically connected with the light emitting control input end HFI, the source of the first transistor M1 is electrically connected with the low voltage end VSS, and the drain of the first transistor M1 is electrically connected with the light emitting control voltage end HFO;

[0369] The gate of the second transistor M2 and the source of the second transistor M2 are electrically connected with the light emitting control reset end HFR, and the source of the second transistor M2 is electrically connected with the on-off control node Q;

[0370] The gate of the third transistor M3 is electrically connected with the on-off control node Q, the source of the third transistor M3 is electrically connected with the high voltage end VDD, and the drain of the third transistor M3 is electrically connected with the light emitting control voltage end HFO;

[0371] The gate of the fourth transistor M4 is electrically connected with the light emitting control reset end HFR, the source of the fourth transistor M4 is electrically connected with the on-off control node Q, and the drain of the fourth transistor M4 is electrically connected with the first intermediate node NZ1;

[0372] The gate of the fifth transistor M5 is electrically connected with the first control node S, the source of the fifth transistor M5 is electrically connected with the first intermediate node NZ1, and the drain of the fifth transistor M5 is electrically connected with the low voltage end VSS;

[0373] The first intermediate node control circuit includes a sixth transistor M6;

[0374] The gate of the sixth transistor M6 is electrically connected with the light emitting control voltage end HFO, the source of the sixth transistor M6 is electrically connected with the low voltage end VSS, and the drain of the sixth transistor M6 is electrically connected with the first intermediate node NZ1;

[0375] The eighth control circuit includes a fourteenth transistor M14;

[0376] A gate of the fourteenth transistor M14 is electrically connected with the light emitting control end EM, a source of the fourteenth transistor M14 is electrically connected with the second control node R, and a drain of the fourteenth transistor M14 is electrically connected with the first control node S;

[0377] The first data write circuit comprises a ninth transistor M9, the second data write circuit comprises a tenth transistor M10, the fifth control circuit comprises an eleventh transistor M11, the sixth control circuit comprises a twelfth transistor M12, and the seventh control circuit comprises a thirteenth transistor M13;

[0378] A gate of the ninth transistor M9 is electrically connected with the driving control end GA, a source of the ninth transistor M9 is electrically connected with the light emitting control data voltage end DE, and a drain of the ninth transistor M9 is electrically connected with the second control node R;

[0379] A gate of the tenth transistor M10 is electrically connected with the light emitting control end EM, a source of the tenth transistor M10 is electrically connected with the on-off data voltage end DS, and a drain of the tenth transistor M10 is electrically connected with the third control node NC3;

[0380] A gate of the eleventh transistor M11 is electrically connected with the third control node NC3, a source of the eleventh transistor M11 is electrically connected with the control data end DC, and a drain of the eleventh transistor M11 is electrically connected with the fourth control node NC4;

[0381] A gate of the twelfth transistor M12 is electrically connected with the third control node NC3, a source of the twelfth transistor M12 is electrically connected with the low voltage end VSS, and a drain of the twelfth transistor M12 is electrically connected with the fourth control node NC4;

[0382] A gate of the thirteenth transistor M13 is electrically connected with the fourth control node NC4, a source of the thirteenth transistor M13 is electrically connected with the low voltage end VSS, and a drain of the thirteenth transistor M13 is electrically connected with the second control node R;

[0383] The first light emitting control circuit comprises a fifteenth transistor M15, and the second light emitting control circuit comprises a sixteenth transistor M16;

[0384] A gate of the fifteenth transistor M15 is electrically connected with the light emitting control voltage end HFO, a source of the fifteenth transistor M15 is electrically connected with the power voltage end ELVDD, and a drain of the fifteenth transistor M15 is electrically connected with the first node N1;

[0385] A gate of the sixteenth transistor M16 is electrically connected with the light-emitting control end EM, a source of the sixteenth transistor M16 is electrically connected with the first node N1, and a drain of the sixteenth transistor M16 is electrically connected with an anode of the organic light-emitting diode O1; and a cathode of the organic light-emitting diode O1 is electrically connected with the low voltage end ELVSS.

[0386] The first energy storage circuit comprises a first capacitor C1, and the second energy storage circuit comprises a second capacitor C2.

[0387] A first end of the C1 is electrically connected with the HFO, and a second end of the C1 is electrically connected with the high voltage end VDD.

[0388] A first end of the C2 is electrically connected with the Q, and a second end of the C2 is electrically connected with the low voltage end VSS.

[0389] The third energy storage circuit comprises a third capacitor C3, and the fourth energy storage circuit comprises a fourth capacitor C4.

[0390] A first end of the C3 is electrically connected with the R, and a second end of the C3 is electrically connected with the high voltage end VDD.

[0391] A first end of the C4 is electrically connected with the NC3, and a second end of the C4 is electrically connected with the low voltage end VSS.

[0392] In at least one embodiment shown in the figure, the second voltage end is the low voltage end VSS, the third voltage end is the high voltage end VDD, the fourth voltage end is the low voltage end VSS, and the sixth voltage end is the low voltage end VSS. Figure 12A In at least one embodiment shown in the figure, the M1 is a p-type transistor, the M2 is an n-type transistor, the M3 is a p-type transistor, the M4 is a p-type transistor, the M5 is an n-type transistor, the M6 is an n-type transistor, the M14 is an n-type transistor, the M9 is an n-type transistor, the M10 is a p-type transistor, the M11 is a p-type transistor, the M12 is an n-type transistor, the M13 is an n-type transistor, and the M15 and the M16 are n-type transistors.

[0393] Figure 12A In at least one embodiment shown in the figure, the pixel circuit works when the VDD provides a 14V voltage signal, the VSS provides a -14V voltage signal, the ELVDD provides a 5V voltage signal, and the ELVSS provides a 0V voltage signal.

[0394] Figure 12A In at least one embodiment shown in the figure, the pixel circuit works when the VDD provides a 14V voltage signal, the VSS provides a -14V voltage signal, the ELVDD provides a 5V voltage signal, and the ELVSS provides a 0V voltage signal.

[0395] ​The high voltage value of the input signal provided by the HFI is 16V, the low voltage value of the input signal provided by the HFI is -16V, the input signal provided by the HFI is a square wave signal, the period of the input signal provided by the HFI is 100μs, and the ratio of the time during which the potential of the input signal is maintained at a low voltage to the time during which the potential of the input signal is maintained at a high voltage is 5 / 95;

[0396] The high voltage value of the reset signal provided by the HFR is 25V, the low voltage value of the reset signal provided by the HFR is -16V, the reset signal provided by the HFR is a square wave signal, the period of the reset signal provided by the HFR is 100μs, and the ratio of the time during which the potential of the reset signal is maintained at a low voltage to the time during which the potential of the reset signal is maintained at a high voltage is 96 / 4;

[0397] The DE provides a -13.6V voltage signal (but not limited to this);

[0398] The DS provides a -14V voltage signal or a 14V voltage signal;

[0399] Taking a display frequency of 60Hz as an example, when performing low gray scale display, the high voltage value of the control data voltage provided by the DC can be 14V, the low voltage value of the control data voltage can be -14V, the control data voltage can be a square wave voltage, the period of the control data voltage can be 16667μs, and the ratio of the time during which the voltage value of the control data voltage is maintained at a low voltage to the time during which the voltage value of the control data voltage is maintained at a high voltage can be 300 / 16367;

[0400] Taking a display frequency of 60Hz as an example, the high voltage value of the light emitting control signal provided by the EM can be 16V, the low voltage value of the light emitting control signal can be -16V, the period of the light emitting control signal can be 16667μs, and the ratio of the time during which the potential of the light emitting control signal is maintained at a high voltage to the time during which the potential of the light emitting control signal is maintained at a low voltage is 200 / 16467;

[0401] Taking a display frequency of 60Hz as an example, the high voltage value of the drive control signal provided by the GA can be 16V, the low voltage value of the drive control signal can be -16V, the period of the drive control signal can be 16667μs, and the ratio of the time during which the potential of the drive control signal is maintained at a high voltage to the time during which the potential of the drive control signal is maintained at a low voltage is 200 / 16467;

[0402] The capacitance value of C1 is 50fF, the capacitance value of C2 is 50fF, the capacitance value of C3 is 50fF, and the capacitance value of C4 is 50fF;

[0403] M1 and M2 are digital trigger TFTs, and the two form a first-order digital trigger.

[0404] M3, M4, M5, M6 are duty cycle adjustment control TFTs;

[0405] M14 and M9 are data voltage write holding TFTs;

[0406] M13, M12, M11, M10 are high and low gray scale switching TFTs;

[0407] M15 and M16 are light emitting control TFTs;

[0408] Figure 12A At least one embodiment of the pixel circuit shown in operation,

[0409] Before the start of a cycle (which can last 100 μs), HFR provides a high voltage signal, M2 is turned on, M4 is turned off, the potential of Q is reset to 25 V, and M3 is turned off;

[0410] After the start of a cycle, HFR provides a low voltage signal, M2 is turned off, M4 is turned on, HFI turns on M1, C1 is written with a low voltage signal provided by VSS, HFO outputs a low voltage signal, M6 is turned off, Q is discharged to VSS, the voltage of S is written to the gate of M5, and the discharge speed of Q is controlled by controlling the size of the saturation current Id of M5;

[0411] After a time t, when the gate-source voltage of M3 is less than the threshold voltage of M3, M3 is turned on, C1 is written with a high voltage signal provided by VDD, HFO outputs a high voltage signal, M6 is turned on, and the potential of Q is quickly discharged to a low voltage;

[0412] Before the end of a cycle (i.e., the last 5 μs of a cycle), HFR provides a high voltage signal, M2 is turned on, M4 is turned off, the potential of Q is reset to 25 V, M3 is turned off, C1 is kept at a high voltage, and HFO continues to output a high voltage signal;

[0413] The next cycle is started, and the above process is repeated.

[0414] Figure 12A At least one embodiment of the pixel circuit shown in operation,

[0415] The voltage of S is written to the gate of M5, the discharge speed of Q is controlled by controlling the size of the saturation current Id of M5, the time t required for the gate-source voltage of M3 to be less than the threshold voltage of M3 is the time during which HFO continues to output a low voltage signal, and different duty cycle light emitting control voltages can be obtained by adjusting the size of the voltage of S.

[0416] In Figure 12AIn at least one embodiment of the pixel circuit shown, M1 is a p-type transistor. At the start of the cycle, HFI provides a low voltage signal to turn on M1 and writes the low voltage signal provided by VSS. After the writing is completed, HFI outputs a high voltage signal to turn off M1. Due to the parasitic capacitance of M1, the voltage value of the light emission control voltage output by HFO will be pulled up, and the final voltage will be slightly higher than the voltage value of the low voltage signal provided by VSS, resulting in the gate-source voltage of M6 being greater than 0, which poses a risk of incomplete shutdown and leakage of M6.

[0417] compared to Figure 12A At least one embodiment of the pixel circuit shown, in Figure 13A In at least one embodiment of the pixel circuit shown, M1 is an n-type transistor. At the start of the cycle, HFI provides a high voltage signal to turn on M1 and writes a low voltage signal provided by VSS. After the writing is completed, HFI provides a low voltage signal to turn off M1. Due to the parasitic capacitance of M1, the voltage value of the light emission control voltage output by HFO will be pulled down. At this time, the gate-source voltage of M6 is less than 0, which solves the risk of M6 being turned on.

[0418] Figure 12A At least one embodiment of the pixel circuit shown, when in operation,

[0419] M9 and M14 are responsible for writing and holding the data voltage. During the data writing phase, GA provides a high voltage signal to turn on M9. The light control data voltage provided by DE is written to S, controlling the duty cycle of the light control voltage output by HFO. At the same time, EM turns off M14 to prevent the potential of S from being affected by the parasitic capacitance of M5.

[0420] M13, M12, M11, and M10 form a high / low grayscale switching module. When displaying high grayscale, the duty cycle adjustment circuit operates continuously. EM outputs a low voltage signal, turns on M10, DS writes a 14V voltage signal, turns off M11, turns on M12, VSS writes a low voltage signal to the gate of M13, and turns off M13. When displaying low grayscale, the duty cycle adjustment circuit operates for only one cycle. When EM provides a low voltage signal, DS writes a -14V voltage signal, turns on M11, turns off M12, and the control voltage provided by DC is written to the gate of M13. After EM provides a high voltage signal, DC continues to provide a low voltage signal, turning off M13 for one cycle. After that, DC provides a high voltage signal to turn on M13, VSS writes a low voltage signal to S to turn off M5, cutting off the Q-point discharge circuit. M3 remains off, and HFO continuously outputs a low voltage signal.

[0421] M15 and M16 are light emitting control TFTs, when the gray scale is switched, the light emitting control data voltage and the on-off data voltage are written, then the EM provides a high voltage signal, the light emitting control voltage outputted by the HFO controls the working time length of M15, controls the light emitting time of the organic light emitting diode, and realizes the gray scale display.

[0422] Figure 12B is Figure 12A The working timing diagram of at least one embodiment of the pixel circuit shown in

[0423] In the specific implementation, the voltage of S is adjusted by switching the voltage value of the light emitting control data voltage provided by the DE, the opening degree of M5 is controlled, and the duty cycle of the light emitting control voltage outputted by the HFO is adjusted.

[0424] Figure 12C is Figure 12A The working timing diagram of at least one embodiment of the pixel circuit shown in

[0425] As Figure 12C shown, when displaying low gray scale, under the control of the control voltage provided by the DC, the HFO only provides a square wave signal in one period, in the period, the time for the HFO to provide a high voltage signal is 75.1us, and 22 gray scale display is realized.

[0426] In Figure 12B , the first time period is S1, the second time period is S2, and the first time period S1 lasts for 200us.

[0427] In Figure 12B , the DE provides a-13.6V voltage signal, in the second time period S2, the potential of S is about-12.92V, and the duty cycle of the light emitting control voltage provided by the HFO is 75.1%.

[0428] In Figure 12C , the data writing stage is SW, and the low gray scale working stage is SC; the duration of SW is 200us, and the duration of SC is 100us.

[0429] In the data writing stage SW, the DE provides a-13.6V voltage signal, and in the low gray scale working stage SC, the duty cycle of the light emitting control voltage provided by the HFO is 75.1%.

[0430] Figure 13A The difference between at least one embodiment of the pixel circuit shown in Figure 12A and at least one embodiment of the pixel circuit shown in is that M1 is an n-type transistor.

[0431] Figure 13AAt least one embodiment of the pixel circuit shown in operation, the high voltage value of the input signal provided by the HFI is 16V, the low voltage value of the input signal provided by the HFI is -16V, the input signal provided by the HFI is a square wave signal, the period of the input signal provided by the HFI is 100us, and the ratio of the time when the potential of the input signal is maintained at a high voltage to the time when the potential of the input signal is at a low voltage is 5 / 95.

[0432] Figure 13B is Figure 13A At least one embodiment of the pixel circuit shown in operation, the timing diagram when displaying a high gray scale.

[0433] Figure 13C is Figure 13A At least one embodiment of the pixel circuit shown in operation, the timing diagram when displaying a low gray scale.

[0434] As Figure 14A As shown in Figure 7 On the basis of at least one embodiment of the pixel circuit shown, the light emitting element is an organic light emitting diode O1;

[0435] The input circuit includes a first transistor M1, the reset circuit includes a second transistor M2, the on-off control circuit includes a third transistor M3, the first control circuit includes a fourth transistor M4, and the second control circuit includes a fifth transistor M5;

[0436] The gate of the first transistor M1 is electrically connected to the light emitting control input end HFI, the source of the first transistor M1 is electrically connected to the high voltage end VDD, and the drain of the first transistor M1 is electrically connected to the light emitting control voltage end HFO;

[0437] The gate of the second transistor M2 and the source of the second transistor M2 are both electrically connected to the light emitting control reset end HFR, and the source of the second transistor M2 is electrically connected to the on-off control node Q;

[0438] The gate of the third transistor M3 is electrically connected to the on-off control node Q, the source of the third transistor M3 is electrically connected to the low voltage end VSS, and the drain of the third transistor M3 is electrically connected to the light emitting control voltage end HFO;

[0439] The gate of the fourth transistor M4 is electrically connected to the light emitting control reset end HFR, the source of the fourth transistor M4 is electrically connected to the on-off control node Q, and the drain of the fourth transistor M4 is electrically connected to the first intermediate node NZ1;

[0440] The gate of the fifth transistor M5 is electrically connected with the first control node S, the source of the fifth transistor M5 is electrically connected with the first intermediate node NZ1, and the drain of the fifth transistor M5 is electrically connected with the high-voltage signal terminal VDDL;

[0441] The first intermediate node control circuit comprises a sixth transistor M6;

[0442] The gate of the sixth transistor M6 is electrically connected with the light-emitting control voltage terminal HFO, the source of the sixth transistor M6 is electrically connected with the high-voltage signal terminal VDDL, and the drain of the sixth transistor M6 is electrically connected with the first intermediate node NZ1;

[0443] The eighth control circuit comprises a fourteenth transistor M14;

[0444] The gate of the fourteenth transistor M14 is electrically connected with the light-emitting control terminal EM, the source of the fourteenth transistor M14 is electrically connected with the second control node R, and the drain of the fourteenth transistor M14 is electrically connected with the first control node S;

[0445] The first data write-in circuit comprises a ninth transistor M9, the second data write-in circuit comprises a tenth transistor M10, the fifth control circuit comprises an eleventh transistor M11, the sixth control circuit comprises a twelfth transistor M12, and the seventh control circuit comprises a thirteenth transistor M13;

[0446] The gate of the ninth transistor M9 is electrically connected with the driving control terminal GA, the source of the ninth transistor M9 is electrically connected with the light-emitting control data voltage terminal DE, and the drain of the ninth transistor M9 is electrically connected with the second control node R;

[0447] The gate of the tenth transistor M10 is electrically connected with the light-emitting control terminal EM, the source of the tenth transistor M10 is electrically connected with the on-off data voltage terminal DS, and the drain of the tenth transistor M10 is electrically connected with the third control node NC3;

[0448] The gate of the eleventh transistor M11 is electrically connected with the third control node NC3, the source of the eleventh transistor M11 is electrically connected with the control data terminal DC, and the drain of the eleventh transistor M11 is electrically connected with the fourth control node NC4;

[0449] The gate of the twelfth transistor M12 is electrically connected with the third control node NC3, the source of the twelfth transistor M12 is electrically connected with the high-voltage terminal VDD, and the drain of the twelfth transistor M12 is electrically connected with the fourth control node NC4;

[0450] The gate of the thirteenth transistor M13 is electrically connected with the fourth control node NC4, the source of the thirteenth transistor M13 is electrically connected with the high voltage terminal VDD, and the drain of the thirteenth transistor M13 is electrically connected with the second control node R;

[0451] The first light emitting control circuit comprises a fifteenth transistor M15, and the second light emitting control circuit comprises a sixteenth transistor M16;

[0452] The gate of the fifteenth transistor M15 is electrically connected with the light emitting control voltage terminal HFO, the source of the fifteenth transistor M15 is electrically connected with the power voltage terminal ELVDD, and the drain of the fifteenth transistor M15 is electrically connected with the first node N1;

[0453] The gate of the sixteenth transistor M16 is electrically connected with the light emitting control terminal EM, the source of the sixteenth transistor M16 is electrically connected with the first node N1, and the drain of the sixteenth transistor M16 is electrically connected with the anode of the organic light emitting diode O1; the cathode of the organic light emitting diode O1 is electrically connected with the low voltage terminal ELVSS;

[0454] The first energy storage circuit comprises a first capacitor C1, and the second energy storage circuit comprises a second capacitor C2;

[0455] The first end of C1 is electrically connected with HFO, and the second end of C1 is electrically connected with the high voltage terminal VDD;

[0456] The first end of C2 is electrically connected with Q, and the second end of C2 is electrically connected with the high voltage terminal VDD;

[0457] The third energy storage circuit comprises a third capacitor C3, and the fourth energy storage circuit comprises a fourth capacitor C4;

[0458] The first end of C3 is electrically connected with R, and the second end of C3 is electrically connected with the high voltage terminal VDD;

[0459] The first end of C4 is electrically connected with NC3, and the second end of C4 is electrically connected with the high voltage terminal VDD.

[0460] In Figure 14A In at least one embodiment shown in the figure, the second voltage terminal is the high voltage terminal VDD, the third voltage terminal is the low voltage terminal VSS, the fourth voltage terminal is the high voltage signal terminal VDDL, and the sixth voltage terminal is the high voltage terminal VDD.

[0461] Optionally, the voltage value of the high voltage signal provided by the high voltage signal terminal VDDL is slightly less than the voltage value of the high voltage signal provided by the high voltage terminal.

[0462] In Figure 14AIn at least one embodiment shown, M1 is an n-type transistor, M2 is a p-type transistor, M3 is an n-type transistor, M4 is an n-type transistor, M5 is a p-type transistor, M6 is a p-type transistor, M14 is a p-type transistor, M9 is a p-type transistor, M10 is an n-type transistor, M11 is an n-type transistor, M12 is a p-type transistor, M13 is a p-type transistor, M15 and M16 are p-type transistors.

[0463] The present application Figure 14A In at least one embodiment shown, VDD provides a 14V voltage signal, VSS provides a -14V voltage signal, ELVDD provides a 5V voltage signal, and ELVSS provides a 0V voltage signal;

[0464] The high voltage value of the input signal provided by the HFI is 16V, the low voltage value of the input signal provided by the HFI is -16V, the input signal provided by the HFI is a square wave signal, the period of the input signal provided by the HFI is 100μs, and the ratio of the time during which the potential of the input signal is maintained at a high voltage to the time during which the potential of the input signal is maintained at a low voltage is 5 / 95;

[0465] The high voltage value of the reset signal provided by the HFR is 16V, the low voltage value of the reset signal provided by the HFR is -25V, the reset signal provided by the HFR is a square wave signal, the period of the reset signal provided by the HFR is 100μs, and the ratio of the time during which the potential of the reset signal is maintained at a low voltage to the time during which the potential of the reset signal is maintained at a high voltage is 4 / 96;

[0466] The DE can provide a 9.6V voltage signal or a 9.88V voltage signal (but not limited thereto);

[0467] The DS can provide a -14V voltage signal or a 14V voltage signal;

[0468] Taking a display frequency of 60Hz as an example, when performing low gray scale display, the high voltage value of the control data voltage provided by the DC can be 14V, the low voltage value of the control data voltage can be -14V, the control data voltage can be a square wave voltage, the period of the control data voltage can be 16667μs, and the ratio of the time during which the voltage value of the control data voltage is maintained at a high voltage to the time during which the voltage value of the control data voltage is maintained at a low voltage can be 300 / 16367;

[0469] Taking a display frequency of 60Hz as an example, the high voltage value of the driving control signal provided by the GA can be 16V, the low voltage value of the driving control signal can be -16V, the period of the driving control signal can be 16667μs, and the ratio of the time during which the potential of the driving control signal is maintained at a low voltage to the time during which the potential of the driving control signal is maintained at a high voltage is 200 / 16467;

[0470] Taking the display frequency of 60Hz as an example, the high voltage value of the light emitting control signal provided by the EM can be 16V, the low voltage value of the light emitting control signal can be -16V, the period of the light emitting control signal can be 16667μs, and the ratio of the time during which the potential of the light emitting control signal is at the high voltage to the time during which the potential of the light emitting control signal is at the low voltage is 200 / 16467;

[0471] The capacitance value of C1 is 50fF, the capacitance value of C2 is 50fF, the capacitance value of C3 is 50fF, and the capacitance value of C4 is 50fF;

[0472] M1 and M2 are digital trigger TFTs, and the two form a first-order digital trigger.

[0473] M3, M4, M5 and M6 are duty cycle adjustment control TFTs;

[0474] M79 and M14 are data voltage writing and holding TFTs;

[0475] M13, M12, M11 and M10 are high-low gray scale switching TFTs;

[0476] M15 and M16 are light emitting control TFTs.

[0477] Figure 14A At least one embodiment shown in operation,

[0478] Before the start of a period (the period lasts for 100μs), the HFR provides a low voltage signal, M2 is opened, M4 is closed, the potential of Q is reset to -25V, and M3 is closed;

[0479] After the start of a period, the HFR provides a high voltage signal, M2 is closed, M4 is opened, the HFI provides a high voltage signal, M1 is opened, the high voltage signal provided by VDD is written to C1, the HFO outputs a high voltage signal, M6 is closed at the same time, Q is charged by VDD, the voltage of S is written to the gate of M5, and the charging speed of Q is controlled by controlling the size of the saturation current Id of M5;

[0480] After a time t, when the gate-source voltage of M3 is greater than the threshold voltage of M3, M3 is opened, the low voltage signal provided by VSS is written to C1, the HFO outputs a low voltage signal, M6 is opened at the same time, and the potential of Q is quickly charged to a high voltage;

[0481] Before the end of a period (i.e., the last 5μs included in the period), the HFR provides a low voltage signal, M2 is opened, M4 is closed, the potential of Q is reset to -25V, M3 is closed, C1 maintains a low voltage, and the HFO continuously outputs a low voltage signal;

[0482] The next cycle starts, and the above process is repeated.

[0483] Figure 14A At least one embodiment shown works,

[0484] The voltage of S is written to the gate of M5, and by controlling the size of the saturation current Id of M5, the charging speed of Q point is controlled. The time required for the potential of Q to charge the gate-source voltage of M3 to be greater than the threshold voltage of M3 is the time for which HFO continuously outputs a high voltage. By adjusting the size of the voltage of S, a light-emitting control voltage with different duty cycles can be obtained.

[0485] In at least one embodiment shown in FIG. 14, M1 is an n-type transistor. At the beginning of the cycle, HFI provides a high voltage signal to open M1, and a high voltage signal provided by VDD is written. After the writing is completed, HFI provides a low voltage signal to close M1. Due to the influence of the parasitic capacitance of M1, the voltage value of the light-emitting control voltage provided by HFO will be pulled down, and the final voltage will be slightly lower than the voltage value of the high voltage signal provided by VDD, resulting in that the gate-source voltage of M6 is less than 0, and there is a risk of incomplete closing of M6 and leakage.

[0486] Compared with Figure 14A In at least one embodiment shown, Figure 15A In at least one embodiment shown, M1 is a p-type transistor. At the beginning of the cycle, HFI provides a low voltage signal to open M1, and a high voltage signal provided by VDD is written. After the writing is completed, HFI provides a high voltage signal to close M1. Due to the influence of the parasitic capacitance of M1, the voltage value of the light-emitting control voltage provided by HFO will be pulled up, and at this time, the gate-source voltage of M6 is greater than 0, solving the risk of M6 being opened.

[0487] Figure 14A At least one embodiment shown works,

[0488] M9 and M14 are responsible for data voltage writing and holding. In the data writing stage, GA provides a low voltage signal to open M9, and the light-emitting control data voltage provided by DE is written to S to control the duty cycle of the light-emitting control voltage output by HFO. At the same time, EM provides a high voltage signal to close M14 to avoid the voltage of S being affected by the parasitic capacitance of M5.

[0489] M13, M12, M11 and M10 constitute a high-low gray scale switching module. When displaying a high gray scale, the duty cycle adjusting circuit works all the time, EM provides a high voltage signal, M10 is opened, DS writes a -14V voltage signal, M11 is closed, M12 is opened, and a high voltage signal provided by VDD is written to the gate of M13, and M13 is closed. When displaying a low gray scale, the duty cycle adjusting circuit only works for one period. When EM provides a high voltage signal, DS writes a 14V voltage signal, M11 is opened, M12 is closed, DC writes a control voltage to the gate of M13. After EM provides a low voltage signal, DC continues to provide a high voltage signal, M13 is closed for one period, and then DC provides a low voltage signal. M13 is opened, VDD writes a high voltage signal to S, M5 is closed, the Q point discharging circuit is cut off, M3 is always kept closed, and HFO continuously outputs a high voltage signal.

[0490] M15 and M16 are light-emitting control TFTs. When the gray scale is switched, a light-emitting control data voltage and a turn-on-off data voltage are written, and then EM provides a low voltage signal. The light-emitting control voltage output by HFO controls the conduction time of M15, controls the light-emitting time of organic light-emitting diode O1, and realizes gray scale display.

[0491] Figure 14B is Figure 14A The simulation working timing diagram of at least one embodiment of the pixel circuit shown in FIG. 8 when displaying a high gray scale.

[0492] In Figure 14B , the label SW is a data writing stage. The data writing stage SW can last for 200μs. In the data writing stage SW, DC provides a low voltage signal, and DE writes a light-emitting control data voltage. Figure 14B In at least one embodiment shown in FIG. 8, DE writes a 9.6V voltage signal.

[0493] In Figure 14B , the label SG is a high gray scale working stage. The high gray scale working stage SG can last for 16476μs. In the high gray scale working stage SG, the duty cycle of the light-emitting control voltage provided by HFO is 85.2%. In the high gray scale working stage SG, EM provides a low voltage signal, and M16 is opened. When HFO provides a low voltage signal, M15 is turned on, and O1 emits light.

[0494] In Figure 14B , the voltage of S is 9.6V.

[0495] In Figure 14C , the label SW is a data writing stage, and the label SC is a low gray scale working stage. The data writing stage SW lasts for 200μs, and the low gray scale working stage SC lasts for 100μs.

[0496] In the data writing stage SW, the DE provides a 9.88V voltage signal, in the low gray scale working stage SC, the duty cycle of the light emitting control voltage provided by the HFO is 20%, and 12 gray scale display is realized.

[0497] Figure 15A At least one embodiment of the pixel circuit shown is different from Figure 14A At least one embodiment of the pixel circuit shown is different from

[0498] The application Figure 15A In at least one embodiment shown, the high voltage value of the input signal provided by the HFI is 16V, the low voltage value of the input signal provided by the HFI is -16V, the input signal provided by the HFI is a square wave signal, the period of the input signal provided by the HFI is 100us, and the ratio of the time when the potential of the input signal is maintained at a low voltage to the time when the potential of the input signal is at a high voltage is 5 / 95.

[0499] Figure 15B The application Figure 15A The simulation working timing diagram of at least one embodiment of the pixel circuit shown when displaying a high gray scale is shown in the figure.

[0500] Figure 15C The application Figure 15A The simulation working timing diagram of at least one embodiment of the pixel circuit shown when displaying a low gray scale is shown in the figure.

[0501] The driving method described in the embodiment of the application is applied to the pixel circuit described above, and the driving method comprises the following steps:

[0502] The first light emitting control circuit controls the communication between the power supply voltage end and the first node under the control of the light emitting control voltage.

[0503] The second light emitting control circuit controls the communication between the first node and the first pole of the light emitting element under the control of the light emitting control signal.

[0504] The light emitting control voltage control circuit controls the light emitting control voltage provided by the light emitting control voltage end under the control of the input signal provided by the light emitting control input end, the reset signal provided by the light emitting control reset end, and the light emitting control signal provided by the light emitting control end, according to the light emitting control data voltage provided by the light emitting control data voltage end, the on-off data voltage provided by the on-off data voltage end, and the control data voltage provided by the control data end.

[0505] The display device described in the embodiment of the application comprises the pixel circuit described above.

[0506] The above is the preferred embodiment of the present application, it should be noted that for those skilled in the art, without departing from the principles described in the present application, can also be made several improvements and refinements, these improvements and refinements should also be considered the scope of protection of the present application.

Claims

1. A pixel circuit, characterized by comprising: The light-emitting element, the first light-emitting control circuit, the second light-emitting control circuit and the light-emitting control voltage control circuit are provided. The first light-emitting control circuit is electrically connected with the light-emitting control voltage terminal, the power voltage terminal and the first node, respectively, and is configured to control the communication between the power voltage terminal and the first node under the control of the light-emitting control voltage provided by the light-emitting control voltage terminal. The second light-emitting control circuit is electrically connected with the light-emitting control terminal, the first node and the first electrode of the light-emitting element, respectively, and is configured to control the communication between the first node and the first electrode of the light-emitting element under the control of the light-emitting control signal provided by the light-emitting control terminal. The light-emitting control voltage control circuit is electrically connected with the light-emitting control voltage terminal, the light-emitting control input terminal, the light-emitting control reset terminal, the light-emitting control terminal, the light-emitting control data voltage terminal, the on-off data voltage terminal and the control data terminal, respectively, and is configured to control the light-emitting control voltage provided by the light-emitting control voltage terminal according to the light-emitting control data voltage provided by the light-emitting control data voltage terminal, the on-off data voltage provided by the on-off data voltage terminal and the control data voltage provided by the control data terminal under the control of the input signal provided by the light-emitting control input terminal, the reset signal provided by the light-emitting control reset terminal and the light-emitting control signal provided by the light-emitting control terminal. The light-emitting control voltage control circuit comprises an input circuit, a reset circuit, an on-off control circuit, a first control circuit, a second control circuit and a first control node control circuit. The input circuit is electrically connected with the light-emitting control input terminal, the second voltage terminal and the light-emitting control voltage terminal, respectively, and is configured to control the communication between the light-emitting control voltage terminal and the second voltage terminal under the control of the input signal provided by the light-emitting control input terminal. The reset circuit is electrically connected with the light-emitting control reset terminal and the on-off control node, respectively, and is configured to control the potential of the on-off control node under the control of the reset signal provided by the light-emitting control reset terminal. The on-off control circuit is electrically connected with the on-off control node, the third voltage terminal and the light-emitting control voltage terminal, respectively, and is configured to control the communication between the light-emitting control voltage terminal and the third voltage terminal under the control of the potential of the on-off control node. The first control circuit is electrically connected with the light-emitting control reset terminal, the on-off control node and the first intermediate node, respectively, and is configured to control the communication between the on-off control node and the first intermediate node under the control of the reset signal. The second control circuit is electrically connected with the first control node, the first intermediate node and the fourth voltage terminal, respectively, and is configured to control the communication between the first intermediate node and the fourth voltage terminal under the control of the potential of the first control node. The first control node control circuit is electrically connected with the first control node, the light-emitting control end, the light-emitting control data voltage end, the on-off data voltage end and the control data end respectively, and is used for controlling the potential of the first control node according to the light-emitting control data voltage, the on-off data voltage and the control data voltage under the control of the light-emitting control signal provided by the light-emitting control end.

2. The pixel circuit of claim 1, wherein, The first intermediate node control circuit is further included; The first intermediate node control circuit is electrically connected with the light-emitting control voltage end, the first intermediate node and the fourth voltage end respectively, and is used for controlling the communication between the first intermediate node and the fourth voltage end under the control of the light-emitting control voltage provided by the light-emitting control voltage end.

3. The pixel circuit of claim 1, wherein, The first energy storage circuit and the second energy storage circuit are further included; The first energy storage circuit is electrically connected with the light-emitting control voltage end, and is used for maintaining the potential of the light-emitting control voltage end; The second energy storage circuit is electrically connected with the on-off control node, and is used for maintaining the potential of the on-off control node.

4. The pixel circuit of claim 1, wherein, The first control node control circuit includes a third control circuit, a fourth control circuit and a second control node control circuit; The third control circuit is electrically connected with the second control node, the fifth voltage end and the first control node respectively, and is used for controlling the communication between the first control node and the fifth voltage end under the control of the potential of the second control node; The fourth control circuit is electrically connected with the sixth voltage end and the first control node respectively, and is used for controlling the potential of the first control node; The second control node control circuit is electrically connected with the second control node, the light-emitting control end, the light-emitting control data voltage end, the on-off data voltage end and the control data end respectively, and is used for controlling the potential of the second control node according to the light-emitting control data voltage, the on-off data voltage and the control data voltage under the control of the light-emitting control signal provided by the light-emitting control end.

5. The pixel circuit of claim 4, wherein, The second control node control circuit includes a first data write-in circuit, a second data write-in circuit, a fifth control circuit, a sixth control circuit and a seventh control circuit; The first data write-in circuit is electrically connected with the light-emitting control end, the light-emitting control data voltage end and the second control node respectively, and is used for writing the light-emitting control data voltage into the second control node under the control of the light-emitting control signal; The second data write-in circuit is electrically connected with the light-emitting control end, the on-off data voltage end and the third control node respectively, and is used for writing the on-off data voltage provided by the on-off data voltage end into the third control node under the control of the light-emitting control signal; The fifth control circuit is electrically connected with the third control node, the control data end and the fourth control node respectively, and is used for writing the control data voltage into the fourth control node under the control of the potential of the third control node; The sixth control circuit is electrically connected with the third control node and the sixth voltage end, and the fourth control node and the sixth voltage end are communicated. The seventh control circuit is electrically connected with the fourth control node, the fifth voltage terminal and the second control node respectively, and is configured to control communication between the second control node and the fifth voltage terminal under control of a potential of the fourth control node.

6. The pixel circuit of claim 1, wherein, The first control node control circuit includes an eighth control circuit and a second control node control circuit; The eighth control circuit is electrically connected with the light-emitting control terminal, the second control node and the first control node respectively, and is configured to control communication between the first control node and the second control node under control of a light-emitting control signal provided by the light-emitting control terminal; The second control node control circuit is electrically connected with the light-emitting control terminal, the driving control terminal, the light-emitting control data voltage terminal, the on-off data voltage terminal and the control data terminal respectively, and is configured to control a potential of the second control node according to the light-emitting control data voltage, the on-off data voltage and the control data voltage under control of a light-emitting control signal provided by the light-emitting control terminal and a driving control signal provided by the driving control terminal.

7. The pixel circuit of claim 6, wherein, The second control node control circuit includes a first data write-in circuit, a second data write-in circuit, a fifth control circuit, a sixth control circuit and a seventh control circuit; The first data write-in circuit is electrically connected with the driving control terminal, the light-emitting control data voltage terminal and the second control node respectively, and is configured to write the light-emitting control data voltage into the second control node under control of the driving control signal; The second data write-in circuit is electrically connected with the light-emitting control terminal, the on-off data voltage terminal and the third control node, and is configured to write the on-off data voltage provided by the on-off data voltage terminal into the third control node under control of the light-emitting control signal; The fifth control circuit is electrically connected with the third control node, the control data terminal and the fourth control node respectively, and is configured to write the control data voltage into the fourth control node under control of a potential of the third control node; The sixth control circuit is electrically connected with the third control node, the sixth voltage terminal and the fourth control node respectively, and is configured to control communication between the fourth control node and the sixth voltage terminal under control of a potential of the third control node; The seventh control circuit is electrically connected with the fourth control node, the sixth voltage terminal and the second control node respectively, and is configured to control communication between the second control node and the sixth voltage terminal under control of a potential of the fourth control node.

8. The pixel circuit of claim 5 or 7, wherein, The display device further includes a third energy storage circuit and a fourth energy storage circuit; The third energy storage circuit is electrically connected with the second control node, and is configured to maintain the potential of the second control node; The fourth energy storage circuit is electrically connected with the third control node, and is configured to maintain the potential of the third control node.

9. The pixel circuit of claim 1, wherein, The input circuit includes a first transistor, the reset circuit includes a second transistor, the on-off control circuit includes a third transistor, the first control circuit includes a fourth transistor, and the second control circuit includes a fifth transistor. The gate of the first transistor is electrically connected with the light-emitting control input end, the first pole of the first transistor is electrically connected with the second voltage end, and the second pole of the first transistor is electrically connected with the light-emitting control voltage end; The gate of the second transistor and the first pole of the second transistor are both electrically connected with the light-emitting control reset end, and the second pole of the second transistor is electrically connected with the on-off control node; The gate of the third transistor is electrically connected with the on-off control node, the first pole of the third transistor is electrically connected with the third voltage end, and the second pole of the third transistor is electrically connected with the light-emitting control voltage end; The gate of the fourth transistor is electrically connected with the light-emitting control reset end, the first pole of the fourth transistor is electrically connected with the on-off control node, and the second pole of the fourth transistor is electrically connected with the first intermediate node; The gate of the fifth transistor is electrically connected with the first control node, the first pole of the fifth transistor is electrically connected with the first intermediate node, and the second pole of the fifth transistor is electrically connected with the fourth voltage end.

10. The pixel circuit of claim 2, wherein, The first intermediate node control circuit comprises a sixth transistor; The gate of the sixth transistor is electrically connected with the light-emitting control voltage end, the first pole of the sixth transistor is electrically connected with the fourth voltage end, and the second pole of the sixth transistor is electrically connected with the first intermediate node.

11. The pixel circuit of claim 4, wherein, The third control circuit comprises a seventh transistor, and the fourth control circuit comprises an eighth transistor; The gate of the seventh transistor is electrically connected with the second control node, the first pole of the seventh transistor is electrically connected with the fifth voltage end, and the second pole of the seventh transistor is electrically connected with the first control node; The gate of the eighth transistor and the first pole of the eighth transistor are both electrically connected with the sixth voltage end, and the second pole of the eighth transistor is electrically connected with the first control node.

12. The pixel circuit of claim 5, wherein, The first data write-in circuit comprises a ninth transistor, the second data write-in circuit comprises a tenth transistor, the fifth control circuit comprises an eleventh transistor, the sixth control circuit comprises a twelfth transistor, and the seventh control circuit comprises a thirteenth transistor; The gate of the ninth transistor is electrically connected with the light-emitting control end, the first pole of the ninth transistor is electrically connected with the light-emitting control data voltage end, and the second pole of the ninth transistor is electrically connected with the second control node; The gate of the tenth transistor is electrically connected with the light-emitting control end, the first pole of the tenth transistor is electrically connected with the on-off data voltage end, and the second pole of the tenth transistor is electrically connected with the third control node; The gate of the eleventh transistor is electrically connected with the third control node, the first pole of the eleventh transistor is electrically connected with the control data end, and the second pole of the eleventh transistor is electrically connected with the fourth control node; The gate of the twelfth transistor is electrically connected with the third control node, the first pole of the twelfth transistor is electrically connected with the sixth voltage end, and the second pole of the twelfth transistor is electrically connected with the fourth control node; A gate of the thirteenth transistor is electrically connected with the fourth control node, a first electrode of the thirteenth transistor is electrically connected with the fifth voltage terminal, and a second electrode of the thirteenth transistor is electrically connected with the second control node.

13. The pixel circuit of claim 6, wherein, The eighth control circuit comprises a fourteenth transistor; A gate of the fourteenth transistor is electrically connected with the light-emitting control terminal, a first electrode of the fourteenth transistor is electrically connected with the second control node, and a second electrode of the fourteenth transistor is electrically connected with the first control node.

14. The pixel circuit of claim 7, wherein, The first data writing circuit comprises a ninth transistor, the second data writing circuit comprises a tenth transistor, the fifth control circuit comprises an eleventh transistor, the sixth control circuit comprises a twelfth transistor, and the seventh control circuit comprises a thirteenth transistor; A gate of the ninth transistor is electrically connected with the driving control terminal, a first electrode of the ninth transistor is electrically connected with the light-emitting control data voltage terminal, and a second electrode of the ninth transistor is electrically connected with the second control node; A gate of the tenth transistor is electrically connected with the light-emitting control terminal, a first electrode of the tenth transistor is electrically connected with the on-off data voltage terminal, and a second electrode of the tenth transistor is electrically connected with the third control node; A gate of the eleventh transistor is electrically connected with the third control node, a first electrode of the eleventh transistor is electrically connected with the control data terminal, and a second electrode of the eleventh transistor is electrically connected with the fourth control node; A gate of the twelfth transistor is electrically connected with the third control node, a first electrode of the twelfth transistor is electrically connected with the sixth voltage terminal, and a second electrode of the twelfth transistor is electrically connected with the fourth control node; A gate of the thirteenth transistor is electrically connected with the fourth control node, a first electrode of the thirteenth transistor is electrically connected with the sixth voltage terminal, and a second electrode of the thirteenth transistor is electrically connected with the second control node.

15. The pixel circuit of claim 1, wherein, The first light-emitting control circuit comprises a fifteenth transistor, and the second light-emitting control circuit comprises a sixteenth transistor; A gate of the fifteenth transistor is electrically connected with the light-emitting control voltage terminal, a first electrode of the fifteenth transistor is electrically connected with the power voltage terminal, and a second electrode of the fifteenth transistor is electrically connected with the first node; A gate of the sixteenth transistor is electrically connected with the light-emitting control terminal, a first electrode of the sixteenth transistor is electrically connected with the first node, and a second electrode of the sixteenth transistor is electrically connected with a first electrode of the light-emitting element.

16. A driving method applied to the pixel circuit according to any one of claims 1 to 15, characterized by, The driving method comprises: The first light-emitting control circuit controls the communication between the power voltage terminal and the first node under the control of the light-emitting control voltage; The second light-emitting control circuit controls the communication between the first node and the first electrode of the light-emitting element under the control of the light-emitting control signal; and The driving method further comprises: The driving control terminal is controlled to be in a high level state under the control of the driving control signal, so that the ninth transistor is turned on, the light-emitting control data voltage terminal is electrically connected with the second control node, and the light-emitting control voltage is input to the second control node; The light-emitting control voltage control circuit controls the light-emitting control voltage provided by the light-emitting control voltage terminal according to the light-emitting control data voltage provided by the light-emitting control data voltage terminal, the on-off data voltage provided by the on-off data voltage terminal and the control data voltage provided by the control data terminal under the control of the input signal provided by the light-emitting control input terminal, the reset signal provided by the light-emitting control reset terminal and the light-emitting control signal provided by the light-emitting control terminal.

17. A display device comprising: A pixel circuit as claimed in any one of claims 1 to 15.

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